HOSTMCU

HOSTMCU_AON

This section provides information on the HOSTMCU_AON Module Instance within this product. Each of the registers within the Module Instance is described separately below.

HOST AON REGISTERS

HOSTMCU_AON Registers Mapping Summary

:HOSTMCU_AON Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
WUCSKPCFG	RW	32	0x0000 0000	0x0000 0004
CFGWICSNS	RW	32	0x0000 0000	0x0000 0008
CFGWUTP	RW	32	0x0000 0000	0x0000 000C
ELPTMREN	RW	32	0x0000 0002	0x0000 0010
CFGTMRWU	RW	32	0x0000 0000	0x0000 0014
TMRWUREQ	RW	32	0x0000 0000	0x0000 0018
CFGWDT	RW	32	0x800E A600	0x0000 001C
WDTREQ	RW	32	0x0000 0000	0x0000 0020
GPWUAND	RW	32	0xFFFF FFFF	0x0000 0028
GPWUOR	RW	32	0xFFFF FFFF	0x0000 002C
GPWUAND_1	RW	32	0x000F FFFF	0x0000 0030
GPWUOR_1	RW	32	0x000F FFFF	0x0000 0034
FCLKARM	RW	32	0x0000 0000	0x0000 0038
SLPTIMES	RW	32	0x0000 0000	0x0000 003C
SLPTIMEF	RW	32	0x0000 0000	0x0000 0040
WUREQ	RW	32	0x0000 0000	0x0000 004C
OREFCLK	RW	32	0x0000 0012	0x0000 0050
WUC	RW	32	0x0000 0004	0x0000 005C

HOSTMCU_AON Instances Register Mapping Summary

HOSTMCU_AON Register Descriptions

:HOSTMCU_AON Common Register Descriptions

:HOSTMCU_AON:WUCSKPCFG

Address offset	0x0000 0004
Description	Wake up Control Skip Configuration
Type	RW

Bits	Field Name	Description		Type	Reset
31:2	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000 0000
1	SKPPDVLD	SKIP POWER DOMAIN VALID Enable skip precise duration for Power Domain if wake up event type is '0': '0' - don't skip '1' - skip		RW	0
		0	DIS Don't skip
		1	EN Skip
0	SKPPRCMVLD	SKIP PRCM VALID Enable skip precise duration for PRCM Shared UP if wake up event type is '0': '0' - don't skip '1' - skip		RW	0
		0	DIS Don't Skip
		1	EN Skip

:HOSTMCU_AON:CFGWICSNS

Address offset	0x0000 0008
Description	Configure WIC SENSE
Type	RW

Bits	Field Name	Description		Type	Reset
31:18	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000
17:0	VAL	Field to control wake up source Set 1 - Enable wake up source. Set 0 - Disable wake up source. Bit 0 : ELP TMR Wake up request Bit 1 : GPIO wake up src 0 Bit 2 : GPIO wake up src 1 Bit 3 : doorbell 0 Bit 4 : doorbell 1 Bit 5 : doorbell 2 Bit 6 : doorbell 3 Bit 7 : doorbell 4 Bit 8 : doorbell 5 Bit 9 : doorbell 6 Bit 10 : doorbell 7 Bit 11 : nab_host_irq Bit 12 : ble_rfc_gpo_8_irq Bit 13 : RTC Bit 14 : DebugSS Csyspwrupreq Bit 15 : DebugSS Forceactive Bit 16 : secured_error_irq Bit 17 : core wdt irq Note: GPIO wakeup src 0 is AND of wakeup sources and GPIO wakup src 1 is OR of wakeup sources		RW	0x0 0000
		0x0 0000	DIS Disable wakeup source
		0x0 0001	TMRREQ_EN ELP timer wakeup request
		0x0 0002	WUSRC0_EN AND of wakeup sources
		0x0 0004	WUSRC1_EN OR of wakeup sources
		0x0 0008	DRBL0_EN Doorbell 0
		0x0 0010	DRBL1_EN Doorbell 1
		0x0 0020	DRBL2_EN Doorbell 2
		0x0 0040	DRBL3_EN Doorbell 3
		0x0 0080	DRBL4_EN Doorbell 4
		0x0 0100	DRBL5_EN Doorbell 5
		0x0 0200	DRBL6_EN Doorbell 6
		0x0 0400	DRBL7_EN Doorbell 7
		0x0 0800	NAB_EN NAB host irq
		0x0 1000	BLERFCGPO_EN BLE RFC GPO 9 irq
		0x0 2000	RTC_EN RTC
		0x0 4000	DBGPWRUP_EN Debugss Csyspwrupreq
		0x0 8000	DBGFRCACT_EN Debugss forecactive
		0x1 0000	SECERR_EN Secure error irq
		0x2 0000	COREWDT_EN Core WDT request

:HOSTMCU_AON:CFGWUTP

Address offset	0x0000 000C
Description	ELP Wake-up Type Configuration. Register to configure wake up type
Type	RW

Bits	Field Name	Description		Type	Reset
31:18	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000
17:0	VAL	Field to configure wake up type Set 0 - Slow Wake up (precise WU). Set 1 - Fast Wake up (assume system is already active when event is triggered). Bit 0 : ELP TMR Wake up request Bit 1 : GPIO wake up src 0 Bit 2 : GPIO wake up src 1 Bit 3 : doorbell 0 Bit 4 : doorbell 1 Bit 5 : doorbell 2 Bit 6 : doorbell 3 Bit 7 : doorbell 4 Bit 8 : doorbell 5 Bit 9 : doorbell 6 Bit 10 : doorbell 7 Bit 11 : nab_host_irq Bit 12 : ble_rfc_gpo_8_irq Bit 13 : RTC Bit 14 : DebugSS Csyspwrupreq Bit 15 : DebugSS Forceactive Bit 16 : secured_error_irq Bit 17 : core wdt irq Note: GPIO wakeup src 0 is AND of wakeup sources and GPIO wakup src 1 is OR of wakeup sources		RW	0x0 0000
		0x0 0000	SLOW Slow wakeup(precise wakup)
		0x0 0001	TMRREQ Fast Wake up
		0x0 0002	WUSRC0 Fast Wake up
		0x0 0004	WUSRC1 Fast Wake up
		0x0 0008	DRBL0 Fast Wake up
		0x0 0010	DRBL1 Fast Wake up
		0x0 0020	DRBL2 Fast Wake up
		0x0 0040	DRBL3 Fast Wake up
		0x0 0080	DRBL4 Fast Wake up
		0x0 0100	DRBL5 Fast Wake up
		0x0 0200	DRBL6 Fast Wake up
		0x0 0400	DRBL7 Fast Wake up
		0x0 0800	NAB Fast Wake up
		0x0 1000	BLERFCGPO Fast Wake up
		0x0 2000	RTC Fast Wake up
		0x0 4000	DBGPWRUP Fast Wake up
		0x0 8000	DBGFRCACT Fast Wake up
		0x1 0000	SECERR Fast Wake up
		0x2 0000	COREWDT Fast Wake up

:HOSTMCU_AON:ELPTMREN

Address offset	0x0000 0010
Description	ELP Timer Enable. Register to configure ELP Timer enable
Type	RW

Bits	Field Name	Description		Type	Reset
31:17	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000
16	ELPTMRLD	ELP TIMER LOAD setting this bit will load the value 2 to the timer		WO	0
15:4	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x000
3	ELPTMRRST	ELP TIMER RESET setting this bit will stop the timer		RW	0
2	ELPTMRSET	ELP TIMER SET starts the timer		RW	0
1	TMRSWCTL	Field to configure the type of timer control		RW	1
		0	HW Hardware control
		1	SW Software control
0	ELPTMREN	Field to enable ELP Timer		RO	0
		Read 0	DIS Disable
		Read 1	EN Enable

:HOSTMCU_AON:CFGTMRWU

Address offset	0x0000 0014
Description	Timer Wake-up Configuration. Register to configure Timer wake up
Type	RW

Bits	Field Name	Description		Type	Reset
31	EN	Field to enable timer wake up Set 1 - Enable BCN threshold IRQ. Set 0 - Otherwise. Timer is kicked upon moving from ACTIVE to POWER DOWN.		RW	0
		0	DIS otherwise
		1	EN Enable BCN threshold IRQ
30:0	THR	Field to configure the Threshold of timer wake up Upon reaching this value wake up event is generated towards the WUC (if not masked in WICSENSE). Resolution slow clock cycles. value must be greater than 1		RW	0x0000 0000

:HOSTMCU_AON:TMRWUREQ

Address offset	0x0000 0018
Description	Timer Wake-up Request Clear. Register to configure timer wake up request
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior	RO	0x0000 0000
0	TMRWUREQ_WRCL	Field to clear timer wake up request. Set this bit to clear	WO	0

:HOSTMCU_AON:CFGWDT

Address offset	0x0000 001C
Description	Watch Dog Timer Configuration. Register to configure watchdog timer
Type	RW

Bits	Field Name	Description		Type	Reset
31	EN	Field to enable watchdog timer		RW	1
		0	DIS Magillem Info : Information not available in the IP-XACT file
		1	EN Magillem Info : Information not available in the IP-XACT file
30:8	THR	Field to configure watchdog timer threshold Upon reaching this value wake up event is generated towards the WUC (if not masked in WICSENSE). Resolution slow clock cycles (min val ~8ms). value must be greater than 1		RW	0x00 0EA6
7:0	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x00

:HOSTMCU_AON:WDTREQ

Address offset	0x0000 0020
Description	Watch Dog Timer Request Clear. Register to clear watchdog timer request
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior	RO	0x0000 0000
0	WDTREQ_WRCL	Field to clear watchdog timer request. Set this bet to clear	WO	0

:HOSTMCU_AON:GPWUAND

Address offset	0x0000 0028
Description	GPIO Wake-up AND IRQ Configuration. Field to configure GPIO wake up AND IRQ 0 to 31
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	BM0T31	Field to bit mask GPIO 0 to 31 select 0-31 GPIOs as wake up source.			RW	0xFFFF FFFF

:HOSTMCU_AON:GPWUOR

Address offset	0x0000 002C
Description	GPIO Wake-up OR IRQ Configuration. Field to configure GPIO wake up OR gate IRQ
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	BM0T31	Field to bit mask GPIO 0 to 31 select 0-31 GPIOs as wake up source.			RW	0xFFFF FFFF

:HOSTMCU_AON:GPWUAND_1

Address offset	0x0000 0030
Description	GPIO Wake-up AND IRQ Configuration. Field to configure GPIO wake up AND IRQ 32 to 44
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	RESERVED316042		RO	0x0 007F
12:0	BM32T44	Field to bit mask 32 to 44 select 32-44 GPIOs as wake up source.	RW	0x1FFF

:HOSTMCU_AON:GPWUOR_1

Address offset	0x0000 0034
Description	GPIO Wake-up OR IRQ Configuration. Field to configure GPIO wake up OR IRQ 32 to 44
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior	RO	0x0 007F
12:0	BM32T44	Field to bit mask 32 to 44 select 32-44 GPIOs as wake up source.	RW	0x1FFF

:HOSTMCU_AON:FCLKARM

Address offset	0x0000 0038
Description	Fast Clock From ARM Command
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior	RO	0x0000
15:0	FCLKARM	Command Latched counter value reflecting the number of fast clocks (host_clk) from rise of SLEEPDEEP indication until ELP WUC start power down sequence. This value should capture the uncertainty of 2-3 slow clocks of synchronization of ARM CMD	RO	0x0000

:HOSTMCU_AON:SLPTIMES

Address offset	0x0000 003C
Description	Sleep Time Slow Clock. Register for sleep time on slow clock
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	SLPTIMES_CLK_RDCL	Sleep time value from last ELP sleep entry (slow clock synced ARM CMD). Slow Clock - Reflects the number of slow clocks in ELP timer.			RO	0x0000 0000

:HOSTMCU_AON:SLPTIMEF

Address offset	0x0000 0040
Description	Sleep Time Fast Clock. Register for sleep time on fast clock
Type	RW

Bits	Field Name	Description	Type	Reset
31:11	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior	RO	0x00 0000
10:0	SLPTIMEF_CLK	Sleep time value from last ELP sleep entry (slow clock synced ARM CMD). Fast Clock - Reflects the number of fast clocks from last Slow clock rise until OCP Read. Note, fast counter value is latched upon OCP Read of SLPTIMES. Counts up t0 51 microsecond.	RO	0x000

:HOSTMCU_AON:WUREQ

Address offset	0x0000 004C
Description	Wake up Request Status
Type	RW

Bits	Field Name	Description		Type	Reset
31:18	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000
17:0	VAL	Field to show the event request Bit 0 : ELP TMR Wake up request Bit 1 : GPIO wake up src 0 Bit 2 : GPIO wake up src 1 Bit 3 : doorbell 0 Bit 4 : doorbell 1 Bit 5 : doorbell 2 Bit 6 : doorbell 3 Bit 7 : doorbell 4 Bit 8 : doorbell 5 Bit 9 : doorbell 6 Bit 10 : doorbell 7 Bit 11 : nab_host_irq Bit 12 : ble_rfc_gpo_8_irq Bit 13 : RTC Bit 14 : DebugSS Csyspwrupreq Bit 15 : DebugSS Force-active Bit 16 : secured_error_irq Bit 17 : core wdt irq Note: GPIO wakeup src 0 is AND of wakeup sources and GPIO wakup src 1 is OR of wakeup sources		RO	0x0 0000
		Read 0x0 0000	CLEAR No event request
		Read 0x0 0001	TMRREQ ELP timer wakeup request
		Read 0x0 0002	WUSRC0 AND of wakeup sources
		Read 0x0 0004	WUSRC1 OR of wakeup sources
		Read 0x0 0008	DRBL0 Doorbell 0
		Read 0x0 0010	DRBL1 Doorbell 1
		Read 0x0 0020	DRBL2 Doorbell 2
		Read 0x0 0040	DRBL3 Doorbell 3
		Read 0x0 0080	DRBL4 Doorbell 4
		Read 0x0 0100	DRBL5 Doorbell 5
		Read 0x0 0200	DRBL6 Doorbell 6
		Read 0x0 0400	DRBL7 Doorbell 7
		Read 0x0 0800	NAB NAB host irq
		Read 0x0 1000	BLERFCGPO BLE RFC GPO 9 irq
		Read 0x0 2000	RTC RTC
		Read 0x0 4000	DBGPWRUP Debugss Csyspwrupreq
		Read 0x0 8000	DBGFRCACT Debugss forecactive
		Read 0x1 0000	SECERR Secure error irq
		Read 0x2 0000	COREWDT Core WDT request

:HOSTMCU_AON:OREFCLK

Address offset	0x0000 0050
Description	OSPI Reference Clock. Field to select the OSPI reference clock
Type	RW

Bits	Field Name	Description		Type	Reset
31:1	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000 0009
0	SEL	SELECTOR '0' - default host clk div2 '1' host clk div 4		RW	0
		0	SEL_0 Host clock div2
		1	SEL_1 Host clock div4

:HOSTMCU_AON:WUC

Address offset	0x0000 005C
Description	Wake-up Control State. Register for Host wake up state
Type	RW

Bits	Field Name	Description		Type	Reset
31:3	RESERVED316042	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior		RO	0x0000 0000
2:0	STA	Field showing the host wake up state 3'b000 - PD_PWR_DN 3'b001 - SHARED_UP 3'b010 - PD_PWR_UP 3'b011 - ACTIVE 3'b100 - DEEPSLEEP		RO	0x4
		Read 0x0	RD_0 PD power down
		Read 0x1	RD_1 Shared domain up
		Read 0x2	RD_2 PD power up
		Read 0x3	RD_3 Active