CORE_AON

This section provides information on the CORE_AON Module Instance within this product. Each of the registers within the Module Instance is described separately below.

CORE AON REGISTERS

CORE_AON Registers Mapping Summary

:CORE_AON Common Register Mapping Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset
INIT	RW	32	0x0000 0000	0x0000 0004
WUCSKP	RW	32	0x0000 0000	0x0000 0008
CPUWAIT	RW	32	0x0000 0012	0x0000 0014
CRMBCTL	RW	32	0x0000 0000	0x0000 0018
CFGWUTP	RW	32	0x0000 0000	0x0000 001C
CFGWICSNS	RW	32	0x0000 0001	0x0000 0024
CFGTMRWU	RW	32	0x0000 0000	0x0000 002C
CFGWDT	RW	32	0x0000 0000	0x0000 0034
WUREQ	RW	32	0x0000 0000	0x0000 0038
CFGSHSLP	RW	32	0x0000 0000	0x0000 0040
FCLKARMCMD	RW	32	0x0000 0000	0x0000 0054
SLPTIMSL	RW	32	0x0000 0000	0x0000 0058
TMREN	RW	32	0x0000 0000	0x0000 005C
CATLSELOV	RW	32	0x0000 0000	0x0000 006C
SLPTIMFAST	RW	32	0x0000 0000	0x0000 0074
IOWUANDIRQ	RW	32	0x0000 0000	0x0000 009C
IOWUORIRQ	RW	32	0x0000 0000	0x0000 00A0
IOWUANDIRQ_1	RW	32	0x0000 0000	0x0000 00A4
IOWUORIRQ_1	RW	32	0x0000 0000	0x0000 00A8
TMRWUREQ	RW	32	0x0000 0000	0x0000 00AC
WDTREQ	RW	32	0x0000 0000	0x0000 00B0
FRCCR	RW	32	0x0000 0000	0x0000 00D8
CRICG	RW	32	0x0000 0000	0x0000 00DC
CRWUC	RW	32	0x0000 0004	0x0000 00E0
NABHIRQCFG	RW	32	0x0000 0000	0x0000 00E4
IOTP0	RW	32	0x0000 0000	0x0000 00E8
IOTP1	RW	32	0x0000 0000	0x0000 00EC
IOOENCFG0	RW	32	0x0000 0000	0x0000 00F8
IOOENCFG1	RW	32	0x0000 0000	0x0000 00FC

CORE_AON Instances Register Mapping Summary

CORE_AON Register Descriptions

:CORE_AON Common Register Descriptions

:CORE_AON:INIT

Address offset	0x0000 0004
Description	INIT
Type	RW

Bits	Field Name	Description	Type	Reset
31:7	Reserved	Reserved	RO	0x000 0000
6:4	TPDESCRF	TYPE DESCRF 0 - Descriptor FIFO memory (mem per bit) is initiated when getting out of reset (at power up or when back from sleep) 1 - Descriptor FIFO memory (mem per bit) is not initiated when getting out of reset (as it's held in retention) TPDESCRF[0] = disable INIT of link_table TPDESCRF[1] = disable INIT of queue_db TPDESCRF[2] = disable INIT of seq_num	RW	0x0
3:1	Reserved	Reserved	RO	0x0
0	DISMMU	DISABLE MMU 0 - MMU memories, VLUT and MBLR are initiated when getting out of reset (at power up or when back from sleep) 1 - MMU memories, VLUT and MBLR are not initiated when getting out of reset (as they're held in retention)	RW	0

:CORE_AON:WUCSKP

Address offset	0x0000 0008
Description	WUC SKIP
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0000
1	PDVLD	POWER DOMAIN VALID Enable skip precise duration for Power Domain if wakup event type is '0': '0' - don't skip '1' - skip	RW	0
0	PRCMVLD	PRCM VLD Enable skip precise duration for PRCM Shared UP if wakup event type is '0': '0' - don't skip '1' - skip	RW	0

:CORE_AON:CPUWAIT

Address offset	0x0000 0014
Description	CPU WAIT
Type	RW

Bits	Field Name	Description	Type	Reset
31:2	Reserved		RO	0x0000 0004
1	OVSEL	OVERRIDE SELECTOR override selector for using the MMR of CPU wait or the ELP FSM '1' - use the MMR mem_m3_cpu_wait '0' - use ELP FSM	RW	1
0	M3	M3 The CPUWAIT allows the boot sequence of the processor M3 to be delayed. This is useful in the case where the Teal processor is used in a SoC, and the program code has to be loaded into SRAM first (e.g. via DMA under the control of another processor). In this case, instead of hold the processor in reset, we can use CPUWAIT de-assertion to defer the start up sequence and allow the system to start after the program code has been successfully loaded into the program SRAM.	RW	0

:CORE_AON:CRMBCTL

Address offset	0x0000 0018
Description	CORE MEDIUM BUSY CONTROL Medium busy AON override option towards IOMUX
Type	RW

Bits	Field Name	Description	Type	Reset
31:9	Reserved	Reserved	RO	0x00 0000
8	OVVAL	OVERRIDE VALUE	RW	0
7:1	Reserved		RO	0x00
0	OVEN	OVERRIDE ENABLE	RW	0

:CORE_AON:CFGWUTP

Address offset	0x0000 001C
Description	CONFIG WAKE UP TYPE
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24:0	VAL	VALUE Set 0 - Slow Wake up (precise WU). Set 1 - Fast Wake up (MX device, assume system is already active when event is triggered). Bit 0 : tmr_wakeup_req Bit 1 : hif_wakeup_int Bit 2 : gpio_wakeup_src[0] Bit 3 : gpio_wakeup_src[1] Bit 4 : evt_mng_m3_irq0 Bit 5 : evt_mng_m3_irq1 Bit 6 : evt_mng_m3_irq2 Bit 7 : evt_mng_m3_irq3 Bit 8 : evt_mng_m3_irq4 Bit 9 : evt_mng_m3_irq5 Bit 10 : evt_mng_m3_irq6 Bit 11 : evt_mng_m3_irq7 Bit 12 : evt_mng_m3_irq8 Bit 13 : evt_mng_m3_irq9 Bit 14 : doorbell0_m2_irq Bit 15 : doorbell1_m2_irq Bit 16 : doorbell2_m2_irq Bit 17 : doorbell3_m2_irq Bit 18 : doorbell4_m2_irq Bit 19 : doorbell5_m2_irq Bit 20 : doorbell6_m2_irq Bit 21 : doorbell7_m2_irq Bit 22 : mem_ns_sw_interrupt_to_cm3 Bit 23 : mem_sec_sw_interrupt_to_cm3 Bit 24 : debugss_core_forceactive	RW	0x000 0000

:CORE_AON:CFGWICSNS

Address offset	0x0000 0024
Description	CONFIG WICSENSE
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24:0	VAL	VALUE Set 1 - Enable wakeup source. Set 0 - Disable wakeup source. Bit 0 : tmr_wakeup_req Bit 1 : hif_wakeup_int Bit 2 : gpio_wakeup_src[0] Bit 3 : gpio_wakeup_src[1] Bit 4 : evt_mng_m3_irq0 Bit 5 : evt_mng_m3_irq1 Bit 6 : evt_mng_m3_irq2 Bit 7 : evt_mng_m3_irq3 Bit 8 : evt_mng_m3_irq4 Bit 9 : evt_mng_m3_irq5 Bit 10 : evt_mng_m3_irq6 Bit 11 : evt_mng_m3_irq7 Bit 12 : evt_mng_m3_irq8 Bit 13 : evt_mng_m3_irq9 Bit 14 : doorbell0_m2_irq Bit 15 : doorbell1_m2_irq Bit 16 : doorbell2_m2_irq Bit 17 : doorbell3_m2_irq Bit 18 : doorbell4_m2_irq Bit 19 : doorbell5_m2_irq Bit 20 : doorbell6_m2_irq Bit 21 : doorbell7_m2_irq Bit 22 : mem_ns_sw_interrupt_to_cm3 Bit 23 : mem_sec_sw_interrupt_to_cm3 Bit 24 : debugss_core_forceactive	RW	0x000 0001

:CORE_AON:CFGTMRWU

Address offset	0x0000 002C
Description	CONFIG TIMER WAKEUP
Type	RW

Bits	Field Name	Description	Type	Reset
31	EN	ENABLE Set 1 - Enable BCN threshold IRQ. Set 0 - Otherwise. Timer is kicked upon moving from ACTIVE to POWER DOWN.	RW	0
30:0	THR	THRESHOLD Upon reaching this value wakeup event is generated towards the WUC (if not masked in WICSENSE). Resolution slow clock cycles. value must be greater than 1	RW	0x0000 0000

:CORE_AON:CFGWDT

Address offset	0x0000 0034
Description	CONFIG WATCHDOG TIMER
Type	RW

Bits	Field Name	Description	Type	Reset
31	EN	ENABLE Set 1 - Enable WDT. Set 0 - Disable WDT.	RW	0
30:8	THR	THRESHOLD Upon reaching this value wakeup event is generated towards the WUC (if not masked in WICSENSE). Resolution slow clock cycles (min val ~8ms). value must be greater than 1	RW	0x00 0000
7:0	Reserved		RO	0x00

:CORE_AON:WUREQ

Address offset	0x0000 0038
Description	WAKEUP REQUEST Bit 0 : wdt_wakeup_req
Type	RW

Bits	Field Name	Description	Type	Reset
31:25	Reserved		RO	0x00
24:0	EVTVAL	EVENT VALUE Bit 0 : tmr_wakeup_req Bit 1 : hif_wakeup_int Bit 2 : gpio_wakeup_src[0] Bit 3 : gpio_wakeup_src[1] Bit 4 : evt_mng_m3_irq0 Bit 5 : evt_mng_m3_irq1 Bit 6 : evt_mng_m3_irq2 Bit 7 : evt_mng_m3_irq3 Bit 8 : evt_mng_m3_irq4 Bit 9 : evt_mng_m3_irq5 Bit 10 : evt_mng_m3_irq6 Bit 11 : evt_mng_m3_irq7 Bit 12 : evt_mng_m3_irq8 Bit 13 : evt_mng_m3_irq9 Bit 14 : doorbell0_m2_irq Bit 15 : doorbell1_m2_irq Bit 16 : doorbell2_m2_irq Bit 17 : doorbell3_m2_irq Bit 18 : doorbell4_m2_irq Bit 19 : doorbell5_m2_irq Bit 20 : doorbell6_m2_irq Bit 21 : doorbell7_m2_irq Bit 22 : mem_ns_sw_interrupt_to_cm3 Bit 23 : mem_sec_sw_interrupt_to_cm3 Bit 24 : debugss_core_forceactive	RO	0x000 0000

:CORE_AON:CFGSHSLP

Address offset	0x0000 0040
Description	CONFIG SHORT SLEEP Hold the device clock request high, to save fref setting time during power up.
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	CLKREQ	CLOCK REQUEST	RW	0

:CORE_AON:FCLKARMCMD

Address offset	0x0000 0054
Description	FAST CLOCK FROM ARM CMD Latched counter value reflecting the number of fast clocks (clk_core_clk) from rise of SLEEPDEEP indication until ELP WUC start power down sequence. This value should capture the uncertainty of 2-3 slow clocks of synchronization of ARM CMD.
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	Reserved	Reserved	RO	0x0000
15:0	FCLKARMCMD	VALUE	RO	0x0000

:CORE_AON:SLPTIMSL

Address offset	0x0000 0058
Description	SLEEP TIME SLOW Sleep time value from last ELP sleep entry (slow clock synced ARM CMD). Slow Clock - Reflects the number of slow clocks in ELP timer.
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	SLPTIMSL_CLK_RDCL	CLOCK read clear			RO	0x0000 0000

:CORE_AON:TMREN

Address offset	0x0000 005C
Description	TIMER ENABLE 1 - ELP Timer is running. 0 - Otherwise.
Type	RW

Bits	Field Name	Description	Type	Reset
31:17	Reserved	Reserved	RO	0x0000
16	TMRLD	TIMER LOAD setting this bit will load the value 2 to the timer	WO	0
15:4	Reserved	Reserved	RO	0x000
3	TMRRST	TIMER RESET setting this bit will stop the timer	RW	0
2	TMRSET	TIMER SET starts the timer	RW	0
1	TMRSWCTL	TIMER SOFTWARE CONTROL '0' - HW CTRL '1' - SW CTRL.	RW	0
0	TMREN	VALUE	RO	0

:CORE_AON:CATLSELOV

Address offset	0x0000 006C
Description	COEX ANTENNA CONTROL SELECT OVERRIDE
Type	RW

Bits	Field Name	Description	Type	Reset
31:12	Reserved	Reserved	RO	0x0 0000
11:8	MEM_CATLSELOV_VAL	VALUE	RW	0x0
7:1	Reserved		RO	0x00
0	MEM_CATLSELOV_EN	ENABLE	RW	0

:CORE_AON:SLPTIMFAST

Address offset	0x0000 0074
Description	SLEEP TIME FAST Sleep time value from last ELP sleep entry (slow clock synced ARM CMD). Fast Clock - Reflects the number of fast clocks from last Slow clock rise until OCP Read. Note, fast counter value is latched upon OCP Read of SLPTIMSL. Counts up t0 51 microsecond.
Type	RW

Bits	Field Name	Description	Type	Reset
31:11	Reserved		RO	0x00 0000
10:0	SLPTIMFAST_CLK	CLOCK	RO	0x000

:CORE_AON:IOWUANDIRQ

Address offset	0x0000 009C
Description	GPIO WAKEUP AND LOGIC IRQ
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	0T31BM	0 TO 31 BITMASK select 0-31 GPIOs as wakeup source.			RW	0x0000 0000

:CORE_AON:IOWUORIRQ

Address offset	0x0000 00A0
Description	GPIO WAKEUP OR LOGIC IRQ
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	0T31BM	0 TO 31 BITMASK select 0-31 GPIOs as wakeup source.			RW	0x0000 0000

:CORE_AON:IOWUANDIRQ_1

Address offset	0x0000 00A4
Description	GPIO WAKEUP AND LOGIC IRQ 1
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	32T44BM	32 TO 44 BITMASK select 32-44 GPIOs as wakeup source.	RW	0x0000

:CORE_AON:IOWUORIRQ_1

Address offset	0x0000 00A8
Description	GPIO WAKEUP OR LOGIC IRQ 1
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved		RO	0x0 0000
12:0	32T44BM	32 TO 44 BITMASK select 32-44 GPIOs as wakeup source.	RW	0x0000

:CORE_AON:TMRWUREQ

Address offset	0x0000 00AC
Description	TIMER WAKEUP REQUEST
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	TMRWUREQ_WRCL	CLEAR write clear	WO	0

:CORE_AON:WDTREQ

Address offset	0x0000 00B0
Description	WATCHDOG TIMER REQUEST
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	WDTREQ_WRCL	CLEAR write clear	WO	0

:CORE_AON:FRCCR

Address offset	0x0000 00D8
Description	FORCE CORE
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved		RO	0x0000 0000
0	MEM_FRCCR	ON host to write here '1' to keep the core awake	RW	0

:CORE_AON:CRICG

Address offset	0x0000 00DC
Description	CORE ICG
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved	Reserved	RO	0x0 0000
12	MEM_CRICG_OVR_VAL	OVERRIDE VALUE once override en is '1', the ICG will work according to the below- '0' - CORE ICG disable '1' - CORE ICG enable	RW	0
11	MEM_CRICG_OVR_EN	OVERRIDE ENABLE use Override value for core ICG- '0' - don't use override '1' - use override	RW	0
10:8	MEM_CRICG_SET_THRESH	SET THRESHOLD Delay Counter value to EN CORE clk- The time we will wait from the moment M3 CLK Enabled	RW	0x0
7:3	Reserved	Reserved	RO	0x00
2:0	MEM_CRICG_CLR_THRESH	CLEAR THRESHOLD Delay Counter value to gate CORE clk- The time we will wait from the moment M3 CLK stopped	RW	0x0

:CORE_AON:CRWUC

Address offset	0x0000 00E0
Description	CORE WUC
Type	RW

Bits	Field Name	Description	Type	Reset
31:3	Reserved	Reserved	RO	0x0000 0000
2:0	STA	STATE 3'b000 - PD_PWR_DN 3'b001 - SHARED_UP 3'b010 - PD_PWR_UP 3'b011 - ACTIVE 3'b100 - DEEPSLEEP	RO	0x4

:CORE_AON:NABHIRQCFG

Address offset	0x0000 00E4
Description	NAB HOST IRQ CONFIG
Type	RW

Bits	Field Name	Description	Type	Reset
31:1	Reserved	Reserved	RO	0x0000 0000
0	POL	POLARITY "1" for negative polarity "0" for positive polarity (GuyS: in order to preserve this at sleep (retention) - ISO latch needs to be implemented. Alternatively, move this polarity cfg bit to upper H/W layer above Nab)	RW	0

:CORE_AON:IOTP0

Address offset	0x0000 00E8
Description	GPIO TO PAD 0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	VALUE SW value to be reflected on GPIO to pad.			RW	0x0000 0000

:CORE_AON:IOTP1

Address offset	0x0000 00EC
Description	GPIO TO PAD 1
Type	RW

Bits	Field Name	Description	Type	Reset
31:24	SRC	SOURCE Set 1 - Used HW source. Set 0 - Used SW source. bit[0] - GPIO3 bit[1] - GPIO4 bit[2] - GPIO5 bit[3] - GPIO6 bit[4] - GPIO26 bit[5] - GPIO27 bit[6] - GPIO28 bit[7] - GPIO29	RW	0x00
23:13	Reserved	Reserved	RO	0x000
12:0	VAL	VALUE SW value to be reflected on GPIO to pad.	RW	0x0000

:CORE_AON:IOOENCFG0

Address offset	0x0000 00F8
Description	GPIO OUT ENABLE CONFIG 0
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	VAL	VALUE Set 0 - Output. Set 1 - Input.			RW	0x0000 0000

:CORE_AON:IOOENCFG1

Address offset	0x0000 00FC
Description	GPIO OUT ENABLE CONFIG 1
Type	RW

Bits	Field Name	Description	Type	Reset
31:13	Reserved	Reserved	RO	0x0 0000
12:0	VAL	VALUE Set 0 - Output. Set 1 - Input.	RW	0x0000