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CC35xxDriverLibrary
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Go to the source code of this file.
| #define WSOC_OCLA_O_EVTMOD 0x00000000U |
| #define WSOC_OCLA_O_AMASK 0x00000004U |
| #define WSOC_OCLA_O_ACOMP 0x00000008U |
| #define WSOC_OCLA_O_BMASK 0x0000000CU |
| #define WSOC_OCLA_O_BCOMP 0x00000010U |
| #define WSOC_OCLA_O_CMASK 0x00000014U |
| #define WSOC_OCLA_O_CCOMP 0x00000018U |
| #define WSOC_OCLA_O_FMASK 0x0000002CU |
| #define WSOC_OCLA_O_FCOMP 0x00000030U |
| #define WSOC_OCLA_O_SUBTRIGX 0x00000034U |
| #define WSOC_OCLA_O_SUBTRIGY 0x00000038U |
| #define WSOC_OCLA_O_SUBTRIGZ 0x0000003CU |
| #define WSOC_OCLA_O_CLKCFG 0x00000040U |
| #define WSOC_OCLA_O_TRIGS 0x00000044U |
| #define WSOC_OCLA_O_TIME 0x00000048U |
| #define WSOC_OCLA_O_MODE 0x0000004CU |
| #define WSOC_OCLA_O_MEMSIZE 0x00000050U |
| #define WSOC_OCLA_O_MEMSIZEEVT 0x00000054U |
| #define WSOC_OCLA_O_MEMSWINF 0x00000058U |
| #define WSOC_OCLA_O_STATESTA 0x0000005CU |
| #define WSOC_OCLA_O_RDDBG0 0x00000060U |
| #define WSOC_OCLA_O_RDDBG1 0x00000064U |
| #define WSOC_OCLA_O_RDMAXTIME 0x0000006CU |
| #define WSOC_OCLA_O_MEMCTL 0x00000070U |
| #define WSOC_OCLA_O_INJECTCTL 0x00000074U |
| #define WSOC_OCLA_O_PORTCFG0 0x00000078U |
| #define WSOC_OCLA_O_PORTCFG1 0x0000007CU |
| #define WSOC_OCLA_O_PORTCFG2 0x00000080U |
| #define WSOC_OCLA_O_PORTCFG3 0x00000084U |
| #define WSOC_OCLA_O_PORTCFG4 0x00000088U |
| #define WSOC_OCLA_O_TPSEL 0x0000008CU |
| #define WSOC_OCLA_O_PORTSEL 0x00000090U |
| #define WSOC_OCLA_O_OUTSEL 0x00000094U |
| #define WSOC_OCLA_O_OUTVAL 0x00000098U |
| #define WSOC_OCLA_O_OUTVALSET 0x0000009CU |
| #define WSOC_OCLA_O_OUTVALCLR 0x000000A0U |
| #define WSOC_OCLA_O_OUTVALTGL 0x000000A4U |
| #define WSOC_OCLA_O_OUTVALPLS 0x000000A8U |
| #define WSOC_OCLA_O_TFSONTRG 0x000000B0U |
| #define WSOC_OCLA_EVTMOD_ASRC_W 3U |
| #define WSOC_OCLA_EVTMOD_ASRC_M 0x00000007U |
| #define WSOC_OCLA_EVTMOD_ASRC_S 0U |
| #define WSOC_OCLA_EVTMOD_AMOD 0x00000008U |
| #define WSOC_OCLA_EVTMOD_AMOD_M 0x00000008U |
| #define WSOC_OCLA_EVTMOD_AMOD_S 3U |
| #define WSOC_OCLA_EVTMOD_BSRC_W 3U |
| #define WSOC_OCLA_EVTMOD_BSRC_M 0x00000070U |
| #define WSOC_OCLA_EVTMOD_BSRC_S 4U |
| #define WSOC_OCLA_EVTMOD_BMOD 0x00000080U |
| #define WSOC_OCLA_EVTMOD_BMOD_M 0x00000080U |
| #define WSOC_OCLA_EVTMOD_BMOD_S 7U |
| #define WSOC_OCLA_EVTMOD_CSRC_W 3U |
| #define WSOC_OCLA_EVTMOD_CSRC_M 0x00000700U |
| #define WSOC_OCLA_EVTMOD_CSRC_S 8U |
| #define WSOC_OCLA_EVTMOD_CMOD 0x00000800U |
| #define WSOC_OCLA_EVTMOD_CMOD_M 0x00000800U |
| #define WSOC_OCLA_EVTMOD_CMOD_S 11U |
| #define WSOC_OCLA_EVTMOD_DSRC_W 3U |
| #define WSOC_OCLA_EVTMOD_DSRC_M 0x00007000U |
| #define WSOC_OCLA_EVTMOD_DSRC_S 12U |
| #define WSOC_OCLA_EVTMOD_DMOD 0x00008000U |
| #define WSOC_OCLA_EVTMOD_DMOD_M 0x00008000U |
| #define WSOC_OCLA_EVTMOD_DMOD_S 15U |
| #define WSOC_OCLA_EVTMOD_ESRC_W 3U |
| #define WSOC_OCLA_EVTMOD_ESRC_M 0x00070000U |
| #define WSOC_OCLA_EVTMOD_ESRC_S 16U |
| #define WSOC_OCLA_EVTMOD_FSRC_W 3U |
| #define WSOC_OCLA_EVTMOD_FSRC_M 0x00700000U |
| #define WSOC_OCLA_EVTMOD_FSRC_S 20U |
| #define WSOC_OCLA_AMASK_MASK_W 32U |
| #define WSOC_OCLA_AMASK_MASK_M 0xFFFFFFFFU |
| #define WSOC_OCLA_AMASK_MASK_S 0U |
| #define WSOC_OCLA_ACOMP_COMP_W 32U |
| #define WSOC_OCLA_ACOMP_COMP_M 0xFFFFFFFFU |
| #define WSOC_OCLA_ACOMP_COMP_S 0U |
| #define WSOC_OCLA_BMASK_MASK_W 32U |
| #define WSOC_OCLA_BMASK_MASK_M 0xFFFFFFFFU |
| #define WSOC_OCLA_BMASK_MASK_S 0U |
| #define WSOC_OCLA_BCOMP_COMP_W 32U |
| #define WSOC_OCLA_BCOMP_COMP_M 0xFFFFFFFFU |
| #define WSOC_OCLA_BCOMP_COMP_S 0U |
| #define WSOC_OCLA_CMASK_MASK_W 32U |
| #define WSOC_OCLA_CMASK_MASK_M 0xFFFFFFFFU |
| #define WSOC_OCLA_CMASK_MASK_S 0U |
| #define WSOC_OCLA_CCOMP_COMP_W 32U |
| #define WSOC_OCLA_CCOMP_COMP_M 0xFFFFFFFFU |
| #define WSOC_OCLA_CCOMP_COMP_S 0U |
| #define WSOC_OCLA_FMASK_MASK_W 32U |
| #define WSOC_OCLA_FMASK_MASK_M 0xFFFFFFFFU |
| #define WSOC_OCLA_FMASK_MASK_S 0U |
| #define WSOC_OCLA_FCOMP_COMP_W 32U |
| #define WSOC_OCLA_FCOMP_COMP_M 0xFFFFFFFFU |
| #define WSOC_OCLA_FCOMP_COMP_S 0U |
| #define WSOC_OCLA_SUBTRIGX_AND_W 6U |
| #define WSOC_OCLA_SUBTRIGX_AND_M 0x0000003FU |
| #define WSOC_OCLA_SUBTRIGX_AND_S 0U |
| #define WSOC_OCLA_SUBTRIGX_NOT_W 6U |
| #define WSOC_OCLA_SUBTRIGX_NOT_M 0x00003F00U |
| #define WSOC_OCLA_SUBTRIGX_NOT_S 8U |
| #define WSOC_OCLA_SUBTRIGY_AND_W 6U |
| #define WSOC_OCLA_SUBTRIGY_AND_M 0x0000003FU |
| #define WSOC_OCLA_SUBTRIGY_AND_S 0U |
| #define WSOC_OCLA_SUBTRIGY_NOT_W 6U |
| #define WSOC_OCLA_SUBTRIGY_NOT_M 0x00003F00U |
| #define WSOC_OCLA_SUBTRIGY_NOT_S 8U |
| #define WSOC_OCLA_SUBTRIGZ_AND_W 6U |
| #define WSOC_OCLA_SUBTRIGZ_AND_M 0x0000003FU |
| #define WSOC_OCLA_SUBTRIGZ_AND_S 0U |
| #define WSOC_OCLA_SUBTRIGZ_NOT_W 6U |
| #define WSOC_OCLA_SUBTRIGZ_NOT_M 0x00003F00U |
| #define WSOC_OCLA_SUBTRIGZ_NOT_S 8U |
| #define WSOC_OCLA_CLKCFG_MOD_W 2U |
| #define WSOC_OCLA_CLKCFG_MOD_M 0x00000003U |
| #define WSOC_OCLA_CLKCFG_MOD_S 0U |
| #define WSOC_OCLA_TRIGS_AND_W 4U |
| #define WSOC_OCLA_TRIGS_AND_M 0x0000000FU |
| #define WSOC_OCLA_TRIGS_AND_S 0U |
| #define WSOC_OCLA_TRIGS_INV_W 4U |
| #define WSOC_OCLA_TRIGS_INV_M 0x000000F0U |
| #define WSOC_OCLA_TRIGS_INV_S 4U |
| #define WSOC_OCLA_TRIGS_TAND_W 4U |
| #define WSOC_OCLA_TRIGS_TAND_M 0x00000F00U |
| #define WSOC_OCLA_TRIGS_TAND_S 8U |
| #define WSOC_OCLA_TRIGS_TINV_W 4U |
| #define WSOC_OCLA_TRIGS_TINV_M 0x0000F000U |
| #define WSOC_OCLA_TRIGS_TINV_S 12U |
| #define WSOC_OCLA_TIME_TIME_W 26U |
| #define WSOC_OCLA_TIME_TIME_M 0x03FFFFFFU |
| #define WSOC_OCLA_TIME_TIME_S 0U |
| #define WSOC_OCLA_MODE_IQMOD_W 5U |
| #define WSOC_OCLA_MODE_IQMOD_M 0x0000001FU |
| #define WSOC_OCLA_MODE_IQMOD_S 0U |
| #define WSOC_OCLA_MODE_EN 0x00000020U |
| #define WSOC_OCLA_MODE_EN_M 0x00000020U |
| #define WSOC_OCLA_MODE_EN_S 5U |
| #define WSOC_OCLA_MODE_DATAMOD_W 2U |
| #define WSOC_OCLA_MODE_DATAMOD_M 0x00000300U |
| #define WSOC_OCLA_MODE_DATAMOD_S 8U |
| #define WSOC_OCLA_MODE_PARAMMOD_W 3U |
| #define WSOC_OCLA_MODE_PARAMMOD_M 0x00001C00U |
| #define WSOC_OCLA_MODE_PARAMMOD_S 10U |
| #define WSOC_OCLA_MODE_SWTCHIGH 0x00004000U |
| #define WSOC_OCLA_MODE_SWTCHIGH_M 0x00004000U |
| #define WSOC_OCLA_MODE_SWTCHIGH_S 14U |
| #define WSOC_OCLA_MODE_SWTCIQDIN 0x00008000U |
| #define WSOC_OCLA_MODE_SWTCIQDIN_M 0x00008000U |
| #define WSOC_OCLA_MODE_SWTCIQDIN_S 15U |
| #define WSOC_OCLA_MODE_D2SAVE_W 2U |
| #define WSOC_OCLA_MODE_D2SAVE_M 0x00030000U |
| #define WSOC_OCLA_MODE_D2SAVE_S 16U |
| #define WSOC_OCLA_MODE_ADDRSW2D 0x00400000U |
| #define WSOC_OCLA_MODE_ADDRSW2D_M 0x00400000U |
| #define WSOC_OCLA_MODE_ADDRSW2D_S 22U |
| #define WSOC_OCLA_MODE_MAXMIN 0x00800000U |
| #define WSOC_OCLA_MODE_MAXMIN_M 0x00800000U |
| #define WSOC_OCLA_MODE_MAXMIN_S 23U |
| #define WSOC_OCLA_MEMSIZE_SIZE_W 8U |
| #define WSOC_OCLA_MEMSIZE_SIZE_M 0x000000FFU |
| #define WSOC_OCLA_MEMSIZE_SIZE_S 0U |
| #define WSOC_OCLA_MEMSIZEEVT_SIZE_W 18U |
| #define WSOC_OCLA_MEMSIZEEVT_SIZE_M 0x0003FFFFU |
| #define WSOC_OCLA_MEMSIZEEVT_SIZE_S 0U |
| #define WSOC_OCLA_MEMSWINF_SWINFO_W 16U |
| #define WSOC_OCLA_MEMSWINF_SWINFO_M 0x0000FFFFU |
| #define WSOC_OCLA_MEMSWINF_SWINFO_S 0U |
| #define WSOC_OCLA_MEMSWINF_EN 0x00010000U |
| #define WSOC_OCLA_MEMSWINF_EN_M 0x00010000U |
| #define WSOC_OCLA_MEMSWINF_EN_S 16U |
| #define WSOC_OCLA_MEMSWINF_TRIG 0x00020000U |
| #define WSOC_OCLA_MEMSWINF_TRIG_M 0x00020000U |
| #define WSOC_OCLA_MEMSWINF_TRIG_S 17U |
| #define WSOC_OCLA_MEMSWINF_SAMP 0x00040000U |
| #define WSOC_OCLA_MEMSWINF_SAMP_M 0x00040000U |
| #define WSOC_OCLA_MEMSWINF_SAMP_S 18U |
| #define WSOC_OCLA_STATESTA_INTRS_W 3U |
| #define WSOC_OCLA_STATESTA_INTRS_M 0x00000007U |
| #define WSOC_OCLA_STATESTA_INTRS_S 0U |
| #define WSOC_OCLA_STATESTA_FIRSTFILL 0x00000008U |
| #define WSOC_OCLA_STATESTA_FIRSTFILL_M 0x00000008U |
| #define WSOC_OCLA_STATESTA_FIRSTFILL_S 3U |
| #define WSOC_OCLA_STATESTA_DATEVT_W 4U |
| #define WSOC_OCLA_STATESTA_DATEVT_M 0x000000F0U |
| #define WSOC_OCLA_STATESTA_DATEVT_S 4U |
| #define WSOC_OCLA_STATESTA_EVTPTR_W 18U |
| #define WSOC_OCLA_STATESTA_EVTPTR_M 0x03FFFF00U |
| #define WSOC_OCLA_STATESTA_EVTPTR_S 8U |
| #define WSOC_OCLA_STATESTA_STATE_W 2U |
| #define WSOC_OCLA_STATESTA_STATE_M 0x0C000000U |
| #define WSOC_OCLA_STATESTA_STATE_S 26U |
| #define WSOC_OCLA_RDDBG0_31TO0_W 32U |
| #define WSOC_OCLA_RDDBG0_31TO0_M 0xFFFFFFFFU |
| #define WSOC_OCLA_RDDBG0_31TO0_S 0U |
| #define WSOC_OCLA_RDDBG1_63TO32_W 32U |
| #define WSOC_OCLA_RDDBG1_63TO32_M 0xFFFFFFFFU |
| #define WSOC_OCLA_RDDBG1_63TO32_S 0U |
| #define WSOC_OCLA_RDMAXTIME_MAXTIME_W 26U |
| #define WSOC_OCLA_RDMAXTIME_MAXTIME_M 0x03FFFFFFU |
| #define WSOC_OCLA_RDMAXTIME_MAXTIME_S 0U |
| #define WSOC_OCLA_MEMCTL_STARTADDR_W 8U |
| #define WSOC_OCLA_MEMCTL_STARTADDR_M 0x000000FFU |
| #define WSOC_OCLA_MEMCTL_STARTADDR_S 0U |
| #define WSOC_OCLA_MEMCTL_SAMPRATE_W 5U |
| #define WSOC_OCLA_MEMCTL_SAMPRATE_M 0x00001F00U |
| #define WSOC_OCLA_MEMCTL_SAMPRATE_S 8U |
| #define WSOC_OCLA_INJECTCTL_START 0x00000001U |
| #define WSOC_OCLA_INJECTCTL_START_M 0x00000001U |
| #define WSOC_OCLA_INJECTCTL_START_S 0U |
| #define WSOC_OCLA_INJECTCTL_STOP 0x00000002U |
| #define WSOC_OCLA_INJECTCTL_STOP_M 0x00000002U |
| #define WSOC_OCLA_INJECTCTL_STOP_S 1U |
| #define WSOC_OCLA_INJECTCTL_MODE 0x00010000U |
| #define WSOC_OCLA_INJECTCTL_MODE_M 0x00010000U |
| #define WSOC_OCLA_INJECTCTL_MODE_S 16U |
| #define WSOC_OCLA_PORTCFG0_BIT0SEL_W 32U |
| #define WSOC_OCLA_PORTCFG0_BIT0SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_PORTCFG0_BIT0SEL_S 0U |
| #define WSOC_OCLA_PORTCFG1_BIT1SEL_W 32U |
| #define WSOC_OCLA_PORTCFG1_BIT1SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_PORTCFG1_BIT1SEL_S 0U |
| #define WSOC_OCLA_PORTCFG2_BIT2SEL_W 32U |
| #define WSOC_OCLA_PORTCFG2_BIT2SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_PORTCFG2_BIT2SEL_S 0U |
| #define WSOC_OCLA_PORTCFG3_BIT3SEL_W 32U |
| #define WSOC_OCLA_PORTCFG3_BIT3SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_PORTCFG3_BIT3SEL_S 0U |
| #define WSOC_OCLA_PORTCFG4_BIT4SEL_W 32U |
| #define WSOC_OCLA_PORTCFG4_BIT4SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_PORTCFG4_BIT4SEL_S 0U |
| #define WSOC_OCLA_TPSEL_SEL_W 32U |
| #define WSOC_OCLA_TPSEL_SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_TPSEL_SEL_S 0U |
| #define WSOC_OCLA_PORTSEL_TP1SEL_W 3U |
| #define WSOC_OCLA_PORTSEL_TP1SEL_M 0x00000007U |
| #define WSOC_OCLA_PORTSEL_TP1SEL_S 0U |
| #define WSOC_OCLA_PORTSEL_TP2SEL_W 3U |
| #define WSOC_OCLA_PORTSEL_TP2SEL_M 0x00000700U |
| #define WSOC_OCLA_PORTSEL_TP2SEL_S 8U |
| #define WSOC_OCLA_OUTSEL_SEL_W 32U |
| #define WSOC_OCLA_OUTSEL_SEL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_OUTSEL_SEL_S 0U |
| #define WSOC_OCLA_OUTVAL_VAL_W 32U |
| #define WSOC_OCLA_OUTVAL_VAL_M 0xFFFFFFFFU |
| #define WSOC_OCLA_OUTVAL_VAL_S 0U |
| #define WSOC_OCLA_OUTVALSET_SET_W 32U |
| #define WSOC_OCLA_OUTVALSET_SET_M 0xFFFFFFFFU |
| #define WSOC_OCLA_OUTVALSET_SET_S 0U |
| #define WSOC_OCLA_OUTVALCLR_CLR_W 32U |
| #define WSOC_OCLA_OUTVALCLR_CLR_M 0xFFFFFFFFU |
| #define WSOC_OCLA_OUTVALCLR_CLR_S 0U |
| #define WSOC_OCLA_OUTVALTGL_TOGGLE_W 32U |
| #define WSOC_OCLA_OUTVALTGL_TOGGLE_M 0xFFFFFFFFU |
| #define WSOC_OCLA_OUTVALTGL_TOGGLE_S 0U |
| #define WSOC_OCLA_OUTVALPLS_PULSE_W 32U |
| #define WSOC_OCLA_OUTVALPLS_PULSE_M 0xFFFFFFFFU |
| #define WSOC_OCLA_OUTVALPLS_PULSE_S 0U |
| #define WSOC_OCLA_TFSONTRG_TIMESTAMP_W 32U |
| #define WSOC_OCLA_TFSONTRG_TIMESTAMP_M 0xFFFFFFFFU |
| #define WSOC_OCLA_TFSONTRG_TIMESTAMP_S 0U |