CC35xxDriverLibrary
hw_spi.h
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1 /******************************************************************************
2 * Filename: hw_spi.h
3 *
4 * Description: Defines and prototypes for the SPI peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
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35 ******************************************************************************/
36 #ifndef __HW_SPI_H__
37 #define __HW_SPI_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the SPI component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Description Register
45 #define SPI_O_DESC 0x00000000U
46 
47 //Interrupt mask
48 #define SPI_O_IMASK 0x00000044U
49 
50 //Raw interrupt status
51 #define SPI_O_RIS 0x00000048U
52 
53 //Masked interrupt status
54 #define SPI_O_MIS 0x0000004CU
55 
56 //Interrupt set register
57 #define SPI_O_ISET 0x00000050U
58 
59 //Interrupt clear register
60 #define SPI_O_ICLR 0x00000054U
61 
62 //Interrupt mask set register
63 #define SPI_O_IMSET 0x00000058U
64 
65 //Interrupt mask clear register
66 #define SPI_O_IMCLR 0x0000005CU
67 
68 //Emulation control register
69 #define SPI_O_EMU 0x00000060U
70 
71 //SPI control register 0
72 #define SPI_O_CTL0 0x00000100U
73 
74 //SPI control register 1
75 #define SPI_O_CTL1 0x00000104U
76 
77 //Clock configuration register 0
78 #define SPI_O_CLKCFG0 0x00000108U
79 
80 //Clock configuration register 1
81 #define SPI_O_CLKCFG1 0x0000010CU
82 
83 //Interrupt FIFO level select register
84 #define SPI_O_IFLS 0x00000110U
85 
86 //DMA Control Register
87 #define SPI_O_DMACR 0x00000114U
88 
89 //Receive CRC register
90 #define SPI_O_RXCRC 0x00000118U
91 
92 //Transmit CRC register
93 #define SPI_O_TXCRC 0x0000011CU
94 
95 //Header update reigster for 32 bits of header data
96 #define SPI_O_TXFHDR32 0x00000120U
97 
98 //Header update reigster for 24 bits of header data
99 #define SPI_O_TXFHDR24 0x00000124U
100 
101 //Header update reigster for 16 bits of data
102 #define SPI_O_TXFHDR16 0x00000128U
103 
104 //Header update reigster for 8 bits of header data
105 #define SPI_O_TXFHDR8 0x0000012CU
106 
107 //Atomic Header control register
108 #define SPI_O_TXFHDRC 0x00000130U
109 
110 //RXDATA Register
111 #define SPI_O_RXDATA 0x00000140U
112 
113 //TXDATA Register
114 #define SPI_O_TXDATA 0x00000150U
115 
116 //Status Register
117 #define SPI_O_STA 0x00000160U
118 
119 //Clock Enable Register
120 #define SPI_O_CLKCFG 0x00001000U
121 
122 
123 
124 /*-----------------------------------REGISTER------------------------------------
125  Register name: DESC
126  Offset name: SPI_O_DESC
127  Relative address: 0x0
128  Description: Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
129  Default Value: 0x00000000
130 
131  Field: MINREV
132  From..to bits: 0...3
133  DefaultValue: 0x0
134  Access type: read-only
135  Description: Minor revision of IP (0-15).
136 
137 */
138 #define SPI_DESC_MINREV_W 4U
139 #define SPI_DESC_MINREV_M 0x0000000FU
140 #define SPI_DESC_MINREV_S 0U
141 /*
142 
143  Field: MAJREV
144  From..to bits: 4...7
145  DefaultValue: 0x0
146  Access type: read-only
147  Description: Major revision of IP (0-15).
148 
149 */
150 #define SPI_DESC_MAJREV_W 4U
151 #define SPI_DESC_MAJREV_M 0x000000F0U
152 #define SPI_DESC_MAJREV_S 4U
153 /*
154 
155  Field: INSTIDX
156  From..to bits: 8...11
157  DefaultValue: 0x0
158  Access type: read-only
159  Description: IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
160 
161 */
162 #define SPI_DESC_INSTIDX_W 4U
163 #define SPI_DESC_INSTIDX_M 0x00000F00U
164 #define SPI_DESC_INSTIDX_S 8U
165 /*
166 
167  Field: STDIPOFF
168  From..to bits: 12...15
169  DefaultValue: 0x0
170  Access type: read-only
171  Description: Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
172 
173  0: Standard IP MMRs do not exist
174 
175  0x1-0xF: Standard IP MMRs begin at offset of (64*[STDIPOFF] from the base IP address)
176 
177 */
178 #define SPI_DESC_STDIPOFF_W 4U
179 #define SPI_DESC_STDIPOFF_M 0x0000F000U
180 #define SPI_DESC_STDIPOFF_S 12U
181 /*
182 
183  Field: MODID
184  From..to bits: 16...31
185  DefaultValue: 0x0
186  Access type: read-only
187  Description: Module identifier used to uniquely identify this IP.
188 
189 */
190 #define SPI_DESC_MODID_W 16U
191 #define SPI_DESC_MODID_M 0xFFFF0000U
192 #define SPI_DESC_MODID_S 16U
193 
194 
195 /*-----------------------------------REGISTER------------------------------------
196  Register name: IMASK
197  Offset name: SPI_O_IMASK
198  Relative address: 0x44
199  Description: Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.*] to [MIS.*] when the corresponding bit-fields are set to 1.
200  Default Value: 0x00000000
201 
202  Field: RXOVF
203  From..to bits: 0...0
204  DefaultValue: 0x0
205  Access type: read-write
206  Description: RXFIFO overflow event mask.
207 
208  ENUMs:
209  SET: Set Interrrupt Mask
210  CLR: Clear Interrupt Mask
211 */
212 #define SPI_IMASK_RXOVF 0x00000001U
213 #define SPI_IMASK_RXOVF_M 0x00000001U
214 #define SPI_IMASK_RXOVF_S 0U
215 #define SPI_IMASK_RXOVF_SET 0x00000001U
216 #define SPI_IMASK_RXOVF_CLR 0x00000000U
217 /*
218 
219  Field: PER
220  From..to bits: 1...1
221  DefaultValue: 0x0
222  Access type: read-write
223  Description: Parity error event mask.
224 
225  ENUMs:
226  SET: Set Interrrupt Mask
227  CLR: Clear Interrupt Mask
228 */
229 #define SPI_IMASK_PER 0x00000002U
230 #define SPI_IMASK_PER_M 0x00000002U
231 #define SPI_IMASK_PER_S 1U
232 #define SPI_IMASK_PER_SET 0x00000002U
233 #define SPI_IMASK_PER_CLR 0x00000000U
234 /*
235 
236  Field: RTOUT
237  From..to bits: 2...2
238  DefaultValue: 0x0
239  Access type: read-write
240  Description: SPI Receive Time-Out event mask.
241 
242  ENUMs:
243  SET: Set Interrrupt Mask
244  CLR: Clear Interrupt Mask
245 */
246 #define SPI_IMASK_RTOUT 0x00000004U
247 #define SPI_IMASK_RTOUT_M 0x00000004U
248 #define SPI_IMASK_RTOUT_S 2U
249 #define SPI_IMASK_RTOUT_SET 0x00000004U
250 #define SPI_IMASK_RTOUT_CLR 0x00000000U
251 /*
252 
253  Field: RX
254  From..to bits: 3...3
255  DefaultValue: 0x0
256  Access type: read-write
257  Description: Receive FIFO event.
258 
259  ENUMs:
260  SET: Set Interrupt Mask
261  CLR: Clear Interrupt Mask
262 */
263 #define SPI_IMASK_RX 0x00000008U
264 #define SPI_IMASK_RX_M 0x00000008U
265 #define SPI_IMASK_RX_S 3U
266 #define SPI_IMASK_RX_SET 0x00000008U
267 #define SPI_IMASK_RX_CLR 0x00000000U
268 /*
269 
270  Field: TX
271  From..to bits: 4...4
272  DefaultValue: 0x0
273  Access type: read-write
274  Description: Transmit FIFO event mask.
275 
276  ENUMs:
277  SET: Set Interrrupt Mask
278  CLR: Clear Interrupt Mask
279 */
280 #define SPI_IMASK_TX 0x00000010U
281 #define SPI_IMASK_TX_M 0x00000010U
282 #define SPI_IMASK_TX_S 4U
283 #define SPI_IMASK_TX_SET 0x00000010U
284 #define SPI_IMASK_TX_CLR 0x00000000U
285 /*
286 
287  Field: TXEMPTY
288  From..to bits: 5...5
289  DefaultValue: 0x0
290  Access type: read-write
291  Description: Transmit FIFO Empty event mask.
292 
293  ENUMs:
294  SET: Set Interrrupt Mask
295  CLR: Clear Interrupt Mask
296 */
297 #define SPI_IMASK_TXEMPTY 0x00000020U
298 #define SPI_IMASK_TXEMPTY_M 0x00000020U
299 #define SPI_IMASK_TXEMPTY_S 5U
300 #define SPI_IMASK_TXEMPTY_SET 0x00000020U
301 #define SPI_IMASK_TXEMPTY_CLR 0x00000000U
302 /*
303 
304  Field: IDLE
305  From..to bits: 6...6
306  DefaultValue: 0x0
307  Access type: read-write
308  Description: SPI Idle event mask.
309 
310  ENUMs:
311  SET: Set Interrrupt Mask
312  CLR: Clear Interrupt Mask
313 */
314 #define SPI_IMASK_IDLE 0x00000040U
315 #define SPI_IMASK_IDLE_M 0x00000040U
316 #define SPI_IMASK_IDLE_S 6U
317 #define SPI_IMASK_IDLE_SET 0x00000040U
318 #define SPI_IMASK_IDLE_CLR 0x00000000U
319 /*
320 
321  Field: DMARX
322  From..to bits: 7...7
323  DefaultValue: 0x0
324  Access type: read-write
325  Description: DMA Done RX event mask.
326 
327  ENUMs:
328  SET: Set Interrrupt Mask
329  CLR: Clear Interrupt Mask
330 */
331 #define SPI_IMASK_DMARX 0x00000080U
332 #define SPI_IMASK_DMARX_M 0x00000080U
333 #define SPI_IMASK_DMARX_S 7U
334 #define SPI_IMASK_DMARX_SET 0x00000080U
335 #define SPI_IMASK_DMARX_CLR 0x00000000U
336 /*
337 
338  Field: DMATX
339  From..to bits: 8...8
340  DefaultValue: 0x0
341  Access type: read-write
342  Description: DMA Done TX event mask.
343 
344  ENUMs:
345  SET: Set Interrrupt Mask
346  CLR: Clear Interrupt Mask
347 */
348 #define SPI_IMASK_DMATX 0x00000100U
349 #define SPI_IMASK_DMATX_M 0x00000100U
350 #define SPI_IMASK_DMATX_S 8U
351 #define SPI_IMASK_DMATX_SET 0x00000100U
352 #define SPI_IMASK_DMATX_CLR 0x00000000U
353 
354 
355 /*-----------------------------------REGISTER------------------------------------
356  Register name: RIS
357  Offset name: SPI_O_RIS
358  Relative address: 0x48
359  Description: Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
360  Default Value: 0x00000000
361 
362  Field: RXOVF
363  From..to bits: 0...0
364  DefaultValue: 0x0
365  Access type: read-only
366  Description: RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
367 
368  ENUMs:
369  SET: Interrupt occurred
370  CLR: Interrupt did not occur
371 */
372 #define SPI_RIS_RXOVF 0x00000001U
373 #define SPI_RIS_RXOVF_M 0x00000001U
374 #define SPI_RIS_RXOVF_S 0U
375 #define SPI_RIS_RXOVF_SET 0x00000001U
376 #define SPI_RIS_RXOVF_CLR 0x00000000U
377 /*
378 
379  Field: PER
380  From..to bits: 1...1
381  DefaultValue: 0x0
382  Access type: read-only
383  Description: Parity error event. This bit is set if a Parity error has been detected
384 
385  ENUMs:
386  SET: Interrupt occurred
387  CLR: Interrupt did not occur
388 */
389 #define SPI_RIS_PER 0x00000002U
390 #define SPI_RIS_PER_M 0x00000002U
391 #define SPI_RIS_PER_S 1U
392 #define SPI_RIS_PER_SET 0x00000002U
393 #define SPI_RIS_PER_CLR 0x00000000U
394 /*
395 
396  Field: RTOUT
397  From..to bits: 2...2
398  DefaultValue: 0x0
399  Access type: read-only
400  Description: SPI Receive Time-Out event. This interrupt is set if no activity is detected on the input clock line within the time period dictated by [CTL1.RTOUT] value. This is applicable only in peripheral mode.
401 
402  ENUMs:
403  SET: Interrupt occurred
404  CLR: Interrupt did not occur
405 */
406 #define SPI_RIS_RTOUT 0x00000004U
407 #define SPI_RIS_RTOUT_M 0x00000004U
408 #define SPI_RIS_RTOUT_S 2U
409 #define SPI_RIS_RTOUT_SET 0x00000004U
410 #define SPI_RIS_RTOUT_CLR 0x00000000U
411 /*
412 
413  Field: RX
414  From..to bits: 3...3
415  DefaultValue: 0x0
416  Access type: read-only
417  Description: Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
418 
419  ENUMs:
420  SET: Interrupt occurred
421  CLR: Interrupt did not occur
422 */
423 #define SPI_RIS_RX 0x00000008U
424 #define SPI_RIS_RX_M 0x00000008U
425 #define SPI_RIS_RX_S 3U
426 #define SPI_RIS_RX_SET 0x00000008U
427 #define SPI_RIS_RX_CLR 0x00000000U
428 /*
429 
430  Field: TX
431  From..to bits: 4...4
432  DefaultValue: 0x0
433  Access type: read-only
434  Description: Transmit FIFO event.This interrupt is set if the selected Transmit FIFO level has been reached.
435 
436  ENUMs:
437  SET: Interrupt occurred
438  CLR: Interrupt did not occur
439 */
440 #define SPI_RIS_TX 0x00000010U
441 #define SPI_RIS_TX_M 0x00000010U
442 #define SPI_RIS_TX_S 4U
443 #define SPI_RIS_TX_SET 0x00000010U
444 #define SPI_RIS_TX_CLR 0x00000000U
445 /*
446 
447  Field: TXEMPTY
448  From..to bits: 5...5
449  DefaultValue: 0x0
450  Access type: read-only
451  Description: Transmit FIFO Empty interrupt mask. This interrupt is set when all data in the Transmit FIFO has been moved to the shift register.
452 
453  ENUMs:
454  SET: Interrupt occurred
455  CLR: Interrupt did not occur
456 */
457 #define SPI_RIS_TXEMPTY 0x00000020U
458 #define SPI_RIS_TXEMPTY_M 0x00000020U
459 #define SPI_RIS_TXEMPTY_S 5U
460 #define SPI_RIS_TXEMPTY_SET 0x00000020U
461 #define SPI_RIS_TXEMPTY_CLR 0x00000000U
462 /*
463 
464  Field: IDLE
465  From..to bits: 6...6
466  DefaultValue: 0x0
467  Access type: read-only
468  Description: SPI has completed transfers and moved to IDLE mode. This bit is set when [STA.BUSY] goes low.
469 
470  ENUMs:
471  SET: Interrupt occurred
472  CLR: Interrupt did not occur
473 */
474 #define SPI_RIS_IDLE 0x00000040U
475 #define SPI_RIS_IDLE_M 0x00000040U
476 #define SPI_RIS_IDLE_S 6U
477 #define SPI_RIS_IDLE_SET 0x00000040U
478 #define SPI_RIS_IDLE_CLR 0x00000000U
479 /*
480 
481  Field: DMARX
482  From..to bits: 7...7
483  DefaultValue: 0x0
484  Access type: read-only
485  Description: DMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows handling of the DMA RX event inside SPI.
486 
487  ENUMs:
488  SET: Interrupt occurred
489  CLR: Interrupt did not occur
490 */
491 #define SPI_RIS_DMARX 0x00000080U
492 #define SPI_RIS_DMARX_M 0x00000080U
493 #define SPI_RIS_DMARX_S 7U
494 #define SPI_RIS_DMARX_SET 0x00000080U
495 #define SPI_RIS_DMARX_CLR 0x00000000U
496 /*
497 
498  Field: DMATX
499  From..to bits: 8...8
500  DefaultValue: 0x0
501  Access type: read-only
502  Description: DMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the TX DMA event inside SPI.
503 
504  ENUMs:
505  SET: Interrupt occurred
506  CLR: Interrupt did not occur
507 */
508 #define SPI_RIS_DMATX 0x00000100U
509 #define SPI_RIS_DMATX_M 0x00000100U
510 #define SPI_RIS_DMATX_S 8U
511 #define SPI_RIS_DMATX_SET 0x00000100U
512 #define SPI_RIS_DMATX_CLR 0x00000000U
513 
514 
515 /*-----------------------------------REGISTER------------------------------------
516  Register name: MIS
517  Offset name: SPI_O_MIS
518  Relative address: 0x4C
519  Description: Masked interrupt status. This register is simply a bitwise AND of the contents of [IMASK.*] and [RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
520  Default Value: 0x00000000
521 
522  Field: RXOVF
523  From..to bits: 0...0
524  DefaultValue: 0x0
525  Access type: read-only
526  Description: Masked RXFIFO overflow event.
527 
528  ENUMs:
529  SET: Interrupt occurred
530  CLR: Interrupt did not occur
531 */
532 #define SPI_MIS_RXOVF 0x00000001U
533 #define SPI_MIS_RXOVF_M 0x00000001U
534 #define SPI_MIS_RXOVF_S 0U
535 #define SPI_MIS_RXOVF_SET 0x00000001U
536 #define SPI_MIS_RXOVF_CLR 0x00000000U
537 /*
538 
539  Field: PER
540  From..to bits: 1...1
541  DefaultValue: 0x0
542  Access type: read-only
543  Description: Masked Parity error event.
544 
545  ENUMs:
546  SET: Interrupt occurred
547  CLR: Interrupt did not occur
548 */
549 #define SPI_MIS_PER 0x00000002U
550 #define SPI_MIS_PER_M 0x00000002U
551 #define SPI_MIS_PER_S 1U
552 #define SPI_MIS_PER_SET 0x00000002U
553 #define SPI_MIS_PER_CLR 0x00000000U
554 /*
555 
556  Field: RTOUT
557  From..to bits: 2...2
558  DefaultValue: 0x0
559  Access type: read-only
560  Description: Masked SPI Receive Time-Out event.
561 
562  ENUMs:
563  SET: Interrupt occurred
564  CLR: Interrupt did not occur
565 */
566 #define SPI_MIS_RTOUT 0x00000004U
567 #define SPI_MIS_RTOUT_M 0x00000004U
568 #define SPI_MIS_RTOUT_S 2U
569 #define SPI_MIS_RTOUT_SET 0x00000004U
570 #define SPI_MIS_RTOUT_CLR 0x00000000U
571 /*
572 
573  Field: RX
574  From..to bits: 3...3
575  DefaultValue: 0x0
576  Access type: read-only
577  Description: Masked receive FIFO event.
578 
579  ENUMs:
580  SET: Interrupt occurred
581  CLR: Interrupt did not occur
582 */
583 #define SPI_MIS_RX 0x00000008U
584 #define SPI_MIS_RX_M 0x00000008U
585 #define SPI_MIS_RX_S 3U
586 #define SPI_MIS_RX_SET 0x00000008U
587 #define SPI_MIS_RX_CLR 0x00000000U
588 /*
589 
590  Field: TX
591  From..to bits: 4...4
592  DefaultValue: 0x0
593  Access type: read-only
594  Description: Masked Transmit FIFO event.
595 
596  ENUMs:
597  SET: Interrupt occurred
598  CLR: Interrupt did not occur
599 */
600 #define SPI_MIS_TX 0x00000010U
601 #define SPI_MIS_TX_M 0x00000010U
602 #define SPI_MIS_TX_S 4U
603 #define SPI_MIS_TX_SET 0x00000010U
604 #define SPI_MIS_TX_CLR 0x00000000U
605 /*
606 
607  Field: TXEMPTY
608  From..to bits: 5...5
609  DefaultValue: 0x0
610  Access type: read-only
611  Description: Masked Transmit FIFO Empty event.
612 
613  ENUMs:
614  SET: Interrupt occurred
615  CLR: Interrupt did not occur
616 */
617 #define SPI_MIS_TXEMPTY 0x00000020U
618 #define SPI_MIS_TXEMPTY_M 0x00000020U
619 #define SPI_MIS_TXEMPTY_S 5U
620 #define SPI_MIS_TXEMPTY_SET 0x00000020U
621 #define SPI_MIS_TXEMPTY_CLR 0x00000000U
622 /*
623 
624  Field: IDLE
625  From..to bits: 6...6
626  DefaultValue: 0x0
627  Access type: read-only
628  Description: Masked SPI IDLE event.
629 
630 
631  ENUMs:
632  SET: Interrupt occurred
633  CLR: Interrupt did not occur
634 */
635 #define SPI_MIS_IDLE 0x00000040U
636 #define SPI_MIS_IDLE_M 0x00000040U
637 #define SPI_MIS_IDLE_S 6U
638 #define SPI_MIS_IDLE_SET 0x00000040U
639 #define SPI_MIS_IDLE_CLR 0x00000000U
640 /*
641 
642  Field: DMARX
643  From..to bits: 7...7
644  DefaultValue: 0x0
645  Access type: read-only
646  Description: Masked DMA Done event for RX.
647 
648  ENUMs:
649  SET: Interrupt occurred
650  CLR: Interrupt did not occur
651 */
652 #define SPI_MIS_DMARX 0x00000080U
653 #define SPI_MIS_DMARX_M 0x00000080U
654 #define SPI_MIS_DMARX_S 7U
655 #define SPI_MIS_DMARX_SET 0x00000080U
656 #define SPI_MIS_DMARX_CLR 0x00000000U
657 /*
658 
659  Field: DMATX
660  From..to bits: 8...8
661  DefaultValue: 0x0
662  Access type: read-only
663  Description: Masked DMA Done event for TX.
664 
665  ENUMs:
666  SET: Interrupt occurred
667  CLR: Interrupt did not occur
668 */
669 #define SPI_MIS_DMATX 0x00000100U
670 #define SPI_MIS_DMATX_M 0x00000100U
671 #define SPI_MIS_DMATX_S 8U
672 #define SPI_MIS_DMATX_SET 0x00000100U
673 #define SPI_MIS_DMATX_CLR 0x00000000U
674 
675 
676 /*-----------------------------------REGISTER------------------------------------
677  Register name: ISET
678  Offset name: SPI_O_ISET
679  Relative address: 0x50
680  Description: Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.*] bit also gets set. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets set.
681  Default Value: 0x00000000
682 
683  Field: RXOVF
684  From..to bits: 0...0
685  DefaultValue: 0x0
686  Access type: write-only
687  Description: Set RXFIFO overflow event.
688 
689  ENUMs:
690  SET: Set Interrupt
691  NO_EFFECT: Writing 0 has no effect
692 */
693 #define SPI_ISET_RXOVF 0x00000001U
694 #define SPI_ISET_RXOVF_M 0x00000001U
695 #define SPI_ISET_RXOVF_S 0U
696 #define SPI_ISET_RXOVF_SET 0x00000001U
697 #define SPI_ISET_RXOVF_NO_EFFECT 0x00000000U
698 /*
699 
700  Field: PER
701  From..to bits: 1...1
702  DefaultValue: 0x0
703  Access type: write-only
704  Description: Set Parity error event.
705 
706  ENUMs:
707  SET: Set Interrupt
708  NO_EFFECT: Writing 0 has no effect
709 */
710 #define SPI_ISET_PER 0x00000002U
711 #define SPI_ISET_PER_M 0x00000002U
712 #define SPI_ISET_PER_S 1U
713 #define SPI_ISET_PER_SET 0x00000002U
714 #define SPI_ISET_PER_NO_EFFECT 0x00000000U
715 /*
716 
717  Field: RTOUT
718  From..to bits: 2...2
719  DefaultValue: 0x0
720  Access type: write-only
721  Description: Set SPI Receive Time-Out Event.
722 
723  ENUMs:
724  SET: Set Interrrupt Mask
725  NO_EFFECT: Writing 0 has no effect
726 */
727 #define SPI_ISET_RTOUT 0x00000004U
728 #define SPI_ISET_RTOUT_M 0x00000004U
729 #define SPI_ISET_RTOUT_S 2U
730 #define SPI_ISET_RTOUT_SET 0x00000004U
731 #define SPI_ISET_RTOUT_NO_EFFECT 0x00000000U
732 /*
733 
734  Field: RX
735  From..to bits: 3...3
736  DefaultValue: 0x0
737  Access type: write-only
738  Description: Set Receive FIFO event.
739 
740  ENUMs:
741  SET: Set Interrupt
742  NO_EFFECT: Writing 0 has no effect
743 */
744 #define SPI_ISET_RX 0x00000008U
745 #define SPI_ISET_RX_M 0x00000008U
746 #define SPI_ISET_RX_S 3U
747 #define SPI_ISET_RX_SET 0x00000008U
748 #define SPI_ISET_RX_NO_EFFECT 0x00000000U
749 /*
750 
751  Field: TX
752  From..to bits: 4...4
753  DefaultValue: 0x0
754  Access type: write-only
755  Description: Set Transmit FIFO event.
756 
757  ENUMs:
758  SET: Set Interrupt
759  NO_EFFECT: Writing 0 has no effect
760 */
761 #define SPI_ISET_TX 0x00000010U
762 #define SPI_ISET_TX_M 0x00000010U
763 #define SPI_ISET_TX_S 4U
764 #define SPI_ISET_TX_SET 0x00000010U
765 #define SPI_ISET_TX_NO_EFFECT 0x00000000U
766 /*
767 
768  Field: TXEMPTY
769  From..to bits: 5...5
770  DefaultValue: 0x0
771  Access type: write-only
772  Description: Set Transmit FIFO Empty event.
773 
774  ENUMs:
775  SET: Set Interrupt
776  NO_EFFECT: Writing 0 has no effect
777 */
778 #define SPI_ISET_TXEMPTY 0x00000020U
779 #define SPI_ISET_TXEMPTY_M 0x00000020U
780 #define SPI_ISET_TXEMPTY_S 5U
781 #define SPI_ISET_TXEMPTY_SET 0x00000020U
782 #define SPI_ISET_TXEMPTY_NO_EFFECT 0x00000000U
783 /*
784 
785  Field: IDLE
786  From..to bits: 6...6
787  DefaultValue: 0x0
788  Access type: write-only
789  Description: Set SPI IDLE event.
790 
791 
792  ENUMs:
793  SET: Set Interrupt
794  NO_EFFECT: Writing 0 has no effect
795 */
796 #define SPI_ISET_IDLE 0x00000040U
797 #define SPI_ISET_IDLE_M 0x00000040U
798 #define SPI_ISET_IDLE_S 6U
799 #define SPI_ISET_IDLE_SET 0x00000040U
800 #define SPI_ISET_IDLE_NO_EFFECT 0x00000000U
801 /*
802 
803  Field: DMARX
804  From..to bits: 7...7
805  DefaultValue: 0x0
806  Access type: write-only
807  Description: Set DMA Done event for RX.
808 
809  ENUMs:
810  SET: Set Interrupt
811  NO_EFFECT: Writing 0 has no effect
812 */
813 #define SPI_ISET_DMARX 0x00000080U
814 #define SPI_ISET_DMARX_M 0x00000080U
815 #define SPI_ISET_DMARX_S 7U
816 #define SPI_ISET_DMARX_SET 0x00000080U
817 #define SPI_ISET_DMARX_NO_EFFECT 0x00000000U
818 /*
819 
820  Field: DMATX
821  From..to bits: 8...8
822  DefaultValue: 0x0
823  Access type: write-only
824  Description: Set DMA Done event for TX.
825 
826  ENUMs:
827  SET: Set Interrupt
828  NO_EFFECT: Writing 0 has no effect
829 */
830 #define SPI_ISET_DMATX 0x00000100U
831 #define SPI_ISET_DMATX_M 0x00000100U
832 #define SPI_ISET_DMATX_S 8U
833 #define SPI_ISET_DMATX_SET 0x00000100U
834 #define SPI_ISET_DMATX_NO_EFFECT 0x00000000U
835 
836 
837 /*-----------------------------------REGISTER------------------------------------
838  Register name: ICLR
839  Offset name: SPI_O_ICLR
840  Relative address: 0x54
841  Description: Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.*] bit also gets cleared. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
842  Default Value: 0x00000000
843 
844  Field: RXOVF
845  From..to bits: 0...0
846  DefaultValue: 0x0
847  Access type: write-only
848  Description: Clear RXFIFO overflow event.
849 
850  ENUMs:
851  CLR: Clear Interrupt
852  NO_EFFECT: Writing 0 has no effect
853 */
854 #define SPI_ICLR_RXOVF 0x00000001U
855 #define SPI_ICLR_RXOVF_M 0x00000001U
856 #define SPI_ICLR_RXOVF_S 0U
857 #define SPI_ICLR_RXOVF_CLR 0x00000001U
858 #define SPI_ICLR_RXOVF_NO_EFFECT 0x00000000U
859 /*
860 
861  Field: PER
862  From..to bits: 1...1
863  DefaultValue: 0x0
864  Access type: write-only
865  Description: Clear Parity error event.
866 
867  ENUMs:
868  CLR: Clear Interrupt
869  NO_EFFECT: Writing 0 has no effect
870 */
871 #define SPI_ICLR_PER 0x00000002U
872 #define SPI_ICLR_PER_M 0x00000002U
873 #define SPI_ICLR_PER_S 1U
874 #define SPI_ICLR_PER_CLR 0x00000002U
875 #define SPI_ICLR_PER_NO_EFFECT 0x00000000U
876 /*
877 
878  Field: RTOUT
879  From..to bits: 2...2
880  DefaultValue: 0x0
881  Access type: write-only
882  Description: Clear SPI Receive Time-Out Event.
883 
884  ENUMs:
885  CLR: Set Interrrupt Mask
886  NO_EFFECT: Writing 0 has no effect
887 */
888 #define SPI_ICLR_RTOUT 0x00000004U
889 #define SPI_ICLR_RTOUT_M 0x00000004U
890 #define SPI_ICLR_RTOUT_S 2U
891 #define SPI_ICLR_RTOUT_CLR 0x00000004U
892 #define SPI_ICLR_RTOUT_NO_EFFECT 0x00000000U
893 /*
894 
895  Field: RX
896  From..to bits: 3...3
897  DefaultValue: 0x0
898  Access type: write-only
899  Description: Clear Receive FIFO event.
900 
901  ENUMs:
902  CLR: Clear Interrupt
903  NO_EFFECT: Writing 0 has no effect
904 */
905 #define SPI_ICLR_RX 0x00000008U
906 #define SPI_ICLR_RX_M 0x00000008U
907 #define SPI_ICLR_RX_S 3U
908 #define SPI_ICLR_RX_CLR 0x00000008U
909 #define SPI_ICLR_RX_NO_EFFECT 0x00000000U
910 /*
911 
912  Field: TX
913  From..to bits: 4...4
914  DefaultValue: 0x0
915  Access type: write-only
916  Description: Clear Transmit FIFO event.
917 
918  ENUMs:
919  CLR: Clear Interrupt
920  NO_EFFECT: Writing 0 has no effect
921 */
922 #define SPI_ICLR_TX 0x00000010U
923 #define SPI_ICLR_TX_M 0x00000010U
924 #define SPI_ICLR_TX_S 4U
925 #define SPI_ICLR_TX_CLR 0x00000010U
926 #define SPI_ICLR_TX_NO_EFFECT 0x00000000U
927 /*
928 
929  Field: TXEMPTY
930  From..to bits: 5...5
931  DefaultValue: 0x0
932  Access type: write-only
933  Description: Clear Transmit FIFO Empty event.
934 
935  ENUMs:
936  CLR: Clear Interrupt
937  NO_EFFECT: Writing 0 has no effect
938 */
939 #define SPI_ICLR_TXEMPTY 0x00000020U
940 #define SPI_ICLR_TXEMPTY_M 0x00000020U
941 #define SPI_ICLR_TXEMPTY_S 5U
942 #define SPI_ICLR_TXEMPTY_CLR 0x00000020U
943 #define SPI_ICLR_TXEMPTY_NO_EFFECT 0x00000000U
944 /*
945 
946  Field: IDLE
947  From..to bits: 6...6
948  DefaultValue: 0x0
949  Access type: write-only
950  Description: Clear SPI IDLE event.
951 
952  ENUMs:
953  CLR: Clear Interrupt
954  NO_EFFECT: Writing 0 has no effect
955 */
956 #define SPI_ICLR_IDLE 0x00000040U
957 #define SPI_ICLR_IDLE_M 0x00000040U
958 #define SPI_ICLR_IDLE_S 6U
959 #define SPI_ICLR_IDLE_CLR 0x00000040U
960 #define SPI_ICLR_IDLE_NO_EFFECT 0x00000000U
961 /*
962 
963  Field: DMARX
964  From..to bits: 7...7
965  DefaultValue: 0x0
966  Access type: write-only
967  Description: Clear DMA Done event for RX.
968 
969  ENUMs:
970  CLR: Clear Interrupt
971  NO_EFFECT: Writing 0 has no effect
972 */
973 #define SPI_ICLR_DMARX 0x00000080U
974 #define SPI_ICLR_DMARX_M 0x00000080U
975 #define SPI_ICLR_DMARX_S 7U
976 #define SPI_ICLR_DMARX_CLR 0x00000080U
977 #define SPI_ICLR_DMARX_NO_EFFECT 0x00000000U
978 /*
979 
980  Field: DMATX
981  From..to bits: 8...8
982  DefaultValue: 0x0
983  Access type: write-only
984  Description: Clear DMA Done event for TX.
985 
986  ENUMs:
987  CLR: Clear Interrupt
988  NO_EFFECT: Writing 0 has no effect
989 */
990 #define SPI_ICLR_DMATX 0x00000100U
991 #define SPI_ICLR_DMATX_M 0x00000100U
992 #define SPI_ICLR_DMATX_S 8U
993 #define SPI_ICLR_DMATX_CLR 0x00000100U
994 #define SPI_ICLR_DMATX_NO_EFFECT 0x00000000U
995 
996 
997 /*-----------------------------------REGISTER------------------------------------
998  Register name: IMSET
999  Offset name: SPI_O_IMSET
1000  Relative address: 0x58
1001  Description: Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.
1002  Default Value: 0x00000000
1003 
1004  Field: RXOVF
1005  From..to bits: 0...0
1006  DefaultValue: 0x0
1007  Access type: write-only
1008  Description: Set RXFIFO overflow event mask
1009 
1010  ENUMs:
1011  SET: Set interrupt mask
1012  NO_EFFECT: Writing 0 has no effect
1013 */
1014 #define SPI_IMSET_RXOVF 0x00000001U
1015 #define SPI_IMSET_RXOVF_M 0x00000001U
1016 #define SPI_IMSET_RXOVF_S 0U
1017 #define SPI_IMSET_RXOVF_SET 0x00000001U
1018 #define SPI_IMSET_RXOVF_NO_EFFECT 0x00000000U
1019 /*
1020 
1021  Field: PER
1022  From..to bits: 1...1
1023  DefaultValue: 0x0
1024  Access type: write-only
1025  Description: Set Parity error event mask
1026 
1027  ENUMs:
1028  SET: Set interrupt mask
1029  NO_EFFECT: Writing 0 has no effect
1030 */
1031 #define SPI_IMSET_PER 0x00000002U
1032 #define SPI_IMSET_PER_M 0x00000002U
1033 #define SPI_IMSET_PER_S 1U
1034 #define SPI_IMSET_PER_SET 0x00000002U
1035 #define SPI_IMSET_PER_NO_EFFECT 0x00000000U
1036 /*
1037 
1038  Field: RTOUT
1039  From..to bits: 2...2
1040  DefaultValue: 0x0
1041  Access type: write-only
1042  Description: Set SPI Receive Time-Out event mask
1043 
1044  ENUMs:
1045  SET: Set interrupt mask
1046  NO_EFFECT: Writing 0 has no effect
1047 */
1048 #define SPI_IMSET_RTOUT 0x00000004U
1049 #define SPI_IMSET_RTOUT_M 0x00000004U
1050 #define SPI_IMSET_RTOUT_S 2U
1051 #define SPI_IMSET_RTOUT_SET 0x00000004U
1052 #define SPI_IMSET_RTOUT_NO_EFFECT 0x00000000U
1053 /*
1054 
1055  Field: RX
1056  From..to bits: 3...3
1057  DefaultValue: 0x0
1058  Access type: write-only
1059  Description: Set Receive FIFO event mask
1060 
1061  ENUMs:
1062  SET: Set interrupt mask
1063  NO_EFFECT: Writing 0 has no effect
1064 */
1065 #define SPI_IMSET_RX 0x00000008U
1066 #define SPI_IMSET_RX_M 0x00000008U
1067 #define SPI_IMSET_RX_S 3U
1068 #define SPI_IMSET_RX_SET 0x00000008U
1069 #define SPI_IMSET_RX_NO_EFFECT 0x00000000U
1070 /*
1071 
1072  Field: TX
1073  From..to bits: 4...4
1074  DefaultValue: 0x0
1075  Access type: write-only
1076  Description: Set Transmit FIFO event mask
1077 
1078  ENUMs:
1079  SET: Set interrupt mask
1080  NO_EFFECT: Writing 0 has no effect
1081 */
1082 #define SPI_IMSET_TX 0x00000010U
1083 #define SPI_IMSET_TX_M 0x00000010U
1084 #define SPI_IMSET_TX_S 4U
1085 #define SPI_IMSET_TX_SET 0x00000010U
1086 #define SPI_IMSET_TX_NO_EFFECT 0x00000000U
1087 /*
1088 
1089  Field: TXEMPTY
1090  From..to bits: 5...5
1091  DefaultValue: 0x0
1092  Access type: write-only
1093  Description: Set Transmit FIFO Empty event mask
1094 
1095  ENUMs:
1096  SET: Set interrupt mask
1097  NO_EFFECT: Writing 0 has no effect
1098 */
1099 #define SPI_IMSET_TXEMPTY 0x00000020U
1100 #define SPI_IMSET_TXEMPTY_M 0x00000020U
1101 #define SPI_IMSET_TXEMPTY_S 5U
1102 #define SPI_IMSET_TXEMPTY_SET 0x00000020U
1103 #define SPI_IMSET_TXEMPTY_NO_EFFECT 0x00000000U
1104 /*
1105 
1106  Field: IDLE
1107  From..to bits: 6...6
1108  DefaultValue: 0x0
1109  Access type: write-only
1110  Description: Set SPI IDLE event mask
1111 
1112 
1113  ENUMs:
1114  SET: Set interrupt mask
1115  NO_EFFECT: Writing 0 has no effect
1116 */
1117 #define SPI_IMSET_IDLE 0x00000040U
1118 #define SPI_IMSET_IDLE_M 0x00000040U
1119 #define SPI_IMSET_IDLE_S 6U
1120 #define SPI_IMSET_IDLE_SET 0x00000040U
1121 #define SPI_IMSET_IDLE_NO_EFFECT 0x00000000U
1122 /*
1123 
1124  Field: DMARX
1125  From..to bits: 7...7
1126  DefaultValue: 0x0
1127  Access type: write-only
1128  Description: Set DMA Done for RX event mask
1129 
1130  ENUMs:
1131  SET: Set interrupt mask
1132  NO_EFFECT: Writing 0 has no effect
1133 */
1134 #define SPI_IMSET_DMARX 0x00000080U
1135 #define SPI_IMSET_DMARX_M 0x00000080U
1136 #define SPI_IMSET_DMARX_S 7U
1137 #define SPI_IMSET_DMARX_SET 0x00000080U
1138 #define SPI_IMSET_DMARX_NO_EFFECT 0x00000000U
1139 /*
1140 
1141  Field: DMATX
1142  From..to bits: 8...8
1143  DefaultValue: 0x0
1144  Access type: write-only
1145  Description: Set DMA Done for TX event mask
1146 
1147  ENUMs:
1148  SET: Set interrupt mask
1149  NO_EFFECT: Writing 0 has no effect
1150 */
1151 #define SPI_IMSET_DMATX 0x00000100U
1152 #define SPI_IMSET_DMATX_M 0x00000100U
1153 #define SPI_IMSET_DMATX_S 8U
1154 #define SPI_IMSET_DMATX_SET 0x00000100U
1155 #define SPI_IMSET_DMATX_NO_EFFECT 0x00000000U
1156 
1157 
1158 /*-----------------------------------REGISTER------------------------------------
1159  Register name: IMCLR
1160  Offset name: SPI_O_IMCLR
1161  Relative address: 0x5C
1162  Description: Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.
1163  Default Value: 0x00000000
1164 
1165  Field: RXOVF
1166  From..to bits: 0...0
1167  DefaultValue: 0x0
1168  Access type: write-only
1169  Description: Clear RXFIFO overflow event mask
1170 
1171  ENUMs:
1172  CLR: Clear interrupt mask
1173  NO_EFFECT: Writing 0 has no effect
1174 */
1175 #define SPI_IMCLR_RXOVF 0x00000001U
1176 #define SPI_IMCLR_RXOVF_M 0x00000001U
1177 #define SPI_IMCLR_RXOVF_S 0U
1178 #define SPI_IMCLR_RXOVF_CLR 0x00000001U
1179 #define SPI_IMCLR_RXOVF_NO_EFFECT 0x00000000U
1180 /*
1181 
1182  Field: PER
1183  From..to bits: 1...1
1184  DefaultValue: 0x0
1185  Access type: write-only
1186  Description: Clear Parity error event mask
1187 
1188  ENUMs:
1189  CLR: Clear interrupt mask
1190  NO_EFFECT: Writing 0 has no effect
1191 */
1192 #define SPI_IMCLR_PER 0x00000002U
1193 #define SPI_IMCLR_PER_M 0x00000002U
1194 #define SPI_IMCLR_PER_S 1U
1195 #define SPI_IMCLR_PER_CLR 0x00000002U
1196 #define SPI_IMCLR_PER_NO_EFFECT 0x00000000U
1197 /*
1198 
1199  Field: RTOUT
1200  From..to bits: 2...2
1201  DefaultValue: 0x0
1202  Access type: write-only
1203  Description: Clear SPI Receive Time-Out event mask
1204 
1205  ENUMs:
1206  CLR: Clear interrupt mask
1207  NO_EFFECT: Writing 0 has no effect
1208 */
1209 #define SPI_IMCLR_RTOUT 0x00000004U
1210 #define SPI_IMCLR_RTOUT_M 0x00000004U
1211 #define SPI_IMCLR_RTOUT_S 2U
1212 #define SPI_IMCLR_RTOUT_CLR 0x00000004U
1213 #define SPI_IMCLR_RTOUT_NO_EFFECT 0x00000000U
1214 /*
1215 
1216  Field: RX
1217  From..to bits: 3...3
1218  DefaultValue: 0x0
1219  Access type: write-only
1220  Description: Clear Receive FIFO event mask
1221 
1222  ENUMs:
1223  CLR: Clear interrupt mask
1224  NO_EFFECT: Writing 0 has no effect
1225 */
1226 #define SPI_IMCLR_RX 0x00000008U
1227 #define SPI_IMCLR_RX_M 0x00000008U
1228 #define SPI_IMCLR_RX_S 3U
1229 #define SPI_IMCLR_RX_CLR 0x00000008U
1230 #define SPI_IMCLR_RX_NO_EFFECT 0x00000000U
1231 /*
1232 
1233  Field: TX
1234  From..to bits: 4...4
1235  DefaultValue: 0x0
1236  Access type: write-only
1237  Description: Clear Transmit FIFO event mask
1238 
1239  ENUMs:
1240  CLR: Clear interrupt mask
1241  NO_EFFECT: Writing 0 has no effect
1242 */
1243 #define SPI_IMCLR_TX 0x00000010U
1244 #define SPI_IMCLR_TX_M 0x00000010U
1245 #define SPI_IMCLR_TX_S 4U
1246 #define SPI_IMCLR_TX_CLR 0x00000010U
1247 #define SPI_IMCLR_TX_NO_EFFECT 0x00000000U
1248 /*
1249 
1250  Field: TXEMPTY
1251  From..to bits: 5...5
1252  DefaultValue: 0x0
1253  Access type: write-only
1254  Description: Clear Transmit FIFO Empty event mask
1255 
1256  ENUMs:
1257  CLR: Clear interrupt mask
1258  NO_EFFECT: Writing 0 has no effect
1259 */
1260 #define SPI_IMCLR_TXEMPTY 0x00000020U
1261 #define SPI_IMCLR_TXEMPTY_M 0x00000020U
1262 #define SPI_IMCLR_TXEMPTY_S 5U
1263 #define SPI_IMCLR_TXEMPTY_CLR 0x00000020U
1264 #define SPI_IMCLR_TXEMPTY_NO_EFFECT 0x00000000U
1265 /*
1266 
1267  Field: IDLE
1268  From..to bits: 6...6
1269  DefaultValue: 0x0
1270  Access type: write-only
1271  Description: Clear SPI IDLE event mask
1272 
1273  ENUMs:
1274  CLR: Clear interrupt mask
1275  NO_EFFECT: Writing 0 has no effect
1276 */
1277 #define SPI_IMCLR_IDLE 0x00000040U
1278 #define SPI_IMCLR_IDLE_M 0x00000040U
1279 #define SPI_IMCLR_IDLE_S 6U
1280 #define SPI_IMCLR_IDLE_CLR 0x00000040U
1281 #define SPI_IMCLR_IDLE_NO_EFFECT 0x00000000U
1282 /*
1283 
1284  Field: DMARX
1285  From..to bits: 7...7
1286  DefaultValue: 0x0
1287  Access type: write-only
1288  Description: Clear DMA Done for RX event mask
1289 
1290  ENUMs:
1291  CLR: Clear interrupt mask
1292  NO_EFFECT: Writing 0 has no effect
1293 */
1294 #define SPI_IMCLR_DMARX 0x00000080U
1295 #define SPI_IMCLR_DMARX_M 0x00000080U
1296 #define SPI_IMCLR_DMARX_S 7U
1297 #define SPI_IMCLR_DMARX_CLR 0x00000080U
1298 #define SPI_IMCLR_DMARX_NO_EFFECT 0x00000000U
1299 /*
1300 
1301  Field: DMATX
1302  From..to bits: 8...8
1303  DefaultValue: 0x0
1304  Access type: write-only
1305  Description: Clear DMA Done for TX event mask
1306 
1307  ENUMs:
1308  CLR: Clear interrupt mask
1309  NO_EFFECT: Writing 0 has no effect
1310 */
1311 #define SPI_IMCLR_DMATX 0x00000100U
1312 #define SPI_IMCLR_DMATX_M 0x00000100U
1313 #define SPI_IMCLR_DMATX_S 8U
1314 #define SPI_IMCLR_DMATX_CLR 0x00000100U
1315 #define SPI_IMCLR_DMATX_NO_EFFECT 0x00000000U
1316 
1317 
1318 /*-----------------------------------REGISTER------------------------------------
1319  Register name: EMU
1320  Offset name: SPI_O_EMU
1321  Relative address: 0x60
1322  Description: Emulation control register. This register controls the behavior of the IP related to core halted input.
1323  Default Value: 0x00000000
1324 
1325  Field: HALT
1326  From..to bits: 0...0
1327  DefaultValue: 0x0
1328  Access type: read-write
1329  Description: Halt control
1330 
1331  ENUMs:
1332  STOP: Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary (end of word boundary, based on DSS configuration) from where it can resume without corruption.
1333  RUN: Free run option. The IP ignores the state of the core halted input.
1334 */
1335 #define SPI_EMU_HALT 0x00000001U
1336 #define SPI_EMU_HALT_M 0x00000001U
1337 #define SPI_EMU_HALT_S 0U
1338 #define SPI_EMU_HALT_STOP 0x00000001U
1339 #define SPI_EMU_HALT_RUN 0x00000000U
1340 
1341 
1342 /*-----------------------------------REGISTER------------------------------------
1343  Register name: CTL0
1344  Offset name: SPI_O_CTL0
1345  Relative address: 0x100
1346  Description: SPI control register 0
1347  Default Value: 0x00000000
1348 
1349  Field: DSS
1350  From..to bits: 0...3
1351  DefaultValue: 0x0
1352  Access type: read-write
1353  Description: Data size select. The applicable DSS values for controller mode operation are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 0x0 to 0x2 are reserved and must not be used.
1354 
1355  ENUMs:
1356  BITS_4: 4-bits data size
1357  BITS_5: 5-bits data size
1358  BITS_6: 6-bits data size
1359  BITS_7: 7-bits data size
1360  BITS_8: 8-bits data size
1361  BITS_9: 9-bits data size
1362  BITS_10: 10-bits data size
1363  BITS_11: 11-bits data size
1364  BITS_12: 12-bits data size
1365  BITS_13: 13-bits data size
1366  BITS_14: 14-bits data size
1367  BITS_15: 15-bits data size
1368  BITS_16: 16-bits data size
1369 */
1370 #define SPI_CTL0_DSS_W 4U
1371 #define SPI_CTL0_DSS_M 0x0000000FU
1372 #define SPI_CTL0_DSS_S 0U
1373 #define SPI_CTL0_DSS_BITS_4 0x00000003U
1374 #define SPI_CTL0_DSS_BITS_5 0x00000004U
1375 #define SPI_CTL0_DSS_BITS_6 0x00000005U
1376 #define SPI_CTL0_DSS_BITS_7 0x00000006U
1377 #define SPI_CTL0_DSS_BITS_8 0x00000007U
1378 #define SPI_CTL0_DSS_BITS_9 0x00000008U
1379 #define SPI_CTL0_DSS_BITS_10 0x00000009U
1380 #define SPI_CTL0_DSS_BITS_11 0x0000000AU
1381 #define SPI_CTL0_DSS_BITS_12 0x0000000BU
1382 #define SPI_CTL0_DSS_BITS_13 0x0000000CU
1383 #define SPI_CTL0_DSS_BITS_14 0x0000000DU
1384 #define SPI_CTL0_DSS_BITS_15 0x0000000EU
1385 #define SPI_CTL0_DSS_BITS_16 0x0000000FU
1386 /*
1387 
1388  Field: FRF
1389  From..to bits: 5...6
1390  DefaultValue: 0x0
1391  Access type: read-write
1392  Description: Frame format select
1393 
1394  ENUMs:
1395  MOTOROLA_3WIRE: Motorola SPI frame format (3 wire mode)
1396  MOTOROLA_4WIRE: Motorola SPI frame format (4 wire mode)
1397  TI_SYNC: TI synchronous serial frame format
1398  MICROWIRE: National Microwire frame format
1399 */
1400 #define SPI_CTL0_FRF_W 2U
1401 #define SPI_CTL0_FRF_M 0x00000060U
1402 #define SPI_CTL0_FRF_S 5U
1403 #define SPI_CTL0_FRF_MOTOROLA_3WIRE 0x00000000U
1404 #define SPI_CTL0_FRF_MOTOROLA_4WIRE 0x00000020U
1405 #define SPI_CTL0_FRF_TI_SYNC 0x00000040U
1406 #define SPI_CTL0_FRF_MICROWIRE 0x00000060U
1407 /*
1408 
1409  Field: SPO
1410  From..to bits: 8...8
1411  DefaultValue: 0x0
1412  Access type: read-write
1413  Description: CLKOUT polarity (Motorola SPI frame format only).
1414 
1415  ENUMs:
1416  LOW: SPI produces a steady state LOW value on the CLKOUT
1417  HIGH: SPI produces a steady state HIGH value on the CLKOUT
1418 */
1419 #define SPI_CTL0_SPO 0x00000100U
1420 #define SPI_CTL0_SPO_M 0x00000100U
1421 #define SPI_CTL0_SPO_S 8U
1422 #define SPI_CTL0_SPO_LOW 0x00000000U
1423 #define SPI_CTL0_SPO_HIGH 0x00000100U
1424 /*
1425 
1426  Field: SPH
1427  From..to bits: 9...9
1428  DefaultValue: 0x0
1429  Access type: read-write
1430  Description: CLKOUT phase (Motorola SPI frame format only).
1431  This bit selects the clock edge that captures data and enables it to change state.
1432  It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture clock edge.
1433 
1434  ENUMs:
1435  FIRST: Data is captured on the first clock edge transition.
1436  SECOND: Data is captured on the second clock edge transition.
1437 */
1438 #define SPI_CTL0_SPH 0x00000200U
1439 #define SPI_CTL0_SPH_M 0x00000200U
1440 #define SPI_CTL0_SPH_S 9U
1441 #define SPI_CTL0_SPH_FIRST 0x00000000U
1442 #define SPI_CTL0_SPH_SECOND 0x00000200U
1443 /*
1444 
1445  Field: HWCSN
1446  From..to bits: 10...10
1447  DefaultValue: 0x0
1448  Access type: read-write
1449  Description: Hardware controlled chip select (CS) value. When set CS is zero till TX FIFO is empty, as in -
1450  a. CS is de-asserted
1451  b. All data bytes are transmitted
1452  c. CS is asserted
1453 
1454  ENUMs:
1455  ENABLE: HWCS Enable
1456  DISABLE: HWCS Disable
1457 */
1458 #define SPI_CTL0_HWCSN 0x00000400U
1459 #define SPI_CTL0_HWCSN_M 0x00000400U
1460 #define SPI_CTL0_HWCSN_S 10U
1461 #define SPI_CTL0_HWCSN_ENABLE 0x00000400U
1462 #define SPI_CTL0_HWCSN_DISABLE 0x00000000U
1463 /*
1464 
1465  Field: FIFORST
1466  From..to bits: 11...11
1467  DefaultValue: 0x0
1468  Access type: read-write
1469  Description: This bit is used to reset transmit and receive FIFO pointers. This bit is auto cleared once the FIFO pointer reset operation is completed.
1470 
1471  ENUMs:
1472  RST_DONE: FIFO pointers reset completed when 0 is read
1473  RST_TRIG: Trigger FIFO pointers reset when written to 1.
1474 */
1475 #define SPI_CTL0_FIFORST 0x00000800U
1476 #define SPI_CTL0_FIFORST_M 0x00000800U
1477 #define SPI_CTL0_FIFORST_S 11U
1478 #define SPI_CTL0_FIFORST_RST_DONE 0x00000000U
1479 #define SPI_CTL0_FIFORST_RST_TRIG 0x00000800U
1480 /*
1481 
1482  Field: CSCLR
1483  From..to bits: 12...12
1484  DefaultValue: 0x0
1485  Access type: read-write
1486  Description: Clear shift register counter on CS inactive.
1487  This bit is relevant only in the peripheral mode, when [CTL1.MS]=0.
1488 
1489  ENUMs:
1490  DISABLE: Disable automatic clear of shift register when CS goes inactive.
1491  ENABLE: Enable automatic clear of shift register when CS goes inactive.
1492 */
1493 #define SPI_CTL0_CSCLR 0x00001000U
1494 #define SPI_CTL0_CSCLR_M 0x00001000U
1495 #define SPI_CTL0_CSCLR_S 12U
1496 #define SPI_CTL0_CSCLR_DISABLE 0x00000000U
1497 #define SPI_CTL0_CSCLR_ENABLE 0x00001000U
1498 /*
1499 
1500  Field: CRCEND
1501  From..to bits: 13...13
1502  DefaultValue: 0x0
1503  Access type: read-write
1504  Description: CRC16 Endianness
1505 
1506  ENUMs:
1507  CRC_END_MSB: Auto-insertion of CRC16 is most-significant byte first
1508  CRC_END_LSB: Auto-insertion of CRC16 is least-significant byte first
1509 */
1510 #define SPI_CTL0_CRCEND 0x00002000U
1511 #define SPI_CTL0_CRCEND_M 0x00002000U
1512 #define SPI_CTL0_CRCEND_S 13U
1513 #define SPI_CTL0_CRCEND_CRC_END_MSB 0x00000000U
1514 #define SPI_CTL0_CRCEND_CRC_END_LSB 0x00002000U
1515 /*
1516 
1517  Field: AUTOCRC
1518  From..to bits: 14...14
1519  DefaultValue: 0x0
1520  Access type: read-write
1521  Description: Auto insert CRC
1522 
1523  ENUMs:
1524  DISABLE: Do not insert CRC into TXFIFO upon TXFIFO underflow
1525 
1526  ENABLE: Insert CRC into TXFIFO upon TXFIFO underflow
1527 */
1528 #define SPI_CTL0_AUTOCRC 0x00004000U
1529 #define SPI_CTL0_AUTOCRC_M 0x00004000U
1530 #define SPI_CTL0_AUTOCRC_S 14U
1531 #define SPI_CTL0_AUTOCRC_DISABLE 0x00000000U
1532 #define SPI_CTL0_AUTOCRC_ENABLE 0x00004000U
1533 /*
1534 
1535  Field: CRCPOLY
1536  From..to bits: 15...15
1537  DefaultValue: 0x0
1538  Access type: read-write
1539  Description: CRC polynomial selection.
1540 
1541  ENUMs:
1542  _8BIT: Selects 8-bit CCITT CRC polynomial
1543  _16BIT: Selects 16-bit CCITT CRC polynomial
1544 */
1545 #define SPI_CTL0_CRCPOLY 0x00008000U
1546 #define SPI_CTL0_CRCPOLY_M 0x00008000U
1547 #define SPI_CTL0_CRCPOLY_S 15U
1548 #define SPI_CTL0_CRCPOLY__8BIT 0x00000000U
1549 #define SPI_CTL0_CRCPOLY__16BIT 0x00008000U
1550 /*
1551 
1552  Field: GPCRCEN
1553  From..to bits: 16...16
1554  DefaultValue: 0x0
1555  Access type: read-write
1556  Description: General purpose CRC enable. This bit enables transmit side CRC unit for general purpose use by software when SPI is disabled ([CTL1.EN] = 0). This bit must be 0 when SPI is enabled.
1557 
1558  ENUMs:
1559  DISABLE: Transmit side CRC unit is not available for general purpose software use
1560  ENABLE: Transmit side CRC unit is available for general purpose software use
1561 */
1562 #define SPI_CTL0_GPCRCEN 0x00010000U
1563 #define SPI_CTL0_GPCRCEN_M 0x00010000U
1564 #define SPI_CTL0_GPCRCEN_S 16U
1565 #define SPI_CTL0_GPCRCEN_DISABLE 0x00000000U
1566 #define SPI_CTL0_GPCRCEN_ENABLE 0x00010000U
1567 /*
1568 
1569  Field: IDLEPOCI
1570  From..to bits: 17...17
1571  DefaultValue: 0x0
1572  Access type: read-write
1573  Description: The Idle value of POCI - when TXFIFO is empty and before data is written into TXFIFO - can be controlled by this field.
1574 
1575  ENUMs:
1576  IDLE_ZERO: POCI output idle value of '0'
1577  IDLE_ONE: POCI outputs idle value of '1'
1578 */
1579 #define SPI_CTL0_IDLEPOCI 0x00020000U
1580 #define SPI_CTL0_IDLEPOCI_M 0x00020000U
1581 #define SPI_CTL0_IDLEPOCI_S 17U
1582 #define SPI_CTL0_IDLEPOCI_IDLE_ZERO 0x00000000U
1583 #define SPI_CTL0_IDLEPOCI_IDLE_ONE 0x00020000U
1584 /*
1585 
1586  Field: CSSEL
1587  From..to bits: 18...19
1588  DefaultValue: 0x0
1589  Access type: read-write
1590  Description: CS select for Multi SPI support
1591  00 - CS0
1592  01 - CS1
1593  10 - CS2
1594  11 - CS3
1595 
1596  ENUMs:
1597  CS0: Select CS0
1598  CS1: Select CS1
1599  CS2: Select CS2
1600  CS3: Select CS3
1601 */
1602 #define SPI_CTL0_CSSEL_W 2U
1603 #define SPI_CTL0_CSSEL_M 0x000C0000U
1604 #define SPI_CTL0_CSSEL_S 18U
1605 #define SPI_CTL0_CSSEL_CS0 0x00000000U
1606 #define SPI_CTL0_CSSEL_CS1 0x00040000U
1607 #define SPI_CTL0_CSSEL_CS2 0x00080000U
1608 #define SPI_CTL0_CSSEL_CS3 0x000C0000U
1609 
1610 
1611 /*-----------------------------------REGISTER------------------------------------
1612  Register name: CTL1
1613  Offset name: SPI_O_CTL1
1614  Relative address: 0x104
1615  Description: SPI control register 1
1616  Default Value: 0x00000004
1617 
1618  Field: EN
1619  From..to bits: 0...0
1620  DefaultValue: 0x0
1621  Access type: read-write
1622  Description: SPI enable.
1623 
1624  ENUMs:
1625  DISABLE: SPI is disabled
1626  ENABLE: SPI Enabled and released for operation.
1627 */
1628 #define SPI_CTL1_EN 0x00000001U
1629 #define SPI_CTL1_EN_M 0x00000001U
1630 #define SPI_CTL1_EN_S 0U
1631 #define SPI_CTL1_EN_DISABLE 0x00000000U
1632 #define SPI_CTL1_EN_ENABLE 0x00000001U
1633 /*
1634 
1635  Field: LBM
1636  From..to bits: 1...1
1637  DefaultValue: 0x0
1638  Access type: read-write
1639  Description: Loop back mode control
1640 
1641  ENUMs:
1642  DISABLE: Disable loopback mode. Normal serial port operation enabled.
1643  ENABLE: Enable loopback mode. Output of transmit serial shifter is connected to input of receive serial shifter internally.
1644 */
1645 #define SPI_CTL1_LBM 0x00000002U
1646 #define SPI_CTL1_LBM_M 0x00000002U
1647 #define SPI_CTL1_LBM_S 1U
1648 #define SPI_CTL1_LBM_DISABLE 0x00000000U
1649 #define SPI_CTL1_LBM_ENABLE 0x00000002U
1650 /*
1651 
1652  Field: MS
1653  From..to bits: 2...2
1654  DefaultValue: 0x1
1655  Access type: read-write
1656  Description: Controller or peripheral mode select. This bit can be modified only when SPI is disabled, [CTL1.EN]=0.
1657 
1658  ENUMs:
1659  PERIPHERAL: Select Peripheral mode
1660  CONTROLLER: Select Controller mode
1661 */
1662 #define SPI_CTL1_MS 0x00000004U
1663 #define SPI_CTL1_MS_M 0x00000004U
1664 #define SPI_CTL1_MS_S 2U
1665 #define SPI_CTL1_MS_PERIPHERAL 0x00000000U
1666 #define SPI_CTL1_MS_CONTROLLER 0x00000004U
1667 /*
1668 
1669  Field: POD
1670  From..to bits: 3...3
1671  DefaultValue: 0x0
1672  Access type: read-write
1673  Description: Peripheral data output disable.
1674  This bit is relevant only in the peripheral mode, [MS]=1. In multiple-peripheral systems, it is possible for a SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the POCI lines from multiple peripherals could be tied together. To operate in such systems, this bit field can be set if the SPI peripheral is not supposed to drive the POCI output.
1675 
1676  ENUMs:
1677  DISABLE: SPI can drive the POCI output in peripheral mode.
1678  ENABLE: SPI cannot drive the POCI output in peripheral mode.
1679 */
1680 #define SPI_CTL1_POD 0x00000008U
1681 #define SPI_CTL1_POD_M 0x00000008U
1682 #define SPI_CTL1_POD_S 3U
1683 #define SPI_CTL1_POD_DISABLE 0x00000000U
1684 #define SPI_CTL1_POD_ENABLE 0x00000008U
1685 /*
1686 
1687  Field: MSB
1688  From..to bits: 4...4
1689  DefaultValue: 0x0
1690  Access type: read-write
1691  Description: MSB first select. Controls the direction of receive and transmit shift register. MSB first configuration (MSB = 1) must be selected when CRC feature is used for SPI communication.
1692 
1693  ENUMs:
1694  LSB: LSB first
1695  MSB: MSB first
1696 */
1697 #define SPI_CTL1_MSB 0x00000010U
1698 #define SPI_CTL1_MSB_M 0x00000010U
1699 #define SPI_CTL1_MSB_S 4U
1700 #define SPI_CTL1_MSB_LSB 0x00000000U
1701 #define SPI_CTL1_MSB_MSB 0x00000010U
1702 /*
1703 
1704  Field: PEN
1705  From..to bits: 5...5
1706  DefaultValue: 0x0
1707  Access type: read-write
1708  Description: Parity enable. If enabled the last bit will be used as parity to evaluate the correct reception of the previous bits.
1709  In case of parity mismatch the parity error flag [RIS.PER] will be set. This feature is available only in SPI controller mode.
1710 
1711  ENUMs:
1712  DISABLE: Disable Parity function
1713  ENABLE: Enable Parity function
1714 */
1715 #define SPI_CTL1_PEN 0x00000020U
1716 #define SPI_CTL1_PEN_M 0x00000020U
1717 #define SPI_CTL1_PEN_S 5U
1718 #define SPI_CTL1_PEN_DISABLE 0x00000000U
1719 #define SPI_CTL1_PEN_ENABLE 0x00000020U
1720 /*
1721 
1722  Field: PES
1723  From..to bits: 6...6
1724  DefaultValue: 0x0
1725  Access type: read-write
1726  Description: Even parity select.
1727 
1728  ENUMs:
1729  ODD: Odd Parity mode
1730  EVEN: Even Parity mode
1731 */
1732 #define SPI_CTL1_PES 0x00000040U
1733 #define SPI_CTL1_PES_M 0x00000040U
1734 #define SPI_CTL1_PES_S 6U
1735 #define SPI_CTL1_PES_ODD 0x00000000U
1736 #define SPI_CTL1_PES_EVEN 0x00000040U
1737 /*
1738 
1739  Field: PBS
1740  From..to bits: 7...7
1741  DefaultValue: 0x0
1742  Access type: read-write
1743  Description: Parity bit select
1744 
1745  ENUMs:
1746  BIT0: Bit 0 is used for Parity
1747  BIT1: Bit 1 is used for Parity, Bit 0 is ignored
1748 */
1749 #define SPI_CTL1_PBS 0x00000080U
1750 #define SPI_CTL1_PBS_M 0x00000080U
1751 #define SPI_CTL1_PBS_S 7U
1752 #define SPI_CTL1_PBS_BIT0 0x00000000U
1753 #define SPI_CTL1_PBS_BIT1 0x00000080U
1754 /*
1755 
1756  Field: CDEN
1757  From..to bits: 11...11
1758  DefaultValue: 0x0
1759  Access type: read-write
1760  Description: Command/Data mode enable. This feature is applicable only in controller mode and for 8-bit transfers ([CTL0.DSS] = 7). The chip select pin is used for command/data signaling in Motorola SPI frame format (3-wire) operation.
1761 
1762  ENUMs:
1763  DISABLE: C/D Mode Disable
1764  ENABLE: C/D Mode Enable
1765 */
1766 #define SPI_CTL1_CDEN 0x00000800U
1767 #define SPI_CTL1_CDEN_M 0x00000800U
1768 #define SPI_CTL1_CDEN_S 11U
1769 #define SPI_CTL1_CDEN_DISABLE 0x00000000U
1770 #define SPI_CTL1_CDEN_ENABLE 0x00000800U
1771 /*
1772 
1773  Field: CDMODE
1774  From..to bits: 12...15
1775  DefaultValue: 0x0
1776  Access type: read-write
1777  Description: Command Data Mode. This bit field value determines the behavior of C/D or CS signal when [CDEN] = 1. CS pin held low indicates command phase and CS pin held high indicates data phase.
1778  When [CDMODE] = 0x0, the CS pin is always held high during transfer indicating data phase only operation (manual mode).
1779  When [CDMODE] = 0xF, the CS pin is always held low during transfer indicating command phase only operation (manual mode).
1780  When [CDMODE] = 0x1 to 0xE, the CS pin is held low for the number of bytes indicated by [CDMODE] value for the command phase and held high for the remaining transfers in the data phase (automatic mode).
1781  When [CDMODE] is set to value 0x1 to 0xE, reading [CDMODE] during operation indicates the remaining bytes to be transferred in the command phase.
1782 
1783  ENUMs:
1784  COMMAND: Manual mode: Command
1785  DATA: Manual mode: Data
1786 */
1787 #define SPI_CTL1_CDMODE_W 4U
1788 #define SPI_CTL1_CDMODE_M 0x0000F000U
1789 #define SPI_CTL1_CDMODE_S 12U
1790 #define SPI_CTL1_CDMODE_COMMAND 0x0000F000U
1791 #define SPI_CTL1_CDMODE_DATA 0x00000000U
1792 /*
1793 
1794  Field: REPTX
1795  From..to bits: 16...23
1796  DefaultValue: 0x0
1797  Access type: read-write
1798  Description: Counter to repeat last transfer
1799  0: repeat last transfer is disabled.
1800  x: repeat the last transfer with the provided value.
1801  The transfer will be started with writing a data into the TX FIFO. Sending the data will be repeated provided value number of times, so the data will be transferred x+1 times in total.
1802  The behavior would be as if the data were be written into the TX FIFO as many times as defined by the value here additionally.
1803  It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
1804 
1805  ENUMs:
1806  DISABLE: REPTX disable
1807 */
1808 #define SPI_CTL1_REPTX_W 8U
1809 #define SPI_CTL1_REPTX_M 0x00FF0000U
1810 #define SPI_CTL1_REPTX_S 16U
1811 #define SPI_CTL1_REPTX_DISABLE 0x00000000U
1812 /*
1813 
1814  Field: RTOUT
1815  From..to bits: 24...29
1816  DefaultValue: 0x0
1817  Access type: read-write
1818  Description: Receive Timeout (only for Peripheral mode)
1819  Defines the number of Clock Cycles before after which the Receive Timeout flag [RIS.RTOUT] is set.
1820  The time is calculated using the control register for the clock selection and divider in the Controller mode configuration.
1821  A value of 0 disables this function.
1822 
1823 */
1824 #define SPI_CTL1_RTOUT_W 6U
1825 #define SPI_CTL1_RTOUT_M 0x3F000000U
1826 #define SPI_CTL1_RTOUT_S 24U
1827 
1828 
1829 /*-----------------------------------REGISTER------------------------------------
1830  Register name: CLKCFG0
1831  Offset name: SPI_O_CLKCFG0
1832  Relative address: 0x108
1833  Description: Clock configuration register 0. This register is used to configure the clock prescaler.
1834  Default Value: 0x00000000
1835 
1836  Field: PRESC
1837  From..to bits: 0...2
1838  DefaultValue: 0x0
1839  Access type: read-write
1840  Description: Prescaler configuration
1841 
1842  ENUMs:
1843  DIV_BY_1: Do not divide clock source
1844  DIV_BY_2: Divide clock source by 2
1845  DIV_BY_3: Divide clock source by 3
1846  DIV_BY_4: Divide clock source by 4
1847  DIV_BY_5: Divide clock source by 5
1848  DIV_BY_6: Divide clock source by 6
1849  DIV_BY_7: Divide clock source by 7
1850  DIV_BY_8: Divide clock source by 8
1851 */
1852 #define SPI_CLKCFG0_PRESC_W 3U
1853 #define SPI_CLKCFG0_PRESC_M 0x00000007U
1854 #define SPI_CLKCFG0_PRESC_S 0U
1855 #define SPI_CLKCFG0_PRESC_DIV_BY_1 0x00000000U
1856 #define SPI_CLKCFG0_PRESC_DIV_BY_2 0x00000001U
1857 #define SPI_CLKCFG0_PRESC_DIV_BY_3 0x00000002U
1858 #define SPI_CLKCFG0_PRESC_DIV_BY_4 0x00000003U
1859 #define SPI_CLKCFG0_PRESC_DIV_BY_5 0x00000004U
1860 #define SPI_CLKCFG0_PRESC_DIV_BY_6 0x00000005U
1861 #define SPI_CLKCFG0_PRESC_DIV_BY_7 0x00000006U
1862 #define SPI_CLKCFG0_PRESC_DIV_BY_8 0x00000007U
1863 
1864 
1865 /*-----------------------------------REGISTER------------------------------------
1866  Register name: CLKCFG1
1867  Offset name: SPI_O_CLKCFG1
1868  Relative address: 0x10C
1869  Description: Clock configuration register 1. This register is used to configure serial clock rate and clock count for delayed sampling in controller mode.
1870  Default Value: 0x00000000
1871 
1872  Field: SCR
1873  From..to bits: 0...9
1874  DefaultValue: 0x0
1875  Access type: read-write
1876  Description: Serial clock divider. This is used to generate the transmit and receive bit rate of the SPI.
1877  The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*2). SCR value can be from 0 to 1023.
1878 
1879 */
1880 #define SPI_CLKCFG1_SCR_W 10U
1881 #define SPI_CLKCFG1_SCR_M 0x000003FFU
1882 #define SPI_CLKCFG1_SCR_S 0U
1883 /*
1884 
1885  Field: DSAMPLE
1886  From..to bits: 16...19
1887  DefaultValue: 0x0
1888  Access type: read-write
1889  Description: Delayed sampling. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles. DSAMPLE values can range from 0 to SCR+1. Typically, values of 1 or 2 would suffice.
1890 
1891 */
1892 #define SPI_CLKCFG1_DSAMPLE_W 4U
1893 #define SPI_CLKCFG1_DSAMPLE_M 0x000F0000U
1894 #define SPI_CLKCFG1_DSAMPLE_S 16U
1895 
1896 
1897 /*-----------------------------------REGISTER------------------------------------
1898  Register name: IFLS
1899  Offset name: SPI_O_IFLS
1900  Relative address: 0x110
1901  Description: Interrupt FIFO level select register. This register can be used to define the levels at which the [RIS.TX], [RIS.RX] flags are triggered. The interrupts are generated based on FIFO level. Out of reset, the [IFLS.TXSEL] and [IFLS.RXSEL] bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
1902  Default Value: 0x00000202
1903 
1904  Field: TXSEL
1905  From..to bits: 0...2
1906  DefaultValue: 0x2
1907  Access type: read-write
1908  Description: Transmit FIFO Level Select. The trigger points for the transmit interrupt are as follows:
1909 
1910  ENUMs:
1911  LVL_OFF: Reserved
1912  LVL_3_4: TX FIFO <= 3/4 empty
1913  LVL_1_2: TX FIFO <= 1/2 empty (default)
1914  LVL_1_4: TX FIFO <= 1/4 empty
1915  LVL_RES4: Reserved
1916  LVL_EMPTY: TX FIFO is empty
1917  LVL_RES6: Reserved
1918  LEVEL_1: Trigger when TX FIFO has >= 1 byte free
1919 */
1920 #define SPI_IFLS_TXSEL_W 3U
1921 #define SPI_IFLS_TXSEL_M 0x00000007U
1922 #define SPI_IFLS_TXSEL_S 0U
1923 #define SPI_IFLS_TXSEL_LVL_OFF 0x00000000U
1924 #define SPI_IFLS_TXSEL_LVL_3_4 0x00000001U
1925 #define SPI_IFLS_TXSEL_LVL_1_2 0x00000002U
1926 #define SPI_IFLS_TXSEL_LVL_1_4 0x00000003U
1927 #define SPI_IFLS_TXSEL_LVL_RES4 0x00000004U
1928 #define SPI_IFLS_TXSEL_LVL_EMPTY 0x00000005U
1929 #define SPI_IFLS_TXSEL_LVL_RES6 0x00000006U
1930 #define SPI_IFLS_TXSEL_LEVEL_1 0x00000007U
1931 /*
1932 
1933  Field: RXSEL
1934  From..to bits: 8...10
1935  DefaultValue: 0x2
1936  Access type: read-write
1937  Description: Receive FIFO Level Select. The trigger points for the receive interrupt are as follows:
1938 
1939  ENUMs:
1940  LVL_OFF: Reserved
1941  LVL_1_4: RX FIFO >= 1/4 full
1942  LVL_1_2: RX FIFO >= 1/2 full (default)
1943  LVL_3_4: RX FIFO >= 3/4 full
1944  LVL_RES4: Reserved
1945  LVL_FULL: RX FIFO is full
1946  LVL_RES6: Reserved
1947  LEVEL_1: Trigger when RX FIFO contains >= 1 byte
1948 
1949 */
1950 #define SPI_IFLS_RXSEL_W 3U
1951 #define SPI_IFLS_RXSEL_M 0x00000700U
1952 #define SPI_IFLS_RXSEL_S 8U
1953 #define SPI_IFLS_RXSEL_LVL_OFF 0x00000000U
1954 #define SPI_IFLS_RXSEL_LVL_1_4 0x00000100U
1955 #define SPI_IFLS_RXSEL_LVL_1_2 0x00000200U
1956 #define SPI_IFLS_RXSEL_LVL_3_4 0x00000300U
1957 #define SPI_IFLS_RXSEL_LVL_RES4 0x00000400U
1958 #define SPI_IFLS_RXSEL_LVL_FULL 0x00000500U
1959 #define SPI_IFLS_RXSEL_LVL_RES6 0x00000600U
1960 #define SPI_IFLS_RXSEL_LEVEL_1 0x00000700U
1961 
1962 
1963 /*-----------------------------------REGISTER------------------------------------
1964  Register name: DMACR
1965  Offset name: SPI_O_DMACR
1966  Relative address: 0x114
1967  Description: DMA Control Register
1968  Default Value: 0x00000000
1969 
1970  Field: RXEN
1971  From..to bits: 0...0
1972  DefaultValue: 0x0
1973  Access type: read-write
1974  Description: Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
1975 
1976  ENUMs:
1977  DISABLE: Disable RX DMA
1978  ENABLE: Enable RX DMA
1979 */
1980 #define SPI_DMACR_RXEN 0x00000001U
1981 #define SPI_DMACR_RXEN_M 0x00000001U
1982 #define SPI_DMACR_RXEN_S 0U
1983 #define SPI_DMACR_RXEN_DISABLE 0x00000000U
1984 #define SPI_DMACR_RXEN_ENABLE 0x00000001U
1985 /*
1986 
1987  Field: TXEN
1988  From..to bits: 8...8
1989  DefaultValue: 0x0
1990  Access type: read-write
1991  Description: Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
1992 
1993  ENUMs:
1994  DISABLE: Disable TX DMA
1995  ENABLE: Enable TX DMA
1996 */
1997 #define SPI_DMACR_TXEN 0x00000100U
1998 #define SPI_DMACR_TXEN_M 0x00000100U
1999 #define SPI_DMACR_TXEN_S 8U
2000 #define SPI_DMACR_TXEN_DISABLE 0x00000000U
2001 #define SPI_DMACR_TXEN_ENABLE 0x00000100U
2002 
2003 
2004 /*-----------------------------------REGISTER------------------------------------
2005  Register name: RXCRC
2006  Offset name: SPI_O_RXCRC
2007  Relative address: 0x118
2008  Description: Receive CRC register. Reading this register provides the computed CRC value from the receive side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when [CTL0.CRCPOLY] = 0 and 0xFFFF when [CTL0.CRCPOLY] = 1 for CCITT CRC polynomials. Bits[15:8] are a don't care when [CTL0.CRCPOLY] = 0.
2009  Default Value: 0x00000000
2010 
2011  Field: DATA
2012  From..to bits: 0...15
2013  DefaultValue: 0x0
2014  Access type: read-write
2015  Description: CRC value
2016 
2017 */
2018 #define SPI_RXCRC_DATA_W 16U
2019 #define SPI_RXCRC_DATA_M 0x0000FFFFU
2020 #define SPI_RXCRC_DATA_S 0U
2021 
2022 
2023 /*-----------------------------------REGISTER------------------------------------
2024  Register name: TXCRC
2025  Offset name: SPI_O_TXCRC
2026  Relative address: 0x11C
2027  Description: Transmit CRC register. Reading this register provides the computed CRC value from the transmit side CRC unit. Reading this register or writing to this register with any value auto initializes the seed. The seed value is 0xFF when [CTL0.CRCPOLY] = 0 and 0xFFFF when [CTL0.CRCPOLY] = 1 for CCITT CRC polynomials. Bits[15:8] are a don't care when [CTL0.CRCPOLY] = 0.
2028  Default Value: 0x00000000
2029 
2030  Field: DATA
2031  From..to bits: 0...15
2032  DefaultValue: 0x0
2033  Access type: read-write
2034  Description: CRC value
2035 
2036 */
2037 #define SPI_TXCRC_DATA_W 16U
2038 #define SPI_TXCRC_DATA_M 0x0000FFFFU
2039 #define SPI_TXCRC_DATA_S 0U
2040 /*
2041 
2042  Field: AUTOCRCINS
2043  From..to bits: 31...31
2044  DefaultValue: 0x0
2045  Access type: read-only
2046  Description: Status to indicate if Auto CRC has been inserted into TXFIFO.
2047  This is applicable only if [CTL0.AUTOCRC] enable bit is set
2048 
2049  ENUMs:
2050  NOT_INSERTED: Auto CRC not yet inserted
2051  INSERTED: Auto CRC inserted
2052 */
2053 #define SPI_TXCRC_AUTOCRCINS 0x80000000U
2054 #define SPI_TXCRC_AUTOCRCINS_M 0x80000000U
2055 #define SPI_TXCRC_AUTOCRCINS_S 31U
2056 #define SPI_TXCRC_AUTOCRCINS_NOT_INSERTED 0x00000000U
2057 #define SPI_TXCRC_AUTOCRCINS_INSERTED 0x80000000U
2058 
2059 
2060 /*-----------------------------------REGISTER------------------------------------
2061  Register name: TXFHDR32
2062  Offset name: SPI_O_TXFHDR32
2063  Relative address: 0x120
2064  Description: Header update reigster for 32 bits of header data.
2065  Default Value: 0x00000000
2066 
2067  Field: DATA
2068  From..to bits: 0...31
2069  DefaultValue: 0x0
2070  Access type: write-only
2071  Description: This field can be used to write four bytes of header data
2072 
2073 */
2074 #define SPI_TXFHDR32_DATA_W 32U
2075 #define SPI_TXFHDR32_DATA_M 0xFFFFFFFFU
2076 #define SPI_TXFHDR32_DATA_S 0U
2077 
2078 
2079 /*-----------------------------------REGISTER------------------------------------
2080  Register name: TXFHDR24
2081  Offset name: SPI_O_TXFHDR24
2082  Relative address: 0x124
2083  Description: Header update reigster for 24 bits of header data.
2084  Default Value: 0x00000000
2085 
2086  Field: DATA
2087  From..to bits: 0...31
2088  DefaultValue: 0x0
2089  Access type: write-only
2090  Description: This field can be used to write three bytes of header data
2091 
2092 */
2093 #define SPI_TXFHDR24_DATA_W 32U
2094 #define SPI_TXFHDR24_DATA_M 0xFFFFFFFFU
2095 #define SPI_TXFHDR24_DATA_S 0U
2096 
2097 
2098 /*-----------------------------------REGISTER------------------------------------
2099  Register name: TXFHDR16
2100  Offset name: SPI_O_TXFHDR16
2101  Relative address: 0x128
2102  Description: Header update reigster for 16 bits of data.
2103  Default Value: 0x00000000
2104 
2105  Field: DATA
2106  From..to bits: 0...31
2107  DefaultValue: 0x0
2108  Access type: write-only
2109  Description: This field can be used to write two bytes of header data
2110 
2111 */
2112 #define SPI_TXFHDR16_DATA_W 32U
2113 #define SPI_TXFHDR16_DATA_M 0xFFFFFFFFU
2114 #define SPI_TXFHDR16_DATA_S 0U
2115 
2116 
2117 /*-----------------------------------REGISTER------------------------------------
2118  Register name: TXFHDR8
2119  Offset name: SPI_O_TXFHDR8
2120  Relative address: 0x12C
2121  Description: Header update reigster for 8 bits of header data.
2122  Default Value: 0x00000000
2123 
2124  Field: DATA
2125  From..to bits: 0...31
2126  DefaultValue: 0x0
2127  Access type: write-only
2128  Description: This field can be used to write one byte of header data
2129 
2130 */
2131 #define SPI_TXFHDR8_DATA_W 32U
2132 #define SPI_TXFHDR8_DATA_M 0xFFFFFFFFU
2133 #define SPI_TXFHDR8_DATA_S 0U
2134 
2135 
2136 /*-----------------------------------REGISTER------------------------------------
2137  Register name: TXFHDRC
2138  Offset name: SPI_O_TXFHDRC
2139  Relative address: 0x130
2140  Description: Atomic Header control register
2141  Default Value: 0x00000000
2142 
2143  Field: HDREN
2144  From..to bits: 0...0
2145  DefaultValue: 0x0
2146  Access type: read-write
2147  Description: Header enable field. When [CSGATE] is set to BLK, this bit has to be set by software to enable this feature. When [CSGATE] is set to UNBLK, this field is set automatically whenever a write to header update registers occurs [TXFHDRn.*]
2148 
2149  ENUMs:
2150  DISABLE: Atomic header update feature disable
2151  ENABLE: Atomic header update feature enable
2152 */
2153 #define SPI_TXFHDRC_HDREN 0x00000001U
2154 #define SPI_TXFHDRC_HDREN_M 0x00000001U
2155 #define SPI_TXFHDRC_HDREN_S 0U
2156 #define SPI_TXFHDRC_HDREN_DISABLE 0x00000000U
2157 #define SPI_TXFHDRC_HDREN_ENABLE 0x00000001U
2158 /*
2159 
2160  Field: HDRIGN
2161  From..to bits: 1...1
2162  DefaultValue: 0x0
2163  Access type: read-write
2164  Description: Header Ignored field. When [CSGATE] is set to BLK, this bit is set when the last Header update register [TXFHDRn.*] is written when CS is low or [HDRCMT] is already set. When [CSGATE] is set to UNBLK, this bit is set only when the header update register is written when [HDRCMT] is already set. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
2165 
2166  ENUMs:
2167  SET: Header update is ignored
2168  CLEAR: Header update is not ignored
2169 */
2170 #define SPI_TXFHDRC_HDRIGN 0x00000002U
2171 #define SPI_TXFHDRC_HDRIGN_M 0x00000002U
2172 #define SPI_TXFHDRC_HDRIGN_S 1U
2173 #define SPI_TXFHDRC_HDRIGN_SET 0x00000002U
2174 #define SPI_TXFHDRC_HDRIGN_CLEAR 0x00000002U
2175 /*
2176 
2177  Field: HDRCMT
2178  From..to bits: 2...2
2179  DefaultValue: 0x0
2180  Access type: read-write
2181  Description: Header Committed field. This bit is set when the [HDREN] bit is set and CS is sampled low. This bit remains 0 otherwise. When set, this bit can be written to a value of 0 to clear.
2182 
2183  ENUMs:
2184  SET: Header update is committed
2185  CLEAR: Header update is not committed
2186 */
2187 #define SPI_TXFHDRC_HDRCMT 0x00000004U
2188 #define SPI_TXFHDRC_HDRCMT_M 0x00000004U
2189 #define SPI_TXFHDRC_HDRCMT_S 2U
2190 #define SPI_TXFHDRC_HDRCMT_SET 0x00000004U
2191 #define SPI_TXFHDRC_HDRCMT_CLEAR 0x00000000U
2192 /*
2193 
2194  Field: CSGATE
2195  From..to bits: 3...3
2196  DefaultValue: 0x0
2197  Access type: read-write
2198  Description: Chip Select Gating control register. If this bit is set header update register writes are blocked when chip select (CS) is active low, and [HDRIGN] bit is set.
2199  This bit resets to 0.
2200 
2201  ENUMs:
2202  BLOCKED: Header update register writes are blocked when CS is active (low)
2203  UNBLOCKED: The first header update register write is not blocked based on CS active status (low).
2204  If no header update occurred when CS was high (inactive), the first header update is allowed when CS is low (active), and the HDRCMT bit is set. The use case is for the external controller to ensure that the SCLK is not driven during this header update.
2205  If the header is already updated when CS is high and inactive, HDRCMT is set immediately when CS drops to active low state, and header writes when CS is low are ignored even if this UNBLK bit is set.
2206 */
2207 #define SPI_TXFHDRC_CSGATE 0x00000008U
2208 #define SPI_TXFHDRC_CSGATE_M 0x00000008U
2209 #define SPI_TXFHDRC_CSGATE_S 3U
2210 #define SPI_TXFHDRC_CSGATE_BLOCKED 0x00000008U
2211 #define SPI_TXFHDRC_CSGATE_UNBLOCKED 0x00000000U
2212 
2213 
2214 /*-----------------------------------REGISTER------------------------------------
2215  Register name: RXDATA
2216  Offset name: SPI_O_RXDATA
2217  Relative address: 0x140
2218  Description: RXDATA Register. Reading this register returns first value in the RX FIFO. If the FIFO is empty the last read value is returned. Writing has no effect and is ignored.
2219  Default Value: 0x00000000
2220 
2221  Field: DATA
2222  From..to bits: 0...15
2223  DefaultValue: 0x0
2224  Access type: read-only
2225  Description: Received Data. When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer is accessed. As data values are read by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current RX FIFO write pointer.
2226  Received data less than 16 bits is automatically right-justified in the receive buffer.
2227 
2228 */
2229 #define SPI_RXDATA_DATA_W 16U
2230 #define SPI_RXDATA_DATA_M 0x0000FFFFU
2231 #define SPI_RXDATA_DATA_S 0U
2232 
2233 
2234 /*-----------------------------------REGISTER------------------------------------
2235  Register name: TXDATA
2236  Offset name: SPI_O_TXDATA
2237  Relative address: 0x150
2238  Description: TXDATA Register. Writing a value in this register puts the data into the TX FIFO. Reading this register returns the last written value.
2239  Default Value: 0x00000000
2240 
2241  Field: DATA
2242  From..to bits: 0...15
2243  DefaultValue: 0x0
2244  Access type: read-write
2245  Description: Transmit Data. When read, the last entry in the transmit FIFO, pointed to by the current FIFO write pointer is accessed.
2246  When written, the entry in the TX FIFO pointed to by the write pointer, is written to. Data values are read from the transmit FIFO by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the output pin at the programmed bit rate.
2247  When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.
2248 
2249 */
2250 #define SPI_TXDATA_DATA_W 16U
2251 #define SPI_TXDATA_DATA_M 0x0000FFFFU
2252 #define SPI_TXDATA_DATA_S 0U
2253 
2254 
2255 /*-----------------------------------REGISTER------------------------------------
2256  Register name: STA
2257  Offset name: SPI_O_STA
2258  Relative address: 0x160
2259  Description: Status Register
2260  Default Value: 0x00000001
2261 
2262  Field: TFE
2263  From..to bits: 0...0
2264  DefaultValue: 0x1
2265  Access type: read-only
2266  Description: Transmit FIFO empty status.
2267 
2268  ENUMs:
2269  NOT_EMPTY: Transmit FIFO is not empty.
2270  EMPTY: Transmit FIFO is empty.
2271 */
2272 #define SPI_STA_TFE 0x00000001U
2273 #define SPI_STA_TFE_M 0x00000001U
2274 #define SPI_STA_TFE_S 0U
2275 #define SPI_STA_TFE_NOT_EMPTY 0x00000000U
2276 #define SPI_STA_TFE_EMPTY 0x00000001U
2277 /*
2278 
2279  Field: TNF
2280  From..to bits: 1...1
2281  DefaultValue: 0x0
2282  Access type: read-only
2283  Description: Transmit FIFO not full status.
2284 
2285  ENUMs:
2286  NOT_FULL: Transmit FIFO is not full.
2287  FULL: Transmit FIFO is full.
2288 */
2289 #define SPI_STA_TNF 0x00000002U
2290 #define SPI_STA_TNF_M 0x00000002U
2291 #define SPI_STA_TNF_S 1U
2292 #define SPI_STA_TNF_NOT_FULL 0x00000002U
2293 #define SPI_STA_TNF_FULL 0x00000000U
2294 /*
2295 
2296  Field: RFE
2297  From..to bits: 2...2
2298  DefaultValue: 0x0
2299  Access type: read-only
2300  Description: Receive FIFO empty status.
2301 
2302  ENUMs:
2303  NOT_EMPTY: Receive FIFO is not empty.
2304  EMPTY: Receive FIFO is empty.
2305 */
2306 #define SPI_STA_RFE 0x00000004U
2307 #define SPI_STA_RFE_M 0x00000004U
2308 #define SPI_STA_RFE_S 2U
2309 #define SPI_STA_RFE_NOT_EMPTY 0x00000000U
2310 #define SPI_STA_RFE_EMPTY 0x00000004U
2311 /*
2312 
2313  Field: RNF
2314  From..to bits: 3...3
2315  DefaultValue: 0x0
2316  Access type: read-only
2317  Description: Receive FIFO not full status.
2318 
2319  ENUMs:
2320  NOT_FULL: Receive FIFO is not full.
2321  FULL: Receive FIFO is full.
2322 */
2323 #define SPI_STA_RNF 0x00000008U
2324 #define SPI_STA_RNF_M 0x00000008U
2325 #define SPI_STA_RNF_S 3U
2326 #define SPI_STA_RNF_NOT_FULL 0x00000008U
2327 #define SPI_STA_RNF_FULL 0x00000000U
2328 /*
2329 
2330  Field: BUSY
2331  From..to bits: 4...4
2332  DefaultValue: 0x0
2333  Access type: read-only
2334  Description: SPI Busy status
2335 
2336  ENUMs:
2337  ACTIVE: SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
2338  IDLE: SPI is in idle mode.
2339 */
2340 #define SPI_STA_BUSY 0x00000010U
2341 #define SPI_STA_BUSY_M 0x00000010U
2342 #define SPI_STA_BUSY_S 4U
2343 #define SPI_STA_BUSY_ACTIVE 0x00000010U
2344 #define SPI_STA_BUSY_IDLE 0x00000000U
2345 /*
2346 
2347  Field: CSD
2348  From..to bits: 5...5
2349  DefaultValue: 0x0
2350  Access type: read-write
2351  Description: Detection of CS deassertion in the middle of a word transmission results in this error being set. This feature is only available in the peripheral mode.
2352 
2353  ENUMs:
2354  ERROR: An error is generated when CS posedge (deassertion) is detected before the entire word is transmitted.
2355  NO_ERROR: No CS posedge is detected before the entire word has been transmitted.
2356 */
2357 #define SPI_STA_CSD 0x00000020U
2358 #define SPI_STA_CSD_M 0x00000020U
2359 #define SPI_STA_CSD_S 5U
2360 #define SPI_STA_CSD_ERROR 0x00000020U
2361 #define SPI_STA_CSD_NO_ERROR 0x00000000U
2362 /*
2363 
2364  Field: TXDONE
2365  From..to bits: 6...6
2366  DefaultValue: 0x0
2367  Access type: read-write
2368  Description: Transmit done. Indicates whether the last bit left the Shift register after a transmission
2369 
2370  ENUMs:
2371  TRANSMIT_DONE: Last bit has been shifted out, and the transmission is done
2372  TRANSMIT_INPROGRESS: Last bit has not yet left the Shift register, and the transmission is ongoing.
2373 */
2374 #define SPI_STA_TXDONE 0x00000040U
2375 #define SPI_STA_TXDONE_M 0x00000040U
2376 #define SPI_STA_TXDONE_S 6U
2377 #define SPI_STA_TXDONE_TRANSMIT_DONE 0x00000040U
2378 #define SPI_STA_TXDONE_TRANSMIT_INPROGRESS 0x00000000U
2379 /*
2380 
2381  Field: TXFIFOLVL
2382  From..to bits: 8...13
2383  DefaultValue: 0x0
2384  Access type: read-only
2385  Description: Indicates how many locations of TXFIFO are currently filled with data
2386 
2387 */
2388 #define SPI_STA_TXFIFOLVL_W 6U
2389 #define SPI_STA_TXFIFOLVL_M 0x00003F00U
2390 #define SPI_STA_TXFIFOLVL_S 8U
2391 
2392 
2393 /*-----------------------------------REGISTER------------------------------------
2394  Register name: CLKCFG
2395  Offset name: SPI_O_CLKCFG
2396  Relative address: 0x1000
2397  Description: Clock Enable Register
2398  Default Value: 0x00000000
2399 
2400  Field: ENABLE
2401  From..to bits: 0...0
2402  DefaultValue: 0x0
2403  Access type: read-write
2404  Description: SPI main clock Enable
2405 
2406 */
2407 #define SPI_CLKCFG_ENABLE 0x00000001U
2408 #define SPI_CLKCFG_ENABLE_M 0x00000001U
2409 #define SPI_CLKCFG_ENABLE_S 0U
2410 
2411 #endif /* __HW_SPI_H__*/