Macros
#define	SOC_IC_O_PRIO0 0x00000000U

#define	SOC_IC_O_PRIO1 0x00000004U

#define	SOC_IC_O_PRIO2 0x00000008U

#define	SOC_IC_O_PRIO3 0x0000000CU

#define	SOC_IC_O_PRIO4 0x00000010U

#define	SOC_IC_O_ERRSTA1 0x00000014U

#define	SOC_IC_O_ERRSTA2 0x00000018U

#define	SOC_IC_O_ADDRCFG1 0x0000001CU

#define	SOC_IC_O_ADDRCFG2 0x00000020U

#define	SOC_IC_O_ADDRCFG3 0x00000024U

#define	SOC_IC_O_ADDRCFG4 0x00000028U

#define	SOC_IC_O_ADDRSTA1 0x0000002CU

#define	SOC_IC_O_ADDRSTA2 0x00000030U

#define	SOC_IC_O_TOMSTCFG 0x00000034U

#define	SOC_IC_O_TOSLVCFG 0x00000038U

#define	SOC_IC_PRIO0_L3WSOCIC_W 3U

#define	SOC_IC_PRIO0_L3WSOCIC_M 0x00000007U

#define	SOC_IC_PRIO0_L3WSOCIC_S 0U

#define	SOC_IC_PRIO0_L3DMARD_W 3U

#define	SOC_IC_PRIO0_L3DMARD_M 0x00000038U

#define	SOC_IC_PRIO0_L3DMARD_S 3U

#define	SOC_IC_PRIO0_L3DMAWR_W 3U

#define	SOC_IC_PRIO0_L3DMAWR_M 0x000001C0U

#define	SOC_IC_PRIO0_L3DMAWR_S 6U

#define	SOC_IC_PRIO0_L3HMCU_W 3U

#define	SOC_IC_PRIO0_L3HMCU_M 0x00000E00U

#define	SOC_IC_PRIO0_L3HMCU_S 9U

#define	SOC_IC_PRIO0_L3I2S_W 3U

#define	SOC_IC_PRIO0_L3I2S_M 0x00007000U

#define	SOC_IC_PRIO0_L3I2S_S 12U

#define	SOC_IC_PRIO0_L3HSM_W 3U

#define	SOC_IC_PRIO0_L3HSM_M 0x00038000U

#define	SOC_IC_PRIO0_L3HSM_S 15U

#define	SOC_IC_PRIO0_HMCUWSOCIC_W 3U

#define	SOC_IC_PRIO0_HMCUWSOCIC_M 0x001C0000U

#define	SOC_IC_PRIO0_HMCUWSOCIC_S 18U

#define	SOC_IC_PRIO0_HMCUDMARD_W 3U

#define	SOC_IC_PRIO0_HMCUDMARD_M 0x00E00000U

#define	SOC_IC_PRIO0_HMCUDMARD_S 21U

#define	SOC_IC_PRIO0_HMCUDMAWR_W 3U

#define	SOC_IC_PRIO0_HMCUDMAWR_M 0x07000000U

#define	SOC_IC_PRIO0_HMCUDMAWR_S 24U

#define	SOC_IC_PRIO0_HMCUI2S_W 3U

#define	SOC_IC_PRIO0_HMCUI2S_M 0x38000000U

#define	SOC_IC_PRIO0_HMCUI2S_S 27U

#define	SOC_IC_PRIO1_HMCUHSM_W 3U

#define	SOC_IC_PRIO1_HMCUHSM_M 0x00000007U

#define	SOC_IC_PRIO1_HMCUHSM_S 0U

#define	SOC_IC_PRIO1_SPWSOCIC_W 3U

#define	SOC_IC_PRIO1_SPWSOCIC_M 0x00000038U

#define	SOC_IC_PRIO1_SPWSOCIC_S 3U

#define	SOC_IC_PRIO1_SPDMARD_W 3U

#define	SOC_IC_PRIO1_SPDMARD_M 0x000001C0U

#define	SOC_IC_PRIO1_SPDMARD_S 6U

#define	SOC_IC_PRIO1_SPDMAWR_W 3U

#define	SOC_IC_PRIO1_SPDMAWR_M 0x00000E00U

#define	SOC_IC_PRIO1_SPDMAWR_S 9U

#define	SOC_IC_PRIO1_SPHMCU_W 3U

#define	SOC_IC_PRIO1_SPHMCU_M 0x00007000U

#define	SOC_IC_PRIO1_SPHMCU_S 12U

#define	SOC_IC_PRIO1_SPHSM_W 3U

#define	SOC_IC_PRIO1_SPHSM_M 0x00038000U

#define	SOC_IC_PRIO1_SPHSM_S 15U

#define	SOC_IC_PRIO1_COREDMARD_W 3U

#define	SOC_IC_PRIO1_COREDMARD_M 0x001C0000U

#define	SOC_IC_PRIO1_COREDMARD_S 18U

#define	SOC_IC_PRIO1_COREDMAWR_W 3U

#define	SOC_IC_PRIO1_COREDMAWR_M 0x00E00000U

#define	SOC_IC_PRIO1_COREDMAWR_S 21U

#define	SOC_IC_PRIO1_COREHMCU_W 3U

#define	SOC_IC_PRIO1_COREHMCU_M 0x07000000U

#define	SOC_IC_PRIO1_COREHMCU_S 24U

#define	SOC_IC_PRIO1_COREHSM_W 3U

#define	SOC_IC_PRIO1_COREHSM_M 0x38000000U

#define	SOC_IC_PRIO1_COREHSM_S 27U

#define	SOC_IC_PRIO2_XIPWSOCIC_W 3U

#define	SOC_IC_PRIO2_XIPWSOCIC_M 0x00000007U

#define	SOC_IC_PRIO2_XIPWSOCIC_S 0U

#define	SOC_IC_PRIO2_XIPDMARD_W 3U

#define	SOC_IC_PRIO2_XIPDMARD_M 0x00000038U

#define	SOC_IC_PRIO2_XIPDMARD_S 3U

#define	SOC_IC_PRIO2_XIPDMAWR_W 3U

#define	SOC_IC_PRIO2_XIPDMAWR_M 0x000001C0U

#define	SOC_IC_PRIO2_XIPDMAWR_S 6U

#define	SOC_IC_PRIO2_XIPHMCU_W 3U

#define	SOC_IC_PRIO2_XIPHMCU_M 0x00000E00U

#define	SOC_IC_PRIO2_XIPHMCU_S 9U

#define	SOC_IC_PRIO2_XIPHSM_W 3U

#define	SOC_IC_PRIO2_XIPHSM_M 0x00007000U

#define	SOC_IC_PRIO2_XIPHSM_S 12U

#define	SOC_IC_PRIO2_HDMAWSOCIC_W 2U

#define	SOC_IC_PRIO2_HDMAWSOCIC_M 0x00018000U

#define	SOC_IC_PRIO2_HDMAWSOCIC_S 15U

#define	SOC_IC_PRIO2_HDMAHOSTMCU_W 2U

#define	SOC_IC_PRIO2_HDMAHOSTMCU_M 0x00060000U

#define	SOC_IC_PRIO2_HDMAHOSTMCU_S 17U

#define	SOC_IC_PRIO2_HDMAHSM_W 2U

#define	SOC_IC_PRIO2_HDMAHSM_M 0x00180000U

#define	SOC_IC_PRIO2_HDMAHSM_S 19U

#define	SOC_IC_PRIO2_HSMWSOCIC_W 3U

#define	SOC_IC_PRIO2_HSMWSOCIC_M 0x00E00000U

#define	SOC_IC_PRIO2_HSMWSOCIC_S 21U

#define	SOC_IC_PRIO2_HSMDMARD_W 3U

#define	SOC_IC_PRIO2_HSMDMARD_M 0x07000000U

#define	SOC_IC_PRIO2_HSMDMARD_S 24U

#define	SOC_IC_PRIO2_HSMDMAWR_W 3U

#define	SOC_IC_PRIO2_HSMDMAWR_M 0x38000000U

#define	SOC_IC_PRIO2_HSMDMAWR_S 27U

#define	SOC_IC_PRIO3_HSMHMCU_W 3U

#define	SOC_IC_PRIO3_HSMHMCU_M 0x00000007U

#define	SOC_IC_PRIO3_HSMHMCU_S 0U

#define	SOC_IC_PRIO3_A2NDMARD_W 3U

#define	SOC_IC_PRIO3_A2NDMARD_M 0x00000038U

#define	SOC_IC_PRIO3_A2NDMARD_S 3U

#define	SOC_IC_PRIO3_A2NDMAWR_W 3U

#define	SOC_IC_PRIO3_A2NDMAWR_M 0x000001C0U

#define	SOC_IC_PRIO3_A2NDMAWR_S 6U

#define	SOC_IC_PRIO3_A2NHMCU_W 3U

#define	SOC_IC_PRIO3_A2NHMCU_M 0x00000E00U

#define	SOC_IC_PRIO3_A2NHMCU_S 9U

#define	SOC_IC_PRIO3_A2NHSM_W 3U

#define	SOC_IC_PRIO3_A2NHSM_M 0x00007000U

#define	SOC_IC_PRIO3_A2NHSM_S 12U

#define	SOC_IC_PRIO3_HMCUHMCU_W 3U

#define	SOC_IC_PRIO3_HMCUHMCU_M 0x00038000U

#define	SOC_IC_PRIO3_HMCUHMCU_S 15U

#define	SOC_IC_PRIO3_CAONWSOCIC_W 3U

#define	SOC_IC_PRIO3_CAONWSOCIC_M 0x001C0000U

#define	SOC_IC_PRIO3_CAONWSOCIC_S 18U

#define	SOC_IC_PRIO3_CAONHMCU_W 3U

#define	SOC_IC_PRIO3_CAONHMCU_M 0x00E00000U

#define	SOC_IC_PRIO3_CAONHMCU_S 21U

#define	SOC_IC_PRIO3_CAONDMARD_W 3U

#define	SOC_IC_PRIO3_CAONDMARD_M 0x07000000U

#define	SOC_IC_PRIO3_CAONDMARD_S 24U

#define	SOC_IC_PRIO3_CAONDMAWR_W 3U

#define	SOC_IC_PRIO3_CAONDMAWR_M 0x38000000U

#define	SOC_IC_PRIO3_CAONDMAWR_S 27U

#define	SOC_IC_PRIO4_CAONI2S_W 3U

#define	SOC_IC_PRIO4_CAONI2S_M 0x00000007U

#define	SOC_IC_PRIO4_CAONI2S_S 0U

#define	SOC_IC_PRIO4_CAONHSM_W 3U

#define	SOC_IC_PRIO4_CAONHSM_M 0x00000038U

#define	SOC_IC_PRIO4_CAONHSM_S 3U

#define	SOC_IC_ERRSTA1_STA1_W 32U

#define	SOC_IC_ERRSTA1_STA1_M 0xFFFFFFFFU

#define	SOC_IC_ERRSTA1_STA1_S 0U

#define	SOC_IC_ERRSTA2_STA2_W 10U

#define	SOC_IC_ERRSTA2_STA2_M 0x000003FFU

#define	SOC_IC_ERRSTA2_STA2_S 0U

#define	SOC_IC_ADDRCFG1_SEL_W 4U

#define	SOC_IC_ADDRCFG1_SEL_M 0x0000000FU

#define	SOC_IC_ADDRCFG1_SEL_S 0U

#define	SOC_IC_ADDRCFG2_LOW_W 32U

#define	SOC_IC_ADDRCFG2_LOW_M 0xFFFFFFFFU

#define	SOC_IC_ADDRCFG2_LOW_S 0U

#define	SOC_IC_ADDRCFG3_HIGH_W 32U

#define	SOC_IC_ADDRCFG3_HIGH_M 0xFFFFFFFFU

#define	SOC_IC_ADDRCFG3_HIGH_S 0U

#define	SOC_IC_ADDRCFG4_MSTIDWR_W 16U

#define	SOC_IC_ADDRCFG4_MSTIDWR_M 0x0000FFFFU

#define	SOC_IC_ADDRCFG4_MSTIDWR_S 0U

#define	SOC_IC_ADDRCFG4_MSTIDRD_W 16U

#define	SOC_IC_ADDRCFG4_MSTIDRD_M 0xFFFF0000U

#define	SOC_IC_ADDRCFG4_MSTIDRD_S 16U

#define	SOC_IC_ADDRSTA1_STA1_W 32U

#define	SOC_IC_ADDRSTA1_STA1_M 0xFFFFFFFFU

#define	SOC_IC_ADDRSTA1_STA1_S 0U

#define	SOC_IC_ADDRSTA2_STA2_W 5U

#define	SOC_IC_ADDRSTA2_STA2_M 0x0000001FU

#define	SOC_IC_ADDRSTA2_STA2_S 0U

#define	SOC_IC_TOMSTCFG_VAL_W 5U

#define	SOC_IC_TOMSTCFG_VAL_M 0x000001F0U

#define	SOC_IC_TOMSTCFG_VAL_S 4U

#define	SOC_IC_TOMSTCFG_SEL_W 4U

#define	SOC_IC_TOMSTCFG_SEL_M 0x00003C00U

#define	SOC_IC_TOMSTCFG_SEL_S 10U

#define	SOC_IC_TOSLVCFG_VAL_W 5U

#define	SOC_IC_TOSLVCFG_VAL_M 0x000001F0U

#define	SOC_IC_TOSLVCFG_VAL_S 4U

Macro Definition Documentation

§ SOC_IC_O_PRIO0

#define SOC_IC_O_PRIO0 0x00000000U

§ SOC_IC_O_PRIO1

#define SOC_IC_O_PRIO1 0x00000004U

§ SOC_IC_O_PRIO2

#define SOC_IC_O_PRIO2 0x00000008U

§ SOC_IC_O_PRIO3

#define SOC_IC_O_PRIO3 0x0000000CU

§ SOC_IC_O_PRIO4

#define SOC_IC_O_PRIO4 0x00000010U

§ SOC_IC_O_ERRSTA1

#define SOC_IC_O_ERRSTA1 0x00000014U

§ SOC_IC_O_ERRSTA2

#define SOC_IC_O_ERRSTA2 0x00000018U

§ SOC_IC_O_ADDRCFG1

#define SOC_IC_O_ADDRCFG1 0x0000001CU

§ SOC_IC_O_ADDRCFG2

#define SOC_IC_O_ADDRCFG2 0x00000020U

§ SOC_IC_O_ADDRCFG3

#define SOC_IC_O_ADDRCFG3 0x00000024U

§ SOC_IC_O_ADDRCFG4

#define SOC_IC_O_ADDRCFG4 0x00000028U

§ SOC_IC_O_ADDRSTA1

#define SOC_IC_O_ADDRSTA1 0x0000002CU

§ SOC_IC_O_ADDRSTA2

#define SOC_IC_O_ADDRSTA2 0x00000030U

§ SOC_IC_O_TOMSTCFG

#define SOC_IC_O_TOMSTCFG 0x00000034U

§ SOC_IC_O_TOSLVCFG

#define SOC_IC_O_TOSLVCFG 0x00000038U

§ SOC_IC_PRIO0_L3WSOCIC_W

#define SOC_IC_PRIO0_L3WSOCIC_W 3U

§ SOC_IC_PRIO0_L3WSOCIC_M

#define SOC_IC_PRIO0_L3WSOCIC_M 0x00000007U

§ SOC_IC_PRIO0_L3WSOCIC_S

#define SOC_IC_PRIO0_L3WSOCIC_S 0U

§ SOC_IC_PRIO0_L3DMARD_W

#define SOC_IC_PRIO0_L3DMARD_W 3U

§ SOC_IC_PRIO0_L3DMARD_M

#define SOC_IC_PRIO0_L3DMARD_M 0x00000038U

§ SOC_IC_PRIO0_L3DMARD_S

#define SOC_IC_PRIO0_L3DMARD_S 3U

§ SOC_IC_PRIO0_L3DMAWR_W

#define SOC_IC_PRIO0_L3DMAWR_W 3U

§ SOC_IC_PRIO0_L3DMAWR_M

#define SOC_IC_PRIO0_L3DMAWR_M 0x000001C0U

§ SOC_IC_PRIO0_L3DMAWR_S

#define SOC_IC_PRIO0_L3DMAWR_S 6U

§ SOC_IC_PRIO0_L3HMCU_W

#define SOC_IC_PRIO0_L3HMCU_W 3U

§ SOC_IC_PRIO0_L3HMCU_M

#define SOC_IC_PRIO0_L3HMCU_M 0x00000E00U

§ SOC_IC_PRIO0_L3HMCU_S

#define SOC_IC_PRIO0_L3HMCU_S 9U

§ SOC_IC_PRIO0_L3I2S_W

#define SOC_IC_PRIO0_L3I2S_W 3U

§ SOC_IC_PRIO0_L3I2S_M

#define SOC_IC_PRIO0_L3I2S_M 0x00007000U

§ SOC_IC_PRIO0_L3I2S_S

#define SOC_IC_PRIO0_L3I2S_S 12U

§ SOC_IC_PRIO0_L3HSM_W

#define SOC_IC_PRIO0_L3HSM_W 3U

§ SOC_IC_PRIO0_L3HSM_M

#define SOC_IC_PRIO0_L3HSM_M 0x00038000U

§ SOC_IC_PRIO0_L3HSM_S

#define SOC_IC_PRIO0_L3HSM_S 15U

§ SOC_IC_PRIO0_HMCUWSOCIC_W

#define SOC_IC_PRIO0_HMCUWSOCIC_W 3U

§ SOC_IC_PRIO0_HMCUWSOCIC_M

#define SOC_IC_PRIO0_HMCUWSOCIC_M 0x001C0000U

§ SOC_IC_PRIO0_HMCUWSOCIC_S

#define SOC_IC_PRIO0_HMCUWSOCIC_S 18U

§ SOC_IC_PRIO0_HMCUDMARD_W

#define SOC_IC_PRIO0_HMCUDMARD_W 3U

§ SOC_IC_PRIO0_HMCUDMARD_M

#define SOC_IC_PRIO0_HMCUDMARD_M 0x00E00000U

§ SOC_IC_PRIO0_HMCUDMARD_S

#define SOC_IC_PRIO0_HMCUDMARD_S 21U

§ SOC_IC_PRIO0_HMCUDMAWR_W

#define SOC_IC_PRIO0_HMCUDMAWR_W 3U

§ SOC_IC_PRIO0_HMCUDMAWR_M

#define SOC_IC_PRIO0_HMCUDMAWR_M 0x07000000U

§ SOC_IC_PRIO0_HMCUDMAWR_S

#define SOC_IC_PRIO0_HMCUDMAWR_S 24U

§ SOC_IC_PRIO0_HMCUI2S_W

#define SOC_IC_PRIO0_HMCUI2S_W 3U

§ SOC_IC_PRIO0_HMCUI2S_M

#define SOC_IC_PRIO0_HMCUI2S_M 0x38000000U

§ SOC_IC_PRIO0_HMCUI2S_S

#define SOC_IC_PRIO0_HMCUI2S_S 27U

§ SOC_IC_PRIO1_HMCUHSM_W

#define SOC_IC_PRIO1_HMCUHSM_W 3U

§ SOC_IC_PRIO1_HMCUHSM_M

#define SOC_IC_PRIO1_HMCUHSM_M 0x00000007U

§ SOC_IC_PRIO1_HMCUHSM_S

#define SOC_IC_PRIO1_HMCUHSM_S 0U

§ SOC_IC_PRIO1_SPWSOCIC_W

#define SOC_IC_PRIO1_SPWSOCIC_W 3U

§ SOC_IC_PRIO1_SPWSOCIC_M

#define SOC_IC_PRIO1_SPWSOCIC_M 0x00000038U

§ SOC_IC_PRIO1_SPWSOCIC_S

#define SOC_IC_PRIO1_SPWSOCIC_S 3U

§ SOC_IC_PRIO1_SPDMARD_W

#define SOC_IC_PRIO1_SPDMARD_W 3U

§ SOC_IC_PRIO1_SPDMARD_M

#define SOC_IC_PRIO1_SPDMARD_M 0x000001C0U

§ SOC_IC_PRIO1_SPDMARD_S

#define SOC_IC_PRIO1_SPDMARD_S 6U

§ SOC_IC_PRIO1_SPDMAWR_W

#define SOC_IC_PRIO1_SPDMAWR_W 3U

§ SOC_IC_PRIO1_SPDMAWR_M

#define SOC_IC_PRIO1_SPDMAWR_M 0x00000E00U

§ SOC_IC_PRIO1_SPDMAWR_S

#define SOC_IC_PRIO1_SPDMAWR_S 9U

§ SOC_IC_PRIO1_SPHMCU_W

#define SOC_IC_PRIO1_SPHMCU_W 3U

§ SOC_IC_PRIO1_SPHMCU_M

#define SOC_IC_PRIO1_SPHMCU_M 0x00007000U

§ SOC_IC_PRIO1_SPHMCU_S

#define SOC_IC_PRIO1_SPHMCU_S 12U

§ SOC_IC_PRIO1_SPHSM_W

#define SOC_IC_PRIO1_SPHSM_W 3U

§ SOC_IC_PRIO1_SPHSM_M

#define SOC_IC_PRIO1_SPHSM_M 0x00038000U

§ SOC_IC_PRIO1_SPHSM_S

#define SOC_IC_PRIO1_SPHSM_S 15U

§ SOC_IC_PRIO1_COREDMARD_W

#define SOC_IC_PRIO1_COREDMARD_W 3U

§ SOC_IC_PRIO1_COREDMARD_M

#define SOC_IC_PRIO1_COREDMARD_M 0x001C0000U

§ SOC_IC_PRIO1_COREDMARD_S

#define SOC_IC_PRIO1_COREDMARD_S 18U

§ SOC_IC_PRIO1_COREDMAWR_W

#define SOC_IC_PRIO1_COREDMAWR_W 3U

§ SOC_IC_PRIO1_COREDMAWR_M

#define SOC_IC_PRIO1_COREDMAWR_M 0x00E00000U

§ SOC_IC_PRIO1_COREDMAWR_S

#define SOC_IC_PRIO1_COREDMAWR_S 21U

§ SOC_IC_PRIO1_COREHMCU_W

#define SOC_IC_PRIO1_COREHMCU_W 3U

§ SOC_IC_PRIO1_COREHMCU_M

#define SOC_IC_PRIO1_COREHMCU_M 0x07000000U

§ SOC_IC_PRIO1_COREHMCU_S

#define SOC_IC_PRIO1_COREHMCU_S 24U

§ SOC_IC_PRIO1_COREHSM_W

#define SOC_IC_PRIO1_COREHSM_W 3U

§ SOC_IC_PRIO1_COREHSM_M

#define SOC_IC_PRIO1_COREHSM_M 0x38000000U

§ SOC_IC_PRIO1_COREHSM_S

#define SOC_IC_PRIO1_COREHSM_S 27U

§ SOC_IC_PRIO2_XIPWSOCIC_W

#define SOC_IC_PRIO2_XIPWSOCIC_W 3U

§ SOC_IC_PRIO2_XIPWSOCIC_M

#define SOC_IC_PRIO2_XIPWSOCIC_M 0x00000007U

§ SOC_IC_PRIO2_XIPWSOCIC_S

#define SOC_IC_PRIO2_XIPWSOCIC_S 0U

§ SOC_IC_PRIO2_XIPDMARD_W

#define SOC_IC_PRIO2_XIPDMARD_W 3U

§ SOC_IC_PRIO2_XIPDMARD_M

#define SOC_IC_PRIO2_XIPDMARD_M 0x00000038U

§ SOC_IC_PRIO2_XIPDMARD_S

#define SOC_IC_PRIO2_XIPDMARD_S 3U

§ SOC_IC_PRIO2_XIPDMAWR_W

#define SOC_IC_PRIO2_XIPDMAWR_W 3U

§ SOC_IC_PRIO2_XIPDMAWR_M

#define SOC_IC_PRIO2_XIPDMAWR_M 0x000001C0U

§ SOC_IC_PRIO2_XIPDMAWR_S

#define SOC_IC_PRIO2_XIPDMAWR_S 6U

§ SOC_IC_PRIO2_XIPHMCU_W

#define SOC_IC_PRIO2_XIPHMCU_W 3U

§ SOC_IC_PRIO2_XIPHMCU_M

#define SOC_IC_PRIO2_XIPHMCU_M 0x00000E00U

§ SOC_IC_PRIO2_XIPHMCU_S

#define SOC_IC_PRIO2_XIPHMCU_S 9U

§ SOC_IC_PRIO2_XIPHSM_W

#define SOC_IC_PRIO2_XIPHSM_W 3U

§ SOC_IC_PRIO2_XIPHSM_M

#define SOC_IC_PRIO2_XIPHSM_M 0x00007000U

§ SOC_IC_PRIO2_XIPHSM_S

#define SOC_IC_PRIO2_XIPHSM_S 12U

§ SOC_IC_PRIO2_HDMAWSOCIC_W

#define SOC_IC_PRIO2_HDMAWSOCIC_W 2U

§ SOC_IC_PRIO2_HDMAWSOCIC_M

#define SOC_IC_PRIO2_HDMAWSOCIC_M 0x00018000U

§ SOC_IC_PRIO2_HDMAWSOCIC_S

#define SOC_IC_PRIO2_HDMAWSOCIC_S 15U

§ SOC_IC_PRIO2_HDMAHOSTMCU_W

#define SOC_IC_PRIO2_HDMAHOSTMCU_W 2U

§ SOC_IC_PRIO2_HDMAHOSTMCU_M

#define SOC_IC_PRIO2_HDMAHOSTMCU_M 0x00060000U

§ SOC_IC_PRIO2_HDMAHOSTMCU_S

#define SOC_IC_PRIO2_HDMAHOSTMCU_S 17U

§ SOC_IC_PRIO2_HDMAHSM_W

#define SOC_IC_PRIO2_HDMAHSM_W 2U

§ SOC_IC_PRIO2_HDMAHSM_M

#define SOC_IC_PRIO2_HDMAHSM_M 0x00180000U

§ SOC_IC_PRIO2_HDMAHSM_S

#define SOC_IC_PRIO2_HDMAHSM_S 19U

§ SOC_IC_PRIO2_HSMWSOCIC_W

#define SOC_IC_PRIO2_HSMWSOCIC_W 3U

§ SOC_IC_PRIO2_HSMWSOCIC_M

#define SOC_IC_PRIO2_HSMWSOCIC_M 0x00E00000U

§ SOC_IC_PRIO2_HSMWSOCIC_S

#define SOC_IC_PRIO2_HSMWSOCIC_S 21U

§ SOC_IC_PRIO2_HSMDMARD_W

#define SOC_IC_PRIO2_HSMDMARD_W 3U

§ SOC_IC_PRIO2_HSMDMARD_M

#define SOC_IC_PRIO2_HSMDMARD_M 0x07000000U

§ SOC_IC_PRIO2_HSMDMARD_S

#define SOC_IC_PRIO2_HSMDMARD_S 24U

§ SOC_IC_PRIO2_HSMDMAWR_W

#define SOC_IC_PRIO2_HSMDMAWR_W 3U

§ SOC_IC_PRIO2_HSMDMAWR_M

#define SOC_IC_PRIO2_HSMDMAWR_M 0x38000000U

§ SOC_IC_PRIO2_HSMDMAWR_S

#define SOC_IC_PRIO2_HSMDMAWR_S 27U

§ SOC_IC_PRIO3_HSMHMCU_W

#define SOC_IC_PRIO3_HSMHMCU_W 3U

§ SOC_IC_PRIO3_HSMHMCU_M

#define SOC_IC_PRIO3_HSMHMCU_M 0x00000007U

§ SOC_IC_PRIO3_HSMHMCU_S

#define SOC_IC_PRIO3_HSMHMCU_S 0U

§ SOC_IC_PRIO3_A2NDMARD_W

#define SOC_IC_PRIO3_A2NDMARD_W 3U

§ SOC_IC_PRIO3_A2NDMARD_M

#define SOC_IC_PRIO3_A2NDMARD_M 0x00000038U

§ SOC_IC_PRIO3_A2NDMARD_S

#define SOC_IC_PRIO3_A2NDMARD_S 3U

§ SOC_IC_PRIO3_A2NDMAWR_W

#define SOC_IC_PRIO3_A2NDMAWR_W 3U

§ SOC_IC_PRIO3_A2NDMAWR_M

#define SOC_IC_PRIO3_A2NDMAWR_M 0x000001C0U

§ SOC_IC_PRIO3_A2NDMAWR_S

#define SOC_IC_PRIO3_A2NDMAWR_S 6U

§ SOC_IC_PRIO3_A2NHMCU_W

#define SOC_IC_PRIO3_A2NHMCU_W 3U

§ SOC_IC_PRIO3_A2NHMCU_M

#define SOC_IC_PRIO3_A2NHMCU_M 0x00000E00U

§ SOC_IC_PRIO3_A2NHMCU_S

#define SOC_IC_PRIO3_A2NHMCU_S 9U

§ SOC_IC_PRIO3_A2NHSM_W

#define SOC_IC_PRIO3_A2NHSM_W 3U

§ SOC_IC_PRIO3_A2NHSM_M

#define SOC_IC_PRIO3_A2NHSM_M 0x00007000U

§ SOC_IC_PRIO3_A2NHSM_S

#define SOC_IC_PRIO3_A2NHSM_S 12U

§ SOC_IC_PRIO3_HMCUHMCU_W

#define SOC_IC_PRIO3_HMCUHMCU_W 3U

§ SOC_IC_PRIO3_HMCUHMCU_M

#define SOC_IC_PRIO3_HMCUHMCU_M 0x00038000U

§ SOC_IC_PRIO3_HMCUHMCU_S

#define SOC_IC_PRIO3_HMCUHMCU_S 15U

§ SOC_IC_PRIO3_CAONWSOCIC_W

#define SOC_IC_PRIO3_CAONWSOCIC_W 3U

§ SOC_IC_PRIO3_CAONWSOCIC_M

#define SOC_IC_PRIO3_CAONWSOCIC_M 0x001C0000U

§ SOC_IC_PRIO3_CAONWSOCIC_S

#define SOC_IC_PRIO3_CAONWSOCIC_S 18U

§ SOC_IC_PRIO3_CAONHMCU_W

#define SOC_IC_PRIO3_CAONHMCU_W 3U

§ SOC_IC_PRIO3_CAONHMCU_M

#define SOC_IC_PRIO3_CAONHMCU_M 0x00E00000U

§ SOC_IC_PRIO3_CAONHMCU_S

#define SOC_IC_PRIO3_CAONHMCU_S 21U

§ SOC_IC_PRIO3_CAONDMARD_W

#define SOC_IC_PRIO3_CAONDMARD_W 3U

§ SOC_IC_PRIO3_CAONDMARD_M

#define SOC_IC_PRIO3_CAONDMARD_M 0x07000000U

§ SOC_IC_PRIO3_CAONDMARD_S

#define SOC_IC_PRIO3_CAONDMARD_S 24U

§ SOC_IC_PRIO3_CAONDMAWR_W

#define SOC_IC_PRIO3_CAONDMAWR_W 3U

§ SOC_IC_PRIO3_CAONDMAWR_M

#define SOC_IC_PRIO3_CAONDMAWR_M 0x38000000U

§ SOC_IC_PRIO3_CAONDMAWR_S

#define SOC_IC_PRIO3_CAONDMAWR_S 27U

§ SOC_IC_PRIO4_CAONI2S_W

#define SOC_IC_PRIO4_CAONI2S_W 3U

§ SOC_IC_PRIO4_CAONI2S_M

#define SOC_IC_PRIO4_CAONI2S_M 0x00000007U

§ SOC_IC_PRIO4_CAONI2S_S

#define SOC_IC_PRIO4_CAONI2S_S 0U

§ SOC_IC_PRIO4_CAONHSM_W

#define SOC_IC_PRIO4_CAONHSM_W 3U

§ SOC_IC_PRIO4_CAONHSM_M

#define SOC_IC_PRIO4_CAONHSM_M 0x00000038U

§ SOC_IC_PRIO4_CAONHSM_S

#define SOC_IC_PRIO4_CAONHSM_S 3U

§ SOC_IC_ERRSTA1_STA1_W

#define SOC_IC_ERRSTA1_STA1_W 32U

§ SOC_IC_ERRSTA1_STA1_M

#define SOC_IC_ERRSTA1_STA1_M 0xFFFFFFFFU

§ SOC_IC_ERRSTA1_STA1_S

#define SOC_IC_ERRSTA1_STA1_S 0U

§ SOC_IC_ERRSTA2_STA2_W

#define SOC_IC_ERRSTA2_STA2_W 10U

§ SOC_IC_ERRSTA2_STA2_M

#define SOC_IC_ERRSTA2_STA2_M 0x000003FFU

§ SOC_IC_ERRSTA2_STA2_S

#define SOC_IC_ERRSTA2_STA2_S 0U

§ SOC_IC_ADDRCFG1_SEL_W

#define SOC_IC_ADDRCFG1_SEL_W 4U

§ SOC_IC_ADDRCFG1_SEL_M

#define SOC_IC_ADDRCFG1_SEL_M 0x0000000FU

§ SOC_IC_ADDRCFG1_SEL_S

#define SOC_IC_ADDRCFG1_SEL_S 0U

§ SOC_IC_ADDRCFG2_LOW_W

#define SOC_IC_ADDRCFG2_LOW_W 32U

§ SOC_IC_ADDRCFG2_LOW_M

#define SOC_IC_ADDRCFG2_LOW_M 0xFFFFFFFFU

§ SOC_IC_ADDRCFG2_LOW_S

#define SOC_IC_ADDRCFG2_LOW_S 0U

§ SOC_IC_ADDRCFG3_HIGH_W

#define SOC_IC_ADDRCFG3_HIGH_W 32U

§ SOC_IC_ADDRCFG3_HIGH_M

#define SOC_IC_ADDRCFG3_HIGH_M 0xFFFFFFFFU

§ SOC_IC_ADDRCFG3_HIGH_S

#define SOC_IC_ADDRCFG3_HIGH_S 0U

§ SOC_IC_ADDRCFG4_MSTIDWR_W

#define SOC_IC_ADDRCFG4_MSTIDWR_W 16U

§ SOC_IC_ADDRCFG4_MSTIDWR_M

#define SOC_IC_ADDRCFG4_MSTIDWR_M 0x0000FFFFU

§ SOC_IC_ADDRCFG4_MSTIDWR_S

#define SOC_IC_ADDRCFG4_MSTIDWR_S 0U

§ SOC_IC_ADDRCFG4_MSTIDRD_W

#define SOC_IC_ADDRCFG4_MSTIDRD_W 16U

§ SOC_IC_ADDRCFG4_MSTIDRD_M

#define SOC_IC_ADDRCFG4_MSTIDRD_M 0xFFFF0000U

§ SOC_IC_ADDRCFG4_MSTIDRD_S

#define SOC_IC_ADDRCFG4_MSTIDRD_S 16U

§ SOC_IC_ADDRSTA1_STA1_W

#define SOC_IC_ADDRSTA1_STA1_W 32U

§ SOC_IC_ADDRSTA1_STA1_M

#define SOC_IC_ADDRSTA1_STA1_M 0xFFFFFFFFU

§ SOC_IC_ADDRSTA1_STA1_S

#define SOC_IC_ADDRSTA1_STA1_S 0U

§ SOC_IC_ADDRSTA2_STA2_W

#define SOC_IC_ADDRSTA2_STA2_W 5U

§ SOC_IC_ADDRSTA2_STA2_M

#define SOC_IC_ADDRSTA2_STA2_M 0x0000001FU

§ SOC_IC_ADDRSTA2_STA2_S

#define SOC_IC_ADDRSTA2_STA2_S 0U

§ SOC_IC_TOMSTCFG_VAL_W

#define SOC_IC_TOMSTCFG_VAL_W 5U

§ SOC_IC_TOMSTCFG_VAL_M

#define SOC_IC_TOMSTCFG_VAL_M 0x000001F0U

§ SOC_IC_TOMSTCFG_VAL_S

#define SOC_IC_TOMSTCFG_VAL_S 4U

§ SOC_IC_TOMSTCFG_SEL_W

#define SOC_IC_TOMSTCFG_SEL_W 4U

§ SOC_IC_TOMSTCFG_SEL_M

#define SOC_IC_TOMSTCFG_SEL_M 0x00003C00U

§ SOC_IC_TOMSTCFG_SEL_S

#define SOC_IC_TOMSTCFG_SEL_S 10U

§ SOC_IC_TOSLVCFG_VAL_W

#define SOC_IC_TOSLVCFG_VAL_W 5U

§ SOC_IC_TOSLVCFG_VAL_M

#define SOC_IC_TOSLVCFG_VAL_M 0x000001F0U

§ SOC_IC_TOSLVCFG_VAL_S

#define SOC_IC_TOSLVCFG_VAL_S 4U

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