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CC35xxDriverLibrary
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Go to the source code of this file.
| #define SOC_AON_O_M3EVTCTL1 0x00000000U |
| #define SOC_AON_O_M3IRQCTL2 0x00000004U |
| #define SOC_AON_O_M3EVTCTL3 0x00000008U |
| #define SOC_AON_O_SPEVTCTL 0x0000000CU |
| #define SOC_AON_O_TMEVTCTL 0x00000010U |
| #define SOC_AON_O_GPT0EVTCTL0 0x00000014U |
| #define SOC_AON_O_GPT1EVTCTL0 0x00000018U |
| #define SOC_AON_O_DB0M33CLR 0x0000001CU |
| #define SOC_AON_O_DB0M33SET 0x00000020U |
| #define SOC_AON_O_DB0M33LOCK 0x00000024U |
| #define SOC_AON_O_DB1M33CLR 0x00000028U |
| #define SOC_AON_O_DB1M33SET 0x0000002CU |
| #define SOC_AON_O_DB1M33LOCK 0x00000030U |
| #define SOC_AON_O_DB4M33CLR 0x00000034U |
| #define SOC_AON_O_DB4M33SET 0x00000038U |
| #define SOC_AON_O_DB4M33LOCK 0x0000003CU |
| #define SOC_AON_O_DB5M33CLR 0x00000040U |
| #define SOC_AON_O_DB5M33SET 0x00000044U |
| #define SOC_AON_O_DB5M33LOCK 0x00000048U |
| #define SOC_AON_O_CMEMSTART 0x0000004CU |
| #define SOC_AON_O_CMEMEND 0x00000050U |
| #define SOC_AON_O_DMEMSTART 0x00000054U |
| #define SOC_AON_O_DMEMEND 0x00000058U |
| #define SOC_AON_O_TCMSTART 0x00000064U |
| #define SOC_AON_O_TCMEND 0x00000068U |
| #define SOC_AON_O_GPIOEVTS0 0x0000007CU |
| #define SOC_AON_O_GPIOEVTS1 0x00000080U |
| #define SOC_AON_O_MEMSSCTL0 0x00000084U |
| #define SOC_AON_O_MEMSSCTL1 0x00000088U |
| #define SOC_AON_O_SPARE0 0x00000090U |
| #define SOC_AON_O_VTORS 0x0000009CU |
| #define SOC_AON_O_VTORNS 0x000000A0U |
| #define SOC_AON_O_CPULOCKS 0x000000A8U |
| #define SOC_AON_O_HOSTLOCKS 0x000000ACU |
| #define SOC_AON_O_HOSTBOOT 0x000000B0U |
| #define SOC_AON_O_SECCFG 0x000000B4U |
| #define SOC_AON_O_DBSIMASK 0x000000B8U |
| #define SOC_AON_O_DBSISET 0x000000BCU |
| #define SOC_AON_O_DBSICLR 0x000000C0U |
| #define SOC_AON_O_DBSIMSET 0x000000C4U |
| #define SOC_AON_O_DBSIMCLR 0x000000C8U |
| #define SOC_AON_O_DBSRIS 0x000000CCU |
| #define SOC_AON_O_DBSMIS 0x000000D0U |
| #define SOC_AON_O_ERRSIMASK 0x000000D4U |
| #define SOC_AON_O_ERRSISET 0x000000D8U |
| #define SOC_AON_O_ERRSICLR 0x000000DCU |
| #define SOC_AON_O_ERRSIMSET 0x000000E0U |
| #define SOC_AON_O_ERRSIMCLR 0x000000E4U |
| #define SOC_AON_O_ERRSRIS 0x000000E8U |
| #define SOC_AON_O_ERRSMIS 0x000000ECU |
| #define SOC_AON_O_GPT0EVTCTL1 0x000000F0U |
| #define SOC_AON_O_GPT1EVTCTL1 0x000000F4U |
| #define SOC_AON_O_ESMSTACST 0x00000104U |
| #define SOC_AON_O_MEMSSCFG 0x0000010CU |
| #define SOC_AON_O_GPIOMIS0S 0x00000138U |
| #define SOC_AON_O_GPIOMIS1S 0x0000013CU |
| #define SOC_AON_O_GPIOFNC0S 0x00000140U |
| #define SOC_AON_O_GPIOFNC1S 0x00000144U |
| #define SOC_AON_O_SPARE1 0x00000148U |
| #define SOC_AON_O_ESM1VAL2ND 0x0000014CU |
| #define SOC_AON_O_ESM2VAL2ND 0x00000150U |
| #define SOC_AON_O_ESM1STA2ND 0x00000154U |
| #define SOC_AON_O_ESM2STA2ND 0x00000158U |
| #define SOC_AON_O_FWCFGHOST 0x0000015CU |
| #define SOC_AON_O_FWCFGDMA 0x00000160U |
| #define SOC_AON_O_FWCFGFPRPH 0x00000164U |
| #define SOC_AON_O_FWCFGM33 0x00000168U |
| #define SOC_AON_O_FWCFGMEMSS 0x0000016CU |
| #define SOC_AON_O_FWIOGENSEL 0x00000170U |
| #define SOC_AON_O_FWPRCMHOST 0x00000174U |
| #define SOC_AON_O_FWPRCMSPAD 0x00000178U |
| #define SOC_AON_O_FWPRCMCMN 0x0000017CU |
| #define SOC_AON_O_FWCKM 0x00000180U |
| #define SOC_AON_O_FWSOCIC 0x00000184U |
| #define SOC_AON_O_FWAONM33S 0x00000188U |
| #define SOC_AON_O_FWAONM33NS 0x0000018CU |
| #define SOC_AON_O_FWAAONM33S 0x00000190U |
| #define SOC_AON_O_FWAAONM33NS 0x00000194U |
| #define SOC_AON_O_FWCMNRTC 0x00000198U |
| #define SOC_AON_O_FWMEMSS0 0x0000019CU |
| #define SOC_AON_O_FWMEMSS1 0x000001A0U |
| #define SOC_AON_O_FWMEMSS2 0x000001A4U |
| #define SOC_AON_O_FWHOSTAON 0x000001A8U |
| #define SOC_AON_O_FWHIF 0x000001B0U |
| #define SOC_AON_O_FWHOST0 0x000001B4U |
| #define SOC_AON_O_FWHOST1 0x000001B8U |
| #define SOC_AON_O_FWHOST2 0x000001BCU |
| #define SOC_AON_O_FWHOST3 0x000001C0U |
| #define SOC_AON_O_FWHOST4 0x000001C4U |
| #define SOC_AON_O_FWHOST5 0x000001C8U |
| #define SOC_AON_O_FWHOST6 0x000001CCU |
| #define SOC_AON_O_FWHOST7 0x000001D0U |
| #define SOC_AON_O_FWHOST8 0x000001D4U |
| #define SOC_AON_O_FWHOST9 0x000001D8U |
| #define SOC_AON_O_FWHOST10 0x000001DCU |
| #define SOC_AON_O_FWHOST11 0x000001E0U |
| #define SOC_AON_O_FWXIPOSPI 0x000001E4U |
| #define SOC_AON_O_FWXIPINDAC 0x000001E8U |
| #define SOC_AON_O_FWXIPGEN 0x000001ECU |
| #define SOC_AON_O_FWXIPUDMAS 0x000001F0U |
| #define SOC_AON_O_FWXIPUDMANS 0x000001F4U |
| #define SOC_AON_O_FWOTFDE0 0x000001F8U |
| #define SOC_AON_O_FWOTFDE1 0x000001FCU |
| #define SOC_AON_O_FWOTFDE2 0x00000200U |
| #define SOC_AON_O_FWOTFDE3 0x00000204U |
| #define SOC_AON_O_FWDMAGEN 0x00000208U |
| #define SOC_AON_O_FWDMA0 0x0000020CU |
| #define SOC_AON_O_FWDMA1 0x00000210U |
| #define SOC_AON_O_FWDMA2 0x00000214U |
| #define SOC_AON_O_FWDMA3 0x00000218U |
| #define SOC_AON_O_FWDMA4 0x0000021CU |
| #define SOC_AON_O_FWDMA5 0x00000220U |
| #define SOC_AON_O_FWDMA6 0x00000224U |
| #define SOC_AON_O_FWDMA7 0x00000228U |
| #define SOC_AON_O_FWDMA8 0x0000022CU |
| #define SOC_AON_O_FWDMA9 0x00000230U |
| #define SOC_AON_O_FWDMA10 0x00000234U |
| #define SOC_AON_O_FWDMA11 0x00000238U |
| #define SOC_AON_O_FWHSMEIPNS 0x0000023CU |
| #define SOC_AON_O_FWHSMEIPS 0x00000240U |
| #define SOC_AON_O_FWHSMWRAPNS 0x00000244U |
| #define SOC_AON_O_FWHSMWRAPS 0x00000248U |
| #define SOC_AON_O_FWHSMDBG 0x0000024CU |
| #define SOC_AON_O_FWI2C0 0x00000250U |
| #define SOC_AON_O_FWI2C1 0x00000254U |
| #define SOC_AON_O_FWSPSPI0 0x00000258U |
| #define SOC_AON_O_FWSPSPI1 0x0000025CU |
| #define SOC_AON_O_FWSPUART0 0x00000260U |
| #define SOC_AON_O_FWSPUART1 0x00000264U |
| #define SOC_AON_O_FWSPGPT0 0x00000268U |
| #define SOC_AON_O_FWSPGPT1 0x0000026CU |
| #define SOC_AON_O_FWSPI2S 0x00000270U |
| #define SOC_AON_O_FWPDM 0x00000274U |
| #define SOC_AON_O_FWSPCAN 0x00000278U |
| #define SOC_AON_O_FWSPADC 0x0000027CU |
| #define SOC_AON_O_FWSPSDMMC 0x00000280U |
| #define SOC_AON_O_FWSPSDIO 0x00000284U |
| #define SOC_AON_O_FWSPUART2 0x00000288U |
| #define SOC_AON_O_UDMANSCTL 0x0000028CU |
| #define SOC_AON_O_FWIOPAD0 0x00000290U |
| #define SOC_AON_O_FWIOPAD1 0x00000294U |
| #define SOC_AON_O_FWIOPAD2 0x00000298U |
| #define SOC_AON_O_FWIOPAD3 0x0000029CU |
| #define SOC_AON_O_FWIOPAD4 0x000002A0U |
| #define SOC_AON_O_FWIOPAD5 0x000002A4U |
| #define SOC_AON_O_FWIOPAD6 0x000002A8U |
| #define SOC_AON_O_FWIOPAD7 0x000002ACU |
| #define SOC_AON_O_FWIOPAD8 0x000002B0U |
| #define SOC_AON_O_FWIOPAD9 0x000002B4U |
| #define SOC_AON_O_FWIOPAD10 0x000002B8U |
| #define SOC_AON_O_FWIOPAD11 0x000002BCU |
| #define SOC_AON_O_FWIOPAD12 0x000002C0U |
| #define SOC_AON_O_FWIOPAD13 0x000002C4U |
| #define SOC_AON_O_FWIOPAD14 0x000002C8U |
| #define SOC_AON_O_FWIOPAD15 0x000002CCU |
| #define SOC_AON_O_FWIOPAD16 0x000002D0U |
| #define SOC_AON_O_FWIOPAD17 0x000002D4U |
| #define SOC_AON_O_FWIOPAD18 0x000002D8U |
| #define SOC_AON_O_FWIOPAD19 0x000002DCU |
| #define SOC_AON_O_FWIOPAD20 0x000002E0U |
| #define SOC_AON_O_FWIOPAD21 0x000002E4U |
| #define SOC_AON_O_FWIOPAD22 0x000002E8U |
| #define SOC_AON_O_FWIOPAD23 0x000002ECU |
| #define SOC_AON_O_FWIOPAD24 0x000002F0U |
| #define SOC_AON_O_FWIOPAD25 0x000002F4U |
| #define SOC_AON_O_FWIOPAD26 0x000002F8U |
| #define SOC_AON_O_FWIOPAD27 0x000002FCU |
| #define SOC_AON_O_FWIOPAD28 0x00000300U |
| #define SOC_AON_O_FWIOPAD29 0x00000304U |
| #define SOC_AON_O_FWIOPAD30 0x00000308U |
| #define SOC_AON_O_FWIOPAD31 0x0000030CU |
| #define SOC_AON_O_FWIOPAD32 0x00000310U |
| #define SOC_AON_O_FWIOPAD33 0x00000314U |
| #define SOC_AON_O_FWIOPAD34 0x00000318U |
| #define SOC_AON_O_FWIOPAD35 0x0000031CU |
| #define SOC_AON_O_FWIOPAD36 0x00000320U |
| #define SOC_AON_O_FWIOPAD37 0x00000324U |
| #define SOC_AON_O_FWIOPAD38 0x00000328U |
| #define SOC_AON_O_FWIOPAD39 0x0000032CU |
| #define SOC_AON_O_FWIOPAD40 0x00000330U |
| #define SOC_AON_O_FWIOPAD41 0x00000334U |
| #define SOC_AON_O_FWIOPAD42 0x00000338U |
| #define SOC_AON_O_FWIOPAD43 0x0000033CU |
| #define SOC_AON_O_FWIOPAD44 0x00000340U |
| #define SOC_AON_O_FWIOPAD45 0x00000344U |
| #define SOC_AON_O_FWIOPAD46 0x00000348U |
| #define SOC_AON_O_FWIOPAD47 0x0000034CU |
| #define SOC_AON_O_FWIOPAD48 0x00000350U |
| #define SOC_AON_O_FWDMA12 0x00000354U |
| #define SOC_AON_O_FWDMA13 0x00000358U |
| #define SOC_AON_O_FWSPARE0 0x0000035CU |
| #define SOC_AON_O_USECSTB 0x00001000U |
| #define SOC_AON_O_DB2M33CLR 0x00001004U |
| #define SOC_AON_O_DB2M33SET 0x00001008U |
| #define SOC_AON_O_DB2M33LOCK 0x0000100CU |
| #define SOC_AON_O_DB3M33CLR 0x00001010U |
| #define SOC_AON_O_DB3M33SET 0x00001014U |
| #define SOC_AON_O_DB3M33LOCK 0x00001018U |
| #define SOC_AON_O_DB6M33CLR 0x0000101CU |
| #define SOC_AON_O_DB6M33SET 0x00001020U |
| #define SOC_AON_O_DB6M33LOCK 0x00001024U |
| #define SOC_AON_O_DB7M33CLR 0x00001028U |
| #define SOC_AON_O_DB7M33SET 0x0000102CU |
| #define SOC_AON_O_DB7M33LOCK 0x00001030U |
| #define SOC_AON_O_GPIOEVT0NS 0x00001044U |
| #define SOC_AON_O_GPIOEVT1NS 0x00001048U |
| #define SOC_AON_O_DBM33NS0 0x00001054U |
| #define SOC_AON_O_DBNSISET 0x00001058U |
| #define SOC_AON_O_DBNSICLR 0x0000105CU |
| #define SOC_AON_O_DBNSIMSET 0x00001060U |
| #define SOC_AON_O_DBNSIMCLR 0x00001064U |
| #define SOC_AON_O_DBNSRIS 0x00001068U |
| #define SOC_AON_O_DBNSMIS 0x0000106CU |
| #define SOC_AON_O_GPIOMIS0NS 0x00001070U |
| #define SOC_AON_O_GPIOMIS1NS 0x00001074U |
| #define SOC_AON_O_GPIOFNC0NS 0x00001078U |
| #define SOC_AON_O_GPIOFNC1NS 0x0000107CU |
| #define SOC_AON_O_SPARE2 0x00001080U |
| #define SOC_AON_O_FUSE 0x00002004U |
| #define SOC_AON_O_ESM1CFG 0x00002048U |
| #define SOC_AON_O_ESM1EN1 0x0000204CU |
| #define SOC_AON_O_ESM1EN2 0x00002050U |
| #define SOC_AON_O_ESM1EN3 0x00002054U |
| #define SOC_AON_O_ESM1EN4 0x00002058U |
| #define SOC_AON_O_ESM1EN5 0x0000205CU |
| #define SOC_AON_O_ESM2EN1 0x00002060U |
| #define SOC_AON_O_ESM2EN2 0x00002064U |
| #define SOC_AON_O_ESM2EN3 0x00002068U |
| #define SOC_AON_O_ESM2EN4 0x0000206CU |
| #define SOC_AON_O_ESM2EN5 0x00002070U |
| #define SOC_AON_O_ESM2CFG 0x00002074U |
| #define SOC_AON_O_DBGSSDSSM 0x000020A4U |
| #define SOC_AON_O_ESM3CFG 0x000020B4U |
| #define SOC_AON_O_ESM3EN1 0x000020B8U |
| #define SOC_AON_O_ESM3EN2 0x000020BCU |
| #define SOC_AON_O_ESM3EN3 0x000020C0U |
| #define SOC_AON_O_ESM3EN4 0x000020C4U |
| #define SOC_AON_O_ESM3EN5 0x000020C8U |
| #define SOC_AON_O_FUSELINE0 0x000020CCU |
| #define SOC_AON_O_FUSELINE1 0x000020D0U |
| #define SOC_AON_O_FUSELINE2 0x000020D4U |
| #define SOC_AON_O_FUSELINE3 0x000020D8U |
| #define SOC_AON_O_FUSELINE4 0x000020DCU |
| #define SOC_AON_O_FUSELINE5 0x000020E0U |
| #define SOC_AON_O_FUSELINE6 0x000020E4U |
| #define SOC_AON_O_FUSELINE7 0x000020E8U |
| #define SOC_AON_O_FUSELINE8 0x000020ECU |
| #define SOC_AON_O_FUSECTL 0x00002100U |
| #define SOC_AON_O_COREMEMCTL 0x00002104U |
| #define SOC_AON_O_COREGPCTL 0x00002108U |
| #define SOC_AON_O_MEMSSGPCTL 0x0000210CU |
| #define SOC_AON_O_BLEFUSECTL 0x00002110U |
| #define SOC_AON_O_SPARE4 0x00002118U |
| #define SOC_AON_O_ESM4CFG 0x0000211CU |
| #define SOC_AON_O_ESM4EN1 0x00002120U |
| #define SOC_AON_O_ESM4EN2 0x00002124U |
| #define SOC_AON_O_ESM4EN3 0x00002128U |
| #define SOC_AON_O_ESM4EN4 0x0000212CU |
| #define SOC_AON_O_ESM4EN5 0x00002130U |
| #define SOC_AON_O_MEMPROT 0x00002140U |
| #define SOC_AON_O_VTORCFG 0x00002144U |
| #define SOC_AON_O_ROMJUMPCTL 0x00002148U |
| #define SOC_AON_O_CRAMPROT1 0x0000214CU |
| #define SOC_AON_O_CRAMPROT0 0x00002150U |
| #define SOC_AON_O_DRAMPROT1 0x00002154U |
| #define SOC_AON_O_DRAMPROT0 0x00002158U |
| #define SOC_AON_O_PRAMPROT0 0x0000215CU |
| #define SOC_AON_O_STRONGPAT 0x00002160U |
| #define SOC_AON_O_UDS0 0x00002164U |
| #define SOC_AON_O_UDS1 0x00002168U |
| #define SOC_AON_O_UDS2 0x0000216CU |
| #define SOC_AON_O_UDS3 0x00002170U |
| #define SOC_AON_O_DBGBUS 0x00002174U |
| #define SOC_AON_O_DEBUGSS 0x0000217CU |
| #define SOC_AON_O_CPEPROT1 0x00002180U |
| #define SOC_AON_O_CPEPROT0 0x00002184U |
| #define SOC_AON_O_FUSESHIFT 0x00002188U |
| #define SOC_AON_O_SECROM 0x0000218CU |
| #define SOC_AON_O_SECUDS 0x00002190U |
| #define SOC_AON_O_PHYPROT1 0x00002198U |
| #define SOC_AON_O_PHYPROT0 0x0000219CU |
| #define SOC_AON_O_ESMDIS 0x000021A0U |
| #define SOC_AON_O_SPARE5 0x000021A4U |
| #define SOC_AON_O_TOPDBG 0x000021A8U |
| #define SOC_AON_O_DB0M3CLR 0x00002370U |
| #define SOC_AON_O_DB0M3SET 0x00002374U |
| #define SOC_AON_O_DB0M3LOCK 0x00002378U |
| #define SOC_AON_O_DB1M3CLR 0x0000237CU |
| #define SOC_AON_O_DB1M3SET 0x00002380U |
| #define SOC_AON_O_DB1M3LOCK 0x00002384U |
| #define SOC_AON_O_DB2M3CLR 0x00002388U |
| #define SOC_AON_O_DB2M3SET 0x0000238CU |
| #define SOC_AON_O_DB2M3LOCK 0x00002390U |
| #define SOC_AON_O_DB3M3CLR 0x00002394U |
| #define SOC_AON_O_DB3M3SET 0x00002398U |
| #define SOC_AON_O_DB3M3LOCK 0x0000239CU |
| #define SOC_AON_O_DB4M3CLR 0x000023A0U |
| #define SOC_AON_O_DB4M3SET 0x000023A4U |
| #define SOC_AON_O_DB4M3LOCK 0x000023A8U |
| #define SOC_AON_O_DB5M3CLR 0x000023ACU |
| #define SOC_AON_O_DB5M3SET 0x000023B0U |
| #define SOC_AON_O_DB5M3LOCK 0x000023B4U |
| #define SOC_AON_O_DB6M3CLR 0x000023B8U |
| #define SOC_AON_O_DB6M3SET 0x000023BCU |
| #define SOC_AON_O_DB6M3LOCK 0x000023C0U |
| #define SOC_AON_O_DB7M3CLR 0x000023C4U |
| #define SOC_AON_O_DB7M3SET 0x000023C8U |
| #define SOC_AON_O_DB7M3LOCK 0x000023CCU |
| #define SOC_AON_O_M3GPIOEVT0 0x000023D0U |
| #define SOC_AON_O_M3GPIOEVT1 0x000023D4U |
| #define SOC_AON_O_FUSELOCK 0x000023E8U |
| #define SOC_AON_O_ROMBOOT 0x000023ECU |
| #define SOC_AON_O_SOCBOOT 0x000023FCU |
| #define SOC_AON_O_ELEVATED 0x00002400U |
| #define SOC_AON_O_M3TCM 0x00002408U |
| #define SOC_AON_O_HSMCFG 0x0000240CU |
| #define SOC_AON_O_ESM5CFG 0x00002410U |
| #define SOC_AON_O_ESM5EN1 0x00002414U |
| #define SOC_AON_O_ESM5EN2 0x00002418U |
| #define SOC_AON_O_ESM5EN3 0x0000241CU |
| #define SOC_AON_O_ESM5EN4 0x00002420U |
| #define SOC_AON_O_ESM5EN5 0x00002424U |
| #define SOC_AON_O_ESM1VAL1ST 0x00002428U |
| #define SOC_AON_O_ESM2VAL1ST 0x0000242CU |
| #define SOC_AON_O_ESM3VAL1ST 0x00002430U |
| #define SOC_AON_O_ESM4VAL1ST 0x00002434U |
| #define SOC_AON_O_ESM5VAL1ST 0x00002438U |
| #define SOC_AON_O_DBM3IMASK 0x00002450U |
| #define SOC_AON_O_DBM3ISET 0x00002454U |
| #define SOC_AON_O_DBM3ICLR 0x00002458U |
| #define SOC_AON_O_DBM3IMSET 0x0000245CU |
| #define SOC_AON_O_DBM3IMCLR 0x00002460U |
| #define SOC_AON_O_DBM3RIS 0x00002464U |
| #define SOC_AON_O_DBM3MIS 0x00002468U |
| #define SOC_AON_O_HOSTCRTX 0x00002680U |
| #define SOC_AON_O_FWCFGSOC 0x00002684U |
| #define SOC_AON_O_FWCOEX 0x00002688U |
| #define SOC_AON_O_FWPRCM 0x0000268CU |
| #define SOC_AON_O_FWFUSE 0x00002690U |
| #define SOC_AON_O_FWGPADC 0x00002694U |
| #define SOC_AON_O_FWDBGSS 0x00002698U |
| #define SOC_AON_O_FWAONM3 0x0000269CU |
| #define SOC_AON_O_FWOCLA 0x000026A0U |
| #define SOC_AON_O_FWCORE 0x000026A4U |
| #define SOC_AON_O_FWAAONM3 0x000026A8U |
| #define SOC_AON_O_FWXIPCFG 0x000026ACU |
| #define SOC_AON_O_FWOTFLCK 0x000026B0U |
| #define SOC_AON_O_FWOTFNLCK 0x000026B4U |
| #define SOC_AON_O_FWCOREAON 0x00002808U |
| #define SOC_AON_O_FWSPARE1 0x0000287CU |
| #define SOC_AON_O_SOCSTA 0x00002898U |
| #define SOC_AON_O_LCCFG 0x0000289CU |
| #define SOC_AON_O_ESM1STA 0x000028A0U |
| #define SOC_AON_O_ESM2STA 0x000028A4U |
| #define SOC_AON_O_ESM1STA1ST 0x000028A8U |
| #define SOC_AON_O_ESM2STA1ST 0x000028ACU |
| #define SOC_AON_O_ESM3STA1ST 0x000028B0U |
| #define SOC_AON_O_ESM4STA1ST 0x000028B4U |
| #define SOC_AON_O_ESM5STA1ST 0x000028B8U |
| #define SOC_AON_O_SECGSERR 0x00002908U |
| #define SOC_AON_O_DRAMCTL 0x0000290CU |
| #define SOC_AON_O_CONNSTPCTL 0x00002910U |
| #define SOC_AON_O_ESMSTATI 0x00002914U |
| #define SOC_AON_O_M3GPIOMIS0 0x00002918U |
| #define SOC_AON_O_M3GPIOMIS1 0x0000291CU |
| #define SOC_AON_O_M3GPIOFNC0 0x00002920U |
| #define SOC_AON_O_M3GPIOFNC1 0x00002924U |
| #define SOC_AON_O_DBGOCLA 0x00002928U |
| #define SOC_AON_O_CPUWAIT 0x0000292CU |
| #define SOC_AON_O_SPARE6 0x00002930U |
| #define SOC_AON_O_SECSTA 0x00002934U |
| #define SOC_AON_O_ESM3VAL2ND 0x00002938U |
| #define SOC_AON_O_ESM4VAL2ND 0x0000293CU |
| #define SOC_AON_O_ESM5VAL2ND 0x00002940U |
| #define SOC_AON_O_ESM3STA 0x00002944U |
| #define SOC_AON_O_ESM4STA 0x00002948U |
| #define SOC_AON_O_ESM5STA 0x0000294CU |
| #define SOC_AON_O_ESM3STA2ND 0x00002950U |
| #define SOC_AON_O_ESM4STA2ND 0x00002954U |
| #define SOC_AON_O_ESM5STA2ND 0x00002958U |
| #define SOC_AON_O_LCSTA 0x0000295CU |
| #define SOC_AON_O_DRMAST 0x00002960U |
| #define SOC_AON_O_FLASHMASK 0x00002964U |
| #define SOC_AON_O_WSOCROM 0x00002968U |
| #define SOC_AON_M3EVTCTL1_SEL0_W 6U |
| #define SOC_AON_M3EVTCTL1_SEL0_M 0x0000003FU |
| #define SOC_AON_M3EVTCTL1_SEL0_S 0U |
| #define SOC_AON_M3EVTCTL1_SEL1_W 6U |
| #define SOC_AON_M3EVTCTL1_SEL1_M 0x00003F00U |
| #define SOC_AON_M3EVTCTL1_SEL1_S 8U |
| #define SOC_AON_M3EVTCTL1_SEL2_W 6U |
| #define SOC_AON_M3EVTCTL1_SEL2_M 0x003F0000U |
| #define SOC_AON_M3EVTCTL1_SEL2_S 16U |
| #define SOC_AON_M3EVTCTL1_SEL3_W 6U |
| #define SOC_AON_M3EVTCTL1_SEL3_M 0x3F000000U |
| #define SOC_AON_M3EVTCTL1_SEL3_S 24U |
| #define SOC_AON_M3IRQCTL2_SEL4_W 6U |
| #define SOC_AON_M3IRQCTL2_SEL4_M 0x0000003FU |
| #define SOC_AON_M3IRQCTL2_SEL4_S 0U |
| #define SOC_AON_M3IRQCTL2_SEL5_W 6U |
| #define SOC_AON_M3IRQCTL2_SEL5_M 0x00003F00U |
| #define SOC_AON_M3IRQCTL2_SEL5_S 8U |
| #define SOC_AON_M3IRQCTL2_SEL6_W 6U |
| #define SOC_AON_M3IRQCTL2_SEL6_M 0x003F0000U |
| #define SOC_AON_M3IRQCTL2_SEL6_S 16U |
| #define SOC_AON_M3IRQCTL2_SEL7_W 6U |
| #define SOC_AON_M3IRQCTL2_SEL7_M 0x3F000000U |
| #define SOC_AON_M3IRQCTL2_SEL7_S 24U |
| #define SOC_AON_M3EVTCTL3_SEL8_W 6U |
| #define SOC_AON_M3EVTCTL3_SEL8_M 0x0000003FU |
| #define SOC_AON_M3EVTCTL3_SEL8_S 0U |
| #define SOC_AON_M3EVTCTL3_SEL9_W 6U |
| #define SOC_AON_M3EVTCTL3_SEL9_M 0x00003F00U |
| #define SOC_AON_M3EVTCTL3_SEL9_S 8U |
| #define SOC_AON_SPEVTCTL_ADC_W 6U |
| #define SOC_AON_SPEVTCTL_ADC_M 0x0000003FU |
| #define SOC_AON_SPEVTCTL_ADC_S 0U |
| #define SOC_AON_SPEVTCTL_I2S_W 7U |
| #define SOC_AON_SPEVTCTL_I2S_M 0x00007F00U |
| #define SOC_AON_SPEVTCTL_I2S_S 8U |
| #define SOC_AON_SPEVTCTL_PDM_W 7U |
| #define SOC_AON_SPEVTCTL_PDM_M 0x007F0000U |
| #define SOC_AON_SPEVTCTL_PDM_S 16U |
| #define SOC_AON_TMEVTCTL_SYSTM0_W 6U |
| #define SOC_AON_TMEVTCTL_SYSTM0_M 0x0000003FU |
| #define SOC_AON_TMEVTCTL_SYSTM0_S 0U |
| #define SOC_AON_TMEVTCTL_SYSTM1_W 6U |
| #define SOC_AON_TMEVTCTL_SYSTM1_M 0x00003F00U |
| #define SOC_AON_TMEVTCTL_SYSTM1_S 8U |
| #define SOC_AON_TMEVTCTL_RTC_W 7U |
| #define SOC_AON_TMEVTCTL_RTC_M 0x007F0000U |
| #define SOC_AON_TMEVTCTL_RTC_S 16U |
| #define SOC_AON_GPT0EVTCTL0_CH0SEL_W 7U |
| #define SOC_AON_GPT0EVTCTL0_CH0SEL_M 0x0000007FU |
| #define SOC_AON_GPT0EVTCTL0_CH0SEL_S 0U |
| #define SOC_AON_GPT0EVTCTL0_CH1SEL_W 7U |
| #define SOC_AON_GPT0EVTCTL0_CH1SEL_M 0x00003F80U |
| #define SOC_AON_GPT0EVTCTL0_CH1SEL_S 7U |
| #define SOC_AON_GPT0EVTCTL0_CH2SEL_W 7U |
| #define SOC_AON_GPT0EVTCTL0_CH2SEL_M 0x001FC000U |
| #define SOC_AON_GPT0EVTCTL0_CH2SEL_S 14U |
| #define SOC_AON_GPT0EVTCTL0_CH3SEL_W 7U |
| #define SOC_AON_GPT0EVTCTL0_CH3SEL_M 0x0FE00000U |
| #define SOC_AON_GPT0EVTCTL0_CH3SEL_S 21U |
| #define SOC_AON_GPT1EVTCTL0_CH0SEL_W 7U |
| #define SOC_AON_GPT1EVTCTL0_CH0SEL_M 0x0000007FU |
| #define SOC_AON_GPT1EVTCTL0_CH0SEL_S 0U |
| #define SOC_AON_GPT1EVTCTL0_CH1SEL_W 7U |
| #define SOC_AON_GPT1EVTCTL0_CH1SEL_M 0x00003F80U |
| #define SOC_AON_GPT1EVTCTL0_CH1SEL_S 7U |
| #define SOC_AON_GPT1EVTCTL0_CH2SEL_W 7U |
| #define SOC_AON_GPT1EVTCTL0_CH2SEL_M 0x001FC000U |
| #define SOC_AON_GPT1EVTCTL0_CH2SEL_S 14U |
| #define SOC_AON_GPT1EVTCTL0_CH3SEL_W 7U |
| #define SOC_AON_GPT1EVTCTL0_CH3SEL_M 0x0FE00000U |
| #define SOC_AON_GPT1EVTCTL0_CH3SEL_S 21U |
| #define SOC_AON_DB0M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB0M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB0M33CLR_CLR_S 0U |
| #define SOC_AON_DB0M33SET_SET 0x00000001U |
| #define SOC_AON_DB0M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB0M33SET_SET_S 0U |
| #define SOC_AON_DB0M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB0M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB0M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB1M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB1M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB1M33CLR_CLR_S 0U |
| #define SOC_AON_DB1M33SET_SET 0x00000001U |
| #define SOC_AON_DB1M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB1M33SET_SET_S 0U |
| #define SOC_AON_DB1M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB1M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB1M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB4M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB4M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB4M33CLR_CLR_S 0U |
| #define SOC_AON_DB4M33SET_SET 0x00000001U |
| #define SOC_AON_DB4M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB4M33SET_SET_S 0U |
| #define SOC_AON_DB4M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB4M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB4M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB5M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB5M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB5M33CLR_CLR_S 0U |
| #define SOC_AON_DB5M33SET_SET 0x00000001U |
| #define SOC_AON_DB5M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB5M33SET_SET_S 0U |
| #define SOC_AON_DB5M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB5M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB5M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_CMEMSTART_ADDR_W 20U |
| #define SOC_AON_CMEMSTART_ADDR_M 0xFFFFF000U |
| #define SOC_AON_CMEMSTART_ADDR_S 12U |
| #define SOC_AON_CMEMEND_ADDR_W 20U |
| #define SOC_AON_CMEMEND_ADDR_M 0xFFFFF000U |
| #define SOC_AON_CMEMEND_ADDR_S 12U |
| #define SOC_AON_DMEMSTART_ADDR_W 20U |
| #define SOC_AON_DMEMSTART_ADDR_M 0xFFFFF000U |
| #define SOC_AON_DMEMSTART_ADDR_S 12U |
| #define SOC_AON_DMEMEND_ADDR_W 20U |
| #define SOC_AON_DMEMEND_ADDR_M 0xFFFFF000U |
| #define SOC_AON_DMEMEND_ADDR_S 12U |
| #define SOC_AON_TCMSTART_ADDR_W 22U |
| #define SOC_AON_TCMSTART_ADDR_M 0xFFFFFC00U |
| #define SOC_AON_TCMSTART_ADDR_S 10U |
| #define SOC_AON_TCMEND_ADDR_W 22U |
| #define SOC_AON_TCMEND_ADDR_M 0xFFFFFC00U |
| #define SOC_AON_TCMEND_ADDR_S 10U |
| #define SOC_AON_GPIOEVTS0_STA31TO0_W 32U |
| #define SOC_AON_GPIOEVTS0_STA31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_GPIOEVTS0_STA31TO0_S 0U |
| #define SOC_AON_GPIOEVTS1_STA44TO32_W 13U |
| #define SOC_AON_GPIOEVTS1_STA44TO32_M 0x00001FFFU |
| #define SOC_AON_GPIOEVTS1_STA44TO32_S 0U |
| #define SOC_AON_MEMSSCTL0_STRVCNTV_W 3U |
| #define SOC_AON_MEMSSCTL0_STRVCNTV_M 0x00000007U |
| #define SOC_AON_MEMSSCTL0_STRVCNTV_S 0U |
| #define SOC_AON_MEMSSCTL0_BFLTMASK 0x00000008U |
| #define SOC_AON_MEMSSCTL0_BFLTMASK_M 0x00000008U |
| #define SOC_AON_MEMSSCTL0_BFLTMASK_S 3U |
| #define SOC_AON_MEMSSCTL0_BFLTMSTA_W 3U |
| #define SOC_AON_MEMSSCTL0_BFLTMSTA_M 0x00000070U |
| #define SOC_AON_MEMSSCTL0_BFLTMSTA_S 4U |
| #define SOC_AON_MEMSSCTL1_BFLTRWSTA_W 3U |
| #define SOC_AON_MEMSSCTL1_BFLTRWSTA_M 0x00000007U |
| #define SOC_AON_MEMSSCTL1_BFLTRWSTA_S 0U |
| #define SOC_AON_SPARE0_BF_W 4U |
| #define SOC_AON_SPARE0_BF_M 0x0000000FU |
| #define SOC_AON_SPARE0_BF_S 0U |
| #define SOC_AON_VTORS_ADDR_W 25U |
| #define SOC_AON_VTORS_ADDR_M 0xFFFFFF80U |
| #define SOC_AON_VTORS_ADDR_S 7U |
| #define SOC_AON_VTORNS_ADDR_W 25U |
| #define SOC_AON_VTORNS_ADDR_M 0xFFFFFF80U |
| #define SOC_AON_VTORNS_ADDR_S 7U |
| #define SOC_AON_CPULOCKS_SVTAIRCR 0x00000001U |
| #define SOC_AON_CPULOCKS_SVTAIRCR_M 0x00000001U |
| #define SOC_AON_CPULOCKS_SVTAIRCR_S 0U |
| #define SOC_AON_CPULOCKS_NSVTOR 0x00000002U |
| #define SOC_AON_CPULOCKS_NSVTOR_M 0x00000002U |
| #define SOC_AON_CPULOCKS_NSVTOR_S 1U |
| #define SOC_AON_CPULOCKS_SMPU 0x00000004U |
| #define SOC_AON_CPULOCKS_SMPU_M 0x00000004U |
| #define SOC_AON_CPULOCKS_SMPU_S 2U |
| #define SOC_AON_CPULOCKS_NSPMU 0x00000008U |
| #define SOC_AON_CPULOCKS_NSPMU_M 0x00000008U |
| #define SOC_AON_CPULOCKS_NSPMU_S 3U |
| #define SOC_AON_CPULOCKS_SAU 0x00000010U |
| #define SOC_AON_CPULOCKS_SAU_M 0x00000010U |
| #define SOC_AON_CPULOCKS_SAU_S 4U |
| #define SOC_AON_HOSTLOCKS_CACHE 0x00000001U |
| #define SOC_AON_HOSTLOCKS_CACHE_M 0x00000001U |
| #define SOC_AON_HOSTLOCKS_CACHE_S 0U |
| #define SOC_AON_HOSTLOCKS_M33 0x00000002U |
| #define SOC_AON_HOSTLOCKS_M33_M 0x00000002U |
| #define SOC_AON_HOSTLOCKS_M33_S 1U |
| #define SOC_AON_HOSTLOCKS_MEMSSANDFW 0x00000004U |
| #define SOC_AON_HOSTLOCKS_MEMSSANDFW_M 0x00000004U |
| #define SOC_AON_HOSTLOCKS_MEMSSANDFW_S 2U |
| #define SOC_AON_HOSTLOCKS_DMA 0x00000008U |
| #define SOC_AON_HOSTLOCKS_DMA_M 0x00000008U |
| #define SOC_AON_HOSTLOCKS_DMA_S 3U |
| #define SOC_AON_HOSTLOCKS_FLASH 0x00000010U |
| #define SOC_AON_HOSTLOCKS_FLASH_M 0x00000010U |
| #define SOC_AON_HOSTLOCKS_FLASH_S 4U |
| #define SOC_AON_HOSTLOCKS_M3EVT 0x00000020U |
| #define SOC_AON_HOSTLOCKS_M3EVT_M 0x00000020U |
| #define SOC_AON_HOSTLOCKS_M3EVT_S 5U |
| #define SOC_AON_HOSTLOCKS_PERIPHEVT 0x00000040U |
| #define SOC_AON_HOSTLOCKS_PERIPHEVT_M 0x00000040U |
| #define SOC_AON_HOSTLOCKS_PERIPHEVT_S 6U |
| #define SOC_AON_HOSTBOOT_DONE 0x00000001U |
| #define SOC_AON_HOSTBOOT_DONE_M 0x00000001U |
| #define SOC_AON_HOSTBOOT_DONE_S 0U |
| #define SOC_AON_SECCFG_BLKDMA 0x00000001U |
| #define SOC_AON_SECCFG_BLKDMA_M 0x00000001U |
| #define SOC_AON_SECCFG_BLKDMA_S 0U |
| #define SOC_AON_SECCFG_SELNSIRQ 0x00000002U |
| #define SOC_AON_SECCFG_SELNSIRQ_M 0x00000002U |
| #define SOC_AON_SECCFG_SELNSIRQ_S 1U |
| #define SOC_AON_SECCFG_BLKSBSWR 0x00000004U |
| #define SOC_AON_SECCFG_BLKSBSWR_M 0x00000004U |
| #define SOC_AON_SECCFG_BLKSBSWR_S 2U |
| #define SOC_AON_DBSIMASK_IMASK_W 4U |
| #define SOC_AON_DBSIMASK_IMASK_M 0x0000000FU |
| #define SOC_AON_DBSIMASK_IMASK_S 0U |
| #define SOC_AON_DBSISET_ISET_W 4U |
| #define SOC_AON_DBSISET_ISET_M 0x0000000FU |
| #define SOC_AON_DBSISET_ISET_S 0U |
| #define SOC_AON_DBSICLR_ICLR_W 4U |
| #define SOC_AON_DBSICLR_ICLR_M 0x0000000FU |
| #define SOC_AON_DBSICLR_ICLR_S 0U |
| #define SOC_AON_DBSIMSET_IMSET_W 4U |
| #define SOC_AON_DBSIMSET_IMSET_M 0x0000000FU |
| #define SOC_AON_DBSIMSET_IMSET_S 0U |
| #define SOC_AON_DBSIMCLR_IMCLR_W 4U |
| #define SOC_AON_DBSIMCLR_IMCLR_M 0x0000000FU |
| #define SOC_AON_DBSIMCLR_IMCLR_S 0U |
| #define SOC_AON_DBSRIS_RIS_W 4U |
| #define SOC_AON_DBSRIS_RIS_M 0x0000000FU |
| #define SOC_AON_DBSRIS_RIS_S 0U |
| #define SOC_AON_DBSMIS_MIS_W 4U |
| #define SOC_AON_DBSMIS_MIS_M 0x0000000FU |
| #define SOC_AON_DBSMIS_MIS_S 0U |
| #define SOC_AON_ERRSIMASK_IMASK_W 9U |
| #define SOC_AON_ERRSIMASK_IMASK_M 0x000001FFU |
| #define SOC_AON_ERRSIMASK_IMASK_S 0U |
| #define SOC_AON_ERRSISET_ISET_W 9U |
| #define SOC_AON_ERRSISET_ISET_M 0x000001FFU |
| #define SOC_AON_ERRSISET_ISET_S 0U |
| #define SOC_AON_ERRSICLR_ICLR_W 9U |
| #define SOC_AON_ERRSICLR_ICLR_M 0x000001FFU |
| #define SOC_AON_ERRSICLR_ICLR_S 0U |
| #define SOC_AON_ERRSIMSET_IMSET_W 9U |
| #define SOC_AON_ERRSIMSET_IMSET_M 0x000001FFU |
| #define SOC_AON_ERRSIMSET_IMSET_S 0U |
| #define SOC_AON_ERRSIMCLR_IMCLR_W 9U |
| #define SOC_AON_ERRSIMCLR_IMCLR_M 0x000001FFU |
| #define SOC_AON_ERRSIMCLR_IMCLR_S 0U |
| #define SOC_AON_ERRSRIS_RIS_W 9U |
| #define SOC_AON_ERRSRIS_RIS_M 0x000001FFU |
| #define SOC_AON_ERRSRIS_RIS_S 0U |
| #define SOC_AON_ERRSMIS_MIS_W 9U |
| #define SOC_AON_ERRSMIS_MIS_M 0x000001FFU |
| #define SOC_AON_ERRSMIS_MIS_S 0U |
| #define SOC_AON_GPT0EVTCTL1_SYNC_W 7U |
| #define SOC_AON_GPT0EVTCTL1_SYNC_M 0x0000007FU |
| #define SOC_AON_GPT0EVTCTL1_SYNC_S 0U |
| #define SOC_AON_GPT0EVTCTL1_TICKEN_W 7U |
| #define SOC_AON_GPT0EVTCTL1_TICKEN_M 0x00007F00U |
| #define SOC_AON_GPT0EVTCTL1_TICKEN_S 8U |
| #define SOC_AON_GPT0EVTCTL1_FAULT_W 7U |
| #define SOC_AON_GPT0EVTCTL1_FAULT_M 0x007F0000U |
| #define SOC_AON_GPT0EVTCTL1_FAULT_S 16U |
| #define SOC_AON_GPT1EVTCTL1_SYNC_W 7U |
| #define SOC_AON_GPT1EVTCTL1_SYNC_M 0x0000007FU |
| #define SOC_AON_GPT1EVTCTL1_SYNC_S 0U |
| #define SOC_AON_GPT1EVTCTL1_TICKEN_W 7U |
| #define SOC_AON_GPT1EVTCTL1_TICKEN_M 0x00007F00U |
| #define SOC_AON_GPT1EVTCTL1_TICKEN_S 8U |
| #define SOC_AON_GPT1EVTCTL1_FAULT_W 7U |
| #define SOC_AON_GPT1EVTCTL1_FAULT_M 0x007F0000U |
| #define SOC_AON_GPT1EVTCTL1_FAULT_S 16U |
| #define SOC_AON_ESMSTACST_ESM1DONE 0x00000001U |
| #define SOC_AON_ESMSTACST_ESM1DONE_M 0x00000001U |
| #define SOC_AON_ESMSTACST_ESM1DONE_S 0U |
| #define SOC_AON_ESMSTACST_ESM1VIO 0x00000002U |
| #define SOC_AON_ESMSTACST_ESM1VIO_M 0x00000002U |
| #define SOC_AON_ESMSTACST_ESM1VIO_S 1U |
| #define SOC_AON_ESMSTACST_ESM2DONE 0x00000100U |
| #define SOC_AON_ESMSTACST_ESM2DONE_M 0x00000100U |
| #define SOC_AON_ESMSTACST_ESM2DONE_S 8U |
| #define SOC_AON_ESMSTACST_ESM2VIO 0x00000200U |
| #define SOC_AON_ESMSTACST_ESM2VIO_M 0x00000200U |
| #define SOC_AON_ESMSTACST_ESM2VIO_S 9U |
| #define SOC_AON_MEMSSCFG_MODE_W 4U |
| #define SOC_AON_MEMSSCFG_MODE_M 0x0000000FU |
| #define SOC_AON_MEMSSCFG_MODE_S 0U |
| #define SOC_AON_GPIOMIS0S_31TO0_W 32U |
| #define SOC_AON_GPIOMIS0S_31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_GPIOMIS0S_31TO0_S 0U |
| #define SOC_AON_GPIOMIS1S_44TO32_W 13U |
| #define SOC_AON_GPIOMIS1S_44TO32_M 0x00001FFFU |
| #define SOC_AON_GPIOMIS1S_44TO32_S 0U |
| #define SOC_AON_GPIOFNC0S_MASK31TO0_W 32U |
| #define SOC_AON_GPIOFNC0S_MASK31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_GPIOFNC0S_MASK31TO0_S 0U |
| #define SOC_AON_GPIOFNC1S_MASK44TO32_W 13U |
| #define SOC_AON_GPIOFNC1S_MASK44TO32_M 0x00001FFFU |
| #define SOC_AON_GPIOFNC1S_MASK44TO32_S 0U |
| #define SOC_AON_SPARE1_BF_W 4U |
| #define SOC_AON_SPARE1_BF_M 0x0000000FU |
| #define SOC_AON_SPARE1_BF_S 0U |
| #define SOC_AON_ESM1VAL2ND_MGCVAL_W 8U |
| #define SOC_AON_ESM1VAL2ND_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM1VAL2ND_MGCVAL_S 0U |
| #define SOC_AON_ESM2VAL2ND_MGCVAL_W 8U |
| #define SOC_AON_ESM2VAL2ND_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM2VAL2ND_MGCVAL_S 0U |
| #define SOC_AON_ESM1STA2ND_DONE 0x00000001U |
| #define SOC_AON_ESM1STA2ND_DONE_M 0x00000001U |
| #define SOC_AON_ESM1STA2ND_DONE_S 0U |
| #define SOC_AON_ESM1STA2ND_FAULT 0x00000002U |
| #define SOC_AON_ESM1STA2ND_FAULT_M 0x00000002U |
| #define SOC_AON_ESM1STA2ND_FAULT_S 1U |
| #define SOC_AON_ESM2STA2ND_DONE 0x00000001U |
| #define SOC_AON_ESM2STA2ND_DONE_M 0x00000001U |
| #define SOC_AON_ESM2STA2ND_DONE_S 0U |
| #define SOC_AON_ESM2STA2ND_FAULT 0x00000002U |
| #define SOC_AON_ESM2STA2ND_FAULT_M 0x00000002U |
| #define SOC_AON_ESM2STA2ND_FAULT_S 1U |
| #define SOC_AON_FWCFGHOST_BYPASS 0x00000001U |
| #define SOC_AON_FWCFGHOST_BYPASS_M 0x00000001U |
| #define SOC_AON_FWCFGHOST_BYPASS_S 0U |
| #define SOC_AON_FWCFGDMA_BYPASS 0x00000001U |
| #define SOC_AON_FWCFGDMA_BYPASS_M 0x00000001U |
| #define SOC_AON_FWCFGDMA_BYPASS_S 0U |
| #define SOC_AON_FWCFGFPRPH_BYPASS 0x00000001U |
| #define SOC_AON_FWCFGFPRPH_BYPASS_M 0x00000001U |
| #define SOC_AON_FWCFGFPRPH_BYPASS_S 0U |
| #define SOC_AON_FWCFGM33_BYPASS 0x00000001U |
| #define SOC_AON_FWCFGM33_BYPASS_M 0x00000001U |
| #define SOC_AON_FWCFGM33_BYPASS_S 0U |
| #define SOC_AON_FWCFGMEMSS_BYPASS 0x00000001U |
| #define SOC_AON_FWCFGMEMSS_BYPASS_M 0x00000001U |
| #define SOC_AON_FWCFGMEMSS_BYPASS_S 0U |
| #define SOC_AON_FWIOGENSEL_M33NS 0x00000001U |
| #define SOC_AON_FWIOGENSEL_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOGENSEL_M33NS_S 0U |
| #define SOC_AON_FWIOGENSEL_M33S 0x00000002U |
| #define SOC_AON_FWIOGENSEL_M33S_M 0x00000002U |
| #define SOC_AON_FWIOGENSEL_M33S_S 1U |
| #define SOC_AON_FWIOGENSEL_CORENS 0x00000004U |
| #define SOC_AON_FWIOGENSEL_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOGENSEL_CORENS_S 2U |
| #define SOC_AON_FWPRCMHOST_M33S 0x00000001U |
| #define SOC_AON_FWPRCMHOST_M33S_M 0x00000001U |
| #define SOC_AON_FWPRCMHOST_M33S_S 0U |
| #define SOC_AON_FWPRCMHOST_CORENS 0x00000002U |
| #define SOC_AON_FWPRCMHOST_CORENS_M 0x00000002U |
| #define SOC_AON_FWPRCMHOST_CORENS_S 1U |
| #define SOC_AON_FWPRCMHOST_M33NS 0x00000004U |
| #define SOC_AON_FWPRCMHOST_M33NS_M 0x00000004U |
| #define SOC_AON_FWPRCMHOST_M33NS_S 2U |
| #define SOC_AON_FWPRCMSPAD_M33NS 0x00000001U |
| #define SOC_AON_FWPRCMSPAD_M33NS_M 0x00000001U |
| #define SOC_AON_FWPRCMSPAD_M33NS_S 0U |
| #define SOC_AON_FWPRCMSPAD_M33S 0x00000002U |
| #define SOC_AON_FWPRCMSPAD_M33S_M 0x00000002U |
| #define SOC_AON_FWPRCMSPAD_M33S_S 1U |
| #define SOC_AON_FWPRCMSPAD_CORENS 0x00000004U |
| #define SOC_AON_FWPRCMSPAD_CORENS_M 0x00000004U |
| #define SOC_AON_FWPRCMSPAD_CORENS_S 2U |
| #define SOC_AON_FWPRCMCMN_M33SWR 0x00000001U |
| #define SOC_AON_FWPRCMCMN_M33SWR_M 0x00000001U |
| #define SOC_AON_FWPRCMCMN_M33SWR_S 0U |
| #define SOC_AON_FWPRCMCMN_M33SRD 0x00000002U |
| #define SOC_AON_FWPRCMCMN_M33SRD_M 0x00000002U |
| #define SOC_AON_FWPRCMCMN_M33SRD_S 1U |
| #define SOC_AON_FWPRCMCMN_M33NSWR 0x00000004U |
| #define SOC_AON_FWPRCMCMN_M33NSWR_M 0x00000004U |
| #define SOC_AON_FWPRCMCMN_M33NSWR_S 2U |
| #define SOC_AON_FWPRCMCMN_M33NSRD 0x00000008U |
| #define SOC_AON_FWPRCMCMN_M33NSRD_M 0x00000008U |
| #define SOC_AON_FWPRCMCMN_M33NSRD_S 3U |
| #define SOC_AON_FWPRCMCMN_CORENSWR 0x00000010U |
| #define SOC_AON_FWPRCMCMN_CORENSWR_M 0x00000010U |
| #define SOC_AON_FWPRCMCMN_CORENSWR_S 4U |
| #define SOC_AON_FWPRCMCMN_CORENSRD 0x00000020U |
| #define SOC_AON_FWPRCMCMN_CORENSRD_M 0x00000020U |
| #define SOC_AON_FWPRCMCMN_CORENSRD_S 5U |
| #define SOC_AON_FWCKM_M33NS 0x00000001U |
| #define SOC_AON_FWCKM_M33NS_M 0x00000001U |
| #define SOC_AON_FWCKM_M33NS_S 0U |
| #define SOC_AON_FWCKM_M33S 0x00000002U |
| #define SOC_AON_FWCKM_M33S_M 0x00000002U |
| #define SOC_AON_FWCKM_M33S_S 1U |
| #define SOC_AON_FWCKM_CORENS 0x00000004U |
| #define SOC_AON_FWCKM_CORENS_M 0x00000004U |
| #define SOC_AON_FWCKM_CORENS_S 2U |
| #define SOC_AON_FWSOCIC_M33NSWR 0x00000001U |
| #define SOC_AON_FWSOCIC_M33NSWR_M 0x00000001U |
| #define SOC_AON_FWSOCIC_M33NSWR_S 0U |
| #define SOC_AON_FWSOCIC_M33NSRD 0x00000002U |
| #define SOC_AON_FWSOCIC_M33NSRD_M 0x00000002U |
| #define SOC_AON_FWSOCIC_M33NSRD_S 1U |
| #define SOC_AON_FWSOCIC_M33SWR 0x00000004U |
| #define SOC_AON_FWSOCIC_M33SWR_M 0x00000004U |
| #define SOC_AON_FWSOCIC_M33SWR_S 2U |
| #define SOC_AON_FWSOCIC_M33SRD 0x00000008U |
| #define SOC_AON_FWSOCIC_M33SRD_M 0x00000008U |
| #define SOC_AON_FWSOCIC_M33SRD_S 3U |
| #define SOC_AON_FWSOCIC_CORENSWR 0x00000010U |
| #define SOC_AON_FWSOCIC_CORENSWR_M 0x00000010U |
| #define SOC_AON_FWSOCIC_CORENSWR_S 4U |
| #define SOC_AON_FWSOCIC_CORENSRD 0x00000020U |
| #define SOC_AON_FWSOCIC_CORENSRD_M 0x00000020U |
| #define SOC_AON_FWSOCIC_CORENSRD_S 5U |
| #define SOC_AON_FWAONM33S_M33NS 0x00000001U |
| #define SOC_AON_FWAONM33S_M33NS_M 0x00000001U |
| #define SOC_AON_FWAONM33S_M33NS_S 0U |
| #define SOC_AON_FWAONM33S_M33S 0x00000002U |
| #define SOC_AON_FWAONM33S_M33S_M 0x00000002U |
| #define SOC_AON_FWAONM33S_M33S_S 1U |
| #define SOC_AON_FWAONM33S_CORENS 0x00000004U |
| #define SOC_AON_FWAONM33S_CORENS_M 0x00000004U |
| #define SOC_AON_FWAONM33S_CORENS_S 2U |
| #define SOC_AON_FWAONM33NS_M33NS 0x00000001U |
| #define SOC_AON_FWAONM33NS_M33NS_M 0x00000001U |
| #define SOC_AON_FWAONM33NS_M33NS_S 0U |
| #define SOC_AON_FWAONM33NS_M33S 0x00000002U |
| #define SOC_AON_FWAONM33NS_M33S_M 0x00000002U |
| #define SOC_AON_FWAONM33NS_M33S_S 1U |
| #define SOC_AON_FWAONM33NS_CORENS 0x00000004U |
| #define SOC_AON_FWAONM33NS_CORENS_M 0x00000004U |
| #define SOC_AON_FWAONM33NS_CORENS_S 2U |
| #define SOC_AON_FWAAONM33S_M33NS 0x00000001U |
| #define SOC_AON_FWAAONM33S_M33NS_M 0x00000001U |
| #define SOC_AON_FWAAONM33S_M33NS_S 0U |
| #define SOC_AON_FWAAONM33S_M33S 0x00000002U |
| #define SOC_AON_FWAAONM33S_M33S_M 0x00000002U |
| #define SOC_AON_FWAAONM33S_M33S_S 1U |
| #define SOC_AON_FWAAONM33S_CORENS 0x00000004U |
| #define SOC_AON_FWAAONM33S_CORENS_M 0x00000004U |
| #define SOC_AON_FWAAONM33S_CORENS_S 2U |
| #define SOC_AON_FWAAONM33NS_M33NS 0x00000001U |
| #define SOC_AON_FWAAONM33NS_M33NS_M 0x00000001U |
| #define SOC_AON_FWAAONM33NS_M33NS_S 0U |
| #define SOC_AON_FWAAONM33NS_M33S 0x00000002U |
| #define SOC_AON_FWAAONM33NS_M33S_M 0x00000002U |
| #define SOC_AON_FWAAONM33NS_M33S_S 1U |
| #define SOC_AON_FWAAONM33NS_CORENS 0x00000004U |
| #define SOC_AON_FWAAONM33NS_CORENS_M 0x00000004U |
| #define SOC_AON_FWAAONM33NS_CORENS_S 2U |
| #define SOC_AON_FWCMNRTC_M33NSWR 0x00000001U |
| #define SOC_AON_FWCMNRTC_M33NSWR_M 0x00000001U |
| #define SOC_AON_FWCMNRTC_M33NSWR_S 0U |
| #define SOC_AON_FWCMNRTC_M33NSRD 0x00000002U |
| #define SOC_AON_FWCMNRTC_M33NSRD_M 0x00000002U |
| #define SOC_AON_FWCMNRTC_M33NSRD_S 1U |
| #define SOC_AON_FWCMNRTC_M33SWR 0x00000004U |
| #define SOC_AON_FWCMNRTC_M33SWR_M 0x00000004U |
| #define SOC_AON_FWCMNRTC_M33SWR_S 2U |
| #define SOC_AON_FWCMNRTC_M33SRD 0x00000008U |
| #define SOC_AON_FWCMNRTC_M33SRD_M 0x00000008U |
| #define SOC_AON_FWCMNRTC_M33SRD_S 3U |
| #define SOC_AON_FWCMNRTC_CORENSWR 0x00000010U |
| #define SOC_AON_FWCMNRTC_CORENSWR_M 0x00000010U |
| #define SOC_AON_FWCMNRTC_CORENSWR_S 4U |
| #define SOC_AON_FWCMNRTC_CORENSRD 0x00000020U |
| #define SOC_AON_FWCMNRTC_CORENSRD_M 0x00000020U |
| #define SOC_AON_FWCMNRTC_CORENSRD_S 5U |
| #define SOC_AON_FWMEMSS0_M33NS 0x00000001U |
| #define SOC_AON_FWMEMSS0_M33NS_M 0x00000001U |
| #define SOC_AON_FWMEMSS0_M33NS_S 0U |
| #define SOC_AON_FWMEMSS0_M33S 0x00000002U |
| #define SOC_AON_FWMEMSS0_M33S_M 0x00000002U |
| #define SOC_AON_FWMEMSS0_M33S_S 1U |
| #define SOC_AON_FWMEMSS0_CORENS 0x00000004U |
| #define SOC_AON_FWMEMSS0_CORENS_M 0x00000004U |
| #define SOC_AON_FWMEMSS0_CORENS_S 2U |
| #define SOC_AON_FWMEMSS0_BASE_W 10U |
| #define SOC_AON_FWMEMSS0_BASE_M 0x00003FF0U |
| #define SOC_AON_FWMEMSS0_BASE_S 4U |
| #define SOC_AON_FWMEMSS0_LEN_W 10U |
| #define SOC_AON_FWMEMSS0_LEN_M 0x03FF0000U |
| #define SOC_AON_FWMEMSS0_LEN_S 16U |
| #define SOC_AON_FWMEMSS1_M33NS 0x00000001U |
| #define SOC_AON_FWMEMSS1_M33NS_M 0x00000001U |
| #define SOC_AON_FWMEMSS1_M33NS_S 0U |
| #define SOC_AON_FWMEMSS1_M33S 0x00000002U |
| #define SOC_AON_FWMEMSS1_M33S_M 0x00000002U |
| #define SOC_AON_FWMEMSS1_M33S_S 1U |
| #define SOC_AON_FWMEMSS1_CORENS 0x00000004U |
| #define SOC_AON_FWMEMSS1_CORENS_M 0x00000004U |
| #define SOC_AON_FWMEMSS1_CORENS_S 2U |
| #define SOC_AON_FWMEMSS1_BASE_W 10U |
| #define SOC_AON_FWMEMSS1_BASE_M 0x00003FF0U |
| #define SOC_AON_FWMEMSS1_BASE_S 4U |
| #define SOC_AON_FWMEMSS1_LEN_W 10U |
| #define SOC_AON_FWMEMSS1_LEN_M 0x03FF0000U |
| #define SOC_AON_FWMEMSS1_LEN_S 16U |
| #define SOC_AON_FWMEMSS2_M33NS 0x00000001U |
| #define SOC_AON_FWMEMSS2_M33NS_M 0x00000001U |
| #define SOC_AON_FWMEMSS2_M33NS_S 0U |
| #define SOC_AON_FWMEMSS2_M33S 0x00000002U |
| #define SOC_AON_FWMEMSS2_M33S_M 0x00000002U |
| #define SOC_AON_FWMEMSS2_M33S_S 1U |
| #define SOC_AON_FWMEMSS2_CORENS 0x00000004U |
| #define SOC_AON_FWMEMSS2_CORENS_M 0x00000004U |
| #define SOC_AON_FWMEMSS2_CORENS_S 2U |
| #define SOC_AON_FWMEMSS2_BASE_W 10U |
| #define SOC_AON_FWMEMSS2_BASE_M 0x00003FF0U |
| #define SOC_AON_FWMEMSS2_BASE_S 4U |
| #define SOC_AON_FWMEMSS2_LEN_W 10U |
| #define SOC_AON_FWMEMSS2_LEN_M 0x03FF0000U |
| #define SOC_AON_FWMEMSS2_LEN_S 16U |
| #define SOC_AON_FWHOSTAON_M33NS 0x00000001U |
| #define SOC_AON_FWHOSTAON_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOSTAON_M33NS_S 0U |
| #define SOC_AON_FWHOSTAON_M33S 0x00000002U |
| #define SOC_AON_FWHOSTAON_M33S_M 0x00000002U |
| #define SOC_AON_FWHOSTAON_M33S_S 1U |
| #define SOC_AON_FWHOSTAON_CORENS 0x00000004U |
| #define SOC_AON_FWHOSTAON_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOSTAON_CORENS_S 2U |
| #define SOC_AON_FWHIF_M33NS 0x00000001U |
| #define SOC_AON_FWHIF_M33NS_M 0x00000001U |
| #define SOC_AON_FWHIF_M33NS_S 0U |
| #define SOC_AON_FWHIF_M33S 0x00000002U |
| #define SOC_AON_FWHIF_M33S_M 0x00000002U |
| #define SOC_AON_FWHIF_M33S_S 1U |
| #define SOC_AON_FWHIF_CORENS 0x00000004U |
| #define SOC_AON_FWHIF_CORENS_M 0x00000004U |
| #define SOC_AON_FWHIF_CORENS_S 2U |
| #define SOC_AON_FWHOST0_M33NS 0x00000001U |
| #define SOC_AON_FWHOST0_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST0_M33NS_S 0U |
| #define SOC_AON_FWHOST0_M33S 0x00000002U |
| #define SOC_AON_FWHOST0_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST0_M33S_S 1U |
| #define SOC_AON_FWHOST0_CORENS 0x00000004U |
| #define SOC_AON_FWHOST0_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST0_CORENS_S 2U |
| #define SOC_AON_FWHOST0_BASE_W 11U |
| #define SOC_AON_FWHOST0_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST0_BASE_S 4U |
| #define SOC_AON_FWHOST0_LEN_W 10U |
| #define SOC_AON_FWHOST0_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST0_LEN_S 16U |
| #define SOC_AON_FWHOST1_M33NS 0x00000001U |
| #define SOC_AON_FWHOST1_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST1_M33NS_S 0U |
| #define SOC_AON_FWHOST1_M33S 0x00000002U |
| #define SOC_AON_FWHOST1_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST1_M33S_S 1U |
| #define SOC_AON_FWHOST1_CORENS 0x00000004U |
| #define SOC_AON_FWHOST1_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST1_CORENS_S 2U |
| #define SOC_AON_FWHOST1_BASE_W 11U |
| #define SOC_AON_FWHOST1_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST1_BASE_S 4U |
| #define SOC_AON_FWHOST1_LEN_W 10U |
| #define SOC_AON_FWHOST1_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST1_LEN_S 16U |
| #define SOC_AON_FWHOST2_M33NS 0x00000001U |
| #define SOC_AON_FWHOST2_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST2_M33NS_S 0U |
| #define SOC_AON_FWHOST2_M33S 0x00000002U |
| #define SOC_AON_FWHOST2_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST2_M33S_S 1U |
| #define SOC_AON_FWHOST2_CORENS 0x00000004U |
| #define SOC_AON_FWHOST2_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST2_CORENS_S 2U |
| #define SOC_AON_FWHOST2_BASE_W 11U |
| #define SOC_AON_FWHOST2_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST2_BASE_S 4U |
| #define SOC_AON_FWHOST2_LEN_W 10U |
| #define SOC_AON_FWHOST2_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST2_LEN_S 16U |
| #define SOC_AON_FWHOST3_M33NS 0x00000001U |
| #define SOC_AON_FWHOST3_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST3_M33NS_S 0U |
| #define SOC_AON_FWHOST3_M33S 0x00000002U |
| #define SOC_AON_FWHOST3_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST3_M33S_S 1U |
| #define SOC_AON_FWHOST3_CORENS 0x00000004U |
| #define SOC_AON_FWHOST3_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST3_CORENS_S 2U |
| #define SOC_AON_FWHOST3_BASE_W 11U |
| #define SOC_AON_FWHOST3_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST3_BASE_S 4U |
| #define SOC_AON_FWHOST3_LEN_W 10U |
| #define SOC_AON_FWHOST3_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST3_LEN_S 16U |
| #define SOC_AON_FWHOST4_M33NS 0x00000001U |
| #define SOC_AON_FWHOST4_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST4_M33NS_S 0U |
| #define SOC_AON_FWHOST4_M33S 0x00000002U |
| #define SOC_AON_FWHOST4_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST4_M33S_S 1U |
| #define SOC_AON_FWHOST4_CORENS 0x00000004U |
| #define SOC_AON_FWHOST4_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST4_CORENS_S 2U |
| #define SOC_AON_FWHOST4_BASE_W 11U |
| #define SOC_AON_FWHOST4_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST4_BASE_S 4U |
| #define SOC_AON_FWHOST4_LEN_W 10U |
| #define SOC_AON_FWHOST4_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST4_LEN_S 16U |
| #define SOC_AON_FWHOST4_BASESEL 0x04000000U |
| #define SOC_AON_FWHOST4_BASESEL_M 0x04000000U |
| #define SOC_AON_FWHOST4_BASESEL_S 26U |
| #define SOC_AON_FWHOST5_M33NS 0x00000001U |
| #define SOC_AON_FWHOST5_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST5_M33NS_S 0U |
| #define SOC_AON_FWHOST5_M33S 0x00000002U |
| #define SOC_AON_FWHOST5_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST5_M33S_S 1U |
| #define SOC_AON_FWHOST5_CORENS 0x00000004U |
| #define SOC_AON_FWHOST5_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST5_CORENS_S 2U |
| #define SOC_AON_FWHOST5_BASE_W 11U |
| #define SOC_AON_FWHOST5_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST5_BASE_S 4U |
| #define SOC_AON_FWHOST5_LEN_W 10U |
| #define SOC_AON_FWHOST5_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST5_LEN_S 16U |
| #define SOC_AON_FWHOST5_BASESEL 0x04000000U |
| #define SOC_AON_FWHOST5_BASESEL_M 0x04000000U |
| #define SOC_AON_FWHOST5_BASESEL_S 26U |
| #define SOC_AON_FWHOST6_M33NS 0x00000001U |
| #define SOC_AON_FWHOST6_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST6_M33NS_S 0U |
| #define SOC_AON_FWHOST6_M33S 0x00000002U |
| #define SOC_AON_FWHOST6_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST6_M33S_S 1U |
| #define SOC_AON_FWHOST6_CORENS 0x00000004U |
| #define SOC_AON_FWHOST6_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST6_CORENS_S 2U |
| #define SOC_AON_FWHOST6_BASE_W 11U |
| #define SOC_AON_FWHOST6_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST6_BASE_S 4U |
| #define SOC_AON_FWHOST6_LEN_W 10U |
| #define SOC_AON_FWHOST6_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST6_LEN_S 16U |
| #define SOC_AON_FWHOST6_BASESEL 0x04000000U |
| #define SOC_AON_FWHOST6_BASESEL_M 0x04000000U |
| #define SOC_AON_FWHOST6_BASESEL_S 26U |
| #define SOC_AON_FWHOST7_M33NS 0x00000001U |
| #define SOC_AON_FWHOST7_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST7_M33NS_S 0U |
| #define SOC_AON_FWHOST7_M33S 0x00000002U |
| #define SOC_AON_FWHOST7_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST7_M33S_S 1U |
| #define SOC_AON_FWHOST7_CORENS 0x00000004U |
| #define SOC_AON_FWHOST7_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST7_CORENS_S 2U |
| #define SOC_AON_FWHOST7_BASE_W 11U |
| #define SOC_AON_FWHOST7_BASE_M 0x00007FF0U |
| #define SOC_AON_FWHOST7_BASE_S 4U |
| #define SOC_AON_FWHOST7_LEN_W 10U |
| #define SOC_AON_FWHOST7_LEN_M 0x03FF0000U |
| #define SOC_AON_FWHOST7_LEN_S 16U |
| #define SOC_AON_FWHOST7_BASESEL 0x04000000U |
| #define SOC_AON_FWHOST7_BASESEL_M 0x04000000U |
| #define SOC_AON_FWHOST7_BASESEL_S 26U |
| #define SOC_AON_FWHOST8_M33NS 0x00000001U |
| #define SOC_AON_FWHOST8_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST8_M33NS_S 0U |
| #define SOC_AON_FWHOST8_M33S 0x00000002U |
| #define SOC_AON_FWHOST8_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST8_M33S_S 1U |
| #define SOC_AON_FWHOST8_CORENS 0x00000004U |
| #define SOC_AON_FWHOST8_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST8_CORENS_S 2U |
| #define SOC_AON_FWHOST9_M33NS 0x00000001U |
| #define SOC_AON_FWHOST9_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST9_M33NS_S 0U |
| #define SOC_AON_FWHOST9_M33S 0x00000002U |
| #define SOC_AON_FWHOST9_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST9_M33S_S 1U |
| #define SOC_AON_FWHOST9_CORENS 0x00000004U |
| #define SOC_AON_FWHOST9_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST9_CORENS_S 2U |
| #define SOC_AON_FWHOST10_M33NS 0x00000001U |
| #define SOC_AON_FWHOST10_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST10_M33NS_S 0U |
| #define SOC_AON_FWHOST10_M33S 0x00000002U |
| #define SOC_AON_FWHOST10_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST10_M33S_S 1U |
| #define SOC_AON_FWHOST10_CORENS 0x00000004U |
| #define SOC_AON_FWHOST10_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST10_CORENS_S 2U |
| #define SOC_AON_FWHOST11_M33NS 0x00000001U |
| #define SOC_AON_FWHOST11_M33NS_M 0x00000001U |
| #define SOC_AON_FWHOST11_M33NS_S 0U |
| #define SOC_AON_FWHOST11_M33S 0x00000002U |
| #define SOC_AON_FWHOST11_M33S_M 0x00000002U |
| #define SOC_AON_FWHOST11_M33S_S 1U |
| #define SOC_AON_FWHOST11_CORENS 0x00000004U |
| #define SOC_AON_FWHOST11_CORENS_M 0x00000004U |
| #define SOC_AON_FWHOST11_CORENS_S 2U |
| #define SOC_AON_FWXIPOSPI_M33NS 0x00000001U |
| #define SOC_AON_FWXIPOSPI_M33NS_M 0x00000001U |
| #define SOC_AON_FWXIPOSPI_M33NS_S 0U |
| #define SOC_AON_FWXIPOSPI_M33S 0x00000002U |
| #define SOC_AON_FWXIPOSPI_M33S_M 0x00000002U |
| #define SOC_AON_FWXIPOSPI_M33S_S 1U |
| #define SOC_AON_FWXIPOSPI_CORENS 0x00000004U |
| #define SOC_AON_FWXIPOSPI_CORENS_M 0x00000004U |
| #define SOC_AON_FWXIPOSPI_CORENS_S 2U |
| #define SOC_AON_FWXIPINDAC_M33NS 0x00000001U |
| #define SOC_AON_FWXIPINDAC_M33NS_M 0x00000001U |
| #define SOC_AON_FWXIPINDAC_M33NS_S 0U |
| #define SOC_AON_FWXIPINDAC_M33S 0x00000002U |
| #define SOC_AON_FWXIPINDAC_M33S_M 0x00000002U |
| #define SOC_AON_FWXIPINDAC_M33S_S 1U |
| #define SOC_AON_FWXIPINDAC_CORENS 0x00000004U |
| #define SOC_AON_FWXIPINDAC_CORENS_M 0x00000004U |
| #define SOC_AON_FWXIPINDAC_CORENS_S 2U |
| #define SOC_AON_FWXIPGEN_M33NS 0x00000001U |
| #define SOC_AON_FWXIPGEN_M33NS_M 0x00000001U |
| #define SOC_AON_FWXIPGEN_M33NS_S 0U |
| #define SOC_AON_FWXIPGEN_M33S 0x00000002U |
| #define SOC_AON_FWXIPGEN_M33S_M 0x00000002U |
| #define SOC_AON_FWXIPGEN_M33S_S 1U |
| #define SOC_AON_FWXIPGEN_CORENS 0x00000004U |
| #define SOC_AON_FWXIPGEN_CORENS_M 0x00000004U |
| #define SOC_AON_FWXIPGEN_CORENS_S 2U |
| #define SOC_AON_FWXIPUDMAS_M33NS 0x00000001U |
| #define SOC_AON_FWXIPUDMAS_M33NS_M 0x00000001U |
| #define SOC_AON_FWXIPUDMAS_M33NS_S 0U |
| #define SOC_AON_FWXIPUDMAS_M33S 0x00000002U |
| #define SOC_AON_FWXIPUDMAS_M33S_M 0x00000002U |
| #define SOC_AON_FWXIPUDMAS_M33S_S 1U |
| #define SOC_AON_FWXIPUDMAS_CORENS 0x00000004U |
| #define SOC_AON_FWXIPUDMAS_CORENS_M 0x00000004U |
| #define SOC_AON_FWXIPUDMAS_CORENS_S 2U |
| #define SOC_AON_FWXIPUDMANS_M33NS 0x00000001U |
| #define SOC_AON_FWXIPUDMANS_M33NS_M 0x00000001U |
| #define SOC_AON_FWXIPUDMANS_M33NS_S 0U |
| #define SOC_AON_FWXIPUDMANS_M33S 0x00000002U |
| #define SOC_AON_FWXIPUDMANS_M33S_M 0x00000002U |
| #define SOC_AON_FWXIPUDMANS_M33S_S 1U |
| #define SOC_AON_FWXIPUDMANS_CORENS 0x00000004U |
| #define SOC_AON_FWXIPUDMANS_CORENS_M 0x00000004U |
| #define SOC_AON_FWXIPUDMANS_CORENS_S 2U |
| #define SOC_AON_FWOTFDE0_M33NS 0x00000001U |
| #define SOC_AON_FWOTFDE0_M33NS_M 0x00000001U |
| #define SOC_AON_FWOTFDE0_M33NS_S 0U |
| #define SOC_AON_FWOTFDE0_M33S 0x00000002U |
| #define SOC_AON_FWOTFDE0_M33S_M 0x00000002U |
| #define SOC_AON_FWOTFDE0_M33S_S 1U |
| #define SOC_AON_FWOTFDE0_CORENS 0x00000004U |
| #define SOC_AON_FWOTFDE0_CORENS_M 0x00000004U |
| #define SOC_AON_FWOTFDE0_CORENS_S 2U |
| #define SOC_AON_FWOTFDE1_M33NS 0x00000001U |
| #define SOC_AON_FWOTFDE1_M33NS_M 0x00000001U |
| #define SOC_AON_FWOTFDE1_M33NS_S 0U |
| #define SOC_AON_FWOTFDE1_M33S 0x00000002U |
| #define SOC_AON_FWOTFDE1_M33S_M 0x00000002U |
| #define SOC_AON_FWOTFDE1_M33S_S 1U |
| #define SOC_AON_FWOTFDE1_CORENS 0x00000004U |
| #define SOC_AON_FWOTFDE1_CORENS_M 0x00000004U |
| #define SOC_AON_FWOTFDE1_CORENS_S 2U |
| #define SOC_AON_FWOTFDE2_M33NS 0x00000001U |
| #define SOC_AON_FWOTFDE2_M33NS_M 0x00000001U |
| #define SOC_AON_FWOTFDE2_M33NS_S 0U |
| #define SOC_AON_FWOTFDE2_M33S 0x00000002U |
| #define SOC_AON_FWOTFDE2_M33S_M 0x00000002U |
| #define SOC_AON_FWOTFDE2_M33S_S 1U |
| #define SOC_AON_FWOTFDE2_CORENS 0x00000004U |
| #define SOC_AON_FWOTFDE2_CORENS_M 0x00000004U |
| #define SOC_AON_FWOTFDE2_CORENS_S 2U |
| #define SOC_AON_FWOTFDE3_M33NS 0x00000001U |
| #define SOC_AON_FWOTFDE3_M33NS_M 0x00000001U |
| #define SOC_AON_FWOTFDE3_M33NS_S 0U |
| #define SOC_AON_FWOTFDE3_M33S 0x00000002U |
| #define SOC_AON_FWOTFDE3_M33S_M 0x00000002U |
| #define SOC_AON_FWOTFDE3_M33S_S 1U |
| #define SOC_AON_FWOTFDE3_CORENS 0x00000004U |
| #define SOC_AON_FWOTFDE3_CORENS_M 0x00000004U |
| #define SOC_AON_FWOTFDE3_CORENS_S 2U |
| #define SOC_AON_FWDMAGEN_M33NS 0x00000001U |
| #define SOC_AON_FWDMAGEN_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMAGEN_M33NS_S 0U |
| #define SOC_AON_FWDMAGEN_M33S 0x00000002U |
| #define SOC_AON_FWDMAGEN_M33S_M 0x00000002U |
| #define SOC_AON_FWDMAGEN_M33S_S 1U |
| #define SOC_AON_FWDMAGEN_CORENS 0x00000004U |
| #define SOC_AON_FWDMAGEN_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMAGEN_CORENS_S 2U |
| #define SOC_AON_FWDMA0_M33NS 0x00000001U |
| #define SOC_AON_FWDMA0_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA0_M33NS_S 0U |
| #define SOC_AON_FWDMA0_M33S 0x00000002U |
| #define SOC_AON_FWDMA0_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA0_M33S_S 1U |
| #define SOC_AON_FWDMA0_CORENS 0x00000004U |
| #define SOC_AON_FWDMA0_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA0_CORENS_S 2U |
| #define SOC_AON_FWDMA1_M33NS 0x00000001U |
| #define SOC_AON_FWDMA1_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA1_M33NS_S 0U |
| #define SOC_AON_FWDMA1_M33S 0x00000002U |
| #define SOC_AON_FWDMA1_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA1_M33S_S 1U |
| #define SOC_AON_FWDMA1_CORENS 0x00000004U |
| #define SOC_AON_FWDMA1_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA1_CORENS_S 2U |
| #define SOC_AON_FWDMA2_M33NS 0x00000001U |
| #define SOC_AON_FWDMA2_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA2_M33NS_S 0U |
| #define SOC_AON_FWDMA2_M33S 0x00000002U |
| #define SOC_AON_FWDMA2_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA2_M33S_S 1U |
| #define SOC_AON_FWDMA2_CORENS 0x00000004U |
| #define SOC_AON_FWDMA2_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA2_CORENS_S 2U |
| #define SOC_AON_FWDMA3_M33NS 0x00000001U |
| #define SOC_AON_FWDMA3_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA3_M33NS_S 0U |
| #define SOC_AON_FWDMA3_M33S 0x00000002U |
| #define SOC_AON_FWDMA3_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA3_M33S_S 1U |
| #define SOC_AON_FWDMA3_CORENS 0x00000004U |
| #define SOC_AON_FWDMA3_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA3_CORENS_S 2U |
| #define SOC_AON_FWDMA4_M33NS 0x00000001U |
| #define SOC_AON_FWDMA4_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA4_M33NS_S 0U |
| #define SOC_AON_FWDMA4_M33S 0x00000002U |
| #define SOC_AON_FWDMA4_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA4_M33S_S 1U |
| #define SOC_AON_FWDMA4_CORENS 0x00000004U |
| #define SOC_AON_FWDMA4_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA4_CORENS_S 2U |
| #define SOC_AON_FWDMA5_M33NS 0x00000001U |
| #define SOC_AON_FWDMA5_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA5_M33NS_S 0U |
| #define SOC_AON_FWDMA5_M33S 0x00000002U |
| #define SOC_AON_FWDMA5_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA5_M33S_S 1U |
| #define SOC_AON_FWDMA5_CORENS 0x00000004U |
| #define SOC_AON_FWDMA5_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA5_CORENS_S 2U |
| #define SOC_AON_FWDMA6_M33NS 0x00000001U |
| #define SOC_AON_FWDMA6_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA6_M33NS_S 0U |
| #define SOC_AON_FWDMA6_M33S 0x00000002U |
| #define SOC_AON_FWDMA6_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA6_M33S_S 1U |
| #define SOC_AON_FWDMA6_CORENS 0x00000004U |
| #define SOC_AON_FWDMA6_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA6_CORENS_S 2U |
| #define SOC_AON_FWDMA7_M33NS 0x00000001U |
| #define SOC_AON_FWDMA7_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA7_M33NS_S 0U |
| #define SOC_AON_FWDMA7_M33S 0x00000002U |
| #define SOC_AON_FWDMA7_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA7_M33S_S 1U |
| #define SOC_AON_FWDMA7_CORENS 0x00000004U |
| #define SOC_AON_FWDMA7_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA7_CORENS_S 2U |
| #define SOC_AON_FWDMA8_M33NS 0x00000001U |
| #define SOC_AON_FWDMA8_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA8_M33NS_S 0U |
| #define SOC_AON_FWDMA8_M33S 0x00000002U |
| #define SOC_AON_FWDMA8_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA8_M33S_S 1U |
| #define SOC_AON_FWDMA8_CORENS 0x00000004U |
| #define SOC_AON_FWDMA8_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA8_CORENS_S 2U |
| #define SOC_AON_FWDMA9_M33NS 0x00000001U |
| #define SOC_AON_FWDMA9_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA9_M33NS_S 0U |
| #define SOC_AON_FWDMA9_M33S 0x00000002U |
| #define SOC_AON_FWDMA9_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA9_M33S_S 1U |
| #define SOC_AON_FWDMA9_CORENS 0x00000004U |
| #define SOC_AON_FWDMA9_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA9_CORENS_S 2U |
| #define SOC_AON_FWDMA10_M33NS 0x00000001U |
| #define SOC_AON_FWDMA10_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA10_M33NS_S 0U |
| #define SOC_AON_FWDMA10_M33S 0x00000002U |
| #define SOC_AON_FWDMA10_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA10_M33S_S 1U |
| #define SOC_AON_FWDMA10_CORENS 0x00000004U |
| #define SOC_AON_FWDMA10_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA10_CORENS_S 2U |
| #define SOC_AON_FWDMA11_M33NS 0x00000001U |
| #define SOC_AON_FWDMA11_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA11_M33NS_S 0U |
| #define SOC_AON_FWDMA11_M33S 0x00000002U |
| #define SOC_AON_FWDMA11_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA11_M33S_S 1U |
| #define SOC_AON_FWDMA11_CORENS 0x00000004U |
| #define SOC_AON_FWDMA11_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA11_CORENS_S 2U |
| #define SOC_AON_FWHSMEIPNS_M33NS 0x00000001U |
| #define SOC_AON_FWHSMEIPNS_M33NS_M 0x00000001U |
| #define SOC_AON_FWHSMEIPNS_M33NS_S 0U |
| #define SOC_AON_FWHSMEIPNS_M33S 0x00000002U |
| #define SOC_AON_FWHSMEIPNS_M33S_M 0x00000002U |
| #define SOC_AON_FWHSMEIPNS_M33S_S 1U |
| #define SOC_AON_FWHSMEIPNS_CORENS 0x00000004U |
| #define SOC_AON_FWHSMEIPNS_CORENS_M 0x00000004U |
| #define SOC_AON_FWHSMEIPNS_CORENS_S 2U |
| #define SOC_AON_FWHSMEIPNS_BASE_W 5U |
| #define SOC_AON_FWHSMEIPNS_BASE_M 0x000001F0U |
| #define SOC_AON_FWHSMEIPNS_BASE_S 4U |
| #define SOC_AON_FWHSMEIPNS_LEN_W 5U |
| #define SOC_AON_FWHSMEIPNS_LEN_M 0x001F0000U |
| #define SOC_AON_FWHSMEIPNS_LEN_S 16U |
| #define SOC_AON_FWHSMEIPS_M33NS 0x00000001U |
| #define SOC_AON_FWHSMEIPS_M33NS_M 0x00000001U |
| #define SOC_AON_FWHSMEIPS_M33NS_S 0U |
| #define SOC_AON_FWHSMEIPS_M33S 0x00000002U |
| #define SOC_AON_FWHSMEIPS_M33S_M 0x00000002U |
| #define SOC_AON_FWHSMEIPS_M33S_S 1U |
| #define SOC_AON_FWHSMEIPS_CORENS 0x00000004U |
| #define SOC_AON_FWHSMEIPS_CORENS_M 0x00000004U |
| #define SOC_AON_FWHSMEIPS_CORENS_S 2U |
| #define SOC_AON_FWHSMEIPS_BASE_W 5U |
| #define SOC_AON_FWHSMEIPS_BASE_M 0x000001F0U |
| #define SOC_AON_FWHSMEIPS_BASE_S 4U |
| #define SOC_AON_FWHSMEIPS_LEN_W 5U |
| #define SOC_AON_FWHSMEIPS_LEN_M 0x001F0000U |
| #define SOC_AON_FWHSMEIPS_LEN_S 16U |
| #define SOC_AON_FWHSMWRAPNS_M33NS 0x00000001U |
| #define SOC_AON_FWHSMWRAPNS_M33NS_M 0x00000001U |
| #define SOC_AON_FWHSMWRAPNS_M33NS_S 0U |
| #define SOC_AON_FWHSMWRAPNS_M33S 0x00000002U |
| #define SOC_AON_FWHSMWRAPNS_M33S_M 0x00000002U |
| #define SOC_AON_FWHSMWRAPNS_M33S_S 1U |
| #define SOC_AON_FWHSMWRAPNS_CORENS 0x00000004U |
| #define SOC_AON_FWHSMWRAPNS_CORENS_M 0x00000004U |
| #define SOC_AON_FWHSMWRAPNS_CORENS_S 2U |
| #define SOC_AON_FWHSMWRAPS_M33NS 0x00000001U |
| #define SOC_AON_FWHSMWRAPS_M33NS_M 0x00000001U |
| #define SOC_AON_FWHSMWRAPS_M33NS_S 0U |
| #define SOC_AON_FWHSMWRAPS_M33S 0x00000002U |
| #define SOC_AON_FWHSMWRAPS_M33S_M 0x00000002U |
| #define SOC_AON_FWHSMWRAPS_M33S_S 1U |
| #define SOC_AON_FWHSMWRAPS_CORENS 0x00000004U |
| #define SOC_AON_FWHSMWRAPS_CORENS_M 0x00000004U |
| #define SOC_AON_FWHSMWRAPS_CORENS_S 2U |
| #define SOC_AON_FWHSMDBG_M33NS 0x00000001U |
| #define SOC_AON_FWHSMDBG_M33NS_M 0x00000001U |
| #define SOC_AON_FWHSMDBG_M33NS_S 0U |
| #define SOC_AON_FWHSMDBG_M33S 0x00000002U |
| #define SOC_AON_FWHSMDBG_M33S_M 0x00000002U |
| #define SOC_AON_FWHSMDBG_M33S_S 1U |
| #define SOC_AON_FWHSMDBG_CORENS 0x00000004U |
| #define SOC_AON_FWHSMDBG_CORENS_M 0x00000004U |
| #define SOC_AON_FWHSMDBG_CORENS_S 2U |
| #define SOC_AON_FWI2C0_M33NS 0x00000001U |
| #define SOC_AON_FWI2C0_M33NS_M 0x00000001U |
| #define SOC_AON_FWI2C0_M33NS_S 0U |
| #define SOC_AON_FWI2C0_M33S 0x00000002U |
| #define SOC_AON_FWI2C0_M33S_M 0x00000002U |
| #define SOC_AON_FWI2C0_M33S_S 1U |
| #define SOC_AON_FWI2C0_CORENS 0x00000004U |
| #define SOC_AON_FWI2C0_CORENS_M 0x00000004U |
| #define SOC_AON_FWI2C0_CORENS_S 2U |
| #define SOC_AON_FWI2C1_M33NS 0x00000001U |
| #define SOC_AON_FWI2C1_M33NS_M 0x00000001U |
| #define SOC_AON_FWI2C1_M33NS_S 0U |
| #define SOC_AON_FWI2C1_M33S 0x00000002U |
| #define SOC_AON_FWI2C1_M33S_M 0x00000002U |
| #define SOC_AON_FWI2C1_M33S_S 1U |
| #define SOC_AON_FWI2C1_CORENS 0x00000004U |
| #define SOC_AON_FWI2C1_CORENS_M 0x00000004U |
| #define SOC_AON_FWI2C1_CORENS_S 2U |
| #define SOC_AON_FWSPSPI0_M33NS 0x00000001U |
| #define SOC_AON_FWSPSPI0_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPSPI0_M33NS_S 0U |
| #define SOC_AON_FWSPSPI0_M33S 0x00000002U |
| #define SOC_AON_FWSPSPI0_M33S_M 0x00000002U |
| #define SOC_AON_FWSPSPI0_M33S_S 1U |
| #define SOC_AON_FWSPSPI0_CORENS 0x00000004U |
| #define SOC_AON_FWSPSPI0_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPSPI0_CORENS_S 2U |
| #define SOC_AON_FWSPSPI1_M33NS 0x00000001U |
| #define SOC_AON_FWSPSPI1_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPSPI1_M33NS_S 0U |
| #define SOC_AON_FWSPSPI1_M33S 0x00000002U |
| #define SOC_AON_FWSPSPI1_M33S_M 0x00000002U |
| #define SOC_AON_FWSPSPI1_M33S_S 1U |
| #define SOC_AON_FWSPSPI1_CORENS 0x00000004U |
| #define SOC_AON_FWSPSPI1_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPSPI1_CORENS_S 2U |
| #define SOC_AON_FWSPUART0_M33NS 0x00000001U |
| #define SOC_AON_FWSPUART0_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPUART0_M33NS_S 0U |
| #define SOC_AON_FWSPUART0_M33S 0x00000002U |
| #define SOC_AON_FWSPUART0_M33S_M 0x00000002U |
| #define SOC_AON_FWSPUART0_M33S_S 1U |
| #define SOC_AON_FWSPUART0_CORENS 0x00000004U |
| #define SOC_AON_FWSPUART0_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPUART0_CORENS_S 2U |
| #define SOC_AON_FWSPUART1_M33NS 0x00000001U |
| #define SOC_AON_FWSPUART1_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPUART1_M33NS_S 0U |
| #define SOC_AON_FWSPUART1_M33S 0x00000002U |
| #define SOC_AON_FWSPUART1_M33S_M 0x00000002U |
| #define SOC_AON_FWSPUART1_M33S_S 1U |
| #define SOC_AON_FWSPUART1_CORENS 0x00000004U |
| #define SOC_AON_FWSPUART1_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPUART1_CORENS_S 2U |
| #define SOC_AON_FWSPGPT0_M33NS 0x00000001U |
| #define SOC_AON_FWSPGPT0_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPGPT0_M33NS_S 0U |
| #define SOC_AON_FWSPGPT0_M33S 0x00000002U |
| #define SOC_AON_FWSPGPT0_M33S_M 0x00000002U |
| #define SOC_AON_FWSPGPT0_M33S_S 1U |
| #define SOC_AON_FWSPGPT0_CORENS 0x00000004U |
| #define SOC_AON_FWSPGPT0_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPGPT0_CORENS_S 2U |
| #define SOC_AON_FWSPGPT1_M33NS 0x00000001U |
| #define SOC_AON_FWSPGPT1_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPGPT1_M33NS_S 0U |
| #define SOC_AON_FWSPGPT1_M33S 0x00000002U |
| #define SOC_AON_FWSPGPT1_M33S_M 0x00000002U |
| #define SOC_AON_FWSPGPT1_M33S_S 1U |
| #define SOC_AON_FWSPGPT1_CORENS 0x00000004U |
| #define SOC_AON_FWSPGPT1_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPGPT1_CORENS_S 2U |
| #define SOC_AON_FWSPI2S_M33NS 0x00000001U |
| #define SOC_AON_FWSPI2S_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPI2S_M33NS_S 0U |
| #define SOC_AON_FWSPI2S_M33S 0x00000002U |
| #define SOC_AON_FWSPI2S_M33S_M 0x00000002U |
| #define SOC_AON_FWSPI2S_M33S_S 1U |
| #define SOC_AON_FWSPI2S_CORENS 0x00000004U |
| #define SOC_AON_FWSPI2S_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPI2S_CORENS_S 2U |
| #define SOC_AON_FWPDM_M33NS 0x00000001U |
| #define SOC_AON_FWPDM_M33NS_M 0x00000001U |
| #define SOC_AON_FWPDM_M33NS_S 0U |
| #define SOC_AON_FWPDM_M33S 0x00000002U |
| #define SOC_AON_FWPDM_M33S_M 0x00000002U |
| #define SOC_AON_FWPDM_M33S_S 1U |
| #define SOC_AON_FWPDM_CORENS 0x00000004U |
| #define SOC_AON_FWPDM_CORENS_M 0x00000004U |
| #define SOC_AON_FWPDM_CORENS_S 2U |
| #define SOC_AON_FWSPCAN_M33NS 0x00000001U |
| #define SOC_AON_FWSPCAN_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPCAN_M33NS_S 0U |
| #define SOC_AON_FWSPCAN_M33S 0x00000002U |
| #define SOC_AON_FWSPCAN_M33S_M 0x00000002U |
| #define SOC_AON_FWSPCAN_M33S_S 1U |
| #define SOC_AON_FWSPCAN_CORENS 0x00000004U |
| #define SOC_AON_FWSPCAN_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPCAN_CORENS_S 2U |
| #define SOC_AON_FWSPADC_M33NS 0x00000001U |
| #define SOC_AON_FWSPADC_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPADC_M33NS_S 0U |
| #define SOC_AON_FWSPADC_M33S 0x00000002U |
| #define SOC_AON_FWSPADC_M33S_M 0x00000002U |
| #define SOC_AON_FWSPADC_M33S_S 1U |
| #define SOC_AON_FWSPADC_CORENS 0x00000004U |
| #define SOC_AON_FWSPADC_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPADC_CORENS_S 2U |
| #define SOC_AON_FWSPSDMMC_M33NS 0x00000001U |
| #define SOC_AON_FWSPSDMMC_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPSDMMC_M33NS_S 0U |
| #define SOC_AON_FWSPSDMMC_M33S 0x00000002U |
| #define SOC_AON_FWSPSDMMC_M33S_M 0x00000002U |
| #define SOC_AON_FWSPSDMMC_M33S_S 1U |
| #define SOC_AON_FWSPSDMMC_CORENS 0x00000004U |
| #define SOC_AON_FWSPSDMMC_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPSDMMC_CORENS_S 2U |
| #define SOC_AON_FWSPSDIO_M33NS 0x00000001U |
| #define SOC_AON_FWSPSDIO_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPSDIO_M33NS_S 0U |
| #define SOC_AON_FWSPSDIO_M33S 0x00000002U |
| #define SOC_AON_FWSPSDIO_M33S_M 0x00000002U |
| #define SOC_AON_FWSPSDIO_M33S_S 1U |
| #define SOC_AON_FWSPSDIO_CORENS 0x00000004U |
| #define SOC_AON_FWSPSDIO_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPSDIO_CORENS_S 2U |
| #define SOC_AON_FWSPUART2_M33NS 0x00000001U |
| #define SOC_AON_FWSPUART2_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPUART2_M33NS_S 0U |
| #define SOC_AON_FWSPUART2_M33S 0x00000002U |
| #define SOC_AON_FWSPUART2_M33S_M 0x00000002U |
| #define SOC_AON_FWSPUART2_M33S_S 1U |
| #define SOC_AON_FWSPUART2_CORENS 0x00000004U |
| #define SOC_AON_FWSPUART2_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPUART2_CORENS_S 2U |
| #define SOC_AON_UDMANSCTL_ACCPER 0x00000001U |
| #define SOC_AON_UDMANSCTL_ACCPER_M 0x00000001U |
| #define SOC_AON_UDMANSCTL_ACCPER_S 0U |
| #define SOC_AON_FWIOPAD0_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD0_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD0_M33NS_S 0U |
| #define SOC_AON_FWIOPAD0_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD0_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD0_M33S_S 1U |
| #define SOC_AON_FWIOPAD0_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD0_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD0_CORENS_S 2U |
| #define SOC_AON_FWIOPAD1_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD1_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD1_M33NS_S 0U |
| #define SOC_AON_FWIOPAD1_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD1_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD1_M33S_S 1U |
| #define SOC_AON_FWIOPAD1_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD1_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD1_CORENS_S 2U |
| #define SOC_AON_FWIOPAD2_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD2_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD2_M33NS_S 0U |
| #define SOC_AON_FWIOPAD2_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD2_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD2_M33S_S 1U |
| #define SOC_AON_FWIOPAD2_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD2_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD2_CORENS_S 2U |
| #define SOC_AON_FWIOPAD3_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD3_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD3_M33NS_S 0U |
| #define SOC_AON_FWIOPAD3_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD3_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD3_M33S_S 1U |
| #define SOC_AON_FWIOPAD3_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD3_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD3_CORENS_S 2U |
| #define SOC_AON_FWIOPAD4_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD4_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD4_M33NS_S 0U |
| #define SOC_AON_FWIOPAD4_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD4_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD4_M33S_S 1U |
| #define SOC_AON_FWIOPAD4_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD4_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD4_CORENS_S 2U |
| #define SOC_AON_FWIOPAD5_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD5_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD5_M33NS_S 0U |
| #define SOC_AON_FWIOPAD5_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD5_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD5_M33S_S 1U |
| #define SOC_AON_FWIOPAD5_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD5_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD5_CORENS_S 2U |
| #define SOC_AON_FWIOPAD6_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD6_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD6_M33NS_S 0U |
| #define SOC_AON_FWIOPAD6_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD6_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD6_M33S_S 1U |
| #define SOC_AON_FWIOPAD6_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD6_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD6_CORENS_S 2U |
| #define SOC_AON_FWIOPAD7_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD7_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD7_M33NS_S 0U |
| #define SOC_AON_FWIOPAD7_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD7_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD7_M33S_S 1U |
| #define SOC_AON_FWIOPAD7_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD7_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD7_CORENS_S 2U |
| #define SOC_AON_FWIOPAD8_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD8_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD8_M33NS_S 0U |
| #define SOC_AON_FWIOPAD8_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD8_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD8_M33S_S 1U |
| #define SOC_AON_FWIOPAD8_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD8_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD8_CORENS_S 2U |
| #define SOC_AON_FWIOPAD9_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD9_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD9_M33NS_S 0U |
| #define SOC_AON_FWIOPAD9_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD9_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD9_M33S_S 1U |
| #define SOC_AON_FWIOPAD9_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD9_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD9_CORENS_S 2U |
| #define SOC_AON_FWIOPAD10_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD10_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD10_M33NS_S 0U |
| #define SOC_AON_FWIOPAD10_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD10_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD10_M33S_S 1U |
| #define SOC_AON_FWIOPAD10_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD10_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD10_CORENS_S 2U |
| #define SOC_AON_FWIOPAD11_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD11_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD11_M33NS_S 0U |
| #define SOC_AON_FWIOPAD11_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD11_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD11_M33S_S 1U |
| #define SOC_AON_FWIOPAD11_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD11_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD11_CORENS_S 2U |
| #define SOC_AON_FWIOPAD12_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD12_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD12_M33NS_S 0U |
| #define SOC_AON_FWIOPAD12_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD12_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD12_M33S_S 1U |
| #define SOC_AON_FWIOPAD12_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD12_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD12_CORENS_S 2U |
| #define SOC_AON_FWIOPAD13_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD13_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD13_M33NS_S 0U |
| #define SOC_AON_FWIOPAD13_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD13_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD13_M33S_S 1U |
| #define SOC_AON_FWIOPAD13_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD13_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD13_CORENS_S 2U |
| #define SOC_AON_FWIOPAD14_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD14_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD14_M33NS_S 0U |
| #define SOC_AON_FWIOPAD14_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD14_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD14_M33S_S 1U |
| #define SOC_AON_FWIOPAD14_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD14_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD14_CORENS_S 2U |
| #define SOC_AON_FWIOPAD15_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD15_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD15_M33NS_S 0U |
| #define SOC_AON_FWIOPAD15_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD15_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD15_M33S_S 1U |
| #define SOC_AON_FWIOPAD15_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD15_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD15_CORENS_S 2U |
| #define SOC_AON_FWIOPAD16_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD16_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD16_M33NS_S 0U |
| #define SOC_AON_FWIOPAD16_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD16_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD16_M33S_S 1U |
| #define SOC_AON_FWIOPAD16_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD16_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD16_CORENS_S 2U |
| #define SOC_AON_FWIOPAD17_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD17_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD17_M33NS_S 0U |
| #define SOC_AON_FWIOPAD17_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD17_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD17_M33S_S 1U |
| #define SOC_AON_FWIOPAD17_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD17_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD17_CORENS_S 2U |
| #define SOC_AON_FWIOPAD18_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD18_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD18_M33NS_S 0U |
| #define SOC_AON_FWIOPAD18_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD18_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD18_M33S_S 1U |
| #define SOC_AON_FWIOPAD18_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD18_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD18_CORENS_S 2U |
| #define SOC_AON_FWIOPAD19_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD19_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD19_M33NS_S 0U |
| #define SOC_AON_FWIOPAD19_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD19_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD19_M33S_S 1U |
| #define SOC_AON_FWIOPAD19_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD19_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD19_CORENS_S 2U |
| #define SOC_AON_FWIOPAD20_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD20_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD20_M33NS_S 0U |
| #define SOC_AON_FWIOPAD20_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD20_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD20_M33S_S 1U |
| #define SOC_AON_FWIOPAD20_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD20_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD20_CORENS_S 2U |
| #define SOC_AON_FWIOPAD21_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD21_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD21_M33NS_S 0U |
| #define SOC_AON_FWIOPAD21_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD21_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD21_M33S_S 1U |
| #define SOC_AON_FWIOPAD21_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD21_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD21_CORENS_S 2U |
| #define SOC_AON_FWIOPAD22_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD22_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD22_M33NS_S 0U |
| #define SOC_AON_FWIOPAD22_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD22_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD22_M33S_S 1U |
| #define SOC_AON_FWIOPAD22_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD22_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD22_CORENS_S 2U |
| #define SOC_AON_FWIOPAD23_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD23_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD23_M33NS_S 0U |
| #define SOC_AON_FWIOPAD23_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD23_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD23_M33S_S 1U |
| #define SOC_AON_FWIOPAD23_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD23_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD23_CORENS_S 2U |
| #define SOC_AON_FWIOPAD24_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD24_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD24_M33NS_S 0U |
| #define SOC_AON_FWIOPAD24_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD24_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD24_M33S_S 1U |
| #define SOC_AON_FWIOPAD24_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD24_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD24_CORENS_S 2U |
| #define SOC_AON_FWIOPAD25_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD25_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD25_M33NS_S 0U |
| #define SOC_AON_FWIOPAD25_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD25_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD25_M33S_S 1U |
| #define SOC_AON_FWIOPAD25_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD25_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD25_CORENS_S 2U |
| #define SOC_AON_FWIOPAD26_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD26_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD26_M33NS_S 0U |
| #define SOC_AON_FWIOPAD26_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD26_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD26_M33S_S 1U |
| #define SOC_AON_FWIOPAD26_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD26_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD26_CORENS_S 2U |
| #define SOC_AON_FWIOPAD27_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD27_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD27_M33NS_S 0U |
| #define SOC_AON_FWIOPAD27_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD27_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD27_M33S_S 1U |
| #define SOC_AON_FWIOPAD27_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD27_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD27_CORENS_S 2U |
| #define SOC_AON_FWIOPAD28_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD28_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD28_M33NS_S 0U |
| #define SOC_AON_FWIOPAD28_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD28_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD28_M33S_S 1U |
| #define SOC_AON_FWIOPAD28_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD28_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD28_CORENS_S 2U |
| #define SOC_AON_FWIOPAD29_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD29_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD29_M33NS_S 0U |
| #define SOC_AON_FWIOPAD29_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD29_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD29_M33S_S 1U |
| #define SOC_AON_FWIOPAD29_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD29_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD29_CORENS_S 2U |
| #define SOC_AON_FWIOPAD30_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD30_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD30_M33NS_S 0U |
| #define SOC_AON_FWIOPAD30_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD30_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD30_M33S_S 1U |
| #define SOC_AON_FWIOPAD30_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD30_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD30_CORENS_S 2U |
| #define SOC_AON_FWIOPAD31_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD31_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD31_M33NS_S 0U |
| #define SOC_AON_FWIOPAD31_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD31_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD31_M33S_S 1U |
| #define SOC_AON_FWIOPAD31_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD31_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD31_CORENS_S 2U |
| #define SOC_AON_FWIOPAD32_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD32_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD32_M33NS_S 0U |
| #define SOC_AON_FWIOPAD32_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD32_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD32_M33S_S 1U |
| #define SOC_AON_FWIOPAD32_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD32_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD32_CORENS_S 2U |
| #define SOC_AON_FWIOPAD33_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD33_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD33_M33NS_S 0U |
| #define SOC_AON_FWIOPAD33_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD33_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD33_M33S_S 1U |
| #define SOC_AON_FWIOPAD33_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD33_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD33_CORENS_S 2U |
| #define SOC_AON_FWIOPAD34_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD34_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD34_M33NS_S 0U |
| #define SOC_AON_FWIOPAD34_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD34_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD34_M33S_S 1U |
| #define SOC_AON_FWIOPAD34_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD34_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD34_CORENS_S 2U |
| #define SOC_AON_FWIOPAD35_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD35_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD35_M33NS_S 0U |
| #define SOC_AON_FWIOPAD35_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD35_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD35_M33S_S 1U |
| #define SOC_AON_FWIOPAD35_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD35_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD35_CORENS_S 2U |
| #define SOC_AON_FWIOPAD36_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD36_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD36_M33NS_S 0U |
| #define SOC_AON_FWIOPAD36_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD36_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD36_M33S_S 1U |
| #define SOC_AON_FWIOPAD36_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD36_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD36_CORENS_S 2U |
| #define SOC_AON_FWIOPAD37_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD37_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD37_M33NS_S 0U |
| #define SOC_AON_FWIOPAD37_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD37_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD37_M33S_S 1U |
| #define SOC_AON_FWIOPAD37_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD37_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD37_CORENS_S 2U |
| #define SOC_AON_FWIOPAD38_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD38_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD38_M33NS_S 0U |
| #define SOC_AON_FWIOPAD38_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD38_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD38_M33S_S 1U |
| #define SOC_AON_FWIOPAD38_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD38_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD38_CORENS_S 2U |
| #define SOC_AON_FWIOPAD39_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD39_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD39_M33NS_S 0U |
| #define SOC_AON_FWIOPAD39_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD39_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD39_M33S_S 1U |
| #define SOC_AON_FWIOPAD39_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD39_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD39_CORENS_S 2U |
| #define SOC_AON_FWIOPAD40_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD40_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD40_M33NS_S 0U |
| #define SOC_AON_FWIOPAD40_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD40_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD40_M33S_S 1U |
| #define SOC_AON_FWIOPAD40_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD40_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD40_CORENS_S 2U |
| #define SOC_AON_FWIOPAD41_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD41_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD41_M33NS_S 0U |
| #define SOC_AON_FWIOPAD41_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD41_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD41_M33S_S 1U |
| #define SOC_AON_FWIOPAD41_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD41_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD41_CORENS_S 2U |
| #define SOC_AON_FWIOPAD42_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD42_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD42_M33NS_S 0U |
| #define SOC_AON_FWIOPAD42_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD42_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD42_M33S_S 1U |
| #define SOC_AON_FWIOPAD42_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD42_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD42_CORENS_S 2U |
| #define SOC_AON_FWIOPAD43_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD43_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD43_M33NS_S 0U |
| #define SOC_AON_FWIOPAD43_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD43_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD43_M33S_S 1U |
| #define SOC_AON_FWIOPAD43_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD43_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD43_CORENS_S 2U |
| #define SOC_AON_FWIOPAD44_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD44_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD44_M33NS_S 0U |
| #define SOC_AON_FWIOPAD44_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD44_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD44_M33S_S 1U |
| #define SOC_AON_FWIOPAD44_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD44_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD44_CORENS_S 2U |
| #define SOC_AON_FWIOPAD45_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD45_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD45_M33NS_S 0U |
| #define SOC_AON_FWIOPAD45_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD45_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD45_M33S_S 1U |
| #define SOC_AON_FWIOPAD45_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD45_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD45_CORENS_S 2U |
| #define SOC_AON_FWIOPAD46_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD46_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD46_M33NS_S 0U |
| #define SOC_AON_FWIOPAD46_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD46_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD46_M33S_S 1U |
| #define SOC_AON_FWIOPAD46_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD46_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD46_CORENS_S 2U |
| #define SOC_AON_FWIOPAD47_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD47_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD47_M33NS_S 0U |
| #define SOC_AON_FWIOPAD47_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD47_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD47_M33S_S 1U |
| #define SOC_AON_FWIOPAD47_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD47_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD47_CORENS_S 2U |
| #define SOC_AON_FWIOPAD48_M33NS 0x00000001U |
| #define SOC_AON_FWIOPAD48_M33NS_M 0x00000001U |
| #define SOC_AON_FWIOPAD48_M33NS_S 0U |
| #define SOC_AON_FWIOPAD48_M33S 0x00000002U |
| #define SOC_AON_FWIOPAD48_M33S_M 0x00000002U |
| #define SOC_AON_FWIOPAD48_M33S_S 1U |
| #define SOC_AON_FWIOPAD48_CORENS 0x00000004U |
| #define SOC_AON_FWIOPAD48_CORENS_M 0x00000004U |
| #define SOC_AON_FWIOPAD48_CORENS_S 2U |
| #define SOC_AON_FWDMA12_M33NS 0x00000001U |
| #define SOC_AON_FWDMA12_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA12_M33NS_S 0U |
| #define SOC_AON_FWDMA12_M33S 0x00000002U |
| #define SOC_AON_FWDMA12_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA12_M33S_S 1U |
| #define SOC_AON_FWDMA12_CORENS 0x00000004U |
| #define SOC_AON_FWDMA12_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA12_CORENS_S 2U |
| #define SOC_AON_FWDMA13_M33NS 0x00000001U |
| #define SOC_AON_FWDMA13_M33NS_M 0x00000001U |
| #define SOC_AON_FWDMA13_M33NS_S 0U |
| #define SOC_AON_FWDMA13_M33S 0x00000002U |
| #define SOC_AON_FWDMA13_M33S_M 0x00000002U |
| #define SOC_AON_FWDMA13_M33S_S 1U |
| #define SOC_AON_FWDMA13_CORENS 0x00000004U |
| #define SOC_AON_FWDMA13_CORENS_M 0x00000004U |
| #define SOC_AON_FWDMA13_CORENS_S 2U |
| #define SOC_AON_FWSPARE0_M33NS 0x00000001U |
| #define SOC_AON_FWSPARE0_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPARE0_M33NS_S 0U |
| #define SOC_AON_FWSPARE0_M33S 0x00000002U |
| #define SOC_AON_FWSPARE0_M33S_M 0x00000002U |
| #define SOC_AON_FWSPARE0_M33S_S 1U |
| #define SOC_AON_FWSPARE0_CORENS 0x00000004U |
| #define SOC_AON_FWSPARE0_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPARE0_CORENS_S 2U |
| #define SOC_AON_USECSTB_US_W 8U |
| #define SOC_AON_USECSTB_US_M 0x000000FFU |
| #define SOC_AON_USECSTB_US_S 0U |
| #define SOC_AON_USECSTB_16US_W 6U |
| #define SOC_AON_USECSTB_16US_M 0x00003F00U |
| #define SOC_AON_USECSTB_16US_S 8U |
| #define SOC_AON_DB2M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB2M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB2M33CLR_CLR_S 0U |
| #define SOC_AON_DB2M33SET_SET 0x00000001U |
| #define SOC_AON_DB2M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB2M33SET_SET_S 0U |
| #define SOC_AON_DB2M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB2M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB2M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB3M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB3M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB3M33CLR_CLR_S 0U |
| #define SOC_AON_DB3M33SET_SET 0x00000001U |
| #define SOC_AON_DB3M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB3M33SET_SET_S 0U |
| #define SOC_AON_DB3M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB3M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB3M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB6M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB6M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB6M33CLR_CLR_S 0U |
| #define SOC_AON_DB6M33SET_SET 0x00000001U |
| #define SOC_AON_DB6M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB6M33SET_SET_S 0U |
| #define SOC_AON_DB6M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB6M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB6M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB7M33CLR_CLR 0x00000001U |
| #define SOC_AON_DB7M33CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB7M33CLR_CLR_S 0U |
| #define SOC_AON_DB7M33SET_SET 0x00000001U |
| #define SOC_AON_DB7M33SET_SET_M 0x00000001U |
| #define SOC_AON_DB7M33SET_SET_S 0U |
| #define SOC_AON_DB7M33LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB7M33LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB7M33LOCK_LOCKBIT_S 0U |
| #define SOC_AON_GPIOEVT0NS_STA31TO0_W 32U |
| #define SOC_AON_GPIOEVT0NS_STA31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_GPIOEVT0NS_STA31TO0_S 0U |
| #define SOC_AON_GPIOEVT1NS_STA44TO32_W 13U |
| #define SOC_AON_GPIOEVT1NS_STA44TO32_M 0x00001FFFU |
| #define SOC_AON_GPIOEVT1NS_STA44TO32_S 0U |
| #define SOC_AON_DBM33NS0_IMASK_W 4U |
| #define SOC_AON_DBM33NS0_IMASK_M 0x0000000FU |
| #define SOC_AON_DBM33NS0_IMASK_S 0U |
| #define SOC_AON_DBNSISET_ISET_W 4U |
| #define SOC_AON_DBNSISET_ISET_M 0x0000000FU |
| #define SOC_AON_DBNSISET_ISET_S 0U |
| #define SOC_AON_DBNSICLR_ICLR_W 4U |
| #define SOC_AON_DBNSICLR_ICLR_M 0x0000000FU |
| #define SOC_AON_DBNSICLR_ICLR_S 0U |
| #define SOC_AON_DBNSIMSET_IMSET_W 4U |
| #define SOC_AON_DBNSIMSET_IMSET_M 0x0000000FU |
| #define SOC_AON_DBNSIMSET_IMSET_S 0U |
| #define SOC_AON_DBNSIMCLR_IMCLR_W 4U |
| #define SOC_AON_DBNSIMCLR_IMCLR_M 0x0000000FU |
| #define SOC_AON_DBNSIMCLR_IMCLR_S 0U |
| #define SOC_AON_DBNSRIS_RIS_W 4U |
| #define SOC_AON_DBNSRIS_RIS_M 0x0000000FU |
| #define SOC_AON_DBNSRIS_RIS_S 0U |
| #define SOC_AON_DBNSMIS_MIS_W 4U |
| #define SOC_AON_DBNSMIS_MIS_M 0x0000000FU |
| #define SOC_AON_DBNSMIS_MIS_S 0U |
| #define SOC_AON_GPIOMIS0NS_31TO0_W 32U |
| #define SOC_AON_GPIOMIS0NS_31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_GPIOMIS0NS_31TO0_S 0U |
| #define SOC_AON_GPIOMIS1NS_44TO32_W 13U |
| #define SOC_AON_GPIOMIS1NS_44TO32_M 0x00001FFFU |
| #define SOC_AON_GPIOMIS1NS_44TO32_S 0U |
| #define SOC_AON_GPIOFNC0NS_MASK31TO0_W 32U |
| #define SOC_AON_GPIOFNC0NS_MASK31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_GPIOFNC0NS_MASK31TO0_S 0U |
| #define SOC_AON_GPIOFNC1NS_MASK44TO32_W 13U |
| #define SOC_AON_GPIOFNC1NS_MASK44TO32_M 0x00001FFFU |
| #define SOC_AON_GPIOFNC1NS_MASK44TO32_S 0U |
| #define SOC_AON_SPARE2_BF_W 4U |
| #define SOC_AON_SPARE2_BF_M 0x0000000FU |
| #define SOC_AON_SPARE2_BF_S 0U |
| #define SOC_AON_FUSE_BOOTLVL_W 4U |
| #define SOC_AON_FUSE_BOOTLVL_M 0x0000000FU |
| #define SOC_AON_FUSE_BOOTLVL_S 0U |
| #define SOC_AON_FUSE_DIS5GHZ 0x00000010U |
| #define SOC_AON_FUSE_DIS5GHZ_M 0x00000010U |
| #define SOC_AON_FUSE_DIS5GHZ_S 4U |
| #define SOC_AON_FUSE_DIS6GHZ 0x00000020U |
| #define SOC_AON_FUSE_DIS6GHZ_M 0x00000020U |
| #define SOC_AON_FUSE_DIS6GHZ_S 5U |
| #define SOC_AON_FUSE_DISBLE 0x00000040U |
| #define SOC_AON_FUSE_DISBLE_M 0x00000040U |
| #define SOC_AON_FUSE_DISBLE_S 6U |
| #define SOC_AON_FUSE_DISBLEM0P 0x00000080U |
| #define SOC_AON_FUSE_DISBLEM0P_M 0x00000080U |
| #define SOC_AON_FUSE_DISBLEM0P_S 7U |
| #define SOC_AON_FUSE_DISM33 0x00000100U |
| #define SOC_AON_FUSE_DISM33_M 0x00000100U |
| #define SOC_AON_FUSE_DISM33_S 8U |
| #define SOC_AON_FUSE_TEMP_W 2U |
| #define SOC_AON_FUSE_TEMP_M 0x00000600U |
| #define SOC_AON_FUSE_TEMP_S 9U |
| #define SOC_AON_FUSE_DISCANFD 0x00000800U |
| #define SOC_AON_FUSE_DISCANFD_M 0x00000800U |
| #define SOC_AON_FUSE_DISCANFD_S 11U |
| #define SOC_AON_FUSE_ENBOOTWDT 0x00001000U |
| #define SOC_AON_FUSE_ENBOOTWDT_M 0x00001000U |
| #define SOC_AON_FUSE_ENBOOTWDT_S 12U |
| #define SOC_AON_FUSE_RANDDLYEN 0x00002000U |
| #define SOC_AON_FUSE_RANDDLYEN_M 0x00002000U |
| #define SOC_AON_FUSE_RANDDLYEN_S 13U |
| #define SOC_AON_FUSE_DISVERB 0x00004000U |
| #define SOC_AON_FUSE_DISVERB_M 0x00004000U |
| #define SOC_AON_FUSE_DISVERB_S 14U |
| #define SOC_AON_FUSE_RESBOOTEXE 0x00008000U |
| #define SOC_AON_FUSE_RESBOOTEXE_M 0x00008000U |
| #define SOC_AON_FUSE_RESBOOTEXE_S 15U |
| #define SOC_AON_FUSE_LDAUTHEN_W 2U |
| #define SOC_AON_FUSE_LDAUTHEN_M 0x00030000U |
| #define SOC_AON_FUSE_LDAUTHEN_S 16U |
| #define SOC_AON_FUSE_PRIVDBGREQ_W 3U |
| #define SOC_AON_FUSE_PRIVDBGREQ_M 0x001C0000U |
| #define SOC_AON_FUSE_PRIVDBGREQ_S 18U |
| #define SOC_AON_FUSE_MEMSTCK_W 3U |
| #define SOC_AON_FUSE_MEMSTCK_M 0x00E00000U |
| #define SOC_AON_FUSE_MEMSTCK_S 21U |
| #define SOC_AON_ESM1CFG_ENTIMEOUT 0x00000001U |
| #define SOC_AON_ESM1CFG_ENTIMEOUT_M 0x00000001U |
| #define SOC_AON_ESM1CFG_ENTIMEOUT_S 0U |
| #define SOC_AON_ESM1CFG_TIMEOUTCNT_W 4U |
| #define SOC_AON_ESM1CFG_TIMEOUTCNT_M 0x00000F00U |
| #define SOC_AON_ESM1CFG_TIMEOUTCNT_S 8U |
| #define SOC_AON_ESM1EN1_EN1 0x00000001U |
| #define SOC_AON_ESM1EN1_EN1_M 0x00000001U |
| #define SOC_AON_ESM1EN1_EN1_S 0U |
| #define SOC_AON_ESM1EN2_EN2 0x00000001U |
| #define SOC_AON_ESM1EN2_EN2_M 0x00000001U |
| #define SOC_AON_ESM1EN2_EN2_S 0U |
| #define SOC_AON_ESM1EN3_EN3 0x00000001U |
| #define SOC_AON_ESM1EN3_EN3_M 0x00000001U |
| #define SOC_AON_ESM1EN3_EN3_S 0U |
| #define SOC_AON_ESM1EN4_EN4 0x00000001U |
| #define SOC_AON_ESM1EN4_EN4_M 0x00000001U |
| #define SOC_AON_ESM1EN4_EN4_S 0U |
| #define SOC_AON_ESM1EN5_EN5 0x00000001U |
| #define SOC_AON_ESM1EN5_EN5_M 0x00000001U |
| #define SOC_AON_ESM1EN5_EN5_S 0U |
| #define SOC_AON_ESM2EN1_EN1 0x00000001U |
| #define SOC_AON_ESM2EN1_EN1_M 0x00000001U |
| #define SOC_AON_ESM2EN1_EN1_S 0U |
| #define SOC_AON_ESM2EN2_EN2 0x00000001U |
| #define SOC_AON_ESM2EN2_EN2_M 0x00000001U |
| #define SOC_AON_ESM2EN2_EN2_S 0U |
| #define SOC_AON_ESM2EN3_EN3 0x00000001U |
| #define SOC_AON_ESM2EN3_EN3_M 0x00000001U |
| #define SOC_AON_ESM2EN3_EN3_S 0U |
| #define SOC_AON_ESM2EN4_EN4 0x00000001U |
| #define SOC_AON_ESM2EN4_EN4_M 0x00000001U |
| #define SOC_AON_ESM2EN4_EN4_S 0U |
| #define SOC_AON_ESM2EN5_EN5 0x00000001U |
| #define SOC_AON_ESM2EN5_EN5_M 0x00000001U |
| #define SOC_AON_ESM2EN5_EN5_S 0U |
| #define SOC_AON_ESM2CFG_ENTIMEOUT 0x00000001U |
| #define SOC_AON_ESM2CFG_ENTIMEOUT_M 0x00000001U |
| #define SOC_AON_ESM2CFG_ENTIMEOUT_S 0U |
| #define SOC_AON_ESM2CFG_TIMEOUTCNT_W 4U |
| #define SOC_AON_ESM2CFG_TIMEOUTCNT_M 0x00000F00U |
| #define SOC_AON_ESM2CFG_TIMEOUTCNT_S 8U |
| #define SOC_AON_DBGSSDSSM_MBOXRSTEN 0x00000001U |
| #define SOC_AON_DBGSSDSSM_MBOXRSTEN_M 0x00000001U |
| #define SOC_AON_DBGSSDSSM_MBOXRSTEN_S 0U |
| #define SOC_AON_DBGSSDSSM_SWJINSTID_W 4U |
| #define SOC_AON_DBGSSDSSM_SWJINSTID_M 0x00001E00U |
| #define SOC_AON_DBGSSDSSM_SWJINSTID_S 9U |
| #define SOC_AON_DBGSSDSSM_WSOCCPU 0x00010000U |
| #define SOC_AON_DBGSSDSSM_WSOCCPU_M 0x00010000U |
| #define SOC_AON_DBGSSDSSM_WSOCCPU_S 16U |
| #define SOC_AON_DBGSSDSSM_WLPHYCPU 0x00020000U |
| #define SOC_AON_DBGSSDSSM_WLPHYCPU_M 0x00020000U |
| #define SOC_AON_DBGSSDSSM_WLPHYCPU_S 17U |
| #define SOC_AON_DBGSSDSSM_BLE 0x00040000U |
| #define SOC_AON_DBGSSDSSM_BLE_M 0x00040000U |
| #define SOC_AON_DBGSSDSSM_BLE_S 18U |
| #define SOC_AON_DBGSSDSSM_APPSCPU 0x00080000U |
| #define SOC_AON_DBGSSDSSM_APPSCPU_M 0x00080000U |
| #define SOC_AON_DBGSSDSSM_APPSCPU_S 19U |
| #define SOC_AON_ESM3CFG_ENTIMEOUT 0x00000001U |
| #define SOC_AON_ESM3CFG_ENTIMEOUT_M 0x00000001U |
| #define SOC_AON_ESM3CFG_ENTIMEOUT_S 0U |
| #define SOC_AON_ESM3CFG_TIMEOUTCNT_W 4U |
| #define SOC_AON_ESM3CFG_TIMEOUTCNT_M 0x00000F00U |
| #define SOC_AON_ESM3CFG_TIMEOUTCNT_S 8U |
| #define SOC_AON_ESM3CFG_BACK2IDLE 0x00010000U |
| #define SOC_AON_ESM3CFG_BACK2IDLE_M 0x00010000U |
| #define SOC_AON_ESM3CFG_BACK2IDLE_S 16U |
| #define SOC_AON_ESM3EN1_EN1 0x00000001U |
| #define SOC_AON_ESM3EN1_EN1_M 0x00000001U |
| #define SOC_AON_ESM3EN1_EN1_S 0U |
| #define SOC_AON_ESM3EN2_EN2 0x00000001U |
| #define SOC_AON_ESM3EN2_EN2_M 0x00000001U |
| #define SOC_AON_ESM3EN2_EN2_S 0U |
| #define SOC_AON_ESM3EN3_EN3 0x00000001U |
| #define SOC_AON_ESM3EN3_EN3_M 0x00000001U |
| #define SOC_AON_ESM3EN3_EN3_S 0U |
| #define SOC_AON_ESM3EN4_EN4 0x00000001U |
| #define SOC_AON_ESM3EN4_EN4_M 0x00000001U |
| #define SOC_AON_ESM3EN4_EN4_S 0U |
| #define SOC_AON_ESM3EN5_EN5 0x00000001U |
| #define SOC_AON_ESM3EN5_EN5_M 0x00000001U |
| #define SOC_AON_ESM3EN5_EN5_S 0U |
| #define SOC_AON_FUSELINE0_DEVLCHW_W 4U |
| #define SOC_AON_FUSELINE0_DEVLCHW_M 0x0000000FU |
| #define SOC_AON_FUSELINE0_DEVLCHW_S 0U |
| #define SOC_AON_FUSELINE0_DEVLCSW_W 4U |
| #define SOC_AON_FUSELINE0_DEVLCSW_M 0x000000F0U |
| #define SOC_AON_FUSELINE0_DEVLCSW_S 4U |
| #define SOC_AON_FUSELINE0_DEVLCSPAT_W 24U |
| #define SOC_AON_FUSELINE0_DEVLCSPAT_M 0xFFFFFF00U |
| #define SOC_AON_FUSELINE0_DEVLCSPAT_S 8U |
| #define SOC_AON_FUSELINE1_UNQ31TO0_W 32U |
| #define SOC_AON_FUSELINE1_UNQ31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE1_UNQ31TO0_S 0U |
| #define SOC_AON_FUSELINE2_UNQ63TO32_W 32U |
| #define SOC_AON_FUSELINE2_UNQ63TO32_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE2_UNQ63TO32_S 0U |
| #define SOC_AON_FUSELINE3_UNQS31TO0_W 32U |
| #define SOC_AON_FUSELINE3_UNQS31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE3_UNQS31TO0_S 0U |
| #define SOC_AON_FUSELINE4_UNQS63TO32_W 32U |
| #define SOC_AON_FUSELINE4_UNQS63TO32_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE4_UNQS63TO32_S 0U |
| #define SOC_AON_FUSELINE5_UNQS95TO64_W 32U |
| #define SOC_AON_FUSELINE5_UNQS95TO64_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE5_UNQS95TO64_S 0U |
| #define SOC_AON_FUSELINE6_UNQS127TO96_W 32U |
| #define SOC_AON_FUSELINE6_UNQS127TO96_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE6_UNQS127TO96_S 0U |
| #define SOC_AON_FUSELINE7_HWCRCEN_W 3U |
| #define SOC_AON_FUSELINE7_HWCRCEN_M 0x00000007U |
| #define SOC_AON_FUSELINE7_HWCRCEN_S 0U |
| #define SOC_AON_FUSELINE7_SWCRCEN_W 3U |
| #define SOC_AON_FUSELINE7_SWCRCEN_M 0x00000038U |
| #define SOC_AON_FUSELINE7_SWCRCEN_S 3U |
| #define SOC_AON_FUSELINE7_BOOTLVL_W 4U |
| #define SOC_AON_FUSELINE7_BOOTLVL_M 0x000003C0U |
| #define SOC_AON_FUSELINE7_BOOTLVL_S 6U |
| #define SOC_AON_FUSELINE7_DIS5GHZ 0x00001000U |
| #define SOC_AON_FUSELINE7_DIS5GHZ_M 0x00001000U |
| #define SOC_AON_FUSELINE7_DIS5GHZ_S 12U |
| #define SOC_AON_FUSELINE7_DIS6GHZ 0x00002000U |
| #define SOC_AON_FUSELINE7_DIS6GHZ_M 0x00002000U |
| #define SOC_AON_FUSELINE7_DIS6GHZ_S 13U |
| #define SOC_AON_FUSELINE7_DISBLE 0x00004000U |
| #define SOC_AON_FUSELINE7_DISBLE_M 0x00004000U |
| #define SOC_AON_FUSELINE7_DISBLE_S 14U |
| #define SOC_AON_FUSELINE7_DISBLEM0P 0x00008000U |
| #define SOC_AON_FUSELINE7_DISBLEM0P_M 0x00008000U |
| #define SOC_AON_FUSELINE7_DISBLEM0P_S 15U |
| #define SOC_AON_FUSELINE7_DISM33 0x00010000U |
| #define SOC_AON_FUSELINE7_DISM33_M 0x00010000U |
| #define SOC_AON_FUSELINE7_DISM33_S 16U |
| #define SOC_AON_FUSELINE7_TEMP_W 2U |
| #define SOC_AON_FUSELINE7_TEMP_M 0x00060000U |
| #define SOC_AON_FUSELINE7_TEMP_S 17U |
| #define SOC_AON_FUSELINE7_DISCANFD 0x00080000U |
| #define SOC_AON_FUSELINE7_DISCANFD_M 0x00080000U |
| #define SOC_AON_FUSELINE7_DISCANFD_S 19U |
| #define SOC_AON_FUSELINE7_MEMSTCK_W 3U |
| #define SOC_AON_FUSELINE7_MEMSTCK_M 0x00700000U |
| #define SOC_AON_FUSELINE7_MEMSTCK_S 20U |
| #define SOC_AON_FUSELINE7_ENBOOTWDT 0x00800000U |
| #define SOC_AON_FUSELINE7_ENBOOTWDT_M 0x00800000U |
| #define SOC_AON_FUSELINE7_ENBOOTWDT_S 23U |
| #define SOC_AON_FUSELINE7_RANDDLYEN 0x01000000U |
| #define SOC_AON_FUSELINE7_RANDDLYEN_M 0x01000000U |
| #define SOC_AON_FUSELINE7_RANDDLYEN_S 24U |
| #define SOC_AON_FUSELINE7_DISVERB 0x02000000U |
| #define SOC_AON_FUSELINE7_DISVERB_M 0x02000000U |
| #define SOC_AON_FUSELINE7_DISVERB_S 25U |
| #define SOC_AON_FUSELINE7_RESBOOTEXE 0x04000000U |
| #define SOC_AON_FUSELINE7_RESBOOTEXE_M 0x04000000U |
| #define SOC_AON_FUSELINE7_RESBOOTEXE_S 26U |
| #define SOC_AON_FUSELINE7_LDAUTHEN_W 2U |
| #define SOC_AON_FUSELINE7_LDAUTHEN_M 0x18000000U |
| #define SOC_AON_FUSELINE7_LDAUTHEN_S 27U |
| #define SOC_AON_FUSELINE7_PRIVDBGREQ_W 3U |
| #define SOC_AON_FUSELINE7_PRIVDBGREQ_M 0xE0000000U |
| #define SOC_AON_FUSELINE7_PRIVDBGREQ_S 29U |
| #define SOC_AON_FUSELINE8_HWCRCVAL_W 32U |
| #define SOC_AON_FUSELINE8_HWCRCVAL_M 0xFFFFFFFFU |
| #define SOC_AON_FUSELINE8_HWCRCVAL_S 0U |
| #define SOC_AON_FUSECTL_OCPDIS 0x00000001U |
| #define SOC_AON_FUSECTL_OCPDIS_M 0x00000001U |
| #define SOC_AON_FUSECTL_OCPDIS_S 0U |
| #define SOC_AON_FUSECTL_OCPEN 0x00000002U |
| #define SOC_AON_FUSECTL_OCPEN_M 0x00000002U |
| #define SOC_AON_FUSECTL_OCPEN_S 1U |
| #define SOC_AON_COREMEMCTL_WLPHYFETCH 0x00000001U |
| #define SOC_AON_COREMEMCTL_WLPHYFETCH_M 0x00000001U |
| #define SOC_AON_COREMEMCTL_WLPHYFETCH_S 0U |
| #define SOC_AON_COREMEMCTL_WSOCMCUFET 0x00000002U |
| #define SOC_AON_COREMEMCTL_WSOCMCUFET_M 0x00000002U |
| #define SOC_AON_COREMEMCTL_WSOCMCUFET_S 1U |
| #define SOC_AON_COREMEMCTL_BLEFETCH 0x00000004U |
| #define SOC_AON_COREMEMCTL_BLEFETCH_M 0x00000004U |
| #define SOC_AON_COREMEMCTL_BLEFETCH_S 2U |
| #define SOC_AON_COREGPCTL_ALLOW 0x00000001U |
| #define SOC_AON_COREGPCTL_ALLOW_M 0x00000001U |
| #define SOC_AON_COREGPCTL_ALLOW_S 0U |
| #define SOC_AON_MEMSSGPCTL_ALLOW 0x00000001U |
| #define SOC_AON_MEMSSGPCTL_ALLOW_M 0x00000001U |
| #define SOC_AON_MEMSSGPCTL_ALLOW_S 0U |
| #define SOC_AON_BLEFUSECTL_CPEOFF 0x00000001U |
| #define SOC_AON_BLEFUSECTL_CPEOFF_M 0x00000001U |
| #define SOC_AON_BLEFUSECTL_CPEOFF_S 0U |
| #define SOC_AON_BLEFUSECTL_MDMOFF 0x00000002U |
| #define SOC_AON_BLEFUSECTL_MDMOFF_M 0x00000002U |
| #define SOC_AON_BLEFUSECTL_MDMOFF_S 1U |
| #define SOC_AON_SPARE4_BIT 0x00000001U |
| #define SOC_AON_SPARE4_BIT_M 0x00000001U |
| #define SOC_AON_SPARE4_BIT_S 0U |
| #define SOC_AON_ESM4CFG_ENTIMEOUT 0x00000001U |
| #define SOC_AON_ESM4CFG_ENTIMEOUT_M 0x00000001U |
| #define SOC_AON_ESM4CFG_ENTIMEOUT_S 0U |
| #define SOC_AON_ESM4CFG_TIMEOUTCNT_W 4U |
| #define SOC_AON_ESM4CFG_TIMEOUTCNT_M 0x00000F00U |
| #define SOC_AON_ESM4CFG_TIMEOUTCNT_S 8U |
| #define SOC_AON_ESM4EN1_EN1 0x00000001U |
| #define SOC_AON_ESM4EN1_EN1_M 0x00000001U |
| #define SOC_AON_ESM4EN1_EN1_S 0U |
| #define SOC_AON_ESM4EN2_EN2 0x00000001U |
| #define SOC_AON_ESM4EN2_EN2_M 0x00000001U |
| #define SOC_AON_ESM4EN2_EN2_S 0U |
| #define SOC_AON_ESM4EN3_EN4 0x00000001U |
| #define SOC_AON_ESM4EN3_EN4_M 0x00000001U |
| #define SOC_AON_ESM4EN3_EN4_S 0U |
| #define SOC_AON_ESM4EN4_EN4 0x00000001U |
| #define SOC_AON_ESM4EN4_EN4_M 0x00000001U |
| #define SOC_AON_ESM4EN4_EN4_S 0U |
| #define SOC_AON_ESM4EN5_EN5 0x00000001U |
| #define SOC_AON_ESM4EN5_EN5_M 0x00000001U |
| #define SOC_AON_ESM4EN5_EN5_S 0U |
| #define SOC_AON_MEMPROT_MEMLOCK 0x00010000U |
| #define SOC_AON_MEMPROT_MEMLOCK_M 0x00010000U |
| #define SOC_AON_MEMPROT_MEMLOCK_S 16U |
| #define SOC_AON_VTORCFG_INIT_W 25U |
| #define SOC_AON_VTORCFG_INIT_M 0xFFFFFF80U |
| #define SOC_AON_VTORCFG_INIT_S 7U |
| #define SOC_AON_ROMJUMPCTL_DIS 0x00000001U |
| #define SOC_AON_ROMJUMPCTL_DIS_M 0x00000001U |
| #define SOC_AON_ROMJUMPCTL_DIS_S 0U |
| #define SOC_AON_CRAMPROT1_WRTH_W 9U |
| #define SOC_AON_CRAMPROT1_WRTH_M 0x0000FF80U |
| #define SOC_AON_CRAMPROT1_WRTH_S 7U |
| #define SOC_AON_CRAMPROT0_WRDIS 0x00000001U |
| #define SOC_AON_CRAMPROT0_WRDIS_M 0x00000001U |
| #define SOC_AON_CRAMPROT0_WRDIS_S 0U |
| #define SOC_AON_DRAMPROT1_FETCHTH_W 8U |
| #define SOC_AON_DRAMPROT1_FETCHTH_M 0x00007F80U |
| #define SOC_AON_DRAMPROT1_FETCHTH_S 7U |
| #define SOC_AON_DRAMPROT0_FETCHDIS 0x00000001U |
| #define SOC_AON_DRAMPROT0_FETCHDIS_M 0x00000001U |
| #define SOC_AON_DRAMPROT0_FETCHDIS_S 0U |
| #define SOC_AON_PRAMPROT0_FETCHDIS 0x00000001U |
| #define SOC_AON_PRAMPROT0_FETCHDIS_M 0x00000001U |
| #define SOC_AON_PRAMPROT0_FETCHDIS_S 0U |
| #define SOC_AON_STRONGPAT_PAT_W 24U |
| #define SOC_AON_STRONGPAT_PAT_M 0x00FFFFFFU |
| #define SOC_AON_STRONGPAT_PAT_S 0U |
| #define SOC_AON_UDS0_31TO0_W 32U |
| #define SOC_AON_UDS0_31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_UDS0_31TO0_S 0U |
| #define SOC_AON_UDS1_63TO32_W 32U |
| #define SOC_AON_UDS1_63TO32_M 0xFFFFFFFFU |
| #define SOC_AON_UDS1_63TO32_S 0U |
| #define SOC_AON_UDS2_95TO64_W 32U |
| #define SOC_AON_UDS2_95TO64_M 0xFFFFFFFFU |
| #define SOC_AON_UDS2_95TO64_S 0U |
| #define SOC_AON_UDS3_127TO96_W 32U |
| #define SOC_AON_UDS3_127TO96_M 0xFFFFFFFFU |
| #define SOC_AON_UDS3_127TO96_S 0U |
| #define SOC_AON_DBGBUS_IOCLKSEL_W 2U |
| #define SOC_AON_DBGBUS_IOCLKSEL_M 0x00000003U |
| #define SOC_AON_DBGBUS_IOCLKSEL_S 0U |
| #define SOC_AON_DBGBUS_OCLASEL 0x00000004U |
| #define SOC_AON_DBGBUS_OCLASEL_M 0x00000004U |
| #define SOC_AON_DBGBUS_OCLASEL_S 2U |
| #define SOC_AON_DBGBUS_ELPUPSEL_W 2U |
| #define SOC_AON_DBGBUS_ELPUPSEL_M 0x00000018U |
| #define SOC_AON_DBGBUS_ELPUPSEL_S 3U |
| #define SOC_AON_DBGBUS_ELPLOSEL_W 2U |
| #define SOC_AON_DBGBUS_ELPLOSEL_M 0x00000060U |
| #define SOC_AON_DBGBUS_ELPLOSEL_S 5U |
| #define SOC_AON_DBGBUS_ELPLOPSEL_W 2U |
| #define SOC_AON_DBGBUS_ELPLOPSEL_M 0x00000180U |
| #define SOC_AON_DBGBUS_ELPLOPSEL_S 7U |
| #define SOC_AON_DBGBUS_ELPUPPSEL_W 2U |
| #define SOC_AON_DBGBUS_ELPUPPSEL_M 0x00000600U |
| #define SOC_AON_DBGBUS_ELPUPPSEL_S 9U |
| #define SOC_AON_DBGBUS_AODSEL 0x00000800U |
| #define SOC_AON_DBGBUS_AODSEL_M 0x00000800U |
| #define SOC_AON_DBGBUS_AODSEL_S 11U |
| #define SOC_AON_DBGBUS_AODPSEL_W 3U |
| #define SOC_AON_DBGBUS_AODPSEL_M 0x00007000U |
| #define SOC_AON_DBGBUS_AODPSEL_S 12U |
| #define SOC_AON_DBGBUS_MUXPSEL_W 2U |
| #define SOC_AON_DBGBUS_MUXPSEL_M 0x00018000U |
| #define SOC_AON_DBGBUS_MUXPSEL_S 15U |
| #define SOC_AON_DBGBUS_SECSEL_W 2U |
| #define SOC_AON_DBGBUS_SECSEL_M 0x00060000U |
| #define SOC_AON_DBGBUS_SECSEL_S 17U |
| #define SOC_AON_DEBUGSS_JTAGUSER_W 32U |
| #define SOC_AON_DEBUGSS_JTAGUSER_M 0xFFFFFFFFU |
| #define SOC_AON_DEBUGSS_JTAGUSER_S 0U |
| #define SOC_AON_CPEPROT1_RFCOVR 0x00000001U |
| #define SOC_AON_CPEPROT1_RFCOVR_M 0x00000001U |
| #define SOC_AON_CPEPROT1_RFCOVR_S 0U |
| #define SOC_AON_CPEPROT1_RFCMODE_W 3U |
| #define SOC_AON_CPEPROT1_RFCMODE_M 0x0000000EU |
| #define SOC_AON_CPEPROT1_RFCMODE_S 1U |
| #define SOC_AON_CPEPROT1_FETCHTH_W 8U |
| #define SOC_AON_CPEPROT1_FETCHTH_M 0x00007F80U |
| #define SOC_AON_CPEPROT1_FETCHTH_S 7U |
| #define SOC_AON_CPEPROT1_GENERAL_W 4U |
| #define SOC_AON_CPEPROT1_GENERAL_M 0x00078000U |
| #define SOC_AON_CPEPROT1_GENERAL_S 15U |
| #define SOC_AON_CPEPROT1_HIACCESS_W 4U |
| #define SOC_AON_CPEPROT1_HIACCESS_M 0x00F00000U |
| #define SOC_AON_CPEPROT1_HIACCESS_S 20U |
| #define SOC_AON_CPEPROT0_FETCHDIS 0x00000001U |
| #define SOC_AON_CPEPROT0_FETCHDIS_M 0x00000001U |
| #define SOC_AON_CPEPROT0_FETCHDIS_S 0U |
| #define SOC_AON_FUSESHIFT_CRCCALC_W 32U |
| #define SOC_AON_FUSESHIFT_CRCCALC_M 0xFFFFFFFFU |
| #define SOC_AON_FUSESHIFT_CRCCALC_S 0U |
| #define SOC_AON_SECROM_HIDEASSETS 0x00000001U |
| #define SOC_AON_SECROM_HIDEASSETS_M 0x00000001U |
| #define SOC_AON_SECROM_HIDEASSETS_S 0U |
| #define SOC_AON_SECROM_UNHIDE 0x00000002U |
| #define SOC_AON_SECROM_UNHIDE_M 0x00000002U |
| #define SOC_AON_SECROM_UNHIDE_S 1U |
| #define SOC_AON_SECUDS_HIDEASSETS 0x00000001U |
| #define SOC_AON_SECUDS_HIDEASSETS_M 0x00000001U |
| #define SOC_AON_SECUDS_HIDEASSETS_S 0U |
| #define SOC_AON_PHYPROT1_FETCHTH_W 8U |
| #define SOC_AON_PHYPROT1_FETCHTH_M 0x00007F80U |
| #define SOC_AON_PHYPROT1_FETCHTH_S 7U |
| #define SOC_AON_PHYPROT0_FETCHDIS 0x00000001U |
| #define SOC_AON_PHYPROT0_FETCHDIS_M 0x00000001U |
| #define SOC_AON_PHYPROT0_FETCHDIS_S 0U |
| #define SOC_AON_ESMDIS_DIS 0x00000001U |
| #define SOC_AON_ESMDIS_DIS_M 0x00000001U |
| #define SOC_AON_ESMDIS_DIS_S 0U |
| #define SOC_AON_SPARE5_BF0 0x00000001U |
| #define SOC_AON_SPARE5_BF0_M 0x00000001U |
| #define SOC_AON_SPARE5_BF0_S 0U |
| #define SOC_AON_SPARE5_BF1 0x00000002U |
| #define SOC_AON_SPARE5_BF1_M 0x00000002U |
| #define SOC_AON_SPARE5_BF1_S 1U |
| #define SOC_AON_SPARE5_BF2 0x00000004U |
| #define SOC_AON_SPARE5_BF2_M 0x00000004U |
| #define SOC_AON_SPARE5_BF2_S 2U |
| #define SOC_AON_TOPDBG_P2SUB_W 5U |
| #define SOC_AON_TOPDBG_P2SUB_M 0x0000001FU |
| #define SOC_AON_TOPDBG_P2SUB_S 0U |
| #define SOC_AON_TOPDBG_P1SUB_W 5U |
| #define SOC_AON_TOPDBG_P1SUB_M 0x00001F00U |
| #define SOC_AON_TOPDBG_P1SUB_S 8U |
| #define SOC_AON_TOPDBG_P2SEL_W 5U |
| #define SOC_AON_TOPDBG_P2SEL_M 0x001F0000U |
| #define SOC_AON_TOPDBG_P2SEL_S 16U |
| #define SOC_AON_TOPDBG_P1SEL_W 5U |
| #define SOC_AON_TOPDBG_P1SEL_M 0x1F000000U |
| #define SOC_AON_TOPDBG_P1SEL_S 24U |
| #define SOC_AON_TOPDBG_TPSEL 0x80000000U |
| #define SOC_AON_TOPDBG_TPSEL_M 0x80000000U |
| #define SOC_AON_TOPDBG_TPSEL_S 31U |
| #define SOC_AON_DB0M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB0M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB0M3CLR_CLR_S 0U |
| #define SOC_AON_DB0M3SET_IRQ 0x00000001U |
| #define SOC_AON_DB0M3SET_IRQ_M 0x00000001U |
| #define SOC_AON_DB0M3SET_IRQ_S 0U |
| #define SOC_AON_DB0M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB0M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB0M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB1M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB1M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB1M3CLR_CLR_S 0U |
| #define SOC_AON_DB1M3SET_SET 0x00000001U |
| #define SOC_AON_DB1M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB1M3SET_SET_S 0U |
| #define SOC_AON_DB1M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB1M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB1M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB2M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB2M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB2M3CLR_CLR_S 0U |
| #define SOC_AON_DB2M3SET_SET 0x00000001U |
| #define SOC_AON_DB2M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB2M3SET_SET_S 0U |
| #define SOC_AON_DB2M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB2M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB2M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB3M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB3M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB3M3CLR_CLR_S 0U |
| #define SOC_AON_DB3M3SET_SET 0x00000001U |
| #define SOC_AON_DB3M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB3M3SET_SET_S 0U |
| #define SOC_AON_DB3M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB3M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB3M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB4M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB4M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB4M3CLR_CLR_S 0U |
| #define SOC_AON_DB4M3SET_SET 0x00000001U |
| #define SOC_AON_DB4M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB4M3SET_SET_S 0U |
| #define SOC_AON_DB4M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB4M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB4M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB5M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB5M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB5M3CLR_CLR_S 0U |
| #define SOC_AON_DB5M3SET_SET 0x00000001U |
| #define SOC_AON_DB5M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB5M3SET_SET_S 0U |
| #define SOC_AON_DB5M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB5M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB5M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB6M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB6M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB6M3CLR_CLR_S 0U |
| #define SOC_AON_DB6M3SET_SET 0x00000001U |
| #define SOC_AON_DB6M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB6M3SET_SET_S 0U |
| #define SOC_AON_DB6M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB6M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB6M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_DB7M3CLR_CLR 0x00000001U |
| #define SOC_AON_DB7M3CLR_CLR_M 0x00000001U |
| #define SOC_AON_DB7M3CLR_CLR_S 0U |
| #define SOC_AON_DB7M3SET_SET 0x00000001U |
| #define SOC_AON_DB7M3SET_SET_M 0x00000001U |
| #define SOC_AON_DB7M3SET_SET_S 0U |
| #define SOC_AON_DB7M3LOCK_LOCKBIT_W 2U |
| #define SOC_AON_DB7M3LOCK_LOCKBIT_M 0x00000003U |
| #define SOC_AON_DB7M3LOCK_LOCKBIT_S 0U |
| #define SOC_AON_M3GPIOEVT0_STA31TO0_W 32U |
| #define SOC_AON_M3GPIOEVT0_STA31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_M3GPIOEVT0_STA31TO0_S 0U |
| #define SOC_AON_M3GPIOEVT1_STA44TO32_W 13U |
| #define SOC_AON_M3GPIOEVT1_STA44TO32_M 0x00001FFFU |
| #define SOC_AON_M3GPIOEVT1_STA44TO32_S 0U |
| #define SOC_AON_FUSELOCK_OCPDIS 0x00000001U |
| #define SOC_AON_FUSELOCK_OCPDIS_M 0x00000001U |
| #define SOC_AON_FUSELOCK_OCPDIS_S 0U |
| #define SOC_AON_ROMBOOT_DONE 0x00000001U |
| #define SOC_AON_ROMBOOT_DONE_M 0x00000001U |
| #define SOC_AON_ROMBOOT_DONE_S 0U |
| #define SOC_AON_SOCBOOT_DONE 0x00000001U |
| #define SOC_AON_SOCBOOT_DONE_M 0x00000001U |
| #define SOC_AON_SOCBOOT_DONE_S 0U |
| #define SOC_AON_ELEVATED_DONE 0x00000001U |
| #define SOC_AON_ELEVATED_DONE_M 0x00000001U |
| #define SOC_AON_ELEVATED_DONE_S 0U |
| #define SOC_AON_M3TCM_ACCESSDIS 0x00000001U |
| #define SOC_AON_M3TCM_ACCESSDIS_M 0x00000001U |
| #define SOC_AON_M3TCM_ACCESSDIS_S 0U |
| #define SOC_AON_HSMCFG_FIPS 0x00000001U |
| #define SOC_AON_HSMCFG_FIPS_M 0x00000001U |
| #define SOC_AON_HSMCFG_FIPS_S 0U |
| #define SOC_AON_HSMCFG_SELFDIS 0x00000002U |
| #define SOC_AON_HSMCFG_SELFDIS_M 0x00000002U |
| #define SOC_AON_HSMCFG_SELFDIS_S 1U |
| #define SOC_AON_HSMCFG_WMSELFDIS 0x00000004U |
| #define SOC_AON_HSMCFG_WMSELFDIS_M 0x00000004U |
| #define SOC_AON_HSMCFG_WMSELFDIS_S 2U |
| #define SOC_AON_HSMCFG_DMAGATEWAY 0x00000008U |
| #define SOC_AON_HSMCFG_DMAGATEWAY_M 0x00000008U |
| #define SOC_AON_HSMCFG_DMAGATEWAY_S 3U |
| #define SOC_AON_HSMCFG_FIREWALL 0x00000010U |
| #define SOC_AON_HSMCFG_FIREWALL_M 0x00000010U |
| #define SOC_AON_HSMCFG_FIREWALL_S 4U |
| #define SOC_AON_HSMCFG_HIDEASSETS 0x00000020U |
| #define SOC_AON_HSMCFG_HIDEASSETS_M 0x00000020U |
| #define SOC_AON_HSMCFG_HIDEASSETS_S 5U |
| #define SOC_AON_ESM5CFG_ENTIMEOUT 0x00000001U |
| #define SOC_AON_ESM5CFG_ENTIMEOUT_M 0x00000001U |
| #define SOC_AON_ESM5CFG_ENTIMEOUT_S 0U |
| #define SOC_AON_ESM5CFG_TIMEOUTCNT_W 4U |
| #define SOC_AON_ESM5CFG_TIMEOUTCNT_M 0x00000F00U |
| #define SOC_AON_ESM5CFG_TIMEOUTCNT_S 8U |
| #define SOC_AON_ESM5EN1_EN1 0x00000001U |
| #define SOC_AON_ESM5EN1_EN1_M 0x00000001U |
| #define SOC_AON_ESM5EN1_EN1_S 0U |
| #define SOC_AON_ESM5EN2_EN2 0x00000001U |
| #define SOC_AON_ESM5EN2_EN2_M 0x00000001U |
| #define SOC_AON_ESM5EN2_EN2_S 0U |
| #define SOC_AON_ESM5EN3_EN3 0x00000001U |
| #define SOC_AON_ESM5EN3_EN3_M 0x00000001U |
| #define SOC_AON_ESM5EN3_EN3_S 0U |
| #define SOC_AON_ESM5EN4_EN1 0x00000001U |
| #define SOC_AON_ESM5EN4_EN1_M 0x00000001U |
| #define SOC_AON_ESM5EN4_EN1_S 0U |
| #define SOC_AON_ESM5EN5_EN5 0x00000001U |
| #define SOC_AON_ESM5EN5_EN5_M 0x00000001U |
| #define SOC_AON_ESM5EN5_EN5_S 0U |
| #define SOC_AON_ESM1VAL1ST_MGCVAL_W 8U |
| #define SOC_AON_ESM1VAL1ST_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM1VAL1ST_MGCVAL_S 0U |
| #define SOC_AON_ESM2VAL1ST_MGCVAL_W 8U |
| #define SOC_AON_ESM2VAL1ST_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM2VAL1ST_MGCVAL_S 0U |
| #define SOC_AON_ESM3VAL1ST_MGCVAL_W 8U |
| #define SOC_AON_ESM3VAL1ST_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM3VAL1ST_MGCVAL_S 0U |
| #define SOC_AON_ESM4VAL1ST_MGCVAL_W 8U |
| #define SOC_AON_ESM4VAL1ST_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM4VAL1ST_MGCVAL_S 0U |
| #define SOC_AON_ESM5VAL1ST_MGCVAL_W 8U |
| #define SOC_AON_ESM5VAL1ST_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM5VAL1ST_MGCVAL_S 0U |
| #define SOC_AON_DBM3IMASK_IMASK_W 8U |
| #define SOC_AON_DBM3IMASK_IMASK_M 0x000000FFU |
| #define SOC_AON_DBM3IMASK_IMASK_S 0U |
| #define SOC_AON_DBM3ISET_ISET_W 8U |
| #define SOC_AON_DBM3ISET_ISET_M 0x000000FFU |
| #define SOC_AON_DBM3ISET_ISET_S 0U |
| #define SOC_AON_DBM3ICLR_ICLR_W 8U |
| #define SOC_AON_DBM3ICLR_ICLR_M 0x000000FFU |
| #define SOC_AON_DBM3ICLR_ICLR_S 0U |
| #define SOC_AON_DBM3IMSET_IMSET_W 8U |
| #define SOC_AON_DBM3IMSET_IMSET_M 0x000000FFU |
| #define SOC_AON_DBM3IMSET_IMSET_S 0U |
| #define SOC_AON_DBM3IMCLR_IMCLR_W 8U |
| #define SOC_AON_DBM3IMCLR_IMCLR_M 0x000000FFU |
| #define SOC_AON_DBM3IMCLR_IMCLR_S 0U |
| #define SOC_AON_DBM3RIS_RIS_W 8U |
| #define SOC_AON_DBM3RIS_RIS_M 0x000000FFU |
| #define SOC_AON_DBM3RIS_RIS_S 0U |
| #define SOC_AON_DBM3MIS_MIS_W 8U |
| #define SOC_AON_DBM3MIS_MIS_M 0x000000FFU |
| #define SOC_AON_DBM3MIS_MIS_S 0U |
| #define SOC_AON_HOSTCRTX_SYSRSTREQ 0x00000001U |
| #define SOC_AON_HOSTCRTX_SYSRSTREQ_M 0x00000001U |
| #define SOC_AON_HOSTCRTX_SYSRSTREQ_S 0U |
| #define SOC_AON_FWCFGSOC_BYPASS 0x00000001U |
| #define SOC_AON_FWCFGSOC_BYPASS_M 0x00000001U |
| #define SOC_AON_FWCFGSOC_BYPASS_S 0U |
| #define SOC_AON_FWCOEX_M33NS 0x00000001U |
| #define SOC_AON_FWCOEX_M33NS_M 0x00000001U |
| #define SOC_AON_FWCOEX_M33NS_S 0U |
| #define SOC_AON_FWCOEX_M33S 0x00000002U |
| #define SOC_AON_FWCOEX_M33S_M 0x00000002U |
| #define SOC_AON_FWCOEX_M33S_S 1U |
| #define SOC_AON_FWCOEX_CORENS 0x00000004U |
| #define SOC_AON_FWCOEX_CORENS_M 0x00000004U |
| #define SOC_AON_FWCOEX_CORENS_S 2U |
| #define SOC_AON_FWPRCM_M33NS 0x00000001U |
| #define SOC_AON_FWPRCM_M33NS_M 0x00000001U |
| #define SOC_AON_FWPRCM_M33NS_S 0U |
| #define SOC_AON_FWPRCM_M33S 0x00000002U |
| #define SOC_AON_FWPRCM_M33S_M 0x00000002U |
| #define SOC_AON_FWPRCM_M33S_S 1U |
| #define SOC_AON_FWPRCM_CORENS 0x00000004U |
| #define SOC_AON_FWPRCM_CORENS_M 0x00000004U |
| #define SOC_AON_FWPRCM_CORENS_S 2U |
| #define SOC_AON_FWFUSE_M33NS 0x00000001U |
| #define SOC_AON_FWFUSE_M33NS_M 0x00000001U |
| #define SOC_AON_FWFUSE_M33NS_S 0U |
| #define SOC_AON_FWFUSE_M33S 0x00000002U |
| #define SOC_AON_FWFUSE_M33S_M 0x00000002U |
| #define SOC_AON_FWFUSE_M33S_S 1U |
| #define SOC_AON_FWFUSE_CORENS 0x00000004U |
| #define SOC_AON_FWFUSE_CORENS_M 0x00000004U |
| #define SOC_AON_FWFUSE_CORENS_S 2U |
| #define SOC_AON_FWGPADC_M33NS 0x00000001U |
| #define SOC_AON_FWGPADC_M33NS_M 0x00000001U |
| #define SOC_AON_FWGPADC_M33NS_S 0U |
| #define SOC_AON_FWGPADC_M33S 0x00000002U |
| #define SOC_AON_FWGPADC_M33S_M 0x00000002U |
| #define SOC_AON_FWGPADC_M33S_S 1U |
| #define SOC_AON_FWGPADC_CORENS 0x00000004U |
| #define SOC_AON_FWGPADC_CORENS_M 0x00000004U |
| #define SOC_AON_FWGPADC_CORENS_S 2U |
| #define SOC_AON_FWDBGSS_M33NS 0x00000001U |
| #define SOC_AON_FWDBGSS_M33NS_M 0x00000001U |
| #define SOC_AON_FWDBGSS_M33NS_S 0U |
| #define SOC_AON_FWDBGSS_M33S 0x00000002U |
| #define SOC_AON_FWDBGSS_M33S_M 0x00000002U |
| #define SOC_AON_FWDBGSS_M33S_S 1U |
| #define SOC_AON_FWDBGSS_CORENS 0x00000004U |
| #define SOC_AON_FWDBGSS_CORENS_M 0x00000004U |
| #define SOC_AON_FWDBGSS_CORENS_S 2U |
| #define SOC_AON_FWAONM3_M33NS 0x00000001U |
| #define SOC_AON_FWAONM3_M33NS_M 0x00000001U |
| #define SOC_AON_FWAONM3_M33NS_S 0U |
| #define SOC_AON_FWAONM3_M33S 0x00000002U |
| #define SOC_AON_FWAONM3_M33S_M 0x00000002U |
| #define SOC_AON_FWAONM3_M33S_S 1U |
| #define SOC_AON_FWAONM3_CORENS 0x00000004U |
| #define SOC_AON_FWAONM3_CORENS_M 0x00000004U |
| #define SOC_AON_FWAONM3_CORENS_S 2U |
| #define SOC_AON_FWOCLA_M33NS 0x00000001U |
| #define SOC_AON_FWOCLA_M33NS_M 0x00000001U |
| #define SOC_AON_FWOCLA_M33NS_S 0U |
| #define SOC_AON_FWOCLA_M33S 0x00000002U |
| #define SOC_AON_FWOCLA_M33S_M 0x00000002U |
| #define SOC_AON_FWOCLA_M33S_S 1U |
| #define SOC_AON_FWOCLA_CORENS 0x00000004U |
| #define SOC_AON_FWOCLA_CORENS_M 0x00000004U |
| #define SOC_AON_FWOCLA_CORENS_S 2U |
| #define SOC_AON_FWCORE_M33NS 0x00000001U |
| #define SOC_AON_FWCORE_M33NS_M 0x00000001U |
| #define SOC_AON_FWCORE_M33NS_S 0U |
| #define SOC_AON_FWCORE_M33S 0x00000002U |
| #define SOC_AON_FWCORE_M33S_M 0x00000002U |
| #define SOC_AON_FWCORE_M33S_S 1U |
| #define SOC_AON_FWCORE_CORENS 0x00000004U |
| #define SOC_AON_FWCORE_CORENS_M 0x00000004U |
| #define SOC_AON_FWCORE_CORENS_S 2U |
| #define SOC_AON_FWAAONM3_M33NS 0x00000001U |
| #define SOC_AON_FWAAONM3_M33NS_M 0x00000001U |
| #define SOC_AON_FWAAONM3_M33NS_S 0U |
| #define SOC_AON_FWAAONM3_M33S 0x00000002U |
| #define SOC_AON_FWAAONM3_M33S_M 0x00000002U |
| #define SOC_AON_FWAAONM3_M33S_S 1U |
| #define SOC_AON_FWAAONM3_CORENS 0x00000004U |
| #define SOC_AON_FWAAONM3_CORENS_M 0x00000004U |
| #define SOC_AON_FWAAONM3_CORENS_S 2U |
| #define SOC_AON_FWXIPCFG_M33NS 0x00000001U |
| #define SOC_AON_FWXIPCFG_M33NS_M 0x00000001U |
| #define SOC_AON_FWXIPCFG_M33NS_S 0U |
| #define SOC_AON_FWXIPCFG_M33S 0x00000002U |
| #define SOC_AON_FWXIPCFG_M33S_M 0x00000002U |
| #define SOC_AON_FWXIPCFG_M33S_S 1U |
| #define SOC_AON_FWXIPCFG_CORENS 0x00000004U |
| #define SOC_AON_FWXIPCFG_CORENS_M 0x00000004U |
| #define SOC_AON_FWXIPCFG_CORENS_S 2U |
| #define SOC_AON_FWOTFLCK_M33NS 0x00000001U |
| #define SOC_AON_FWOTFLCK_M33NS_M 0x00000001U |
| #define SOC_AON_FWOTFLCK_M33NS_S 0U |
| #define SOC_AON_FWOTFLCK_M33S 0x00000002U |
| #define SOC_AON_FWOTFLCK_M33S_M 0x00000002U |
| #define SOC_AON_FWOTFLCK_M33S_S 1U |
| #define SOC_AON_FWOTFLCK_CORENS 0x00000004U |
| #define SOC_AON_FWOTFLCK_CORENS_M 0x00000004U |
| #define SOC_AON_FWOTFLCK_CORENS_S 2U |
| #define SOC_AON_FWOTFNLCK_M33NS 0x00000001U |
| #define SOC_AON_FWOTFNLCK_M33NS_M 0x00000001U |
| #define SOC_AON_FWOTFNLCK_M33NS_S 0U |
| #define SOC_AON_FWOTFNLCK_M33S 0x00000002U |
| #define SOC_AON_FWOTFNLCK_M33S_M 0x00000002U |
| #define SOC_AON_FWOTFNLCK_M33S_S 1U |
| #define SOC_AON_FWOTFNLCK_CORENS 0x00000004U |
| #define SOC_AON_FWOTFNLCK_CORENS_M 0x00000004U |
| #define SOC_AON_FWOTFNLCK_CORENS_S 2U |
| #define SOC_AON_FWCOREAON_M33NS 0x00000001U |
| #define SOC_AON_FWCOREAON_M33NS_M 0x00000001U |
| #define SOC_AON_FWCOREAON_M33NS_S 0U |
| #define SOC_AON_FWCOREAON_M33S 0x00000002U |
| #define SOC_AON_FWCOREAON_M33S_M 0x00000002U |
| #define SOC_AON_FWCOREAON_M33S_S 1U |
| #define SOC_AON_FWCOREAON_CORENS 0x00000004U |
| #define SOC_AON_FWCOREAON_CORENS_M 0x00000004U |
| #define SOC_AON_FWCOREAON_CORENS_S 2U |
| #define SOC_AON_FWSPARE1_M33NS 0x00000001U |
| #define SOC_AON_FWSPARE1_M33NS_M 0x00000001U |
| #define SOC_AON_FWSPARE1_M33NS_S 0U |
| #define SOC_AON_FWSPARE1_M33S 0x00000002U |
| #define SOC_AON_FWSPARE1_M33S_M 0x00000002U |
| #define SOC_AON_FWSPARE1_M33S_S 1U |
| #define SOC_AON_FWSPARE1_CORENS 0x00000004U |
| #define SOC_AON_FWSPARE1_CORENS_M 0x00000004U |
| #define SOC_AON_FWSPARE1_CORENS_S 2U |
| #define SOC_AON_SOCSTA_BOOTSTA_W 32U |
| #define SOC_AON_SOCSTA_BOOTSTA_M 0xFFFFFFFFU |
| #define SOC_AON_SOCSTA_BOOTSTA_S 0U |
| #define SOC_AON_LCCFG_DEVPARAMS_W 24U |
| #define SOC_AON_LCCFG_DEVPARAMS_M 0xFFFFFF00U |
| #define SOC_AON_LCCFG_DEVPARAMS_S 8U |
| #define SOC_AON_ESM1STA_STATE_W 4U |
| #define SOC_AON_ESM1STA_STATE_M 0x0000000FU |
| #define SOC_AON_ESM1STA_STATE_S 0U |
| #define SOC_AON_ESM2STA_STATE_W 4U |
| #define SOC_AON_ESM2STA_STATE_M 0x0000000FU |
| #define SOC_AON_ESM2STA_STATE_S 0U |
| #define SOC_AON_ESM1STA1ST_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM1STA1ST_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM1STA1ST_MGCVDONE_S 0U |
| #define SOC_AON_ESM1STA1ST_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM1STA1ST_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM1STA1ST_MGCVFLT_S 1U |
| #define SOC_AON_ESM2STA1ST_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM2STA1ST_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM2STA1ST_MGCVDONE_S 0U |
| #define SOC_AON_ESM2STA1ST_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM2STA1ST_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM2STA1ST_MGCVFLT_S 1U |
| #define SOC_AON_ESM3STA1ST_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM3STA1ST_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM3STA1ST_MGCVDONE_S 0U |
| #define SOC_AON_ESM3STA1ST_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM3STA1ST_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM3STA1ST_MGCVFLT_S 1U |
| #define SOC_AON_ESM4STA1ST_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM4STA1ST_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM4STA1ST_MGCVDONE_S 0U |
| #define SOC_AON_ESM4STA1ST_MGCVFAULT 0x00000002U |
| #define SOC_AON_ESM4STA1ST_MGCVFAULT_M 0x00000002U |
| #define SOC_AON_ESM4STA1ST_MGCVFAULT_S 1U |
| #define SOC_AON_ESM5STA1ST_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM5STA1ST_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM5STA1ST_MGCVDONE_S 0U |
| #define SOC_AON_ESM5STA1ST_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM5STA1ST_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM5STA1ST_MGCVFLT_S 1U |
| #define SOC_AON_SECGSERR_EN 0x00000001U |
| #define SOC_AON_SECGSERR_EN_M 0x00000001U |
| #define SOC_AON_SECGSERR_EN_S 0U |
| #define SOC_AON_DRAMCTL_ERASEASST 0x00000001U |
| #define SOC_AON_DRAMCTL_ERASEASST_M 0x00000001U |
| #define SOC_AON_DRAMCTL_ERASEASST_S 0U |
| #define SOC_AON_CONNSTPCTL_SWITCH 0x00000001U |
| #define SOC_AON_CONNSTPCTL_SWITCH_M 0x00000001U |
| #define SOC_AON_CONNSTPCTL_SWITCH_S 0U |
| #define SOC_AON_ESMSTATI_ESM3DONE 0x00000001U |
| #define SOC_AON_ESMSTATI_ESM3DONE_M 0x00000001U |
| #define SOC_AON_ESMSTATI_ESM3DONE_S 0U |
| #define SOC_AON_ESMSTATI_ESM3VIO 0x00000002U |
| #define SOC_AON_ESMSTATI_ESM3VIO_M 0x00000002U |
| #define SOC_AON_ESMSTATI_ESM3VIO_S 1U |
| #define SOC_AON_ESMSTATI_ESM4DONE 0x00000100U |
| #define SOC_AON_ESMSTATI_ESM4DONE_M 0x00000100U |
| #define SOC_AON_ESMSTATI_ESM4DONE_S 8U |
| #define SOC_AON_ESMSTATI_ESM4VIO 0x00000200U |
| #define SOC_AON_ESMSTATI_ESM4VIO_M 0x00000200U |
| #define SOC_AON_ESMSTATI_ESM4VIO_S 9U |
| #define SOC_AON_ESMSTATI_ESM5DONE 0x00010000U |
| #define SOC_AON_ESMSTATI_ESM5DONE_M 0x00010000U |
| #define SOC_AON_ESMSTATI_ESM5DONE_S 16U |
| #define SOC_AON_ESMSTATI_ESM5VIO 0x00020000U |
| #define SOC_AON_ESMSTATI_ESM5VIO_M 0x00020000U |
| #define SOC_AON_ESMSTATI_ESM5VIO_S 17U |
| #define SOC_AON_M3GPIOMIS0_31TO0_W 32U |
| #define SOC_AON_M3GPIOMIS0_31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_M3GPIOMIS0_31TO0_S 0U |
| #define SOC_AON_M3GPIOMIS1_44TO32_W 13U |
| #define SOC_AON_M3GPIOMIS1_44TO32_M 0x00001FFFU |
| #define SOC_AON_M3GPIOMIS1_44TO32_S 0U |
| #define SOC_AON_M3GPIOFNC0_MASK31TO0_W 32U |
| #define SOC_AON_M3GPIOFNC0_MASK31TO0_M 0xFFFFFFFFU |
| #define SOC_AON_M3GPIOFNC0_MASK31TO0_S 0U |
| #define SOC_AON_M3GPIOFNC1_MASK44TO32_W 13U |
| #define SOC_AON_M3GPIOFNC1_MASK44TO32_M 0x00001FFFU |
| #define SOC_AON_M3GPIOFNC1_MASK44TO32_S 0U |
| #define SOC_AON_DBGOCLA_SELLSB_W 3U |
| #define SOC_AON_DBGOCLA_SELLSB_M 0x00000007U |
| #define SOC_AON_DBGOCLA_SELLSB_S 0U |
| #define SOC_AON_DBGOCLA_SELMSB_W 3U |
| #define SOC_AON_DBGOCLA_SELMSB_M 0x00000038U |
| #define SOC_AON_DBGOCLA_SELMSB_S 3U |
| #define SOC_AON_DBGOCLA_AODTP1SEL_W 3U |
| #define SOC_AON_DBGOCLA_AODTP1SEL_M 0x000001C0U |
| #define SOC_AON_DBGOCLA_AODTP1SEL_S 6U |
| #define SOC_AON_DBGOCLA_AODTP2SEL_W 3U |
| #define SOC_AON_DBGOCLA_AODTP2SEL_M 0x00000E00U |
| #define SOC_AON_DBGOCLA_AODTP2SEL_S 9U |
| #define SOC_AON_CPUWAIT_EXIT 0x00000001U |
| #define SOC_AON_CPUWAIT_EXIT_M 0x00000001U |
| #define SOC_AON_CPUWAIT_EXIT_S 0U |
| #define SOC_AON_SPARE6_BF_W 4U |
| #define SOC_AON_SPARE6_BF_M 0x0000000FU |
| #define SOC_AON_SPARE6_BF_S 0U |
| #define SOC_AON_SECSTA_HIDEASST 0x00000001U |
| #define SOC_AON_SECSTA_HIDEASST_M 0x00000001U |
| #define SOC_AON_SECSTA_HIDEASST_S 0U |
| #define SOC_AON_SECSTA_UDSRDEN 0x00000002U |
| #define SOC_AON_SECSTA_UDSRDEN_M 0x00000002U |
| #define SOC_AON_SECSTA_UDSRDEN_S 1U |
| #define SOC_AON_SECSTA_DEVATTEST 0x00000004U |
| #define SOC_AON_SECSTA_DEVATTEST_M 0x00000004U |
| #define SOC_AON_SECSTA_DEVATTEST_S 2U |
| #define SOC_AON_SECSTA_SECBYPASS 0x00000010U |
| #define SOC_AON_SECSTA_SECBYPASS_M 0x00000010U |
| #define SOC_AON_SECSTA_SECBYPASS_S 4U |
| #define SOC_AON_SECSTA_HWCRCEN_W 3U |
| #define SOC_AON_SECSTA_HWCRCEN_M 0x000000E0U |
| #define SOC_AON_SECSTA_HWCRCEN_S 5U |
| #define SOC_AON_SECSTA_PRCMSOP_W 2U |
| #define SOC_AON_SECSTA_PRCMSOP_M 0x00000300U |
| #define SOC_AON_SECSTA_PRCMSOP_S 8U |
| #define SOC_AON_SECSTA_EFCERR_W 5U |
| #define SOC_AON_SECSTA_EFCERR_M 0x0000F800U |
| #define SOC_AON_SECSTA_EFCERR_S 11U |
| #define SOC_AON_SECSTA_EFCLDDONE 0x00010000U |
| #define SOC_AON_SECSTA_EFCLDDONE_M 0x00010000U |
| #define SOC_AON_SECSTA_EFCLDDONE_S 16U |
| #define SOC_AON_SECSTA_LCVALID 0x00020000U |
| #define SOC_AON_SECSTA_LCVALID_M 0x00020000U |
| #define SOC_AON_SECSTA_LCVALID_S 17U |
| #define SOC_AON_SECSTA_COREEN 0x00040000U |
| #define SOC_AON_SECSTA_COREEN_M 0x00040000U |
| #define SOC_AON_SECSTA_COREEN_S 18U |
| #define SOC_AON_SECSTA_LCPATMATCH 0x00080000U |
| #define SOC_AON_SECSTA_LCPATMATCH_M 0x00080000U |
| #define SOC_AON_SECSTA_LCPATMATCH_S 19U |
| #define SOC_AON_SECSTA_CRCPASSED 0x00100000U |
| #define SOC_AON_SECSTA_CRCPASSED_M 0x00100000U |
| #define SOC_AON_SECSTA_CRCPASSED_S 20U |
| #define SOC_AON_SECSTA_CRCIGNORE 0x00200000U |
| #define SOC_AON_SECSTA_CRCIGNORE_M 0x00200000U |
| #define SOC_AON_SECSTA_CRCIGNORE_S 21U |
| #define SOC_AON_SECSTA_LCSTRONG 0x00400000U |
| #define SOC_AON_SECSTA_LCSTRONG_M 0x00400000U |
| #define SOC_AON_SECSTA_LCSTRONG_S 22U |
| #define SOC_AON_SECSTA_BOOTROM 0x00800000U |
| #define SOC_AON_SECSTA_BOOTROM_M 0x00800000U |
| #define SOC_AON_SECSTA_BOOTROM_S 23U |
| #define SOC_AON_SECSTA_ROMASSETS 0x01000000U |
| #define SOC_AON_SECSTA_ROMASSETS_M 0x01000000U |
| #define SOC_AON_SECSTA_ROMASSETS_S 24U |
| #define SOC_AON_SECSTA_ELEVMODE 0x02000000U |
| #define SOC_AON_SECSTA_ELEVMODE_M 0x02000000U |
| #define SOC_AON_SECSTA_ELEVMODE_S 25U |
| #define SOC_AON_ESM3VAL2ND_MGCVAL_W 8U |
| #define SOC_AON_ESM3VAL2ND_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM3VAL2ND_MGCVAL_S 0U |
| #define SOC_AON_ESM4VAL2ND_MGCVAL_W 8U |
| #define SOC_AON_ESM4VAL2ND_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM4VAL2ND_MGCVAL_S 0U |
| #define SOC_AON_ESM5VAL2ND_MGCVAL_W 8U |
| #define SOC_AON_ESM5VAL2ND_MGCVAL_M 0x000000FFU |
| #define SOC_AON_ESM5VAL2ND_MGCVAL_S 0U |
| #define SOC_AON_ESM3STA_STATE_W 4U |
| #define SOC_AON_ESM3STA_STATE_M 0x0000000FU |
| #define SOC_AON_ESM3STA_STATE_S 0U |
| #define SOC_AON_ESM4STA_STATE_W 4U |
| #define SOC_AON_ESM4STA_STATE_M 0x0000000FU |
| #define SOC_AON_ESM4STA_STATE_S 0U |
| #define SOC_AON_ESM5STA_STATE_W 4U |
| #define SOC_AON_ESM5STA_STATE_M 0x0000000FU |
| #define SOC_AON_ESM5STA_STATE_S 0U |
| #define SOC_AON_ESM3STA2ND_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM3STA2ND_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM3STA2ND_MGCVDONE_S 0U |
| #define SOC_AON_ESM3STA2ND_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM3STA2ND_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM3STA2ND_MGCVFLT_S 1U |
| #define SOC_AON_ESM4STA2ND_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM4STA2ND_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM4STA2ND_MGCVDONE_S 0U |
| #define SOC_AON_ESM4STA2ND_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM4STA2ND_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM4STA2ND_MGCVFLT_S 1U |
| #define SOC_AON_ESM5STA2ND_MGCVDONE 0x00000001U |
| #define SOC_AON_ESM5STA2ND_MGCVDONE_M 0x00000001U |
| #define SOC_AON_ESM5STA2ND_MGCVDONE_S 0U |
| #define SOC_AON_ESM5STA2ND_MGCVFLT 0x00000002U |
| #define SOC_AON_ESM5STA2ND_MGCVFLT_M 0x00000002U |
| #define SOC_AON_ESM5STA2ND_MGCVFLT_S 1U |
| #define SOC_AON_LCSTA_LIFECYCLE_W 4U |
| #define SOC_AON_LCSTA_LIFECYCLE_M 0x0000000FU |
| #define SOC_AON_LCSTA_LIFECYCLE_S 0U |
| #define SOC_AON_LCSTA_SWMNG_W 4U |
| #define SOC_AON_LCSTA_SWMNG_M 0x00000F00U |
| #define SOC_AON_LCSTA_SWMNG_S 8U |
| #define SOC_AON_DRMAST_ERSDRMDN 0x00000001U |
| #define SOC_AON_DRMAST_ERSDRMDN_M 0x00000001U |
| #define SOC_AON_DRMAST_ERSDRMDN_S 0U |
| #define SOC_AON_FLASHMASK_FLASHMASKOV 0x00000001U |
| #define SOC_AON_FLASHMASK_FLASHMASKOV_M 0x00000001U |
| #define SOC_AON_FLASHMASK_FLASHMASKOV_S 0U |
| #define SOC_AON_WSOCROM_UNHIDE 0x00000001U |
| #define SOC_AON_WSOCROM_UNHIDE_M 0x00000001U |
| #define SOC_AON_WSOCROM_UNHIDE_S 0U |