CC35xxDriverLibrary
Macros
hw_soc_aaon.h File Reference
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Macros

#define SOC_AAON_O_DMASIMASK   0x00000000U
 
#define SOC_AAON_O_DMASISET   0x00000004U
 
#define SOC_AAON_O_DMASICLR   0x00000008U
 
#define SOC_AAON_O_DMASIMSET   0x0000000CU
 
#define SOC_AAON_O_DMASIMCLR   0x00000010U
 
#define SOC_AAON_O_DMASRIS   0x00000014U
 
#define SOC_AAON_O_DMASMIS   0x00000018U
 
#define SOC_AAON_O_DMANSIMASK   0x00001000U
 
#define SOC_AAON_O_DMANSISET   0x00001004U
 
#define SOC_AAON_O_DMANSICLR   0x00001008U
 
#define SOC_AAON_O_DMANSIMSET   0x0000100CU
 
#define SOC_AAON_O_DMANSIMCLR   0x00001010U
 
#define SOC_AAON_O_DMANSRIS   0x00001014U
 
#define SOC_AAON_O_DMANSMIS   0x00001018U
 
#define SOC_AAON_O_DMAM3IMASK   0x00002000U
 
#define SOC_AAON_O_DMAM3ISET   0x00002004U
 
#define SOC_AAON_O_DMAM3ICLR   0x00002008U
 
#define SOC_AAON_O_DMAM3IMSET   0x0000200CU
 
#define SOC_AAON_O_DMAM3IMCLR   0x00002010U
 
#define SOC_AAON_O_DMAM3RIS   0x00002014U
 
#define SOC_AAON_O_DMAM3MIS   0x00002018U
 
#define SOC_AAON_DMASIMASK_IMASK_W   12U
 
#define SOC_AAON_DMASIMASK_IMASK_M   0x00000FFFU
 
#define SOC_AAON_DMASIMASK_IMASK_S   0U
 
#define SOC_AAON_DMASISET_ISET_W   12U
 
#define SOC_AAON_DMASISET_ISET_M   0x00000FFFU
 
#define SOC_AAON_DMASISET_ISET_S   0U
 
#define SOC_AAON_DMASICLR_ICLR_W   12U
 
#define SOC_AAON_DMASICLR_ICLR_M   0x00000FFFU
 
#define SOC_AAON_DMASICLR_ICLR_S   0U
 
#define SOC_AAON_DMASIMSET_IMSET_W   12U
 
#define SOC_AAON_DMASIMSET_IMSET_M   0x00000FFFU
 
#define SOC_AAON_DMASIMSET_IMSET_S   0U
 
#define SOC_AAON_DMASIMCLR_IMCLR_W   12U
 
#define SOC_AAON_DMASIMCLR_IMCLR_M   0x00000FFFU
 
#define SOC_AAON_DMASIMCLR_IMCLR_S   0U
 
#define SOC_AAON_DMASRIS_RIS_W   12U
 
#define SOC_AAON_DMASRIS_RIS_M   0x00000FFFU
 
#define SOC_AAON_DMASRIS_RIS_S   0U
 
#define SOC_AAON_DMASMIS_MIS_W   12U
 
#define SOC_AAON_DMASMIS_MIS_M   0x00000FFFU
 
#define SOC_AAON_DMASMIS_MIS_S   0U
 
#define SOC_AAON_DMANSIMASK_IMASK_W   12U
 
#define SOC_AAON_DMANSIMASK_IMASK_M   0x00000FFFU
 
#define SOC_AAON_DMANSIMASK_IMASK_S   0U
 
#define SOC_AAON_DMANSISET_ISET_W   12U
 
#define SOC_AAON_DMANSISET_ISET_M   0x00000FFFU
 
#define SOC_AAON_DMANSISET_ISET_S   0U
 
#define SOC_AAON_DMANSICLR_ICLR_W   12U
 
#define SOC_AAON_DMANSICLR_ICLR_M   0x00000FFFU
 
#define SOC_AAON_DMANSICLR_ICLR_S   0U
 
#define SOC_AAON_DMANSIMSET_IMSET_W   12U
 
#define SOC_AAON_DMANSIMSET_IMSET_M   0x00000FFFU
 
#define SOC_AAON_DMANSIMSET_IMSET_S   0U
 
#define SOC_AAON_DMANSIMCLR_IMCLR_W   12U
 
#define SOC_AAON_DMANSIMCLR_IMCLR_M   0x00000FFFU
 
#define SOC_AAON_DMANSIMCLR_IMCLR_S   0U
 
#define SOC_AAON_DMANSRIS_RIS_W   12U
 
#define SOC_AAON_DMANSRIS_RIS_M   0x00000FFFU
 
#define SOC_AAON_DMANSRIS_RIS_S   0U
 
#define SOC_AAON_DMANSMIS_MIS_W   12U
 
#define SOC_AAON_DMANSMIS_MIS_M   0x00000FFFU
 
#define SOC_AAON_DMANSMIS_MIS_S   0U
 
#define SOC_AAON_DMAM3IMASK_IMASK_W   12U
 
#define SOC_AAON_DMAM3IMASK_IMASK_M   0x00000FFFU
 
#define SOC_AAON_DMAM3IMASK_IMASK_S   0U
 
#define SOC_AAON_DMAM3ISET_ISET_W   12U
 
#define SOC_AAON_DMAM3ISET_ISET_M   0x00000FFFU
 
#define SOC_AAON_DMAM3ISET_ISET_S   0U
 
#define SOC_AAON_DMAM3ICLR_ICLR_W   12U
 
#define SOC_AAON_DMAM3ICLR_ICLR_M   0x00000FFFU
 
#define SOC_AAON_DMAM3ICLR_ICLR_S   0U
 
#define SOC_AAON_DMAM3IMSET_IMSET_W   12U
 
#define SOC_AAON_DMAM3IMSET_IMSET_M   0x00000FFFU
 
#define SOC_AAON_DMAM3IMSET_IMSET_S   0U
 
#define SOC_AAON_DMAM3IMCLR_IMCLR_W   12U
 
#define SOC_AAON_DMAM3IMCLR_IMCLR_M   0x00000FFFU
 
#define SOC_AAON_DMAM3IMCLR_IMCLR_S   0U
 
#define SOC_AAON_DMAM3RIS_RIS_W   12U
 
#define SOC_AAON_DMAM3RIS_RIS_M   0x00000FFFU
 
#define SOC_AAON_DMAM3RIS_RIS_S   0U
 
#define SOC_AAON_DMAM3MIS_MIS_W   12U
 
#define SOC_AAON_DMAM3MIS_MIS_M   0x00000FFFU
 
#define SOC_AAON_DMAM3MIS_MIS_S   0U
 

Macro Definition Documentation

§ SOC_AAON_O_DMASIMASK

#define SOC_AAON_O_DMASIMASK   0x00000000U

Referenced by DMADisableInt(), and DMAEnableInt().

§ SOC_AAON_O_DMASISET

#define SOC_AAON_O_DMASISET   0x00000004U

§ SOC_AAON_O_DMASICLR

#define SOC_AAON_O_DMASICLR   0x00000008U

Referenced by DMAClearInt(), and DMAIntStatus().

§ SOC_AAON_O_DMASIMSET

#define SOC_AAON_O_DMASIMSET   0x0000000CU

§ SOC_AAON_O_DMASIMCLR

#define SOC_AAON_O_DMASIMCLR   0x00000010U

§ SOC_AAON_O_DMASRIS

#define SOC_AAON_O_DMASRIS   0x00000014U

§ SOC_AAON_O_DMASMIS

#define SOC_AAON_O_DMASMIS   0x00000018U

Referenced by DMAIntStatus().

§ SOC_AAON_O_DMANSIMASK

#define SOC_AAON_O_DMANSIMASK   0x00001000U

§ SOC_AAON_O_DMANSISET

#define SOC_AAON_O_DMANSISET   0x00001004U

§ SOC_AAON_O_DMANSICLR

#define SOC_AAON_O_DMANSICLR   0x00001008U

§ SOC_AAON_O_DMANSIMSET

#define SOC_AAON_O_DMANSIMSET   0x0000100CU

§ SOC_AAON_O_DMANSIMCLR

#define SOC_AAON_O_DMANSIMCLR   0x00001010U

§ SOC_AAON_O_DMANSRIS

#define SOC_AAON_O_DMANSRIS   0x00001014U

§ SOC_AAON_O_DMANSMIS

#define SOC_AAON_O_DMANSMIS   0x00001018U

§ SOC_AAON_O_DMAM3IMASK

#define SOC_AAON_O_DMAM3IMASK   0x00002000U

§ SOC_AAON_O_DMAM3ISET

#define SOC_AAON_O_DMAM3ISET   0x00002004U

§ SOC_AAON_O_DMAM3ICLR

#define SOC_AAON_O_DMAM3ICLR   0x00002008U

§ SOC_AAON_O_DMAM3IMSET

#define SOC_AAON_O_DMAM3IMSET   0x0000200CU

§ SOC_AAON_O_DMAM3IMCLR

#define SOC_AAON_O_DMAM3IMCLR   0x00002010U

§ SOC_AAON_O_DMAM3RIS

#define SOC_AAON_O_DMAM3RIS   0x00002014U

§ SOC_AAON_O_DMAM3MIS

#define SOC_AAON_O_DMAM3MIS   0x00002018U

§ SOC_AAON_DMASIMASK_IMASK_W

#define SOC_AAON_DMASIMASK_IMASK_W   12U

§ SOC_AAON_DMASIMASK_IMASK_M

#define SOC_AAON_DMASIMASK_IMASK_M   0x00000FFFU

§ SOC_AAON_DMASIMASK_IMASK_S

#define SOC_AAON_DMASIMASK_IMASK_S   0U

§ SOC_AAON_DMASISET_ISET_W

#define SOC_AAON_DMASISET_ISET_W   12U

§ SOC_AAON_DMASISET_ISET_M

#define SOC_AAON_DMASISET_ISET_M   0x00000FFFU

§ SOC_AAON_DMASISET_ISET_S

#define SOC_AAON_DMASISET_ISET_S   0U

§ SOC_AAON_DMASICLR_ICLR_W

#define SOC_AAON_DMASICLR_ICLR_W   12U

§ SOC_AAON_DMASICLR_ICLR_M

#define SOC_AAON_DMASICLR_ICLR_M   0x00000FFFU

§ SOC_AAON_DMASICLR_ICLR_S

#define SOC_AAON_DMASICLR_ICLR_S   0U

§ SOC_AAON_DMASIMSET_IMSET_W

#define SOC_AAON_DMASIMSET_IMSET_W   12U

§ SOC_AAON_DMASIMSET_IMSET_M

#define SOC_AAON_DMASIMSET_IMSET_M   0x00000FFFU

§ SOC_AAON_DMASIMSET_IMSET_S

#define SOC_AAON_DMASIMSET_IMSET_S   0U

§ SOC_AAON_DMASIMCLR_IMCLR_W

#define SOC_AAON_DMASIMCLR_IMCLR_W   12U

§ SOC_AAON_DMASIMCLR_IMCLR_M

#define SOC_AAON_DMASIMCLR_IMCLR_M   0x00000FFFU

§ SOC_AAON_DMASIMCLR_IMCLR_S

#define SOC_AAON_DMASIMCLR_IMCLR_S   0U

§ SOC_AAON_DMASRIS_RIS_W

#define SOC_AAON_DMASRIS_RIS_W   12U

§ SOC_AAON_DMASRIS_RIS_M

#define SOC_AAON_DMASRIS_RIS_M   0x00000FFFU

§ SOC_AAON_DMASRIS_RIS_S

#define SOC_AAON_DMASRIS_RIS_S   0U

§ SOC_AAON_DMASMIS_MIS_W

#define SOC_AAON_DMASMIS_MIS_W   12U

§ SOC_AAON_DMASMIS_MIS_M

#define SOC_AAON_DMASMIS_MIS_M   0x00000FFFU

§ SOC_AAON_DMASMIS_MIS_S

#define SOC_AAON_DMASMIS_MIS_S   0U

§ SOC_AAON_DMANSIMASK_IMASK_W

#define SOC_AAON_DMANSIMASK_IMASK_W   12U

§ SOC_AAON_DMANSIMASK_IMASK_M

#define SOC_AAON_DMANSIMASK_IMASK_M   0x00000FFFU

§ SOC_AAON_DMANSIMASK_IMASK_S

#define SOC_AAON_DMANSIMASK_IMASK_S   0U

§ SOC_AAON_DMANSISET_ISET_W

#define SOC_AAON_DMANSISET_ISET_W   12U

§ SOC_AAON_DMANSISET_ISET_M

#define SOC_AAON_DMANSISET_ISET_M   0x00000FFFU

§ SOC_AAON_DMANSISET_ISET_S

#define SOC_AAON_DMANSISET_ISET_S   0U

§ SOC_AAON_DMANSICLR_ICLR_W

#define SOC_AAON_DMANSICLR_ICLR_W   12U

§ SOC_AAON_DMANSICLR_ICLR_M

#define SOC_AAON_DMANSICLR_ICLR_M   0x00000FFFU

§ SOC_AAON_DMANSICLR_ICLR_S

#define SOC_AAON_DMANSICLR_ICLR_S   0U

§ SOC_AAON_DMANSIMSET_IMSET_W

#define SOC_AAON_DMANSIMSET_IMSET_W   12U

§ SOC_AAON_DMANSIMSET_IMSET_M

#define SOC_AAON_DMANSIMSET_IMSET_M   0x00000FFFU

§ SOC_AAON_DMANSIMSET_IMSET_S

#define SOC_AAON_DMANSIMSET_IMSET_S   0U

§ SOC_AAON_DMANSIMCLR_IMCLR_W

#define SOC_AAON_DMANSIMCLR_IMCLR_W   12U

§ SOC_AAON_DMANSIMCLR_IMCLR_M

#define SOC_AAON_DMANSIMCLR_IMCLR_M   0x00000FFFU

§ SOC_AAON_DMANSIMCLR_IMCLR_S

#define SOC_AAON_DMANSIMCLR_IMCLR_S   0U

§ SOC_AAON_DMANSRIS_RIS_W

#define SOC_AAON_DMANSRIS_RIS_W   12U

§ SOC_AAON_DMANSRIS_RIS_M

#define SOC_AAON_DMANSRIS_RIS_M   0x00000FFFU

§ SOC_AAON_DMANSRIS_RIS_S

#define SOC_AAON_DMANSRIS_RIS_S   0U

§ SOC_AAON_DMANSMIS_MIS_W

#define SOC_AAON_DMANSMIS_MIS_W   12U

§ SOC_AAON_DMANSMIS_MIS_M

#define SOC_AAON_DMANSMIS_MIS_M   0x00000FFFU

§ SOC_AAON_DMANSMIS_MIS_S

#define SOC_AAON_DMANSMIS_MIS_S   0U

§ SOC_AAON_DMAM3IMASK_IMASK_W

#define SOC_AAON_DMAM3IMASK_IMASK_W   12U

§ SOC_AAON_DMAM3IMASK_IMASK_M

#define SOC_AAON_DMAM3IMASK_IMASK_M   0x00000FFFU

§ SOC_AAON_DMAM3IMASK_IMASK_S

#define SOC_AAON_DMAM3IMASK_IMASK_S   0U

§ SOC_AAON_DMAM3ISET_ISET_W

#define SOC_AAON_DMAM3ISET_ISET_W   12U

§ SOC_AAON_DMAM3ISET_ISET_M

#define SOC_AAON_DMAM3ISET_ISET_M   0x00000FFFU

§ SOC_AAON_DMAM3ISET_ISET_S

#define SOC_AAON_DMAM3ISET_ISET_S   0U

§ SOC_AAON_DMAM3ICLR_ICLR_W

#define SOC_AAON_DMAM3ICLR_ICLR_W   12U

§ SOC_AAON_DMAM3ICLR_ICLR_M

#define SOC_AAON_DMAM3ICLR_ICLR_M   0x00000FFFU

§ SOC_AAON_DMAM3ICLR_ICLR_S

#define SOC_AAON_DMAM3ICLR_ICLR_S   0U

§ SOC_AAON_DMAM3IMSET_IMSET_W

#define SOC_AAON_DMAM3IMSET_IMSET_W   12U

§ SOC_AAON_DMAM3IMSET_IMSET_M

#define SOC_AAON_DMAM3IMSET_IMSET_M   0x00000FFFU

§ SOC_AAON_DMAM3IMSET_IMSET_S

#define SOC_AAON_DMAM3IMSET_IMSET_S   0U

§ SOC_AAON_DMAM3IMCLR_IMCLR_W

#define SOC_AAON_DMAM3IMCLR_IMCLR_W   12U

§ SOC_AAON_DMAM3IMCLR_IMCLR_M

#define SOC_AAON_DMAM3IMCLR_IMCLR_M   0x00000FFFU

§ SOC_AAON_DMAM3IMCLR_IMCLR_S

#define SOC_AAON_DMAM3IMCLR_IMCLR_S   0U

§ SOC_AAON_DMAM3RIS_RIS_W

#define SOC_AAON_DMAM3RIS_RIS_W   12U

§ SOC_AAON_DMAM3RIS_RIS_M

#define SOC_AAON_DMAM3RIS_RIS_M   0x00000FFFU

§ SOC_AAON_DMAM3RIS_RIS_S

#define SOC_AAON_DMAM3RIS_RIS_S   0U

§ SOC_AAON_DMAM3MIS_MIS_W

#define SOC_AAON_DMAM3MIS_MIS_W   12U

§ SOC_AAON_DMAM3MIS_MIS_M

#define SOC_AAON_DMAM3MIS_MIS_M   0x00000FFFU

§ SOC_AAON_DMAM3MIS_MIS_S

#define SOC_AAON_DMAM3MIS_MIS_S   0U