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CC35xxDriverLibrary
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Go to the source code of this file.
| #define SDIO_CORE_O_CCCR00 0x00000000U |
| #define SDIO_CORE_O_CCCR04 0x00000004U |
| #define SDIO_CORE_O_CCCR08 0x00000008U |
| #define SDIO_CORE_O_CCCR10 0x00000010U |
| #define SDIO_CORE_O_CCCR14 0x00000014U |
| #define SDIO_CORE_O_CCCR40 0x00000040U |
| #define SDIO_CORE_O_CCCR44 0x00000044U |
| #define SDIO_CORE_O_CCCR48 0x00000048U |
| #define SDIO_CORE_O_CCCR60 0x00000060U |
| #define SDIO_CORE_O_CCCR64 0x00000064U |
| #define SDIO_CORE_O_CCCR68 0x00000068U |
| #define SDIO_CORE_O_CCCR80 0x00000080U |
| #define SDIO_CORE_O_CCCR84 0x00000084U |
| #define SDIO_CORE_O_CCCR88 0x00000088U |
| #define SDIO_CORE_O_CCCR8C 0x0000008CU |
| #define SDIO_CORE_O_CCCR90 0x00000090U |
| #define SDIO_CORE_O_CCCR94 0x00000094U |
| #define SDIO_CORE_O_CCCR98 0x00000098U |
| #define SDIO_CORE_O_CCCR9C 0x0000009CU |
| #define SDIO_CORE_O_CCCRA0 0x000000A0U |
| #define SDIO_CORE_O_CCCRA4 0x000000A4U |
| #define SDIO_CORE_O_CCCRC0 0x000000C0U |
| #define SDIO_CORE_O_CCCRC4 0x000000C4U |
| #define SDIO_CORE_O_FBR1R100 0x00000100U |
| #define SDIO_CORE_O_FBR1R108 0x00000108U |
| #define SDIO_CORE_O_FBR1R110 0x00000110U |
| #define SDIO_CORE_O_FBR2R200 0x00000200U |
| #define SDIO_CORE_O_FBR2R208 0x00000208U |
| #define SDIO_CORE_O_FBR2R210 0x00000210U |
| #define SDIO_CORE_O_CISP1ADDR 0x0001FFE0U |
| #define SDIO_CORE_O_CISP2ADDR 0x0001FFE4U |
| #define SDIO_CORE_O_CISP3ADDR 0x0001FFE8U |
| #define SDIO_CORE_O_CISP4ADDR 0x0001FFECU |
| #define SDIO_CORE_O_CISP5ADDR 0x0001FFF0U |
| #define SDIO_CORE_CCCR00_CCCR_W 4U |
| #define SDIO_CORE_CCCR00_CCCR_M 0x0000000FU |
| #define SDIO_CORE_CCCR00_CCCR_S 0U |
| #define SDIO_CORE_CCCR00_SDIO_W 4U |
| #define SDIO_CORE_CCCR00_SDIO_M 0x000000F0U |
| #define SDIO_CORE_CCCR00_SDIO_S 4U |
| #define SDIO_CORE_CCCR00_SD_W 4U |
| #define SDIO_CORE_CCCR00_SD_M 0x00000F00U |
| #define SDIO_CORE_CCCR00_SD_S 8U |
| #define SDIO_CORE_CCCR00_FN1EN 0x00020000U |
| #define SDIO_CORE_CCCR00_FN1EN_M 0x00020000U |
| #define SDIO_CORE_CCCR00_FN1EN_S 17U |
| #define SDIO_CORE_CCCR00_FN1RDY 0x02000000U |
| #define SDIO_CORE_CCCR00_FN1RDY_M 0x02000000U |
| #define SDIO_CORE_CCCR00_FN1RDY_S 25U |
| #define SDIO_CORE_CCCR04_CINTEN 0x00000001U |
| #define SDIO_CORE_CCCR04_CINTEN_M 0x00000001U |
| #define SDIO_CORE_CCCR04_CINTEN_S 0U |
| #define SDIO_CORE_CCCR04_FN1INTEN 0x00000002U |
| #define SDIO_CORE_CCCR04_FN1INTEN_M 0x00000002U |
| #define SDIO_CORE_CCCR04_FN1INTEN_S 1U |
| #define SDIO_CORE_CCCR04_FN1INTPEND 0x00000200U |
| #define SDIO_CORE_CCCR04_FN1INTPEND_M 0x00000200U |
| #define SDIO_CORE_CCCR04_FN1INTPEND_S 9U |
| #define SDIO_CORE_CCCR04_SDIOABORT_W 3U |
| #define SDIO_CORE_CCCR04_SDIOABORT_M 0x00070000U |
| #define SDIO_CORE_CCCR04_SDIOABORT_S 16U |
| #define SDIO_CORE_CCCR04_SDIORSTREQ 0x00080000U |
| #define SDIO_CORE_CCCR04_SDIORSTREQ_M 0x00080000U |
| #define SDIO_CORE_CCCR04_SDIORSTREQ_S 19U |
| #define SDIO_CORE_CCCR04_BW_W 2U |
| #define SDIO_CORE_CCCR04_BW_M 0x03000000U |
| #define SDIO_CORE_CCCR04_BW_S 24U |
| #define SDIO_CORE_CCCR04_CDDIS 0x80000000U |
| #define SDIO_CORE_CCCR04_CDDIS_M 0x80000000U |
| #define SDIO_CORE_CCCR04_CDDIS_S 31U |
| #define SDIO_CORE_CCCR08_SDC 0x00000001U |
| #define SDIO_CORE_CCCR08_SDC_M 0x00000001U |
| #define SDIO_CORE_CCCR08_SDC_S 0U |
| #define SDIO_CORE_CCCR08_SMB 0x00000002U |
| #define SDIO_CORE_CCCR08_SMB_M 0x00000002U |
| #define SDIO_CORE_CCCR08_SMB_S 1U |
| #define SDIO_CORE_CCCR08_SRW 0x00000004U |
| #define SDIO_CORE_CCCR08_SRW_M 0x00000004U |
| #define SDIO_CORE_CCCR08_SRW_S 2U |
| #define SDIO_CORE_CCCR08_SBS 0x00000008U |
| #define SDIO_CORE_CCCR08_SBS_M 0x00000008U |
| #define SDIO_CORE_CCCR08_SBS_S 3U |
| #define SDIO_CORE_CCCR08_S4MI 0x00000010U |
| #define SDIO_CORE_CCCR08_S4MI_M 0x00000010U |
| #define SDIO_CORE_CCCR08_S4MI_S 4U |
| #define SDIO_CORE_CCCR08_E4MI 0x00000020U |
| #define SDIO_CORE_CCCR08_E4MI_M 0x00000020U |
| #define SDIO_CORE_CCCR08_E4MI_S 5U |
| #define SDIO_CORE_CCCR08_LSC 0x00000040U |
| #define SDIO_CORE_CCCR08_LSC_M 0x00000040U |
| #define SDIO_CORE_CCCR08_LSC_S 6U |
| #define SDIO_CORE_CCCR08_BLS4 0x00000080U |
| #define SDIO_CORE_CCCR08_BLS4_M 0x00000080U |
| #define SDIO_CORE_CCCR08_BLS4_S 7U |
| #define SDIO_CORE_CCCR08_CISPTR0_W 8U |
| #define SDIO_CORE_CCCR08_CISPTR0_M 0x0000FF00U |
| #define SDIO_CORE_CCCR08_CISPTR0_S 8U |
| #define SDIO_CORE_CCCR08_CISPTR1_W 16U |
| #define SDIO_CORE_CCCR08_CISPTR1_M 0xFFFF0000U |
| #define SDIO_CORE_CCCR08_CISPTR1_S 16U |
| #define SDIO_CORE_CCCR10_FN0BLKSIZE_W 12U |
| #define SDIO_CORE_CCCR10_FN0BLKSIZE_M 0x00000FFFU |
| #define SDIO_CORE_CCCR10_FN0BLKSIZE_S 0U |
| #define SDIO_CORE_CCCR10_SHS 0x01000000U |
| #define SDIO_CORE_CCCR10_SHS_M 0x01000000U |
| #define SDIO_CORE_CCCR10_SHS_S 24U |
| #define SDIO_CORE_CCCR10_EHS 0x02000000U |
| #define SDIO_CORE_CCCR10_EHS_M 0x02000000U |
| #define SDIO_CORE_CCCR10_EHS_S 25U |
| #define SDIO_CORE_CCCR14_SAI 0x00010000U |
| #define SDIO_CORE_CCCR14_SAI_M 0x00010000U |
| #define SDIO_CORE_CCCR14_SAI_S 16U |
| #define SDIO_CORE_CCCR14_EAI 0x00020000U |
| #define SDIO_CORE_CCCR14_EAI_M 0x00020000U |
| #define SDIO_CORE_CCCR14_EAI_S 17U |
| #define SDIO_CORE_CCCR40_FN1ELPSTA 0x00010000U |
| #define SDIO_CORE_CCCR40_FN1ELPSTA_M 0x00010000U |
| #define SDIO_CORE_CCCR40_FN1ELPSTA_S 16U |
| #define SDIO_CORE_CCCR44_FN1OBIEN 0x00000001U |
| #define SDIO_CORE_CCCR44_FN1OBIEN_M 0x00000001U |
| #define SDIO_CORE_CCCR44_FN1OBIEN_S 0U |
| #define SDIO_CORE_CCCR44_FN1OBIINV 0x00000002U |
| #define SDIO_CORE_CCCR44_FN1OBIINV_M 0x00000002U |
| #define SDIO_CORE_CCCR44_FN1OBIINV_S 1U |
| #define SDIO_CORE_CCCR44_FN1GPIMSK_W 7U |
| #define SDIO_CORE_CCCR44_FN1GPIMSK_M 0x00007F00U |
| #define SDIO_CORE_CCCR44_FN1GPIMSK_S 8U |
| #define SDIO_CORE_CCCR44_FN1STA 0x00008000U |
| #define SDIO_CORE_CCCR44_FN1STA_M 0x00008000U |
| #define SDIO_CORE_CCCR44_FN1STA_S 15U |
| #define SDIO_CORE_CCCR44_FN1GPISTA_W 7U |
| #define SDIO_CORE_CCCR44_FN1GPISTA_M 0x007F0000U |
| #define SDIO_CORE_CCCR44_FN1GPISTA_S 16U |
| #define SDIO_CORE_CCCR44_FN1GPICLR_W 6U |
| #define SDIO_CORE_CCCR44_FN1GPICLR_M 0x3F000000U |
| #define SDIO_CORE_CCCR44_FN1GPICLR_S 24U |
| #define SDIO_CORE_CCCR48_FN1BUSY 0x00000001U |
| #define SDIO_CORE_CCCR48_FN1BUSY_M 0x00000001U |
| #define SDIO_CORE_CCCR48_FN1BUSY_S 0U |
| #define SDIO_CORE_CCCR48_FN1BUSYOV 0x00000002U |
| #define SDIO_CORE_CCCR48_FN1BUSYOV_M 0x00000002U |
| #define SDIO_CORE_CCCR48_FN1BUSYOV_S 1U |
| #define SDIO_CORE_CCCR68_CMDERR_W 6U |
| #define SDIO_CORE_CCCR68_CMDERR_M 0x003F0000U |
| #define SDIO_CORE_CCCR68_CMDERR_S 16U |
| #define SDIO_CORE_CCCR80_OCR_W 24U |
| #define SDIO_CORE_CCCR80_OCR_M 0x00FFFFFFU |
| #define SDIO_CORE_CCCR80_OCR_S 0U |
| #define SDIO_CORE_CCCR84_SDCMDST_W 5U |
| #define SDIO_CORE_CCCR84_SDCMDST_M 0x0000001FU |
| #define SDIO_CORE_CCCR84_SDCMDST_S 0U |
| #define SDIO_CORE_CCCR84_SDRESPST_W 3U |
| #define SDIO_CORE_CCCR84_SDRESPST_M 0x000000E0U |
| #define SDIO_CORE_CCCR84_SDRESPST_S 5U |
| #define SDIO_CORE_CCCR84_SDDAT3ST_W 4U |
| #define SDIO_CORE_CCCR84_SDDAT3ST_M 0x00000F00U |
| #define SDIO_CORE_CCCR84_SDDAT3ST_S 8U |
| #define SDIO_CORE_CCCR84_SDDAT0ST_W 5U |
| #define SDIO_CORE_CCCR84_SDDAT0ST_M 0x001F0000U |
| #define SDIO_CORE_CCCR84_SDDAT0ST_S 16U |
| #define SDIO_CORE_CCCR84_SDDAT1ST_W 5U |
| #define SDIO_CORE_CCCR84_SDDAT1ST_M 0x03E00000U |
| #define SDIO_CORE_CCCR84_SDDAT1ST_S 21U |
| #define SDIO_CORE_CCCR84_SDDAT2ST_W 4U |
| #define SDIO_CORE_CCCR84_SDDAT2ST_M 0x3C000000U |
| #define SDIO_CORE_CCCR84_SDDAT2ST_S 26U |
| #define SDIO_CORE_CCCR88_RCA_W 16U |
| #define SDIO_CORE_CCCR88_RCA_M 0xFFFF0000U |
| #define SDIO_CORE_CCCR88_RCA_S 16U |
| #define SDIO_CORE_CCCRA0_OCPSTA0_W 4U |
| #define SDIO_CORE_CCCRA0_OCPSTA0_M 0x000F0000U |
| #define SDIO_CORE_CCCRA0_OCPSTA0_S 16U |
| #define SDIO_CORE_CCCRA0_OCPSTA1_W 4U |
| #define SDIO_CORE_CCCRA0_OCPSTA1_M 0x00F00000U |
| #define SDIO_CORE_CCCRA0_OCPSTA1_S 20U |
| #define SDIO_CORE_CCCRA4_RAWTMRVAL_W 5U |
| #define SDIO_CORE_CCCRA4_RAWTMRVAL_M 0x0000001FU |
| #define SDIO_CORE_CCCRA4_RAWTMRVAL_S 0U |
| #define SDIO_CORE_CCCRA4_USECTMRVAL_W 6U |
| #define SDIO_CORE_CCCRA4_USECTMRVAL_M 0x00003F00U |
| #define SDIO_CORE_CCCRA4_USECTMRVAL_S 8U |
| #define SDIO_CORE_CCCRC0_WUCMD53 0x00010000U |
| #define SDIO_CORE_CCCRC0_WUCMD53_M 0x00010000U |
| #define SDIO_CORE_CCCRC0_WUCMD53_S 16U |
| #define SDIO_CORE_CCCRC0_WUHOSTRD 0x00020000U |
| #define SDIO_CORE_CCCRC0_WUHOSTRD_M 0x00020000U |
| #define SDIO_CORE_CCCRC0_WUHOSTRD_S 17U |
| #define SDIO_CORE_CCCRC0_WUHOSTWR 0x00040000U |
| #define SDIO_CORE_CCCRC0_WUHOSTWR_M 0x00040000U |
| #define SDIO_CORE_CCCRC0_WUHOSTWR_S 18U |
| #define SDIO_CORE_CCCRC0_WUADDR 0x00080000U |
| #define SDIO_CORE_CCCRC0_WUADDR_M 0x00080000U |
| #define SDIO_CORE_CCCRC0_WUADDR_S 19U |
| #define SDIO_CORE_CCCRC0_WUELP 0x00100000U |
| #define SDIO_CORE_CCCRC0_WUELP_M 0x00100000U |
| #define SDIO_CORE_CCCRC0_WUELP_S 20U |
| #define SDIO_CORE_CCCRC0_WUAUT 0x00200000U |
| #define SDIO_CORE_CCCRC0_WUAUT_M 0x00200000U |
| #define SDIO_CORE_CCCRC0_WUAUT_S 21U |
| #define SDIO_CORE_CCCRC4_FN1GPISTA_W 7U |
| #define SDIO_CORE_CCCRC4_FN1GPISTA_M 0x0000007FU |
| #define SDIO_CORE_CCCRC4_FN1GPISTA_S 0U |
| #define SDIO_CORE_FBR1R100_SDIO_W 4U |
| #define SDIO_CORE_FBR1R100_SDIO_M 0x0000000FU |
| #define SDIO_CORE_FBR1R100_SDIO_S 0U |
| #define SDIO_CORE_FBR1R100_CSA 0x00000040U |
| #define SDIO_CORE_FBR1R100_CSA_M 0x00000040U |
| #define SDIO_CORE_FBR1R100_CSA_S 6U |
| #define SDIO_CORE_FBR1R108_CISPTR0_W 8U |
| #define SDIO_CORE_FBR1R108_CISPTR0_M 0x0000FF00U |
| #define SDIO_CORE_FBR1R108_CISPTR0_S 8U |
| #define SDIO_CORE_FBR1R108_CISPTR1_W 16U |
| #define SDIO_CORE_FBR1R108_CISPTR1_M 0xFFFF0000U |
| #define SDIO_CORE_FBR1R108_CISPTR1_S 16U |
| #define SDIO_CORE_FBR1R110_FNBLKSIZE_W 12U |
| #define SDIO_CORE_FBR1R110_FNBLKSIZE_M 0x00000FFFU |
| #define SDIO_CORE_FBR1R110_FNBLKSIZE_S 0U |
| #define SDIO_CORE_FBR2R200_SDIO_W 4U |
| #define SDIO_CORE_FBR2R200_SDIO_M 0x0000000FU |
| #define SDIO_CORE_FBR2R200_SDIO_S 0U |
| #define SDIO_CORE_FBR2R200_CSA 0x00000040U |
| #define SDIO_CORE_FBR2R200_CSA_M 0x00000040U |
| #define SDIO_CORE_FBR2R200_CSA_S 6U |
| #define SDIO_CORE_FBR2R208_CISPTR0_W 8U |
| #define SDIO_CORE_FBR2R208_CISPTR0_M 0x0000FF00U |
| #define SDIO_CORE_FBR2R208_CISPTR0_S 8U |
| #define SDIO_CORE_FBR2R208_CISPTR1_W 16U |
| #define SDIO_CORE_FBR2R208_CISPTR1_M 0xFFFF0000U |
| #define SDIO_CORE_FBR2R208_CISPTR1_S 16U |
| #define SDIO_CORE_FBR2R210_FNBLKSIZE_W 12U |
| #define SDIO_CORE_FBR2R210_FNBLKSIZE_M 0x00000FFFU |
| #define SDIO_CORE_FBR2R210_FNBLKSIZE_S 0U |
| #define SDIO_CORE_CISP1ADDR_PCH1ADDR_W 16U |
| #define SDIO_CORE_CISP1ADDR_PCH1ADDR_M 0x0000FFFFU |
| #define SDIO_CORE_CISP1ADDR_PCH1ADDR_S 0U |
| #define SDIO_CORE_CISP1ADDR_PCH1DAT_W 8U |
| #define SDIO_CORE_CISP1ADDR_PCH1DAT_M 0x00FF0000U |
| #define SDIO_CORE_CISP1ADDR_PCH1DAT_S 16U |
| #define SDIO_CORE_CISP2ADDR_PCH2ADDR_W 16U |
| #define SDIO_CORE_CISP2ADDR_PCH2ADDR_M 0x0000FFFFU |
| #define SDIO_CORE_CISP2ADDR_PCH2ADDR_S 0U |
| #define SDIO_CORE_CISP2ADDR_PCH2DAT_W 8U |
| #define SDIO_CORE_CISP2ADDR_PCH2DAT_M 0x00FF0000U |
| #define SDIO_CORE_CISP2ADDR_PCH2DAT_S 16U |
| #define SDIO_CORE_CISP3ADDR_PCH3ADDR_W 16U |
| #define SDIO_CORE_CISP3ADDR_PCH3ADDR_M 0x0000FFFFU |
| #define SDIO_CORE_CISP3ADDR_PCH3ADDR_S 0U |
| #define SDIO_CORE_CISP3ADDR_PCH3DAT_W 8U |
| #define SDIO_CORE_CISP3ADDR_PCH3DAT_M 0x00FF0000U |
| #define SDIO_CORE_CISP3ADDR_PCH3DAT_S 16U |
| #define SDIO_CORE_CISP4ADDR_PCH4ADDR_W 16U |
| #define SDIO_CORE_CISP4ADDR_PCH4ADDR_M 0x0000FFFFU |
| #define SDIO_CORE_CISP4ADDR_PCH4ADDR_S 0U |
| #define SDIO_CORE_CISP4ADDR_PCH4DAT_W 8U |
| #define SDIO_CORE_CISP4ADDR_PCH4DAT_M 0x00FF0000U |
| #define SDIO_CORE_CISP4ADDR_PCH4DAT_S 16U |
| #define SDIO_CORE_CISP5ADDR_PCH5ADDR_W 16U |
| #define SDIO_CORE_CISP5ADDR_PCH5ADDR_M 0x0000FFFFU |
| #define SDIO_CORE_CISP5ADDR_PCH5ADDR_S 0U |
| #define SDIO_CORE_CISP5ADDR_PCH5DAT_W 8U |
| #define SDIO_CORE_CISP5ADDR_PCH5DAT_M 0x00FF0000U |
| #define SDIO_CORE_CISP5ADDR_PCH5DAT_S 16U |