Macros
#define	RTC_O_DESC 0x00000000U

#define	RTC_O_CTL 0x00000004U

#define	RTC_O_ARMSET 0x00000008U

#define	RTC_O_ARMCLR 0x0000000CU

#define	RTC_O_TIME250N 0x00000010U

#define	RTC_O_TIME1U 0x00000014U

#define	RTC_O_TIME8U 0x00000018U

#define	RTC_O_TIME524M 0x0000001CU

#define	RTC_O_CH0CC250N 0x00000020U

#define	RTC_O_CH0CC1U 0x00000024U

#define	RTC_O_CH0CC8U 0x00000028U

#define	RTC_O_CH1CC8U 0x00000038U

#define	RTC_O_CH1CFG 0x0000003CU

#define	RTC_O_IMASK 0x00000044U

#define	RTC_O_RIS 0x00000048U

#define	RTC_O_MIS 0x0000004CU

#define	RTC_O_ISET 0x00000050U

#define	RTC_O_ICLR 0x00000054U

#define	RTC_O_IMSET 0x00000058U

#define	RTC_O_IMCLR 0x0000005CU

#define	RTC_O_EMU 0x00000060U

#define	RTC_O_DTB 0x00000064U

#define	RTC_O_DTIME 0x00000068U

#define	RTC_DESC_MINREV_W 4U

#define	RTC_DESC_MINREV_M 0x0000000FU

#define	RTC_DESC_MINREV_S 0U

#define	RTC_DESC_MAJREV_W 4U

#define	RTC_DESC_MAJREV_M 0x000000F0U

#define	RTC_DESC_MAJREV_S 4U

#define	RTC_DESC_INSTIDX_W 4U

#define	RTC_DESC_INSTIDX_M 0x00000F00U

#define	RTC_DESC_INSTIDX_S 8U

#define	RTC_DESC_STDIPOFF_W 4U

#define	RTC_DESC_STDIPOFF_M 0x0000F000U

#define	RTC_DESC_STDIPOFF_S 12U

#define	RTC_DESC_MODID_W 16U

#define	RTC_DESC_MODID_M 0xFFFF0000U

#define	RTC_DESC_MODID_S 16U

#define	RTC_CTL_RST 0x00000001U

#define	RTC_CTL_RST_M 0x00000001U

#define	RTC_CTL_RST_S 0U

#define	RTC_CTL_RST_NOEFF 0x00000000U

#define	RTC_CTL_RST_CLR 0x00000001U

#define	RTC_ARMSET_CH0 0x00000001U

#define	RTC_ARMSET_CH0_M 0x00000001U

#define	RTC_ARMSET_CH0_S 0U

#define	RTC_ARMSET_CH0_NOEFF 0x00000000U

#define	RTC_ARMSET_CH0_SET 0x00000001U

#define	RTC_ARMSET_CH1 0x00000002U

#define	RTC_ARMSET_CH1_M 0x00000002U

#define	RTC_ARMSET_CH1_S 1U

#define	RTC_ARMSET_CH1_NOEFF 0x00000000U

#define	RTC_ARMSET_CH1_SET 0x00000002U

#define	RTC_ARMCLR_CH0 0x00000001U

#define	RTC_ARMCLR_CH0_M 0x00000001U

#define	RTC_ARMCLR_CH0_S 0U

#define	RTC_ARMCLR_CH0_NOEFF 0x00000000U

#define	RTC_ARMCLR_CH0_CLR 0x00000001U

#define	RTC_ARMCLR_CH1 0x00000002U

#define	RTC_ARMCLR_CH1_M 0x00000002U

#define	RTC_ARMCLR_CH1_S 1U

#define	RTC_ARMCLR_CH1_NOEFF 0x00000000U

#define	RTC_ARMCLR_CH1_CLR 0x00000002U

#define	RTC_TIME250N_VAL_W 32U

#define	RTC_TIME250N_VAL_M 0xFFFFFFFFU

#define	RTC_TIME250N_VAL_S 0U

#define	RTC_TIME1U_VAL_W 32U

#define	RTC_TIME1U_VAL_M 0xFFFFFFFFU

#define	RTC_TIME1U_VAL_S 0U

#define	RTC_TIME8U_VAL_W 32U

#define	RTC_TIME8U_VAL_M 0xFFFFFFFFU

#define	RTC_TIME8U_VAL_S 0U

#define	RTC_TIME524M_VAL_W 32U

#define	RTC_TIME524M_VAL_M 0xFFFFFFFFU

#define	RTC_TIME524M_VAL_S 0U

#define	RTC_CH0CC250N_VAL_W 32U

#define	RTC_CH0CC250N_VAL_M 0xFFFFFFFFU

#define	RTC_CH0CC250N_VAL_S 0U

#define	RTC_CH0CC1U_VAL_W 32U

#define	RTC_CH0CC1U_VAL_M 0xFFFFFFFFU

#define	RTC_CH0CC1U_VAL_S 0U

#define	RTC_CH0CC8U_VAL_W 32U

#define	RTC_CH0CC8U_VAL_M 0xFFFFFFFFU

#define	RTC_CH0CC8U_VAL_S 0U

#define	RTC_CH1CC8U_VAL_W 21U

#define	RTC_CH1CC8U_VAL_M 0x001FFFFFU

#define	RTC_CH1CC8U_VAL_S 0U

#define	RTC_CH1CFG_EDGE 0x00000001U

#define	RTC_CH1CFG_EDGE_M 0x00000001U

#define	RTC_CH1CFG_EDGE_S 0U

#define	RTC_CH1CFG_EDGE_RISE 0x00000000U

#define	RTC_CH1CFG_EDGE_FALL 0x00000001U

#define	RTC_IMASK_EV0 0x00000001U

#define	RTC_IMASK_EV0_M 0x00000001U

#define	RTC_IMASK_EV0_S 0U

#define	RTC_IMASK_EV0_DIS 0x00000000U

#define	RTC_IMASK_EV0_EN 0x00000001U

#define	RTC_IMASK_EV1 0x00000002U

#define	RTC_IMASK_EV1_M 0x00000002U

#define	RTC_IMASK_EV1_S 1U

#define	RTC_IMASK_EV1_DIS 0x00000000U

#define	RTC_IMASK_EV1_EN 0x00000002U

#define	RTC_RIS_EV0 0x00000001U

#define	RTC_RIS_EV0_M 0x00000001U

#define	RTC_RIS_EV0_S 0U

#define	RTC_RIS_EV0_CLR 0x00000000U

#define	RTC_RIS_EV0_SET 0x00000001U

#define	RTC_RIS_EV1 0x00000002U

#define	RTC_RIS_EV1_M 0x00000002U

#define	RTC_RIS_EV1_S 1U

#define	RTC_RIS_EV1_CLR 0x00000000U

#define	RTC_RIS_EV1_SET 0x00000002U

#define	RTC_MIS_EV0 0x00000001U

#define	RTC_MIS_EV0_M 0x00000001U

#define	RTC_MIS_EV0_S 0U

#define	RTC_MIS_EV0_CLR 0x00000000U

#define	RTC_MIS_EV0_SET 0x00000001U

#define	RTC_MIS_EV1 0x00000002U

#define	RTC_MIS_EV1_M 0x00000002U

#define	RTC_MIS_EV1_S 1U

#define	RTC_MIS_EV1_CLR 0x00000000U

#define	RTC_MIS_EV1_SET 0x00000002U

#define	RTC_ISET_EV0 0x00000001U

#define	RTC_ISET_EV0_M 0x00000001U

#define	RTC_ISET_EV0_S 0U

#define	RTC_ISET_EV0_NO_EFFECT 0x00000000U

#define	RTC_ISET_EV0_SET 0x00000001U

#define	RTC_ISET_EV1 0x00000002U

#define	RTC_ISET_EV1_M 0x00000002U

#define	RTC_ISET_EV1_S 1U

#define	RTC_ISET_EV1_NO_EFFECT 0x00000000U

#define	RTC_ISET_EV1_SET 0x00000002U

#define	RTC_ICLR_EV0 0x00000001U

#define	RTC_ICLR_EV0_M 0x00000001U

#define	RTC_ICLR_EV0_S 0U

#define	RTC_ICLR_EV0_NO_EFF 0x00000000U

#define	RTC_ICLR_EV0_CLR 0x00000001U

#define	RTC_ICLR_EV1 0x00000002U

#define	RTC_ICLR_EV1_M 0x00000002U

#define	RTC_ICLR_EV1_S 1U

#define	RTC_ICLR_EV1_NO_EFF 0x00000000U

#define	RTC_ICLR_EV1_CLR 0x00000002U

#define	RTC_IMSET_EV0 0x00000001U

#define	RTC_IMSET_EV0_M 0x00000001U

#define	RTC_IMSET_EV0_S 0U

#define	RTC_IMSET_EV0_NO_EFF 0x00000000U

#define	RTC_IMSET_EV0_SET 0x00000001U

#define	RTC_IMSET_EV1 0x00000002U

#define	RTC_IMSET_EV1_M 0x00000002U

#define	RTC_IMSET_EV1_S 1U

#define	RTC_IMSET_EV1_NO_EFF 0x00000000U

#define	RTC_IMSET_EV1_SET 0x00000002U

#define	RTC_IMCLR_EV0 0x00000001U

#define	RTC_IMCLR_EV0_M 0x00000001U

#define	RTC_IMCLR_EV0_S 0U

#define	RTC_IMCLR_EV0_NO_EFF 0x00000000U

#define	RTC_IMCLR_EV0_CLR 0x00000001U

#define	RTC_IMCLR_EV1 0x00000002U

#define	RTC_IMCLR_EV1_M 0x00000002U

#define	RTC_IMCLR_EV1_S 1U

#define	RTC_IMCLR_EV1_NO_EFF 0x00000000U

#define	RTC_IMCLR_EV1_CLR 0x00000002U

#define	RTC_EMU_HALT 0x00000001U

#define	RTC_EMU_HALT_M 0x00000001U

#define	RTC_EMU_HALT_S 0U

#define	RTC_EMU_HALT_STOP 0x00000001U

#define	RTC_EMU_HALT_RUN 0x00000000U

#define	RTC_DTB_SEL_W 4U

#define	RTC_DTB_SEL_M 0x0000000FU

#define	RTC_DTB_SEL_S 0U

#define	RTC_DTB_SEL_DIS 0x00000000U

Macro Definition Documentation

§ RTC_O_DESC

#define RTC_O_DESC 0x00000000U

§ RTC_O_CTL

#define RTC_O_CTL 0x00000004U

§ RTC_O_ARMSET

#define RTC_O_ARMSET 0x00000008U

§ RTC_O_ARMCLR

#define RTC_O_ARMCLR 0x0000000CU

§ RTC_O_TIME250N

#define RTC_O_TIME250N 0x00000010U

§ RTC_O_TIME1U

#define RTC_O_TIME1U 0x00000014U

§ RTC_O_TIME8U

#define RTC_O_TIME8U 0x00000018U

§ RTC_O_TIME524M

#define RTC_O_TIME524M 0x0000001CU

§ RTC_O_CH0CC250N

#define RTC_O_CH0CC250N 0x00000020U

§ RTC_O_CH0CC1U

#define RTC_O_CH0CC1U 0x00000024U

§ RTC_O_CH0CC8U

#define RTC_O_CH0CC8U 0x00000028U

§ RTC_O_CH1CC8U

#define RTC_O_CH1CC8U 0x00000038U

§ RTC_O_CH1CFG

#define RTC_O_CH1CFG 0x0000003CU

§ RTC_O_IMASK

#define RTC_O_IMASK 0x00000044U

§ RTC_O_RIS

#define RTC_O_RIS 0x00000048U

§ RTC_O_MIS

#define RTC_O_MIS 0x0000004CU

§ RTC_O_ISET

#define RTC_O_ISET 0x00000050U

§ RTC_O_ICLR

#define RTC_O_ICLR 0x00000054U

§ RTC_O_IMSET

#define RTC_O_IMSET 0x00000058U

§ RTC_O_IMCLR

#define RTC_O_IMCLR 0x0000005CU

§ RTC_O_EMU

#define RTC_O_EMU 0x00000060U

§ RTC_O_DTB

#define RTC_O_DTB 0x00000064U

§ RTC_O_DTIME

#define RTC_O_DTIME 0x00000068U

§ RTC_DESC_MINREV_W

#define RTC_DESC_MINREV_W 4U

§ RTC_DESC_MINREV_M

#define RTC_DESC_MINREV_M 0x0000000FU

§ RTC_DESC_MINREV_S

#define RTC_DESC_MINREV_S 0U

§ RTC_DESC_MAJREV_W

#define RTC_DESC_MAJREV_W 4U

§ RTC_DESC_MAJREV_M

#define RTC_DESC_MAJREV_M 0x000000F0U

§ RTC_DESC_MAJREV_S

#define RTC_DESC_MAJREV_S 4U

§ RTC_DESC_INSTIDX_W

#define RTC_DESC_INSTIDX_W 4U

§ RTC_DESC_INSTIDX_M

#define RTC_DESC_INSTIDX_M 0x00000F00U

§ RTC_DESC_INSTIDX_S

#define RTC_DESC_INSTIDX_S 8U

§ RTC_DESC_STDIPOFF_W

#define RTC_DESC_STDIPOFF_W 4U

§ RTC_DESC_STDIPOFF_M

#define RTC_DESC_STDIPOFF_M 0x0000F000U

§ RTC_DESC_STDIPOFF_S

#define RTC_DESC_STDIPOFF_S 12U

§ RTC_DESC_MODID_W

#define RTC_DESC_MODID_W 16U

§ RTC_DESC_MODID_M

#define RTC_DESC_MODID_M 0xFFFF0000U

§ RTC_DESC_MODID_S

#define RTC_DESC_MODID_S 16U

§ RTC_CTL_RST

#define RTC_CTL_RST 0x00000001U

§ RTC_CTL_RST_M

#define RTC_CTL_RST_M 0x00000001U

§ RTC_CTL_RST_S

#define RTC_CTL_RST_S 0U

§ RTC_CTL_RST_NOEFF

#define RTC_CTL_RST_NOEFF 0x00000000U

§ RTC_CTL_RST_CLR

#define RTC_CTL_RST_CLR 0x00000001U

§ RTC_ARMSET_CH0

#define RTC_ARMSET_CH0 0x00000001U

§ RTC_ARMSET_CH0_M

#define RTC_ARMSET_CH0_M 0x00000001U

§ RTC_ARMSET_CH0_S

#define RTC_ARMSET_CH0_S 0U

§ RTC_ARMSET_CH0_NOEFF

#define RTC_ARMSET_CH0_NOEFF 0x00000000U

§ RTC_ARMSET_CH0_SET

#define RTC_ARMSET_CH0_SET 0x00000001U

§ RTC_ARMSET_CH1

#define RTC_ARMSET_CH1 0x00000002U

§ RTC_ARMSET_CH1_M

#define RTC_ARMSET_CH1_M 0x00000002U

§ RTC_ARMSET_CH1_S

#define RTC_ARMSET_CH1_S 1U

§ RTC_ARMSET_CH1_NOEFF

#define RTC_ARMSET_CH1_NOEFF 0x00000000U

§ RTC_ARMSET_CH1_SET

#define RTC_ARMSET_CH1_SET 0x00000002U

§ RTC_ARMCLR_CH0

#define RTC_ARMCLR_CH0 0x00000001U

§ RTC_ARMCLR_CH0_M

#define RTC_ARMCLR_CH0_M 0x00000001U

§ RTC_ARMCLR_CH0_S

#define RTC_ARMCLR_CH0_S 0U

§ RTC_ARMCLR_CH0_NOEFF

#define RTC_ARMCLR_CH0_NOEFF 0x00000000U

§ RTC_ARMCLR_CH0_CLR

#define RTC_ARMCLR_CH0_CLR 0x00000001U

§ RTC_ARMCLR_CH1

#define RTC_ARMCLR_CH1 0x00000002U

§ RTC_ARMCLR_CH1_M

#define RTC_ARMCLR_CH1_M 0x00000002U

§ RTC_ARMCLR_CH1_S

#define RTC_ARMCLR_CH1_S 1U

§ RTC_ARMCLR_CH1_NOEFF

#define RTC_ARMCLR_CH1_NOEFF 0x00000000U

§ RTC_ARMCLR_CH1_CLR

#define RTC_ARMCLR_CH1_CLR 0x00000002U

§ RTC_TIME250N_VAL_W

#define RTC_TIME250N_VAL_W 32U

§ RTC_TIME250N_VAL_M

#define RTC_TIME250N_VAL_M 0xFFFFFFFFU

§ RTC_TIME250N_VAL_S

#define RTC_TIME250N_VAL_S 0U

§ RTC_TIME1U_VAL_W

#define RTC_TIME1U_VAL_W 32U

§ RTC_TIME1U_VAL_M

#define RTC_TIME1U_VAL_M 0xFFFFFFFFU

§ RTC_TIME1U_VAL_S

#define RTC_TIME1U_VAL_S 0U

§ RTC_TIME8U_VAL_W

#define RTC_TIME8U_VAL_W 32U

§ RTC_TIME8U_VAL_M

#define RTC_TIME8U_VAL_M 0xFFFFFFFFU

§ RTC_TIME8U_VAL_S

#define RTC_TIME8U_VAL_S 0U

§ RTC_TIME524M_VAL_W

#define RTC_TIME524M_VAL_W 32U

§ RTC_TIME524M_VAL_M

#define RTC_TIME524M_VAL_M 0xFFFFFFFFU

§ RTC_TIME524M_VAL_S

#define RTC_TIME524M_VAL_S 0U

§ RTC_CH0CC250N_VAL_W

#define RTC_CH0CC250N_VAL_W 32U

§ RTC_CH0CC250N_VAL_M

#define RTC_CH0CC250N_VAL_M 0xFFFFFFFFU

§ RTC_CH0CC250N_VAL_S

#define RTC_CH0CC250N_VAL_S 0U

§ RTC_CH0CC1U_VAL_W

#define RTC_CH0CC1U_VAL_W 32U

§ RTC_CH0CC1U_VAL_M

#define RTC_CH0CC1U_VAL_M 0xFFFFFFFFU

§ RTC_CH0CC1U_VAL_S

#define RTC_CH0CC1U_VAL_S 0U

§ RTC_CH0CC8U_VAL_W

#define RTC_CH0CC8U_VAL_W 32U

§ RTC_CH0CC8U_VAL_M

#define RTC_CH0CC8U_VAL_M 0xFFFFFFFFU

§ RTC_CH0CC8U_VAL_S

#define RTC_CH0CC8U_VAL_S 0U

§ RTC_CH1CC8U_VAL_W

#define RTC_CH1CC8U_VAL_W 21U

§ RTC_CH1CC8U_VAL_M

#define RTC_CH1CC8U_VAL_M 0x001FFFFFU

§ RTC_CH1CC8U_VAL_S

#define RTC_CH1CC8U_VAL_S 0U

§ RTC_CH1CFG_EDGE

#define RTC_CH1CFG_EDGE 0x00000001U

§ RTC_CH1CFG_EDGE_M

#define RTC_CH1CFG_EDGE_M 0x00000001U

§ RTC_CH1CFG_EDGE_S

#define RTC_CH1CFG_EDGE_S 0U

§ RTC_CH1CFG_EDGE_RISE

#define RTC_CH1CFG_EDGE_RISE 0x00000000U

§ RTC_CH1CFG_EDGE_FALL

#define RTC_CH1CFG_EDGE_FALL 0x00000001U

§ RTC_IMASK_EV0

#define RTC_IMASK_EV0 0x00000001U

§ RTC_IMASK_EV0_M

#define RTC_IMASK_EV0_M 0x00000001U

§ RTC_IMASK_EV0_S

#define RTC_IMASK_EV0_S 0U

§ RTC_IMASK_EV0_DIS

#define RTC_IMASK_EV0_DIS 0x00000000U

§ RTC_IMASK_EV0_EN

#define RTC_IMASK_EV0_EN 0x00000001U

§ RTC_IMASK_EV1

#define RTC_IMASK_EV1 0x00000002U

§ RTC_IMASK_EV1_M

#define RTC_IMASK_EV1_M 0x00000002U

§ RTC_IMASK_EV1_S

#define RTC_IMASK_EV1_S 1U

§ RTC_IMASK_EV1_DIS

#define RTC_IMASK_EV1_DIS 0x00000000U

§ RTC_IMASK_EV1_EN

#define RTC_IMASK_EV1_EN 0x00000002U

§ RTC_RIS_EV0

#define RTC_RIS_EV0 0x00000001U

§ RTC_RIS_EV0_M

#define RTC_RIS_EV0_M 0x00000001U

§ RTC_RIS_EV0_S

#define RTC_RIS_EV0_S 0U

§ RTC_RIS_EV0_CLR

#define RTC_RIS_EV0_CLR 0x00000000U

§ RTC_RIS_EV0_SET

#define RTC_RIS_EV0_SET 0x00000001U

§ RTC_RIS_EV1

#define RTC_RIS_EV1 0x00000002U

§ RTC_RIS_EV1_M

#define RTC_RIS_EV1_M 0x00000002U

§ RTC_RIS_EV1_S

#define RTC_RIS_EV1_S 1U

§ RTC_RIS_EV1_CLR

#define RTC_RIS_EV1_CLR 0x00000000U

§ RTC_RIS_EV1_SET

#define RTC_RIS_EV1_SET 0x00000002U

§ RTC_MIS_EV0

#define RTC_MIS_EV0 0x00000001U

§ RTC_MIS_EV0_M

#define RTC_MIS_EV0_M 0x00000001U

§ RTC_MIS_EV0_S

#define RTC_MIS_EV0_S 0U

§ RTC_MIS_EV0_CLR

#define RTC_MIS_EV0_CLR 0x00000000U

§ RTC_MIS_EV0_SET

#define RTC_MIS_EV0_SET 0x00000001U

§ RTC_MIS_EV1

#define RTC_MIS_EV1 0x00000002U

§ RTC_MIS_EV1_M

#define RTC_MIS_EV1_M 0x00000002U

§ RTC_MIS_EV1_S

#define RTC_MIS_EV1_S 1U

§ RTC_MIS_EV1_CLR

#define RTC_MIS_EV1_CLR 0x00000000U

§ RTC_MIS_EV1_SET

#define RTC_MIS_EV1_SET 0x00000002U

§ RTC_ISET_EV0

#define RTC_ISET_EV0 0x00000001U

§ RTC_ISET_EV0_M

#define RTC_ISET_EV0_M 0x00000001U

§ RTC_ISET_EV0_S

#define RTC_ISET_EV0_S 0U

§ RTC_ISET_EV0_NO_EFFECT

#define RTC_ISET_EV0_NO_EFFECT 0x00000000U

§ RTC_ISET_EV0_SET

#define RTC_ISET_EV0_SET 0x00000001U

§ RTC_ISET_EV1

#define RTC_ISET_EV1 0x00000002U

§ RTC_ISET_EV1_M

#define RTC_ISET_EV1_M 0x00000002U

§ RTC_ISET_EV1_S

#define RTC_ISET_EV1_S 1U

§ RTC_ISET_EV1_NO_EFFECT

#define RTC_ISET_EV1_NO_EFFECT 0x00000000U

§ RTC_ISET_EV1_SET

#define RTC_ISET_EV1_SET 0x00000002U

§ RTC_ICLR_EV0

#define RTC_ICLR_EV0 0x00000001U

§ RTC_ICLR_EV0_M

#define RTC_ICLR_EV0_M 0x00000001U

§ RTC_ICLR_EV0_S

#define RTC_ICLR_EV0_S 0U

§ RTC_ICLR_EV0_NO_EFF

#define RTC_ICLR_EV0_NO_EFF 0x00000000U

§ RTC_ICLR_EV0_CLR

#define RTC_ICLR_EV0_CLR 0x00000001U

§ RTC_ICLR_EV1

#define RTC_ICLR_EV1 0x00000002U

§ RTC_ICLR_EV1_M

#define RTC_ICLR_EV1_M 0x00000002U

§ RTC_ICLR_EV1_S

#define RTC_ICLR_EV1_S 1U

§ RTC_ICLR_EV1_NO_EFF

#define RTC_ICLR_EV1_NO_EFF 0x00000000U

§ RTC_ICLR_EV1_CLR

#define RTC_ICLR_EV1_CLR 0x00000002U

§ RTC_IMSET_EV0

#define RTC_IMSET_EV0 0x00000001U

§ RTC_IMSET_EV0_M

#define RTC_IMSET_EV0_M 0x00000001U

§ RTC_IMSET_EV0_S

#define RTC_IMSET_EV0_S 0U

§ RTC_IMSET_EV0_NO_EFF

#define RTC_IMSET_EV0_NO_EFF 0x00000000U

§ RTC_IMSET_EV0_SET

#define RTC_IMSET_EV0_SET 0x00000001U

§ RTC_IMSET_EV1

#define RTC_IMSET_EV1 0x00000002U

§ RTC_IMSET_EV1_M

#define RTC_IMSET_EV1_M 0x00000002U

§ RTC_IMSET_EV1_S

#define RTC_IMSET_EV1_S 1U

§ RTC_IMSET_EV1_NO_EFF

#define RTC_IMSET_EV1_NO_EFF 0x00000000U

§ RTC_IMSET_EV1_SET

#define RTC_IMSET_EV1_SET 0x00000002U

§ RTC_IMCLR_EV0

#define RTC_IMCLR_EV0 0x00000001U

§ RTC_IMCLR_EV0_M

#define RTC_IMCLR_EV0_M 0x00000001U

§ RTC_IMCLR_EV0_S

#define RTC_IMCLR_EV0_S 0U

§ RTC_IMCLR_EV0_NO_EFF

#define RTC_IMCLR_EV0_NO_EFF 0x00000000U

§ RTC_IMCLR_EV0_CLR

#define RTC_IMCLR_EV0_CLR 0x00000001U

§ RTC_IMCLR_EV1

#define RTC_IMCLR_EV1 0x00000002U

§ RTC_IMCLR_EV1_M

#define RTC_IMCLR_EV1_M 0x00000002U

§ RTC_IMCLR_EV1_S

#define RTC_IMCLR_EV1_S 1U

§ RTC_IMCLR_EV1_NO_EFF

#define RTC_IMCLR_EV1_NO_EFF 0x00000000U

§ RTC_IMCLR_EV1_CLR

#define RTC_IMCLR_EV1_CLR 0x00000002U

§ RTC_EMU_HALT

#define RTC_EMU_HALT 0x00000001U

§ RTC_EMU_HALT_M

#define RTC_EMU_HALT_M 0x00000001U

§ RTC_EMU_HALT_S

#define RTC_EMU_HALT_S 0U

§ RTC_EMU_HALT_STOP

#define RTC_EMU_HALT_STOP 0x00000001U

§ RTC_EMU_HALT_RUN

#define RTC_EMU_HALT_RUN 0x00000000U

§ RTC_DTB_SEL_W

#define RTC_DTB_SEL_W 4U

§ RTC_DTB_SEL_M

#define RTC_DTB_SEL_M 0x0000000FU

§ RTC_DTB_SEL_S

#define RTC_DTB_SEL_S 0U

§ RTC_DTB_SEL_DIS

#define RTC_DTB_SEL_DIS 0x00000000U

Macros