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CC35xxDriverLibrary
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Go to the source code of this file.
| #define PDM_O_DESC 0x00000000U |
| #define PDM_O_DESCEX 0x00000004U |
| #define PDM_O_IMASK 0x00000044U |
| #define PDM_O_RIS 0x00000048U |
| #define PDM_O_MIS 0x0000004CU |
| #define PDM_O_ISET 0x00000050U |
| #define PDM_O_ICLR 0x00000054U |
| #define PDM_O_EMU 0x00000060U |
| #define PDM_O_CTL 0x00000100U |
| #define PDM_O_ICLKCTL 0x00000104U |
| #define PDM_O_FIFOCTL1 0x00000108U |
| #define PDM_O_FIFODATA 0x0000010CU |
| #define PDM_O_CCTL 0x00000110U |
| #define PDM_O_OSR 0x00000114U |
| #define PDM_O_STA 0x00000118U |
| #define PDM_O_FIFOCTL2 0x00000120U |
| #define PDM_O_FIFOSR 0x00000124U |
| #define PDM_O_AVGVAL0 0x00000200U |
| #define PDM_O_PKVAL0 0x00000204U |
| #define PDM_O_AVGPOW0 0x00000208U |
| #define PDM_O_AVGVAL1 0x0000020CU |
| #define PDM_O_PKVAL1 0x00000210U |
| #define PDM_O_AVGPOW1 0x00000214U |
| #define PDM_O_STPCTL 0x00000300U |
| #define PDM_O_STPXCAPT 0x00000304U |
| #define PDM_O_STPXPER 0x00000308U |
| #define PDM_O_STPSCAPT 0x0000030CU |
| #define PDM_O_STPSPER 0x00000310U |
| #define PDM_O_STPINTRG 0x00000314U |
| #define PDM_O_STPSSET 0x00000318U |
| #define PDM_O_STPSADD 0x0000031CU |
| #define PDM_O_STPXMIN 0x00000320U |
| #define PDM_O_STPWCNT 0x00000324U |
| #define PDM_O_STPXCNT 0x00000328U |
| #define PDM_O_STPSTAT 0x0000032CU |
| #define PDM_O_CLKCFG 0x00001000U |
| #define PDM_O_ADFSCTL1 0x00001004U |
| #define PDM_O_ADFSCTL2 0x00001008U |
| #define PDM_DESC_MINREV_W 4U |
| #define PDM_DESC_MINREV_M 0x0000000FU |
| #define PDM_DESC_MINREV_S 0U |
| #define PDM_DESC_MINREV_MINIMUM 0x00000000U |
| #define PDM_DESC_MINREV_MAXIMUM 0x0000000FU |
| #define PDM_DESC_MAJREV_W 4U |
| #define PDM_DESC_MAJREV_M 0x000000F0U |
| #define PDM_DESC_MAJREV_S 4U |
| #define PDM_DESC_MAJREV_MINIMUM 0x00000000U |
| #define PDM_DESC_MAJREV_MAXIMUM 0x000000F0U |
| #define PDM_DESC_INSTIDX_W 4U |
| #define PDM_DESC_INSTIDX_M 0x00000F00U |
| #define PDM_DESC_INSTIDX_S 8U |
| #define PDM_DESC_INSTIDX_MINIMUM 0x00000000U |
| #define PDM_DESC_INSTIDX_MAXIMUM 0x00000F00U |
| #define PDM_DESC_STDIPOFF_W 4U |
| #define PDM_DESC_STDIPOFF_M 0x0000F000U |
| #define PDM_DESC_STDIPOFF_S 12U |
| #define PDM_DESC_STDIPOFF_MINIMUM 0x00000000U |
| #define PDM_DESC_STDIPOFF_MAXIMUM 0x0000F000U |
| #define PDM_DESC_MODID_W 16U |
| #define PDM_DESC_MODID_M 0xFFFF0000U |
| #define PDM_DESC_MODID_S 16U |
| #define PDM_DESC_MODID_MINIMUM 0x00000000U |
| #define PDM_DESC_MODID_MAXIMUM 0xFFFF0000U |
| #define PDM_DESCEX_NUMCHAN_W 3U |
| #define PDM_DESCEX_NUMCHAN_M 0x00000007U |
| #define PDM_DESCEX_NUMCHAN_S 0U |
| #define PDM_DESCEX_NUMCHAN_MINIMUM 0x00000000U |
| #define PDM_DESCEX_NUMCHAN_MAXIMUM 0x00000007U |
| #define PDM_IMASK_PDMDATA 0x00000001U |
| #define PDM_IMASK_PDMDATA_M 0x00000001U |
| #define PDM_IMASK_PDMDATA_S 0U |
| #define PDM_IMASK_PDMDATA_CLR 0x00000000U |
| #define PDM_IMASK_PDMDATA_SET 0x00000001U |
| #define PDM_IMASK_OVFL 0x00000040U |
| #define PDM_IMASK_OVFL_M 0x00000040U |
| #define PDM_IMASK_OVFL_S 6U |
| #define PDM_IMASK_OVFL_CLR 0x00000000U |
| #define PDM_IMASK_OVFL_SET 0x00000040U |
| #define PDM_IMASK_UNFL 0x00000080U |
| #define PDM_IMASK_UNFL_M 0x00000080U |
| #define PDM_IMASK_UNFL_S 7U |
| #define PDM_IMASK_UNFL_CLR 0x00000000U |
| #define PDM_IMASK_UNFL_SET 0x00000080U |
| #define PDM_IMASK_STPTRIG 0x00000100U |
| #define PDM_IMASK_STPTRIG_M 0x00000100U |
| #define PDM_IMASK_STPTRIG_S 8U |
| #define PDM_IMASK_STPTRIG_SET 0x00000100U |
| #define PDM_IMASK_STPTRIG_CLR 0x00000000U |
| #define PDM_IMASK_DMADONE 0x00000200U |
| #define PDM_IMASK_DMADONE_M 0x00000200U |
| #define PDM_IMASK_DMADONE_S 9U |
| #define PDM_IMASK_DMADONE_CLR 0x00000000U |
| #define PDM_IMASK_DMADONE_SET 0x00000200U |
| #define PDM_RIS_PDMDATA 0x00000001U |
| #define PDM_RIS_PDMDATA_M 0x00000001U |
| #define PDM_RIS_PDMDATA_S 0U |
| #define PDM_RIS_PDMDATA_CLR 0x00000000U |
| #define PDM_RIS_PDMDATA_SET 0x00000001U |
| #define PDM_RIS_OVFL 0x00000040U |
| #define PDM_RIS_OVFL_M 0x00000040U |
| #define PDM_RIS_OVFL_S 6U |
| #define PDM_RIS_OVFL_CLR 0x00000000U |
| #define PDM_RIS_OVFL_SET 0x00000040U |
| #define PDM_RIS_UNFL 0x00000080U |
| #define PDM_RIS_UNFL_M 0x00000080U |
| #define PDM_RIS_UNFL_S 7U |
| #define PDM_RIS_UNFL_CLR 0x00000000U |
| #define PDM_RIS_UNFL_SET 0x00000080U |
| #define PDM_RIS_STPTRIG 0x00000100U |
| #define PDM_RIS_STPTRIG_M 0x00000100U |
| #define PDM_RIS_STPTRIG_S 8U |
| #define PDM_RIS_STPTRIG_SET 0x00000100U |
| #define PDM_RIS_STPTRIG_CLR 0x00000000U |
| #define PDM_RIS_DMADONE 0x00000200U |
| #define PDM_RIS_DMADONE_M 0x00000200U |
| #define PDM_RIS_DMADONE_S 9U |
| #define PDM_RIS_DMADONE_CLR 0x00000000U |
| #define PDM_RIS_DMADONE_SET 0x00000200U |
| #define PDM_MIS_PDMDATA 0x00000001U |
| #define PDM_MIS_PDMDATA_M 0x00000001U |
| #define PDM_MIS_PDMDATA_S 0U |
| #define PDM_MIS_PDMDATA_CLR 0x00000000U |
| #define PDM_MIS_PDMDATA_SET 0x00000001U |
| #define PDM_MIS_OVFL 0x00000040U |
| #define PDM_MIS_OVFL_M 0x00000040U |
| #define PDM_MIS_OVFL_S 6U |
| #define PDM_MIS_OVFL_CLR 0x00000000U |
| #define PDM_MIS_OVFL_SET 0x00000040U |
| #define PDM_MIS_UNFL 0x00000080U |
| #define PDM_MIS_UNFL_M 0x00000080U |
| #define PDM_MIS_UNFL_S 7U |
| #define PDM_MIS_UNFL_CLR 0x00000000U |
| #define PDM_MIS_UNFL_SET 0x00000080U |
| #define PDM_MIS_STPTRIG 0x00000100U |
| #define PDM_MIS_STPTRIG_M 0x00000100U |
| #define PDM_MIS_STPTRIG_S 8U |
| #define PDM_MIS_STPTRIG_SET 0x00000100U |
| #define PDM_MIS_STPTRIG_CLR 0x00000000U |
| #define PDM_MIS_DMADONE 0x00000200U |
| #define PDM_MIS_DMADONE_M 0x00000200U |
| #define PDM_MIS_DMADONE_S 9U |
| #define PDM_MIS_DMADONE_CLR 0x00000000U |
| #define PDM_MIS_DMADONE_SET 0x00000200U |
| #define PDM_ISET_PDMDATA 0x00000001U |
| #define PDM_ISET_PDMDATA_M 0x00000001U |
| #define PDM_ISET_PDMDATA_S 0U |
| #define PDM_ISET_PDMDATA_NO_EFFECT 0x00000000U |
| #define PDM_ISET_PDMDATA_SET 0x00000001U |
| #define PDM_ISET_OVFL 0x00000040U |
| #define PDM_ISET_OVFL_M 0x00000040U |
| #define PDM_ISET_OVFL_S 6U |
| #define PDM_ISET_OVFL_NO_EFFECT 0x00000000U |
| #define PDM_ISET_OVFL_SET 0x00000040U |
| #define PDM_ISET_UNFL 0x00000080U |
| #define PDM_ISET_UNFL_M 0x00000080U |
| #define PDM_ISET_UNFL_S 7U |
| #define PDM_ISET_UNFL_NO_EFFECT 0x00000000U |
| #define PDM_ISET_UNFL_SET 0x00000080U |
| #define PDM_ISET_STPTRIG 0x00000100U |
| #define PDM_ISET_STPTRIG_M 0x00000100U |
| #define PDM_ISET_STPTRIG_S 8U |
| #define PDM_ISET_STPTRIG_SET 0x00000100U |
| #define PDM_ISET_STPTRIG_NO_EFFECT 0x00000000U |
| #define PDM_ISET_DMADONE 0x00000200U |
| #define PDM_ISET_DMADONE_M 0x00000200U |
| #define PDM_ISET_DMADONE_S 9U |
| #define PDM_ISET_DMADONE_NO_EFFECT 0x00000000U |
| #define PDM_ISET_DMADONE_SET 0x00000200U |
| #define PDM_ICLR_PDMDATA 0x00000001U |
| #define PDM_ICLR_PDMDATA_M 0x00000001U |
| #define PDM_ICLR_PDMDATA_S 0U |
| #define PDM_ICLR_PDMDATA_NO_EFFECT 0x00000000U |
| #define PDM_ICLR_PDMDATA_CLR 0x00000001U |
| #define PDM_ICLR_OVFL 0x00000040U |
| #define PDM_ICLR_OVFL_M 0x00000040U |
| #define PDM_ICLR_OVFL_S 6U |
| #define PDM_ICLR_OVFL_NO_EFFECT 0x00000000U |
| #define PDM_ICLR_OVFL_CLR 0x00000040U |
| #define PDM_ICLR_UNFL 0x00000080U |
| #define PDM_ICLR_UNFL_M 0x00000080U |
| #define PDM_ICLR_UNFL_S 7U |
| #define PDM_ICLR_UNFL_NO_EFFECT 0x00000000U |
| #define PDM_ICLR_UNFL_CLR 0x00000080U |
| #define PDM_ICLR_STPTRIG 0x00000100U |
| #define PDM_ICLR_STPTRIG_M 0x00000100U |
| #define PDM_ICLR_STPTRIG_S 8U |
| #define PDM_ICLR_STPTRIG_CLR 0x00000100U |
| #define PDM_ICLR_STPTRIG_NO_EFFECT 0x00000000U |
| #define PDM_ICLR_DMADONE 0x00000200U |
| #define PDM_ICLR_DMADONE_M 0x00000200U |
| #define PDM_ICLR_DMADONE_S 9U |
| #define PDM_ICLR_DMADONE_NO_EFFECT 0x00000000U |
| #define PDM_ICLR_DMADONE_CLR 0x00000200U |
| #define PDM_EMU_HALT 0x00000001U |
| #define PDM_EMU_HALT_M 0x00000001U |
| #define PDM_EMU_HALT_S 0U |
| #define PDM_EMU_HALT_STOP 0x00000001U |
| #define PDM_EMU_HALT_RUN 0x00000000U |
| #define PDM_CTL_ENPDM 0x00000001U |
| #define PDM_CTL_ENPDM_M 0x00000001U |
| #define PDM_CTL_ENPDM_S 0U |
| #define PDM_CTL_ENPDM_DIS 0x00000000U |
| #define PDM_CTL_ENPDM_EN 0x00000001U |
| #define PDM_ICLKCTL_IDIV_W 10U |
| #define PDM_ICLKCTL_IDIV_M 0x000003FFU |
| #define PDM_ICLKCTL_IDIV_S 0U |
| #define PDM_ICLKCTL_IDIV_MIN 0x00000000U |
| #define PDM_ICLKCTL_IDIV_MAX 0x000003FFU |
| #define PDM_ICLKCTL_BCLKEN 0x00010000U |
| #define PDM_ICLKCTL_BCLKEN_M 0x00010000U |
| #define PDM_ICLKCTL_BCLKEN_S 16U |
| #define PDM_ICLKCTL_BCLKEN_DIS 0x00000000U |
| #define PDM_ICLKCTL_BCLKEN_EN 0x00010000U |
| #define PDM_ICLKCTL_RESERED17_W 15U |
| #define PDM_ICLKCTL_RESERED17_M 0xFFFE0000U |
| #define PDM_ICLKCTL_RESERED17_S 17U |
| #define PDM_FIFOCTL1_ENFIFO0 0x00000001U |
| #define PDM_FIFOCTL1_ENFIFO0_M 0x00000001U |
| #define PDM_FIFOCTL1_ENFIFO0_S 0U |
| #define PDM_FIFOCTL1_ENFIFO0_DIS 0x00000000U |
| #define PDM_FIFOCTL1_ENFIFO0_EN 0x00000001U |
| #define PDM_FIFOCTL1_ENFIFO1 0x00000002U |
| #define PDM_FIFOCTL1_ENFIFO1_M 0x00000002U |
| #define PDM_FIFOCTL1_ENFIFO1_S 1U |
| #define PDM_FIFOCTL1_ENFIFO1_DIS 0x00000000U |
| #define PDM_FIFOCTL1_ENFIFO1_EN 0x00000002U |
| #define PDM_FIFODATA_VALUE_W 32U |
| #define PDM_FIFODATA_VALUE_M 0xFFFFFFFFU |
| #define PDM_FIFODATA_VALUE_S 0U |
| #define PDM_FIFODATA_VALUE_MINIMUM 0x00000000U |
| #define PDM_FIFODATA_VALUE_MAXIMUM 0xFFFFFFFFU |
| #define PDM_CCTL_CHEN_W 3U |
| #define PDM_CCTL_CHEN_M 0x00000007U |
| #define PDM_CCTL_CHEN_S 0U |
| #define PDM_CCTL_CHEN_CH0ENABLE 0x00000001U |
| #define PDM_CCTL_CHEN_CH0_1ENABLE 0x00000002U |
| #define PDM_CCTL_CHEN_MANC 0x00000004U |
| #define PDM_CCTL_CHEN_DISABLE 0x00000000U |
| #define PDM_CCTL_DFS_W 2U |
| #define PDM_CCTL_DFS_M 0x00000300U |
| #define PDM_CCTL_DFS_S 8U |
| #define PDM_CCTL_DFS_SINC1 0x00000000U |
| #define PDM_CCTL_DFS_SINC2 0x00000100U |
| #define PDM_CCTL_DFS_SINC3 0x00000200U |
| #define PDM_CCTL_DFS_SINC4 0x00000300U |
| #define PDM_CCTL_ALIGN 0x00000400U |
| #define PDM_CCTL_ALIGN_M 0x00000400U |
| #define PDM_CCTL_ALIGN_S 10U |
| #define PDM_CCTL_ALIGN_RIGHT 0x00000000U |
| #define PDM_CCTL_ALIGN_LEFT 0x00000400U |
| #define PDM_CCTL_DATAFMT 0x00000800U |
| #define PDM_CCTL_DATAFMT_M 0x00000800U |
| #define PDM_CCTL_DATAFMT_S 11U |
| #define PDM_CCTL_DATAFMT_OFFSET 0x00000000U |
| #define PDM_CCTL_DATAFMT_TWOSCOMP 0x00000800U |
| #define PDM_CCTL_ENPKCH0 0x00010000U |
| #define PDM_CCTL_ENPKCH0_M 0x00010000U |
| #define PDM_CCTL_ENPKCH0_S 16U |
| #define PDM_CCTL_ENPKCH0_EN 0x00010000U |
| #define PDM_CCTL_ENPKCH0_DIS 0x00000000U |
| #define PDM_CCTL_ENPKCH1 0x00020000U |
| #define PDM_CCTL_ENPKCH1_M 0x00020000U |
| #define PDM_CCTL_ENPKCH1_S 17U |
| #define PDM_CCTL_ENPKCH1_EN 0x00020000U |
| #define PDM_CCTL_ENPKCH1_DIS 0x00000000U |
| #define PDM_CCTL_ENPOWCH0 0x00040000U |
| #define PDM_CCTL_ENPOWCH0_M 0x00040000U |
| #define PDM_CCTL_ENPOWCH0_S 18U |
| #define PDM_CCTL_ENPOWCH0_EN 0x00040000U |
| #define PDM_CCTL_ENPOWCH0_DIS 0x00000000U |
| #define PDM_CCTL_ENPOWCH1 0x00080000U |
| #define PDM_CCTL_ENPOWCH1_M 0x00080000U |
| #define PDM_CCTL_ENPOWCH1_S 19U |
| #define PDM_CCTL_ENPOWCH1_EN 0x00080000U |
| #define PDM_CCTL_ENPOWCH1_DIS 0x00000000U |
| #define PDM_CCTL_SELSCALE_W 3U |
| #define PDM_CCTL_SELSCALE_M 0x00700000U |
| #define PDM_CCTL_SELSCALE_S 20U |
| #define PDM_CCTL_SELSCALE_VAL0 0x00000000U |
| #define PDM_CCTL_SELSCALE_VAL1 0x00100000U |
| #define PDM_CCTL_SELSCALE_VAL2 0x00200000U |
| #define PDM_CCTL_SELSCALE_VAL3 0x00300000U |
| #define PDM_CCTL_SELSCALE_VAL4 0x00400000U |
| #define PDM_CCTL_SELSCALE_VAL5 0x00500000U |
| #define PDM_CCTL_SELSCALE_VAL6 0x00600000U |
| #define PDM_CCTL_SELSCALE_VAL7 0x00700000U |
| #define PDM_CCTL_CH0CLKEG 0x01000000U |
| #define PDM_CCTL_CH0CLKEG_M 0x01000000U |
| #define PDM_CCTL_CH0CLKEG_S 24U |
| #define PDM_CCTL_CH0CLKEG_RISING 0x00000000U |
| #define PDM_CCTL_CH0CLKEG_FALLING 0x01000000U |
| #define PDM_CCTL_CH0IPSEL_W 2U |
| #define PDM_CCTL_CH0IPSEL_M 0x06000000U |
| #define PDM_CCTL_CH0IPSEL_S 25U |
| #define PDM_CCTL_CH0IPSEL_DATA0 0x00000000U |
| #define PDM_CCTL_CH0IPSEL_DATA1 0x02000000U |
| #define PDM_CCTL_CH0IPSEL_SDM 0x04000000U |
| #define PDM_CCTL_CH0IPSEL_RESERVED 0x06000000U |
| #define PDM_CCTL_CH1CLKEG 0x10000000U |
| #define PDM_CCTL_CH1CLKEG_M 0x10000000U |
| #define PDM_CCTL_CH1CLKEG_S 28U |
| #define PDM_CCTL_CH1CLKEG_RISING 0x00000000U |
| #define PDM_CCTL_CH1CLKEG_FALLING 0x10000000U |
| #define PDM_CCTL_CH1IPSEL_W 2U |
| #define PDM_CCTL_CH1IPSEL_M 0x60000000U |
| #define PDM_CCTL_CH1IPSEL_S 29U |
| #define PDM_CCTL_CH1IPSEL_DATA0 0x00000000U |
| #define PDM_CCTL_CH1IPSEL_DATA1 0x20000000U |
| #define PDM_CCTL_CH1IPSEL_SDM 0x40000000U |
| #define PDM_CCTL_CH1IPSEL_RESERVED 0x60000000U |
| #define PDM_OSR_VALUE_W 8U |
| #define PDM_OSR_VALUE_M 0x000000FFU |
| #define PDM_OSR_VALUE_S 0U |
| #define PDM_OSR_VALUE_MINIMUM 0x00000001U |
| #define PDM_OSR_VALUE_MAXIMUM 0x000000FFU |
| #define PDM_STA_AGCRDY 0x00000001U |
| #define PDM_STA_AGCRDY_M 0x00000001U |
| #define PDM_STA_AGCRDY_S 0U |
| #define PDM_STA_AGCRDY_NOT_RDY 0x00000000U |
| #define PDM_STA_AGCRDY_RDY 0x00000001U |
| #define PDM_STA_MANCLK 0x00020000U |
| #define PDM_STA_MANCLK_M 0x00020000U |
| #define PDM_STA_MANCLK_S 17U |
| #define PDM_STA_MANCLK_UNLOCKED 0x00000000U |
| #define PDM_STA_MANCLK_LOCKED 0x00020000U |
| #define PDM_FIFOCTL2_TRGLVL_W 4U |
| #define PDM_FIFOCTL2_TRGLVL_M 0x0000000FU |
| #define PDM_FIFOCTL2_TRGLVL_S 0U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_1 0x00000000U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_2 0x00000001U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_3 0x00000002U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_4 0x00000003U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_5 0x00000004U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_6 0x00000005U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_7 0x00000006U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_8 0x00000007U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_9 0x00000008U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_10 0x00000009U |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_11 0x0000000AU |
| #define PDM_FIFOCTL2_TRGLVL_LEVEL_12 0x0000000BU |
| #define PDM_FIFOCTL2_FIFOFLSH 0x00000080U |
| #define PDM_FIFOCTL2_FIFOFLSH_M 0x00000080U |
| #define PDM_FIFOCTL2_FIFOFLSH_S 7U |
| #define PDM_FIFOCTL2_FIFOFLSH_NOFLUSH 0x00000000U |
| #define PDM_FIFOCTL2_FIFOFLSH_FLUSH 0x00000080U |
| #define PDM_FIFOSR_CH0FCNT_W 4U |
| #define PDM_FIFOSR_CH0FCNT_M 0x0000000FU |
| #define PDM_FIFOSR_CH0FCNT_S 0U |
| #define PDM_FIFOSR_CH0FCNT_MINIMUM 0x00000000U |
| #define PDM_FIFOSR_CH0FCNT_MAXIMUM 0x0000000FU |
| #define PDM_FIFOSR_CH0FEMP 0x00000040U |
| #define PDM_FIFOSR_CH0FEMP_M 0x00000040U |
| #define PDM_FIFOSR_CH0FEMP_S 6U |
| #define PDM_FIFOSR_CH0FEMP_CLEARED 0x00000000U |
| #define PDM_FIFOSR_CH0FEMP_SET 0x00000040U |
| #define PDM_FIFOSR_CH0FFULL 0x00000080U |
| #define PDM_FIFOSR_CH0FFULL_M 0x00000080U |
| #define PDM_FIFOSR_CH0FFULL_S 7U |
| #define PDM_FIFOSR_CH0FFULL_CLEARED 0x00000000U |
| #define PDM_FIFOSR_CH0FFULL_SET 0x00000080U |
| #define PDM_FIFOSR_CH1FCNT_W 4U |
| #define PDM_FIFOSR_CH1FCNT_M 0x00000F00U |
| #define PDM_FIFOSR_CH1FCNT_S 8U |
| #define PDM_FIFOSR_CH1FCNT_MINIMUM 0x00000000U |
| #define PDM_FIFOSR_CH1FCNT_MAXIMUM 0x00000F00U |
| #define PDM_FIFOSR_CH1FEMP 0x00004000U |
| #define PDM_FIFOSR_CH1FEMP_M 0x00004000U |
| #define PDM_FIFOSR_CH1FEMP_S 14U |
| #define PDM_FIFOSR_CH1FEMP_CLEARED 0x00000000U |
| #define PDM_FIFOSR_CH1FEMP_SET 0x00004000U |
| #define PDM_FIFOSR_CH1FFULL 0x00008000U |
| #define PDM_FIFOSR_CH1FFULL_M 0x00008000U |
| #define PDM_FIFOSR_CH1FFULL_S 15U |
| #define PDM_FIFOSR_CH1FFULL_CLEARED 0x00000000U |
| #define PDM_FIFOSR_CH1FFULL_SET 0x00008000U |
| #define PDM_AVGVAL0_VALUE_W 32U |
| #define PDM_AVGVAL0_VALUE_M 0xFFFFFFFFU |
| #define PDM_AVGVAL0_VALUE_S 0U |
| #define PDM_AVGVAL0_VALUE_MINIMUM 0x00000000U |
| #define PDM_AVGVAL0_VALUE_MAXIMUM 0xFFFFFFFFU |
| #define PDM_PKVAL0_VALUE_W 24U |
| #define PDM_PKVAL0_VALUE_M 0x00FFFFFFU |
| #define PDM_PKVAL0_VALUE_S 0U |
| #define PDM_PKVAL0_VALUE_MINIMUM 0x00000000U |
| #define PDM_PKVAL0_VALUE_MAXIMUM 0x007FFFFFU |
| #define PDM_AVGPOW0_VALUE_W 32U |
| #define PDM_AVGPOW0_VALUE_M 0xFFFFFFFFU |
| #define PDM_AVGPOW0_VALUE_S 0U |
| #define PDM_AVGPOW0_VALUE_MINIMUM 0x00000000U |
| #define PDM_AVGPOW0_VALUE_MAXIMUM 0xFFFFFFFFU |
| #define PDM_AVGVAL1_VALUE_W 32U |
| #define PDM_AVGVAL1_VALUE_M 0xFFFFFFFFU |
| #define PDM_AVGVAL1_VALUE_S 0U |
| #define PDM_AVGVAL1_VALUE_MINIMUM 0x00000000U |
| #define PDM_AVGVAL1_VALUE_MAXIMUM 0xFFFFFFFFU |
| #define PDM_PKVAL1_VALUE_W 24U |
| #define PDM_PKVAL1_VALUE_M 0x00FFFFFFU |
| #define PDM_PKVAL1_VALUE_S 0U |
| #define PDM_PKVAL1_VALUE_MINIMUM 0x00000000U |
| #define PDM_PKVAL1_VALUE_MAXIMUM 0x007FFFFFU |
| #define PDM_AVGPOW1_VALUE_W 32U |
| #define PDM_AVGPOW1_VALUE_M 0xFFFFFFFFU |
| #define PDM_AVGPOW1_VALUE_S 0U |
| #define PDM_AVGPOW1_VALUE_MINIMUM 0x00000000U |
| #define PDM_AVGPOW1_VALUE_MAXIMUM 0xFFFFFFFFU |
| #define PDM_STPCTL_STPEN 0x00000001U |
| #define PDM_STPCTL_STPEN_M 0x00000001U |
| #define PDM_STPCTL_STPEN_S 0U |
| #define PDM_STPCTL_STPEN_DIS 0x00000000U |
| #define PDM_STPCTL_STPEN_EN 0x00000001U |
| #define PDM_STPXCAPT_CAPTVAL_W 16U |
| #define PDM_STPXCAPT_CAPTVAL_M 0x0000FFFFU |
| #define PDM_STPXCAPT_CAPTVAL_S 0U |
| #define PDM_STPXCAPT_CAPTVAL_MINIMUM 0x00000000U |
| #define PDM_STPXCAPT_CAPTVAL_MAXIMUM 0x0000FFFFU |
| #define PDM_STPXPER_VALUE_W 16U |
| #define PDM_STPXPER_VALUE_M 0x0000FFFFU |
| #define PDM_STPXPER_VALUE_S 0U |
| #define PDM_STPXPER_VALUE_MINIMUM 0x00000000U |
| #define PDM_STPXPER_VALUE_MAXIMUM 0x0000FFFFU |
| #define PDM_STPSCAPT_CAPTVAL_W 16U |
| #define PDM_STPSCAPT_CAPTVAL_M 0x0000FFFFU |
| #define PDM_STPSCAPT_CAPTVAL_S 0U |
| #define PDM_STPSCAPT_CAPTVAL_MINIMUM 0x00000000U |
| #define PDM_STPSCAPT_CAPTVAL_MAXIMUM 0x0000FFFFU |
| #define PDM_STPSPER_VALUE_W 16U |
| #define PDM_STPSPER_VALUE_M 0x0000FFFFU |
| #define PDM_STPSPER_VALUE_S 0U |
| #define PDM_STPSPER_VALUE_MINIMUM 0x00000000U |
| #define PDM_STPSPER_VALUE_MAXIMUM 0x0000FFFFU |
| #define PDM_STPINTRG_INSTRWCT_W 16U |
| #define PDM_STPINTRG_INSTRWCT_M 0x0000FFFFU |
| #define PDM_STPINTRG_INSTRWCT_S 0U |
| #define PDM_STPINTRG_INSTRWCT_MINIMUM 0x00000000U |
| #define PDM_STPINTRG_INSTRWCT_MAXIMUM 0x0000FFFFU |
| #define PDM_STPSSET_VALUE_W 16U |
| #define PDM_STPSSET_VALUE_M 0x0000FFFFU |
| #define PDM_STPSSET_VALUE_S 0U |
| #define PDM_STPSSET_VALUE_MINIMUM 0x00000000U |
| #define PDM_STPSSET_VALUE_MAXIMUM 0x0000FFFFU |
| #define PDM_STPSADD_VALINC_W 16U |
| #define PDM_STPSADD_VALINC_M 0x0000FFFFU |
| #define PDM_STPSADD_VALINC_S 0U |
| #define PDM_STPSADD_VALINC_MINIMUM 0x00000000U |
| #define PDM_STPSADD_VALINC_MAXIMUM 0x0000FFFFU |
| #define PDM_STPXMIN_VALUE_W 16U |
| #define PDM_STPXMIN_VALUE_M 0x0000FFFFU |
| #define PDM_STPXMIN_VALUE_S 0U |
| #define PDM_STPXMIN_VALUE_MINIMUM 0x00000000U |
| #define PDM_STPXMIN_VALUE_MAXIMUM 0x0000FFFFU |
| #define PDM_STPWCNT_CURRVAL_W 16U |
| #define PDM_STPWCNT_CURRVAL_M 0x0000FFFFU |
| #define PDM_STPWCNT_CURRVAL_S 0U |
| #define PDM_STPWCNT_CURRVAL_MINIMUM 0x00000000U |
| #define PDM_STPWCNT_CURRVAL_MAXIMUM 0x0000FFFFU |
| #define PDM_STPXCNT_CURRVAL_W 16U |
| #define PDM_STPXCNT_CURRVAL_M 0x0000FFFFU |
| #define PDM_STPXCNT_CURRVAL_S 0U |
| #define PDM_STPXCNT_CURRVAL_MINIMUM 0x00000000U |
| #define PDM_STPXCNT_CURRVAL_MAXIMUM 0x0000FFFFU |
| #define PDM_STPSTAT_INRDY 0x00000002U |
| #define PDM_STPSTAT_INRDY_M 0x00000002U |
| #define PDM_STPSTAT_INRDY_S 1U |
| #define PDM_STPSTAT_INRDY_CLR 0x00000000U |
| #define PDM_STPSTAT_INRDY_SET 0x00000002U |
| #define PDM_CLKCFG_CLKEN 0x00000001U |
| #define PDM_CLKCFG_CLKEN_M 0x00000001U |
| #define PDM_CLKCFG_CLKEN_S 0U |
| #define PDM_CLKCFG_CLKEN_DIS 0x00000000U |
| #define PDM_CLKCFG_CLKEN_EN 0x00000001U |
| #define PDM_CLKCFG_CLKSEL_W 3U |
| #define PDM_CLKCFG_CLKSEL_M 0x00000070U |
| #define PDM_CLKCFG_CLKSEL_S 4U |
| #define PDM_CLKCFG_CLKSEL_SEL_0 0x00000000U |
| #define PDM_CLKCFG_CLKSEL_SEL_1 0x00000010U |
| #define PDM_CLKCFG_CLKSEL_SEL_2 0x00000020U |
| #define PDM_CLKCFG_CLKSEL_SEL_3 0x00000030U |
| #define PDM_CLKCFG_ADFSEN 0x00000080U |
| #define PDM_CLKCFG_ADFSEN_M 0x00000080U |
| #define PDM_CLKCFG_ADFSEN_S 7U |
| #define PDM_CLKCFG_ADFSEN_DIS 0x00000000U |
| #define PDM_CLKCFG_ADFSEN_EN 0x00000080U |
| #define PDM_ADFSCTL1_TREF_W 21U |
| #define PDM_ADFSCTL1_TREF_M 0x001FFFFFU |
| #define PDM_ADFSCTL1_TREF_S 0U |
| #define PDM_ADFSCTL2_DELTA_W 17U |
| #define PDM_ADFSCTL2_DELTA_M 0x0001FFFFU |
| #define PDM_ADFSCTL2_DELTA_S 0U |
| #define PDM_ADFSCTL2_DLTASIGN 0x00020000U |
| #define PDM_ADFSCTL2_DLTASIGN_M 0x00020000U |
| #define PDM_ADFSCTL2_DLTASIGN_S 17U |
| #define PDM_ADFSCTL2_DLTASIGN_POS 0x00000000U |
| #define PDM_ADFSCTL2_DLTASIGN_NEG 0x00020000U |
| #define PDM_ADFSCTL2_DIV_W 10U |
| #define PDM_ADFSCTL2_DIV_M 0x3FF00000U |
| #define PDM_ADFSCTL2_DIV_S 20U |