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Macros
#define	OSPI_O_CONFIG 0x00000000U

#define	OSPI_O_DEV_INSTR_RD_CONFIG 0x00000004U

#define	OSPI_O_DEV_INSTR_WR_CONFIG 0x00000008U

#define	OSPI_O_DEV_DELAY 0x0000000CU

#define	OSPI_O_RD_DATA_CAPTURE 0x00000010U

#define	OSPI_O_DEV_SIZE_CONFIG 0x00000014U

#define	OSPI_O_SRAM_PARTITION_CFG 0x00000018U

#define	OSPI_O_IND_AHB_ADDR_TRIGGER 0x0000001CU

#define	OSPI_O_DMA_PERIPH_CONFIG 0x00000020U

#define	OSPI_O_REMAP_ADDR 0x00000024U

#define	OSPI_O_MODE_BIT_CONFIG 0x00000028U

#define	OSPI_O_SRAM_FILL 0x0000002CU

#define	OSPI_O_TX_THRESH 0x00000030U

#define	OSPI_O_RX_THRESH 0x00000034U

#define	OSPI_O_WRITE_COMPLETION_CTRL 0x00000038U

#define	OSPI_O_NO_OF_POLLS_BEF_EXP 0x0000003CU

#define	OSPI_O_IRQ_STATUS 0x00000040U

#define	OSPI_O_IRQ_MASK 0x00000044U

#define	OSPI_O_LOWER_WR_PROT 0x00000050U

#define	OSPI_O_UPPER_WR_PROT 0x00000054U

#define	OSPI_O_WR_PROT_CTRL 0x00000058U

#define	OSPI_O_INDIRECT_READ_XFER_CTRL 0x00000060U

#define	OSPI_O_INDIRECT_READ_XFER_WATERMARK 0x00000064U

#define	OSPI_O_INDIRECT_READ_XFER_START 0x00000068U

#define	OSPI_O_INDIRECT_READ_XFER_NUM_BYTES 0x0000006CU

#define	OSPI_O_INDIRECT_WRITE_XFER_CTRL 0x00000070U

#define	OSPI_O_INDIRECT_WRITE_XFER_WATERMARK 0x00000074U

#define	OSPI_O_INDIRECT_WRITE_XFER_START 0x00000078U

#define	OSPI_O_INDIRECT_WRITE_XFER_NUM_BYTES 0x0000007CU

#define	OSPI_O_INDIRECT_TRIGGER_ADDR_RANGE 0x00000080U

#define	OSPI_O_FLASH_COMMAND_CTRL_MEM 0x0000008CU

#define	OSPI_O_FLASH_CMD_CTRL 0x00000090U

#define	OSPI_O_FLASH_CMD_ADDR 0x00000094U

#define	OSPI_O_FLASH_RD_DATA_LOWER 0x000000A0U

#define	OSPI_O_FLASH_RD_DATA_UPPER 0x000000A4U

#define	OSPI_O_FLASH_WR_DATA_LOWER 0x000000A8U

#define	OSPI_O_FLASH_WR_DATA_UPPER 0x000000ACU

#define	OSPI_O_POLLING_FLASH_STATUS 0x000000B0U

#define	OSPI_O_PHY_CONFIGURATION 0x000000B4U

#define	OSPI_O_PHY_MASTER_CONTROL 0x000000B8U

#define	OSPI_O_DLL_OBSERVABLE_LOWER 0x000000BCU

#define	OSPI_O_DLL_OBSERVABLE_UPPER 0x000000C0U

#define	OSPI_O_OPCODE_EXT_LOWER 0x000000E0U

#define	OSPI_O_OPCODE_EXT_UPPER 0x000000E4U

#define	OSPI_O_MODULE_ID 0x000000FCU

#define	OSPI_CONFIG_ENB_SPI 0x00000001U

#define	OSPI_CONFIG_ENB_SPI_M 0x00000001U

#define	OSPI_CONFIG_ENB_SPI_S 0U

#define	OSPI_CONFIG_ENB_SPI_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENB_SPI_ENABLE 0x00000001U

#define	OSPI_CONFIG_SEL_CLK_POL 0x00000002U

#define	OSPI_CONFIG_SEL_CLK_POL_M 0x00000002U

#define	OSPI_CONFIG_SEL_CLK_POL_S 1U

#define	OSPI_CONFIG_SEL_CLK_POL_DISABLE 0x00000000U

#define	OSPI_CONFIG_SEL_CLK_POL_ENABLE 0x00000002U

#define	OSPI_CONFIG_SEL_CLK_PHASE 0x00000004U

#define	OSPI_CONFIG_SEL_CLK_PHASE_M 0x00000004U

#define	OSPI_CONFIG_SEL_CLK_PHASE_S 2U

#define	OSPI_CONFIG_SEL_CLK_PHASE_DISABLE 0x00000000U

#define	OSPI_CONFIG_SEL_CLK_PHASE_ENABLE 0x00000004U

#define	OSPI_CONFIG_PHY_MODE_ENABLE 0x00000008U

#define	OSPI_CONFIG_PHY_MODE_ENABLE_M 0x00000008U

#define	OSPI_CONFIG_PHY_MODE_ENABLE_S 3U

#define	OSPI_CONFIG_PHY_MODE_ENABLE_DISABLE 0x00000000U

#define	OSPI_CONFIG_PHY_MODE_ENABLE_ENABLE 0x00000008U

#define	OSPI_CONFIG_HOLD_PIN 0x00000010U

#define	OSPI_CONFIG_HOLD_PIN_M 0x00000010U

#define	OSPI_CONFIG_HOLD_PIN_S 4U

#define	OSPI_CONFIG_HOLD_PIN_DISABLE 0x00000000U

#define	OSPI_CONFIG_HOLD_PIN_ENABLE 0x00000010U

#define	OSPI_CONFIG_RESET_PIN 0x00000020U

#define	OSPI_CONFIG_RESET_PIN_M 0x00000020U

#define	OSPI_CONFIG_RESET_PIN_S 5U

#define	OSPI_CONFIG_RESET_PIN_DISABLE 0x00000000U

#define	OSPI_CONFIG_RESET_PIN_ENABLE 0x00000020U

#define	OSPI_CONFIG_RESET_CFG 0x00000040U

#define	OSPI_CONFIG_RESET_CFG_M 0x00000040U

#define	OSPI_CONFIG_RESET_CFG_S 6U

#define	OSPI_CONFIG_RESET_CFG_DISABLE 0x00000000U

#define	OSPI_CONFIG_RESET_CFG_ENABLE 0x00000040U

#define	OSPI_CONFIG_ENB_DIR_ACC_CTLR 0x00000080U

#define	OSPI_CONFIG_ENB_DIR_ACC_CTLR_M 0x00000080U

#define	OSPI_CONFIG_ENB_DIR_ACC_CTLR_S 7U

#define	OSPI_CONFIG_ENB_DIR_ACC_CTLR_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENB_DIR_ACC_CTLR_ENABLE 0x00000080U

#define	OSPI_CONFIG_ENB_LEGACY_IP_MODE 0x00000100U

#define	OSPI_CONFIG_ENB_LEGACY_IP_MODE_M 0x00000100U

#define	OSPI_CONFIG_ENB_LEGACY_IP_MODE_S 8U

#define	OSPI_CONFIG_ENB_LEGACY_IP_MODE_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENB_LEGACY_IP_MODE_ENABLE 0x00000100U

#define	OSPI_CONFIG_PERIPH_SEL_DEC 0x00000200U

#define	OSPI_CONFIG_PERIPH_SEL_DEC_M 0x00000200U

#define	OSPI_CONFIG_PERIPH_SEL_DEC_S 9U

#define	OSPI_CONFIG_PERIPH_SEL_DEC_DISABLE 0x00000000U

#define	OSPI_CONFIG_PERIPH_SEL_DEC_ENABLE 0x00000200U

#define	OSPI_CONFIG_PERIPH_CS_LINES_W 4U

#define	OSPI_CONFIG_PERIPH_CS_LINES_M 0x00003C00U

#define	OSPI_CONFIG_PERIPH_CS_LINES_S 10U

#define	OSPI_CONFIG_PERIPH_CS_LINES_MINIMUM 0x00000000U

#define	OSPI_CONFIG_PERIPH_CS_LINES_MAXIMUM 0x00003C00U

#define	OSPI_CONFIG_WR_PROT_FLASH 0x00004000U

#define	OSPI_CONFIG_WR_PROT_FLASH_M 0x00004000U

#define	OSPI_CONFIG_WR_PROT_FLASH_S 14U

#define	OSPI_CONFIG_WR_PROT_FLASH_DISABLE 0x00000000U

#define	OSPI_CONFIG_WR_PROT_FLASH_ENABLE 0x00004000U

#define	OSPI_CONFIG_ENB_DMA_IF 0x00008000U

#define	OSPI_CONFIG_ENB_DMA_IF_M 0x00008000U

#define	OSPI_CONFIG_ENB_DMA_IF_S 15U

#define	OSPI_CONFIG_ENB_DMA_IF_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENB_DMA_IF_ENABLE 0x00008000U

#define	OSPI_CONFIG_ENB_AHB_ADDR_REMAP 0x00010000U

#define	OSPI_CONFIG_ENB_AHB_ADDR_REMAP_M 0x00010000U

#define	OSPI_CONFIG_ENB_AHB_ADDR_REMAP_S 16U

#define	OSPI_CONFIG_ENB_AHB_ADDR_REMAP_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENB_AHB_ADDR_REMAP_ENABLE 0x00010000U

#define	OSPI_CONFIG_ENTER_XIP_MODE 0x00020000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_M 0x00020000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_S 17U

#define	OSPI_CONFIG_ENTER_XIP_MODE_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_ENABLE 0x00020000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_IMM 0x00040000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_IMM_M 0x00040000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_IMM_S 18U

#define	OSPI_CONFIG_ENTER_XIP_MODE_IMM_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENTER_XIP_MODE_IMM_ENABLE 0x00040000U

#define	OSPI_CONFIG_MSTR_BAUD_DIV_W 4U

#define	OSPI_CONFIG_MSTR_BAUD_DIV_M 0x00780000U

#define	OSPI_CONFIG_MSTR_BAUD_DIV_S 19U

#define	OSPI_CONFIG_MSTR_BAUD_DIV_MINIMUM 0x00000000U

#define	OSPI_CONFIG_MSTR_BAUD_DIV_MAXIMUM 0x00780000U

#define	OSPI_CONFIG_ENABLE_AHB_DECODER 0x00800000U

#define	OSPI_CONFIG_ENABLE_AHB_DECODER_M 0x00800000U

#define	OSPI_CONFIG_ENABLE_AHB_DECODER_S 23U

#define	OSPI_CONFIG_ENABLE_AHB_DECODER_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENABLE_AHB_DECODER_ENABLE 0x00800000U

#define	OSPI_CONFIG_ENABLE_DTR_PROTOCOL 0x01000000U

#define	OSPI_CONFIG_ENABLE_DTR_PROTOCOL_M 0x01000000U

#define	OSPI_CONFIG_ENABLE_DTR_PROTOCOL_S 24U

#define	OSPI_CONFIG_ENABLE_DTR_PROTOCOL_DISABLE 0x00000000U

#define	OSPI_CONFIG_ENABLE_DTR_PROTOCOL_ENABLE 0x01000000U

#define	OSPI_CONFIG_PIPELINE_PHY 0x02000000U

#define	OSPI_CONFIG_PIPELINE_PHY_M 0x02000000U

#define	OSPI_CONFIG_PIPELINE_PHY_S 25U

#define	OSPI_CONFIG_PIPELINE_PHY_DISABLE 0x00000000U

#define	OSPI_CONFIG_PIPELINE_PHY_ENABLE 0x02000000U

#define	OSPI_CONFIG_CRC_ENABLE 0x20000000U

#define	OSPI_CONFIG_CRC_ENABLE_M 0x20000000U

#define	OSPI_CONFIG_CRC_ENABLE_S 29U

#define	OSPI_CONFIG_CRC_ENABLE_DISABLE 0x00000000U

#define	OSPI_CONFIG_CRC_ENABLE_ENABLE 0x20000000U

#define	OSPI_CONFIG_DUAL_BYTE_OPCODE_EN 0x40000000U

#define	OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_M 0x40000000U

#define	OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_S 30U

#define	OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_DISABLE 0x00000000U

#define	OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_ENABLE 0x40000000U

#define	OSPI_CONFIG_IDLE 0x80000000U

#define	OSPI_CONFIG_IDLE_M 0x80000000U

#define	OSPI_CONFIG_IDLE_S 31U

#define	OSPI_CONFIG_IDLE_DISABLE 0x00000000U

#define	OSPI_CONFIG_IDLE_ENABLE 0x80000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_W 8U

#define	OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_M 0x000000FFU

#define	OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_S 0U

#define	OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_MAXIMUM 0x000000FFU

#define	OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_W 2U

#define	OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_M 0x00000300U

#define	OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_S 8U

#define	OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_MAXIMUM 0x00000300U

#define	OSPI_DEV_INSTR_RD_CONFIG_DDR_EN 0x00000400U

#define	OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_M 0x00000400U

#define	OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_S 10U

#define	OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_DISABLE 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_ENABLE 0x00000400U

#define	OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS 0x00000800U

#define	OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_M 0x00000800U

#define	OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_S 11U

#define	OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_DISABLE 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_ENABLE 0x00000800U

#define	OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_W 2U

#define	OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_M 0x00003000U

#define	OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_S 12U

#define	OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_MAXIMUM 0x00003000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_W 2U

#define	OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_M 0x00030000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_S 16U

#define	OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_MAXIMUM 0x00030000U

#define	OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE 0x00100000U

#define	OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_M 0x00100000U

#define	OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_S 20U

#define	OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_DISABLE 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_ENABLE 0x00100000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_W 5U

#define	OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_M 0x1F000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_S 24U

#define	OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_MAXIMUM 0x1F000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_W 8U

#define	OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_M 0x000000FFU

#define	OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_S 0U

#define	OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_MAXIMUM 0x000000FFU

#define	OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS 0x00000100U

#define	OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_M 0x00000100U

#define	OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_S 8U

#define	OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_DISABLE 0x00000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_ENABLE 0x00000100U

#define	OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_W 2U

#define	OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_M 0x00003000U

#define	OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_S 12U

#define	OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_MAXIMUM 0x00003000U

#define	OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_W 2U

#define	OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_M 0x00030000U

#define	OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_S 16U

#define	OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_MAXIMUM 0x00030000U

#define	OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_W 5U

#define	OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_M 0x1F000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_S 24U

#define	OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_MINIMUM 0x00000000U

#define	OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_MAXIMUM 0x1F000000U

#define	OSPI_DEV_DELAY_D_INIT_W 8U

#define	OSPI_DEV_DELAY_D_INIT_M 0x000000FFU

#define	OSPI_DEV_DELAY_D_INIT_S 0U

#define	OSPI_DEV_DELAY_D_INIT_MINIMUM 0x00000000U

#define	OSPI_DEV_DELAY_D_INIT_MAXIMUM 0x000000FFU

#define	OSPI_DEV_DELAY_D_AFTER_W 8U

#define	OSPI_DEV_DELAY_D_AFTER_M 0x0000FF00U

#define	OSPI_DEV_DELAY_D_AFTER_S 8U

#define	OSPI_DEV_DELAY_D_AFTER_MINIMUM 0x00000000U

#define	OSPI_DEV_DELAY_D_AFTER_MAXIMUM 0x0000FF00U

#define	OSPI_DEV_DELAY_D_BTWN_W 8U

#define	OSPI_DEV_DELAY_D_BTWN_M 0x00FF0000U

#define	OSPI_DEV_DELAY_D_BTWN_S 16U

#define	OSPI_DEV_DELAY_D_BTWN_MINIMUM 0x00000000U

#define	OSPI_DEV_DELAY_D_BTWN_MAXIMUM 0x00FF0000U

#define	OSPI_DEV_DELAY_D_NSS_W 8U

#define	OSPI_DEV_DELAY_D_NSS_M 0xFF000000U

#define	OSPI_DEV_DELAY_D_NSS_S 24U

#define	OSPI_DEV_DELAY_D_NSS_MINIMUM 0x00000000U

#define	OSPI_DEV_DELAY_D_NSS_MAXIMUM 0xFF000000U

#define	OSPI_RD_DATA_CAPTURE_BYPASS 0x00000001U

#define	OSPI_RD_DATA_CAPTURE_BYPASS_M 0x00000001U

#define	OSPI_RD_DATA_CAPTURE_BYPASS_S 0U

#define	OSPI_RD_DATA_CAPTURE_BYPASS_DISABLE 0x00000000U

#define	OSPI_RD_DATA_CAPTURE_BYPASS_ENABLE 0x00000001U

#define	OSPI_RD_DATA_CAPTURE_DELAY_W 4U

#define	OSPI_RD_DATA_CAPTURE_DELAY_M 0x0000001EU

#define	OSPI_RD_DATA_CAPTURE_DELAY_S 1U

#define	OSPI_RD_DATA_CAPTURE_DELAY_MINIMUM 0x00000000U

#define	OSPI_RD_DATA_CAPTURE_DELAY_MAXIMUM 0x0000001EU

#define	OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL 0x00000020U

#define	OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_M 0x00000020U

#define	OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_S 5U

#define	OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_DISABLE 0x00000000U

#define	OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_ENABLE 0x00000020U

#define	OSPI_RD_DATA_CAPTURE_DQS_ENABLE 0x00000100U

#define	OSPI_RD_DATA_CAPTURE_DQS_ENABLE_M 0x00000100U

#define	OSPI_RD_DATA_CAPTURE_DQS_ENABLE_S 8U

#define	OSPI_RD_DATA_CAPTURE_DQS_ENABLE_DISABLE 0x00000000U

#define	OSPI_RD_DATA_CAPTURE_DQS_ENABLE_ENABLE 0x00000100U

#define	OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_W 4U

#define	OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_M 0x000F0000U

#define	OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_S 16U

#define	OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_MINIMUM 0x00000000U

#define	OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_MAXIMUM 0x000F0000U

#define	OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_W 4U

#define	OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_M 0x0000000FU

#define	OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_S 0U

#define	OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_MAXIMUM 0x0000000FU

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_W 12U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_M 0x0000FFF0U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_S 4U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_MAXIMUM 0x0000FFF0U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_W 5U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_M 0x001F0000U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_S 16U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_MAXIMUM 0x001F0000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_W 2U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_M 0x00600000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_S 21U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_MAXIMUM 0x00600000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_W 2U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_M 0x01800000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_S 23U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_MAXIMUM 0x01800000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_W 2U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_M 0x06000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_S 25U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_MAXIMUM 0x06000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_W 2U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_M 0x18000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_S 27U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_MINIMUM 0x00000000U

#define	OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_MAXIMUM 0x18000000U

#define	OSPI_SRAM_PARTITION_CFG_THRESHOLD_W 8U

#define	OSPI_SRAM_PARTITION_CFG_THRESHOLD_M 0x000000FFU

#define	OSPI_SRAM_PARTITION_CFG_THRESHOLD_S 0U

#define	OSPI_IND_AHB_ADDR_TRIGGER_ADDR_W 32U

#define	OSPI_IND_AHB_ADDR_TRIGGER_ADDR_M 0xFFFFFFFFU

#define	OSPI_IND_AHB_ADDR_TRIGGER_ADDR_S 0U

#define	OSPI_IND_AHB_ADDR_TRIGGER_ADDR_MINIMUM 0x00000000U

#define	OSPI_IND_AHB_ADDR_TRIGGER_ADDR_MAXIMUM 0xFFFFFFFFU

#define	OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_W 4U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_M 0x0000000FU

#define	OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_S 0U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_MINIMUM 0x00000000U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_MAXIMUM 0x0000000FU

#define	OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_W 4U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_M 0x00000F00U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_S 8U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_MINIMUM 0x00000000U

#define	OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_MAXIMUM 0x00000F00U

#define	OSPI_REMAP_ADDR_VALUE_W 32U

#define	OSPI_REMAP_ADDR_VALUE_M 0xFFFFFFFFU

#define	OSPI_REMAP_ADDR_VALUE_S 0U

#define	OSPI_REMAP_ADDR_VALUE_MINIMUM 0x00000000U

#define	OSPI_REMAP_ADDR_VALUE_MAXIMUM 0xFFFFFFFFU

#define	OSPI_MODE_BIT_CONFIG_MODE_W 8U

#define	OSPI_MODE_BIT_CONFIG_MODE_M 0x000000FFU

#define	OSPI_MODE_BIT_CONFIG_MODE_S 0U

#define	OSPI_MODE_BIT_CONFIG_MODE_MINIMUM 0x00000000U

#define	OSPI_MODE_BIT_CONFIG_MODE_MAXIMUM 0x000000FFU

#define	OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_W 3U

#define	OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_M 0x00000700U

#define	OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_S 8U

#define	OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_MINIMUM 0x00000000U

#define	OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_MAXIMUM 0x00000700U

#define	OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE 0x00008000U

#define	OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_M 0x00008000U

#define	OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_S 15U

#define	OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_DISABLE 0x00000000U

#define	OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_ENABLE 0x00008000U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_W 8U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_M 0x00FF0000U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_S 16U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_MINIMUM 0x00000000U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_MAXIMUM 0x00FF0000U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_W 8U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_M 0xFF000000U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_S 24U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_MINIMUM 0x00000000U

#define	OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_MAXIMUM 0xFF000000U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_W 16U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_M 0x0000FFFFU

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_S 0U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_MINIMUM 0x00000000U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_MAXIMUM 0x0000FFFFU

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_W 16U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_M 0xFFFF0000U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_S 16U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_MINIMUM 0x00000000U

#define	OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_MAXIMUM 0xFFFF0000U

#define	OSPI_TX_THRESH_LEVEL_W 5U

#define	OSPI_TX_THRESH_LEVEL_M 0x0000001FU

#define	OSPI_TX_THRESH_LEVEL_S 0U

#define	OSPI_TX_THRESH_LEVEL_MINIMUM 0x00000000U

#define	OSPI_TX_THRESH_LEVEL_MAXIMUM 0x0000001FU

#define	OSPI_RX_THRESH_LEVEL_W 5U

#define	OSPI_RX_THRESH_LEVEL_M 0x0000001FU

#define	OSPI_RX_THRESH_LEVEL_S 0U

#define	OSPI_RX_THRESH_LEVEL_MINIMUM 0x00000000U

#define	OSPI_RX_THRESH_LEVEL_MAXIMUM 0x0000001FU

#define	OSPI_WRITE_COMPLETION_CTRL_OPCODE_W 8U

#define	OSPI_WRITE_COMPLETION_CTRL_OPCODE_M 0x000000FFU

#define	OSPI_WRITE_COMPLETION_CTRL_OPCODE_S 0U

#define	OSPI_WRITE_COMPLETION_CTRL_OPCODE_MINIMUM 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_OPCODE_MAXIMUM 0x000000FFU

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_W 3U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_M 0x00000700U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_S 8U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_MINIMUM 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_MAXIMUM 0x00000700U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN 0x00000800U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_M 0x00000800U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_S 11U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_DISABLE 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_ENABLE 0x00000800U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY 0x00002000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_M 0x00002000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_S 13U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_DISABLE 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_ENABLE 0x00002000U

#define	OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING 0x00004000U

#define	OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_M 0x00004000U

#define	OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_S 14U

#define	OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_DISABLE 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_ENABLE 0x00004000U

#define	OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP 0x00008000U

#define	OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_M 0x00008000U

#define	OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_S 15U

#define	OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_DISABLE 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_ENABLE 0x00008000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_W 8U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_M 0x00FF0000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_S 16U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_MINIMUM 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_MAXIMUM 0x00FF0000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_W 8U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_M 0xFF000000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_S 24U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_MINIMUM 0x00000000U

#define	OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_MAXIMUM 0xFF000000U

#define	OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_W 32U

#define	OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_M 0xFFFFFFFFU

#define	OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_S 0U

#define	OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_MINIMUM 0x00000000U

#define	OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_MAXIMUM 0xFFFFFFFFU

#define	OSPI_IRQ_STATUS_MODE_M_FAIL 0x00000001U

#define	OSPI_IRQ_STATUS_MODE_M_FAIL_M 0x00000001U

#define	OSPI_IRQ_STATUS_MODE_M_FAIL_S 0U

#define	OSPI_IRQ_STATUS_MODE_M_FAIL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_MODE_M_FAIL_ENABLE 0x00000001U

#define	OSPI_IRQ_STATUS_UNDERFLOW_DET 0x00000002U

#define	OSPI_IRQ_STATUS_UNDERFLOW_DET_M 0x00000002U

#define	OSPI_IRQ_STATUS_UNDERFLOW_DET_S 1U

#define	OSPI_IRQ_STATUS_UNDERFLOW_DET_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_UNDERFLOW_DET_ENABLE 0x00000002U

#define	OSPI_IRQ_STATUS_INDIRECT_OP_DONE 0x00000004U

#define	OSPI_IRQ_STATUS_INDIRECT_OP_DONE_M 0x00000004U

#define	OSPI_IRQ_STATUS_INDIRECT_OP_DONE_S 2U

#define	OSPI_IRQ_STATUS_INDIRECT_OP_DONE_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_INDIRECT_OP_DONE_ENABLE 0x00000004U

#define	OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT 0x00000008U

#define	OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_M 0x00000008U

#define	OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_S 3U

#define	OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_ENABLE 0x00000008U

#define	OSPI_IRQ_STATUS_PROT_WR_ATTEMPT 0x00000010U

#define	OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_M 0x00000010U

#define	OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_S 4U

#define	OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_ENABLE 0x00000010U

#define	OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET 0x00000020U

#define	OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_M 0x00000020U

#define	OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_S 5U

#define	OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_ENABLE 0x00000020U

#define	OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH 0x00000040U

#define	OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_M 0x00000040U

#define	OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_S 6U

#define	OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_ENABLE 0x00000040U

#define	OSPI_IRQ_STATUS_RECV_OVERFLOW 0x00000080U

#define	OSPI_IRQ_STATUS_RECV_OVERFLOW_M 0x00000080U

#define	OSPI_IRQ_STATUS_RECV_OVERFLOW_S 7U

#define	OSPI_IRQ_STATUS_RECV_OVERFLOW_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_RECV_OVERFLOW_ENABLE 0x00000080U

#define	OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL 0x00000100U

#define	OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_M 0x00000100U

#define	OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_S 8U

#define	OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_ENABLE 0x00000100U

#define	OSPI_IRQ_STATUS_TX_FIFO_FULL 0x00000200U

#define	OSPI_IRQ_STATUS_TX_FIFO_FULL_M 0x00000200U

#define	OSPI_IRQ_STATUS_TX_FIFO_FULL_S 9U

#define	OSPI_IRQ_STATUS_TX_FIFO_FULL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_TX_FIFO_FULL_ENABLE 0x00000200U

#define	OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY 0x00000400U

#define	OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_M 0x00000400U

#define	OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_S 10U

#define	OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_ENABLE 0x00000400U

#define	OSPI_IRQ_STATUS_RX_FIFO_FULL 0x00000800U

#define	OSPI_IRQ_STATUS_RX_FIFO_FULL_M 0x00000800U

#define	OSPI_IRQ_STATUS_RX_FIFO_FULL_S 11U

#define	OSPI_IRQ_STATUS_RX_FIFO_FULL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_RX_FIFO_FULL_ENABLE 0x00000800U

#define	OSPI_IRQ_STATUS_INDRD_SRAM_FULL 0x00001000U

#define	OSPI_IRQ_STATUS_INDRD_SRAM_FULL_M 0x00001000U

#define	OSPI_IRQ_STATUS_INDRD_SRAM_FULL_S 12U

#define	OSPI_IRQ_STATUS_INDRD_SRAM_FULL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_INDRD_SRAM_FULL_ENABLE 0x00001000U

#define	OSPI_IRQ_STATUS_POLL_EXP_INT 0x00002000U

#define	OSPI_IRQ_STATUS_POLL_EXP_INT_M 0x00002000U

#define	OSPI_IRQ_STATUS_POLL_EXP_INT_S 13U

#define	OSPI_IRQ_STATUS_POLL_EXP_INT_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_POLL_EXP_INT_ENABLE 0x00002000U

#define	OSPI_IRQ_STATUS_STIG_REQ_INT 0x00004000U

#define	OSPI_IRQ_STATUS_STIG_REQ_INT_M 0x00004000U

#define	OSPI_IRQ_STATUS_STIG_REQ_INT_S 14U

#define	OSPI_IRQ_STATUS_STIG_REQ_INT_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_STIG_REQ_INT_ENABLE 0x00004000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_ERR 0x00010000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_M 0x00010000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_S 16U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_ENABLE 0x00010000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_VAL 0x00020000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_M 0x00020000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_S 17U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_ENABLE 0x00020000U

#define	OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK 0x00040000U

#define	OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_M 0x00040000U

#define	OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_S 18U

#define	OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_ENABLE 0x00040000U

#define	OSPI_IRQ_STATUS_ECC_FAIL 0x00080000U

#define	OSPI_IRQ_STATUS_ECC_FAIL_M 0x00080000U

#define	OSPI_IRQ_STATUS_ECC_FAIL_S 19U

#define	OSPI_IRQ_STATUS_ECC_FAIL_DISABLE 0x00000000U

#define	OSPI_IRQ_STATUS_ECC_FAIL_ENABLE 0x00080000U

#define	OSPI_IRQ_MASK_MODE_M_FAIL_MASK 0x00000001U

#define	OSPI_IRQ_MASK_MODE_M_FAIL_MASK_M 0x00000001U

#define	OSPI_IRQ_MASK_MODE_M_FAIL_MASK_S 0U

#define	OSPI_IRQ_MASK_MODE_M_FAIL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_MODE_M_FAIL_MASK_ENABLE 0x00000001U

#define	OSPI_IRQ_MASK_UNDERFLOW_DET_MASK 0x00000002U

#define	OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_M 0x00000002U

#define	OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_S 1U

#define	OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_ENABLE 0x00000002U

#define	OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK 0x00000004U

#define	OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_M 0x00000004U

#define	OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_S 2U

#define	OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_ENABLE 0x00000004U

#define	OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK 0x00000008U

#define	OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_M 0x00000008U

#define	OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_S 3U

#define	OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_ENABLE 0x00000008U

#define	OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK 0x00000010U

#define	OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_M 0x00000010U

#define	OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_S 4U

#define	OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_ENABLE 0x00000010U

#define	OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK 0x00000020U

#define	OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_M 0x00000020U

#define	OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_S 5U

#define	OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_ENABLE 0x00000020U

#define	OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK 0x00000040U

#define	OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_M 0x00000040U

#define	OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_S 6U

#define	OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_ENABLE 0x00000040U

#define	OSPI_IRQ_MASK_RECV_OVERFLOW_MASK 0x00000080U

#define	OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_M 0x00000080U

#define	OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_S 7U

#define	OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_ENABLE 0x00000080U

#define	OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK 0x00000100U

#define	OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_M 0x00000100U

#define	OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_S 8U

#define	OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_ENABLE 0x00000100U

#define	OSPI_IRQ_MASK_TX_FIFO_FULL_MASK 0x00000200U

#define	OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_M 0x00000200U

#define	OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_S 9U

#define	OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_ENABLE 0x00000200U

#define	OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK 0x00000400U

#define	OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_M 0x00000400U

#define	OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_S 10U

#define	OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_ENABLE 0x00000400U

#define	OSPI_IRQ_MASK_RX_FIFO_FULL_MASK 0x00000800U

#define	OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_M 0x00000800U

#define	OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_S 11U

#define	OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_ENABLE 0x00000800U

#define	OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK 0x00001000U

#define	OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_M 0x00001000U

#define	OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_S 12U

#define	OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_ENABLE 0x00001000U

#define	OSPI_IRQ_MASK_POLL_EXP_INT_MASK 0x00002000U

#define	OSPI_IRQ_MASK_POLL_EXP_INT_MASK_M 0x00002000U

#define	OSPI_IRQ_MASK_POLL_EXP_INT_MASK_S 13U

#define	OSPI_IRQ_MASK_POLL_EXP_INT_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_POLL_EXP_INT_MASK_ENABLE 0x00002000U

#define	OSPI_IRQ_MASK_STIG_REQ_MASK 0x00004000U

#define	OSPI_IRQ_MASK_STIG_REQ_MASK_M 0x00004000U

#define	OSPI_IRQ_MASK_STIG_REQ_MASK_S 14U

#define	OSPI_IRQ_MASK_STIG_REQ_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_STIG_REQ_MASK_ENABLE 0x00004000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK 0x00010000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_M 0x00010000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_S 16U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_ENABLE 0x00010000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK 0x00020000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_M 0x00020000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_S 17U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_ENABLE 0x00020000U

#define	OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK 0x00040000U

#define	OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_M 0x00040000U

#define	OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_S 18U

#define	OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_ENABLE 0x00040000U

#define	OSPI_IRQ_MASK_ECC_FAIL_MASK 0x00080000U

#define	OSPI_IRQ_MASK_ECC_FAIL_MASK_M 0x00080000U

#define	OSPI_IRQ_MASK_ECC_FAIL_MASK_S 19U

#define	OSPI_IRQ_MASK_ECC_FAIL_MASK_DISABLE 0x00000000U

#define	OSPI_IRQ_MASK_ECC_FAIL_MASK_ENABLE 0x00080000U

#define	OSPI_LOWER_WR_PROT_SUBSECTOR_W 32U

#define	OSPI_LOWER_WR_PROT_SUBSECTOR_M 0xFFFFFFFFU

#define	OSPI_LOWER_WR_PROT_SUBSECTOR_S 0U

#define	OSPI_LOWER_WR_PROT_SUBSECTOR_MINIMUM 0x00000000U

#define	OSPI_LOWER_WR_PROT_SUBSECTOR_MAXIMUM 0xFFFFFFFFU

#define	OSPI_UPPER_WR_PROT_SUBSECTOR_W 32U

#define	OSPI_UPPER_WR_PROT_SUBSECTOR_M 0xFFFFFFFFU

#define	OSPI_UPPER_WR_PROT_SUBSECTOR_S 0U

#define	OSPI_UPPER_WR_PROT_SUBSECTOR_MINIMUM 0x00000000U

#define	OSPI_UPPER_WR_PROT_SUBSECTOR_MAXIMUM 0xFFFFFFFFU

#define	OSPI_WR_PROT_CTRL_INV 0x00000001U

#define	OSPI_WR_PROT_CTRL_INV_M 0x00000001U

#define	OSPI_WR_PROT_CTRL_INV_S 0U

#define	OSPI_WR_PROT_CTRL_INV_DISABLE 0x00000000U

#define	OSPI_WR_PROT_CTRL_INV_ENABLE 0x00000001U

#define	OSPI_WR_PROT_CTRL_ENB 0x00000002U

#define	OSPI_WR_PROT_CTRL_ENB_M 0x00000002U

#define	OSPI_WR_PROT_CTRL_ENB_S 1U

#define	OSPI_WR_PROT_CTRL_ENB_DISABLE 0x00000000U

#define	OSPI_WR_PROT_CTRL_ENB_ENABLE 0x00000002U

#define	OSPI_INDIRECT_READ_XFER_CTRL_START 0x00000001U

#define	OSPI_INDIRECT_READ_XFER_CTRL_START_M 0x00000001U

#define	OSPI_INDIRECT_READ_XFER_CTRL_START_S 0U

#define	OSPI_INDIRECT_READ_XFER_CTRL_START_DISABLE 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_START_ENABLE 0x00000001U

#define	OSPI_INDIRECT_READ_XFER_CTRL_CANCEL 0x00000002U

#define	OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_M 0x00000002U

#define	OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_S 1U

#define	OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_DISABLE 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_ENABLE 0x00000002U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS 0x00000004U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_M 0x00000004U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_S 2U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_DISABLE 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_ENABLE 0x00000004U

#define	OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL 0x00000008U

#define	OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_M 0x00000008U

#define	OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_S 3U

#define	OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_DISABLE 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_ENABLE 0x00000008U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED 0x00000010U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_M 0x00000010U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_S 4U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_DISABLE 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_ENABLE 0x00000010U

#define	OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS 0x00000020U

#define	OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_M 0x00000020U

#define	OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_S 5U

#define	OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_DISABLE 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_ENABLE 0x00000020U

#define	OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_W 2U

#define	OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_M 0x000000C0U

#define	OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_S 6U

#define	OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_MAXIMUM 0x000000C0U

#define	OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_W 32U

#define	OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_M 0xFFFFFFFFU

#define	OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_S 0U

#define	OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_MAXIMUM 0xFFFFFFFFU

#define	OSPI_INDIRECT_READ_XFER_START_ADDR_W 32U

#define	OSPI_INDIRECT_READ_XFER_START_ADDR_M 0xFFFFFFFFU

#define	OSPI_INDIRECT_READ_XFER_START_ADDR_S 0U

#define	OSPI_INDIRECT_READ_XFER_START_ADDR_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_START_ADDR_MAXIMUM 0xFFFFFFFFU

#define	OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_W 32U

#define	OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_M 0xFFFFFFFFU

#define	OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_S 0U

#define	OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_MAXIMUM 0xFFFFFFFFU

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_START 0x00000001U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_START_M 0x00000001U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_START_S 0U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_START_DISABLE 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_START_ENABLE 0x00000001U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL 0x00000002U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_M 0x00000002U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_S 1U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_DISABLE 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_ENABLE 0x00000002U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS 0x00000004U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_M 0x00000004U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_S 2U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_DISABLE 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_ENABLE 0x00000004U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED 0x00000010U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_M 0x00000010U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_S 4U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_DISABLE 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_ENABLE 0x00000010U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS 0x00000020U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_M 0x00000020U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_S 5U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_DISABLE 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_ENABLE 0x00000020U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_W 2U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_M 0x000000C0U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_S 6U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_MAXIMUM 0x000000C0U

#define	OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_W 32U

#define	OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_M 0xFFFFFFFFU

#define	OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_S 0U

#define	OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_MAXIMUM 0xFFFFFFFFU

#define	OSPI_INDIRECT_WRITE_XFER_START_ADDR_W 32U

#define	OSPI_INDIRECT_WRITE_XFER_START_ADDR_M 0xFFFFFFFFU

#define	OSPI_INDIRECT_WRITE_XFER_START_ADDR_S 0U

#define	OSPI_INDIRECT_WRITE_XFER_START_ADDR_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_START_ADDR_MAXIMUM 0xFFFFFFFFU

#define	OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_W 32U

#define	OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_M 0xFFFFFFFFU

#define	OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_S 0U

#define	OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_MAXIMUM 0xFFFFFFFFU

#define	OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_W 4U

#define	OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_M 0x0000000FU

#define	OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_S 0U

#define	OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_MINIMUM 0x00000000U

#define	OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_MAXIMUM 0x0000000FU

#define	OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ 0x00000001U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_M 0x00000001U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_S 0U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_DISABLE 0x00000000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_ENABLE 0x00000001U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS 0x00000002U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_M 0x00000002U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_S 1U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_DISABLE 0x00000000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_ENABLE 0x00000002U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_W 8U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_M 0x0000FF00U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_S 8U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_MINIMUM 0x00000000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_MAXIMUM 0x0000FF00U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_W 3U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_M 0x00070000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_S 16U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_MINIMUM 0x00000000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_MAXIMUM 0x00070000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_W 9U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_M 0x1FF00000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_S 20U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_MINIMUM 0x00000000U

#define	OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_MAXIMUM 0x1FF00000U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC 0x00000001U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_M 0x00000001U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_S 0U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_ENABLE 0x00000001U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS 0x00000002U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_M 0x00000002U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_S 1U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_ENABLE 0x00000002U

#define	OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN 0x00000004U

#define	OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_M 0x00000004U

#define	OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_S 2U

#define	OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_ENABLE 0x00000004U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_W 4U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_M 0x00000078U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_S 3U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_IDLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_ADDR_BYTES 0x00000008U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_STIG_MODE_BYTE 0x00000010U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_STIG_DUMMY_BYTES 0x00000018U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_DATA 0x00000020U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_STIG_DATA_LOWER 0x00000028U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_STIG_DATA_UPPER 0x00000030U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_AFTER_WRITE 0x00000038U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_AFTER_WRITE2 0x00000040U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_LET_TXFIFO_EMPTY 0x00000050U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_WAIT 0x00000058U

#define	OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_DATA_PIPE 0x00000060U

#define	OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_W 5U

#define	OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_M 0x00000F80U

#define	OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_S 7U

#define	OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_MINIMUM 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_MAXIMUM 0x00000F80U

#define	OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_W 3U

#define	OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_M 0x00007000U

#define	OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_S 12U

#define	OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_MINIMUM 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_MAXIMUM 0x00007000U

#define	OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA 0x00008000U

#define	OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_M 0x00008000U

#define	OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_S 15U

#define	OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_ENABLE 0x00008000U

#define	OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_W 2U

#define	OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_M 0x00030000U

#define	OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_S 16U

#define	OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_MINIMUM 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_MAXIMUM 0x00030000U

#define	OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT 0x00040000U

#define	OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_M 0x00040000U

#define	OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_S 18U

#define	OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_ENABLE 0x00040000U

#define	OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR 0x00080000U

#define	OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_M 0x00080000U

#define	OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_S 19U

#define	OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_ENABLE 0x00080000U

#define	OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_W 3U

#define	OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_M 0x00700000U

#define	OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_S 20U

#define	OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_MINIMUM 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_MAXIMUM 0x00700000U

#define	OSPI_FLASH_CMD_CTRL_ENB_READ_DATA 0x00800000U

#define	OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_M 0x00800000U

#define	OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_S 23U

#define	OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_DISABLE 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_ENABLE 0x00800000U

#define	OSPI_FLASH_CMD_CTRL_CMD_OPCODE_W 8U

#define	OSPI_FLASH_CMD_CTRL_CMD_OPCODE_M 0xFF000000U

#define	OSPI_FLASH_CMD_CTRL_CMD_OPCODE_S 24U

#define	OSPI_FLASH_CMD_CTRL_CMD_OPCODE_MINIMUM 0x00000000U

#define	OSPI_FLASH_CMD_CTRL_CMD_OPCODE_MAXIMUM 0xFF000000U

#define	OSPI_FLASH_CMD_ADDR_ADDR_W 32U

#define	OSPI_FLASH_CMD_ADDR_ADDR_M 0xFFFFFFFFU

#define	OSPI_FLASH_CMD_ADDR_ADDR_S 0U

#define	OSPI_FLASH_CMD_ADDR_ADDR_MINIMUM 0x00000000U

#define	OSPI_FLASH_CMD_ADDR_ADDR_MAXIMUM 0xFFFFFFFFU

#define	OSPI_FLASH_RD_DATA_LOWER_DATA_W 32U

#define	OSPI_FLASH_RD_DATA_LOWER_DATA_M 0xFFFFFFFFU

#define	OSPI_FLASH_RD_DATA_LOWER_DATA_S 0U

#define	OSPI_FLASH_RD_DATA_LOWER_DATA_MINIMUM 0x00000000U

#define	OSPI_FLASH_RD_DATA_LOWER_DATA_MAXIMUM 0xFFFFFFFFU

#define	OSPI_FLASH_RD_DATA_UPPER_DATA_W 32U

#define	OSPI_FLASH_RD_DATA_UPPER_DATA_M 0xFFFFFFFFU

#define	OSPI_FLASH_RD_DATA_UPPER_DATA_S 0U

#define	OSPI_FLASH_RD_DATA_UPPER_DATA_MINIMUM 0x00000000U

#define	OSPI_FLASH_RD_DATA_UPPER_DATA_MAXIMUM 0xFFFFFFFFU

#define	OSPI_FLASH_WR_DATA_LOWER_DATA_W 32U

#define	OSPI_FLASH_WR_DATA_LOWER_DATA_M 0xFFFFFFFFU

#define	OSPI_FLASH_WR_DATA_LOWER_DATA_S 0U

#define	OSPI_FLASH_WR_DATA_LOWER_DATA_MINIMUM 0x00000000U

#define	OSPI_FLASH_WR_DATA_LOWER_DATA_MAXIMUM 0xFFFFFFFFU

#define	OSPI_FLASH_WR_DATA_UPPER_DATA_W 32U

#define	OSPI_FLASH_WR_DATA_UPPER_DATA_M 0xFFFFFFFFU

#define	OSPI_FLASH_WR_DATA_UPPER_DATA_S 0U

#define	OSPI_FLASH_WR_DATA_UPPER_DATA_MINIMUM 0x00000000U

#define	OSPI_FLASH_WR_DATA_UPPER_DATA_MAXIMUM 0xFFFFFFFFU

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_W 8U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_M 0x000000FFU

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_S 0U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_MINIMUM 0x00000000U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_MAXIMUM 0x000000FFU

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID 0x00000100U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_M 0x00000100U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_S 8U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_DISABLE 0x00000000U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_ENABLE 0x00000100U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_W 5U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_M 0x001F0000U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_S 16U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_MINIMUM 0x00000000U

#define	OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_MAXIMUM 0x001F0000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_W 7U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_M 0x0000007FU

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_S 0U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_MINIMUM 0x00000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_MAXIMUM 0x0000007FU

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_W 7U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_M 0x007F0000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_S 16U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_MINIMUM 0x00000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_MAXIMUM 0x007F0000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS 0x20000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_M 0x20000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_S 29U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_DISABLE 0x00000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_ENABLE 0x20000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET 0x40000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_M 0x40000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_S 30U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_DISABLE 0x00000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_ENABLE 0x40000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC 0x80000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_M 0x80000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_S 31U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_DISABLE 0x00000000U

#define	OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_ENABLE 0x80000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_W 7U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_M 0x0000007FU

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_S 0U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_MINIMUM 0x00000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_MAXIMUM 0x0000007FU

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_W 3U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_M 0x00070000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_S 16U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_MINIMUM 0x00000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_MAXIMUM 0x00070000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_W 3U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_M 0x00700000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_S 20U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_MINIMUM 0x00000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_MAXIMUM 0x00700000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE 0x00800000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_M 0x00800000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_S 23U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_DISABLE 0x00000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_ENABLE 0x00800000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE 0x01000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_M 0x01000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_S 24U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_DISABLE 0x00000000U

#define	OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_ENABLE 0x01000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK 0x00000001U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_M 0x00000001U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_S 0U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DISABLE 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_ENABLE 0x00000001U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_W 2U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_M 0x00000006U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_S 1U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_MAXIMUM 0x00000006U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_W 5U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_M 0x000000F8U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_S 3U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_MAXIMUM 0x000000F8U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_W 7U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_M 0x00007F00U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_S 8U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_MAXIMUM 0x00007F00U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK 0x00008000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_M 0x00008000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_S 15U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_DISABLE 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_ENABLE 0x00008000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_W 8U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_M 0x00FF0000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_S 16U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_MAXIMUM 0x00FF0000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_W 8U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_M 0xFF000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_S 24U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_MAXIMUM 0xFF000000U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_W 7U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_M 0x0000007FU

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_S 0U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_MAXIMUM 0x0000007FU

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_W 7U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_M 0x007F0000U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_S 16U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_MINIMUM 0x00000000U

#define	OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_MAXIMUM 0x007F0000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_W 8U

#define	OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_M 0x000000FFU

#define	OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_S 0U

#define	OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_MINIMUM 0x00000000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_MAXIMUM 0x000000FFU

#define	OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_W 8U

#define	OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_M 0x0000FF00U

#define	OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_S 8U

#define	OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_MINIMUM 0x00000000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_MAXIMUM 0x0000FF00U

#define	OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_W 8U

#define	OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_M 0x00FF0000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_S 16U

#define	OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_MINIMUM 0x00000000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_MAXIMUM 0x00FF0000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_W 8U

#define	OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_M 0xFF000000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_S 24U

#define	OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_MINIMUM 0x00000000U

#define	OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_MAXIMUM 0xFF000000U

#define	OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_W 8U

#define	OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_M 0x00FF0000U

#define	OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_S 16U

#define	OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_MINIMUM 0x00000000U

#define	OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_MAXIMUM 0x00FF0000U

#define	OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_W 8U

#define	OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_M 0xFF000000U

#define	OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_S 24U

#define	OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_MINIMUM 0x00000000U

#define	OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_MAXIMUM 0xFF000000U

#define	OSPI_MODULE_ID_CONF_W 2U

#define	OSPI_MODULE_ID_CONF_M 0x00000003U

#define	OSPI_MODULE_ID_CONF_S 0U

#define	OSPI_MODULE_ID_CONF_MINIMUM 0x00000000U

#define	OSPI_MODULE_ID_CONF_MAXIMUM 0x00000003U

#define	OSPI_MODULE_ID_MODULE_ID_W 16U

#define	OSPI_MODULE_ID_MODULE_ID_M 0x00FFFF00U

#define	OSPI_MODULE_ID_MODULE_ID_S 8U

#define	OSPI_MODULE_ID_MODULE_ID_MINIMUM 0x00000000U

#define	OSPI_MODULE_ID_MODULE_ID_MAXIMUM 0x00FFFF00U

#define	OSPI_MODULE_ID_FIX_PATCH_W 8U

#define	OSPI_MODULE_ID_FIX_PATCH_M 0xFF000000U

#define	OSPI_MODULE_ID_FIX_PATCH_S 24U

#define	OSPI_MODULE_ID_FIX_PATCH_MINIMUM 0x00000000U

#define	OSPI_MODULE_ID_FIX_PATCH_MAXIMUM 0xFF000000U

Macro Definition Documentation

§ OSPI_O_CONFIG

#define OSPI_O_CONFIG 0x00000000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_O_DEV_INSTR_RD_CONFIG

#define OSPI_O_DEV_INSTR_RD_CONFIG 0x00000004U

§ OSPI_O_DEV_INSTR_WR_CONFIG

#define OSPI_O_DEV_INSTR_WR_CONFIG 0x00000008U

§ OSPI_O_DEV_DELAY

#define OSPI_O_DEV_DELAY 0x0000000CU

§ OSPI_O_RD_DATA_CAPTURE

#define OSPI_O_RD_DATA_CAPTURE 0x00000010U

§ OSPI_O_DEV_SIZE_CONFIG

#define OSPI_O_DEV_SIZE_CONFIG 0x00000014U

§ OSPI_O_SRAM_PARTITION_CFG

#define OSPI_O_SRAM_PARTITION_CFG 0x00000018U

§ OSPI_O_IND_AHB_ADDR_TRIGGER

#define OSPI_O_IND_AHB_ADDR_TRIGGER 0x0000001CU

§ OSPI_O_DMA_PERIPH_CONFIG

#define OSPI_O_DMA_PERIPH_CONFIG 0x00000020U

§ OSPI_O_REMAP_ADDR

#define OSPI_O_REMAP_ADDR 0x00000024U

§ OSPI_O_MODE_BIT_CONFIG

#define OSPI_O_MODE_BIT_CONFIG 0x00000028U

§ OSPI_O_SRAM_FILL

#define OSPI_O_SRAM_FILL 0x0000002CU

§ OSPI_O_TX_THRESH

#define OSPI_O_TX_THRESH 0x00000030U

§ OSPI_O_RX_THRESH

#define OSPI_O_RX_THRESH 0x00000034U

§ OSPI_O_WRITE_COMPLETION_CTRL

#define OSPI_O_WRITE_COMPLETION_CTRL 0x00000038U

§ OSPI_O_NO_OF_POLLS_BEF_EXP

#define OSPI_O_NO_OF_POLLS_BEF_EXP 0x0000003CU

§ OSPI_O_IRQ_STATUS

#define OSPI_O_IRQ_STATUS 0x00000040U

§ OSPI_O_IRQ_MASK

#define OSPI_O_IRQ_MASK 0x00000044U

§ OSPI_O_LOWER_WR_PROT

#define OSPI_O_LOWER_WR_PROT 0x00000050U

§ OSPI_O_UPPER_WR_PROT

#define OSPI_O_UPPER_WR_PROT 0x00000054U

§ OSPI_O_WR_PROT_CTRL

#define OSPI_O_WR_PROT_CTRL 0x00000058U

§ OSPI_O_INDIRECT_READ_XFER_CTRL

#define OSPI_O_INDIRECT_READ_XFER_CTRL 0x00000060U

§ OSPI_O_INDIRECT_READ_XFER_WATERMARK

#define OSPI_O_INDIRECT_READ_XFER_WATERMARK 0x00000064U

§ OSPI_O_INDIRECT_READ_XFER_START

#define OSPI_O_INDIRECT_READ_XFER_START 0x00000068U

§ OSPI_O_INDIRECT_READ_XFER_NUM_BYTES

#define OSPI_O_INDIRECT_READ_XFER_NUM_BYTES 0x0000006CU

§ OSPI_O_INDIRECT_WRITE_XFER_CTRL

#define OSPI_O_INDIRECT_WRITE_XFER_CTRL 0x00000070U

§ OSPI_O_INDIRECT_WRITE_XFER_WATERMARK

#define OSPI_O_INDIRECT_WRITE_XFER_WATERMARK 0x00000074U

§ OSPI_O_INDIRECT_WRITE_XFER_START

#define OSPI_O_INDIRECT_WRITE_XFER_START 0x00000078U

§ OSPI_O_INDIRECT_WRITE_XFER_NUM_BYTES

#define OSPI_O_INDIRECT_WRITE_XFER_NUM_BYTES 0x0000007CU

§ OSPI_O_INDIRECT_TRIGGER_ADDR_RANGE

#define OSPI_O_INDIRECT_TRIGGER_ADDR_RANGE 0x00000080U

§ OSPI_O_FLASH_COMMAND_CTRL_MEM

#define OSPI_O_FLASH_COMMAND_CTRL_MEM 0x0000008CU

§ OSPI_O_FLASH_CMD_CTRL

#define OSPI_O_FLASH_CMD_CTRL 0x00000090U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_O_FLASH_CMD_ADDR

#define OSPI_O_FLASH_CMD_ADDR 0x00000094U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_O_FLASH_RD_DATA_LOWER

#define OSPI_O_FLASH_RD_DATA_LOWER 0x000000A0U

§ OSPI_O_FLASH_RD_DATA_UPPER

#define OSPI_O_FLASH_RD_DATA_UPPER 0x000000A4U

§ OSPI_O_FLASH_WR_DATA_LOWER

#define OSPI_O_FLASH_WR_DATA_LOWER 0x000000A8U

§ OSPI_O_FLASH_WR_DATA_UPPER

#define OSPI_O_FLASH_WR_DATA_UPPER 0x000000ACU

§ OSPI_O_POLLING_FLASH_STATUS

#define OSPI_O_POLLING_FLASH_STATUS 0x000000B0U

§ OSPI_O_PHY_CONFIGURATION

#define OSPI_O_PHY_CONFIGURATION 0x000000B4U

§ OSPI_O_PHY_MASTER_CONTROL

#define OSPI_O_PHY_MASTER_CONTROL 0x000000B8U

§ OSPI_O_DLL_OBSERVABLE_LOWER

#define OSPI_O_DLL_OBSERVABLE_LOWER 0x000000BCU

§ OSPI_O_DLL_OBSERVABLE_UPPER

#define OSPI_O_DLL_OBSERVABLE_UPPER 0x000000C0U

§ OSPI_O_OPCODE_EXT_LOWER

#define OSPI_O_OPCODE_EXT_LOWER 0x000000E0U

§ OSPI_O_OPCODE_EXT_UPPER

#define OSPI_O_OPCODE_EXT_UPPER 0x000000E4U

§ OSPI_O_MODULE_ID

#define OSPI_O_MODULE_ID 0x000000FCU

§ OSPI_CONFIG_ENB_SPI

#define OSPI_CONFIG_ENB_SPI 0x00000001U

§ OSPI_CONFIG_ENB_SPI_M

#define OSPI_CONFIG_ENB_SPI_M 0x00000001U

§ OSPI_CONFIG_ENB_SPI_S

#define OSPI_CONFIG_ENB_SPI_S 0U

§ OSPI_CONFIG_ENB_SPI_DISABLE

#define OSPI_CONFIG_ENB_SPI_DISABLE 0x00000000U

§ OSPI_CONFIG_ENB_SPI_ENABLE

#define OSPI_CONFIG_ENB_SPI_ENABLE 0x00000001U

§ OSPI_CONFIG_SEL_CLK_POL

#define OSPI_CONFIG_SEL_CLK_POL 0x00000002U

§ OSPI_CONFIG_SEL_CLK_POL_M

#define OSPI_CONFIG_SEL_CLK_POL_M 0x00000002U

§ OSPI_CONFIG_SEL_CLK_POL_S

#define OSPI_CONFIG_SEL_CLK_POL_S 1U

§ OSPI_CONFIG_SEL_CLK_POL_DISABLE

#define OSPI_CONFIG_SEL_CLK_POL_DISABLE 0x00000000U

§ OSPI_CONFIG_SEL_CLK_POL_ENABLE

#define OSPI_CONFIG_SEL_CLK_POL_ENABLE 0x00000002U

§ OSPI_CONFIG_SEL_CLK_PHASE

#define OSPI_CONFIG_SEL_CLK_PHASE 0x00000004U

§ OSPI_CONFIG_SEL_CLK_PHASE_M

#define OSPI_CONFIG_SEL_CLK_PHASE_M 0x00000004U

§ OSPI_CONFIG_SEL_CLK_PHASE_S

#define OSPI_CONFIG_SEL_CLK_PHASE_S 2U

§ OSPI_CONFIG_SEL_CLK_PHASE_DISABLE

#define OSPI_CONFIG_SEL_CLK_PHASE_DISABLE 0x00000000U

§ OSPI_CONFIG_SEL_CLK_PHASE_ENABLE

#define OSPI_CONFIG_SEL_CLK_PHASE_ENABLE 0x00000004U

§ OSPI_CONFIG_PHY_MODE_ENABLE

#define OSPI_CONFIG_PHY_MODE_ENABLE 0x00000008U

§ OSPI_CONFIG_PHY_MODE_ENABLE_M

#define OSPI_CONFIG_PHY_MODE_ENABLE_M 0x00000008U

§ OSPI_CONFIG_PHY_MODE_ENABLE_S

#define OSPI_CONFIG_PHY_MODE_ENABLE_S 3U

§ OSPI_CONFIG_PHY_MODE_ENABLE_DISABLE

#define OSPI_CONFIG_PHY_MODE_ENABLE_DISABLE 0x00000000U

§ OSPI_CONFIG_PHY_MODE_ENABLE_ENABLE

#define OSPI_CONFIG_PHY_MODE_ENABLE_ENABLE 0x00000008U

§ OSPI_CONFIG_HOLD_PIN

#define OSPI_CONFIG_HOLD_PIN 0x00000010U

§ OSPI_CONFIG_HOLD_PIN_M

#define OSPI_CONFIG_HOLD_PIN_M 0x00000010U

§ OSPI_CONFIG_HOLD_PIN_S

#define OSPI_CONFIG_HOLD_PIN_S 4U

§ OSPI_CONFIG_HOLD_PIN_DISABLE

#define OSPI_CONFIG_HOLD_PIN_DISABLE 0x00000000U

§ OSPI_CONFIG_HOLD_PIN_ENABLE

#define OSPI_CONFIG_HOLD_PIN_ENABLE 0x00000010U

§ OSPI_CONFIG_RESET_PIN

#define OSPI_CONFIG_RESET_PIN 0x00000020U

§ OSPI_CONFIG_RESET_PIN_M

#define OSPI_CONFIG_RESET_PIN_M 0x00000020U

§ OSPI_CONFIG_RESET_PIN_S

#define OSPI_CONFIG_RESET_PIN_S 5U

§ OSPI_CONFIG_RESET_PIN_DISABLE

#define OSPI_CONFIG_RESET_PIN_DISABLE 0x00000000U

§ OSPI_CONFIG_RESET_PIN_ENABLE

#define OSPI_CONFIG_RESET_PIN_ENABLE 0x00000020U

§ OSPI_CONFIG_RESET_CFG

#define OSPI_CONFIG_RESET_CFG 0x00000040U

§ OSPI_CONFIG_RESET_CFG_M

#define OSPI_CONFIG_RESET_CFG_M 0x00000040U

§ OSPI_CONFIG_RESET_CFG_S

#define OSPI_CONFIG_RESET_CFG_S 6U

§ OSPI_CONFIG_RESET_CFG_DISABLE

#define OSPI_CONFIG_RESET_CFG_DISABLE 0x00000000U

§ OSPI_CONFIG_RESET_CFG_ENABLE

#define OSPI_CONFIG_RESET_CFG_ENABLE 0x00000040U

§ OSPI_CONFIG_ENB_DIR_ACC_CTLR

#define OSPI_CONFIG_ENB_DIR_ACC_CTLR 0x00000080U

§ OSPI_CONFIG_ENB_DIR_ACC_CTLR_M

#define OSPI_CONFIG_ENB_DIR_ACC_CTLR_M 0x00000080U

§ OSPI_CONFIG_ENB_DIR_ACC_CTLR_S

#define OSPI_CONFIG_ENB_DIR_ACC_CTLR_S 7U

§ OSPI_CONFIG_ENB_DIR_ACC_CTLR_DISABLE

#define OSPI_CONFIG_ENB_DIR_ACC_CTLR_DISABLE 0x00000000U

§ OSPI_CONFIG_ENB_DIR_ACC_CTLR_ENABLE

#define OSPI_CONFIG_ENB_DIR_ACC_CTLR_ENABLE 0x00000080U

§ OSPI_CONFIG_ENB_LEGACY_IP_MODE

#define OSPI_CONFIG_ENB_LEGACY_IP_MODE 0x00000100U

§ OSPI_CONFIG_ENB_LEGACY_IP_MODE_M

#define OSPI_CONFIG_ENB_LEGACY_IP_MODE_M 0x00000100U

§ OSPI_CONFIG_ENB_LEGACY_IP_MODE_S

#define OSPI_CONFIG_ENB_LEGACY_IP_MODE_S 8U

§ OSPI_CONFIG_ENB_LEGACY_IP_MODE_DISABLE

#define OSPI_CONFIG_ENB_LEGACY_IP_MODE_DISABLE 0x00000000U

§ OSPI_CONFIG_ENB_LEGACY_IP_MODE_ENABLE

#define OSPI_CONFIG_ENB_LEGACY_IP_MODE_ENABLE 0x00000100U

§ OSPI_CONFIG_PERIPH_SEL_DEC

#define OSPI_CONFIG_PERIPH_SEL_DEC 0x00000200U

§ OSPI_CONFIG_PERIPH_SEL_DEC_M

#define OSPI_CONFIG_PERIPH_SEL_DEC_M 0x00000200U

§ OSPI_CONFIG_PERIPH_SEL_DEC_S

#define OSPI_CONFIG_PERIPH_SEL_DEC_S 9U

§ OSPI_CONFIG_PERIPH_SEL_DEC_DISABLE

#define OSPI_CONFIG_PERIPH_SEL_DEC_DISABLE 0x00000000U

§ OSPI_CONFIG_PERIPH_SEL_DEC_ENABLE

#define OSPI_CONFIG_PERIPH_SEL_DEC_ENABLE 0x00000200U

§ OSPI_CONFIG_PERIPH_CS_LINES_W

#define OSPI_CONFIG_PERIPH_CS_LINES_W 4U

§ OSPI_CONFIG_PERIPH_CS_LINES_M

#define OSPI_CONFIG_PERIPH_CS_LINES_M 0x00003C00U

§ OSPI_CONFIG_PERIPH_CS_LINES_S

#define OSPI_CONFIG_PERIPH_CS_LINES_S 10U

§ OSPI_CONFIG_PERIPH_CS_LINES_MINIMUM

#define OSPI_CONFIG_PERIPH_CS_LINES_MINIMUM 0x00000000U

§ OSPI_CONFIG_PERIPH_CS_LINES_MAXIMUM

#define OSPI_CONFIG_PERIPH_CS_LINES_MAXIMUM 0x00003C00U

§ OSPI_CONFIG_WR_PROT_FLASH

#define OSPI_CONFIG_WR_PROT_FLASH 0x00004000U

§ OSPI_CONFIG_WR_PROT_FLASH_M

#define OSPI_CONFIG_WR_PROT_FLASH_M 0x00004000U

§ OSPI_CONFIG_WR_PROT_FLASH_S

#define OSPI_CONFIG_WR_PROT_FLASH_S 14U

§ OSPI_CONFIG_WR_PROT_FLASH_DISABLE

#define OSPI_CONFIG_WR_PROT_FLASH_DISABLE 0x00000000U

§ OSPI_CONFIG_WR_PROT_FLASH_ENABLE

#define OSPI_CONFIG_WR_PROT_FLASH_ENABLE 0x00004000U

§ OSPI_CONFIG_ENB_DMA_IF

#define OSPI_CONFIG_ENB_DMA_IF 0x00008000U

§ OSPI_CONFIG_ENB_DMA_IF_M

#define OSPI_CONFIG_ENB_DMA_IF_M 0x00008000U

§ OSPI_CONFIG_ENB_DMA_IF_S

#define OSPI_CONFIG_ENB_DMA_IF_S 15U

§ OSPI_CONFIG_ENB_DMA_IF_DISABLE

#define OSPI_CONFIG_ENB_DMA_IF_DISABLE 0x00000000U

§ OSPI_CONFIG_ENB_DMA_IF_ENABLE

#define OSPI_CONFIG_ENB_DMA_IF_ENABLE 0x00008000U

§ OSPI_CONFIG_ENB_AHB_ADDR_REMAP

#define OSPI_CONFIG_ENB_AHB_ADDR_REMAP 0x00010000U

§ OSPI_CONFIG_ENB_AHB_ADDR_REMAP_M

#define OSPI_CONFIG_ENB_AHB_ADDR_REMAP_M 0x00010000U

§ OSPI_CONFIG_ENB_AHB_ADDR_REMAP_S

#define OSPI_CONFIG_ENB_AHB_ADDR_REMAP_S 16U

§ OSPI_CONFIG_ENB_AHB_ADDR_REMAP_DISABLE

#define OSPI_CONFIG_ENB_AHB_ADDR_REMAP_DISABLE 0x00000000U

§ OSPI_CONFIG_ENB_AHB_ADDR_REMAP_ENABLE

#define OSPI_CONFIG_ENB_AHB_ADDR_REMAP_ENABLE 0x00010000U

§ OSPI_CONFIG_ENTER_XIP_MODE

#define OSPI_CONFIG_ENTER_XIP_MODE 0x00020000U

§ OSPI_CONFIG_ENTER_XIP_MODE_M

#define OSPI_CONFIG_ENTER_XIP_MODE_M 0x00020000U

§ OSPI_CONFIG_ENTER_XIP_MODE_S

#define OSPI_CONFIG_ENTER_XIP_MODE_S 17U

§ OSPI_CONFIG_ENTER_XIP_MODE_DISABLE

#define OSPI_CONFIG_ENTER_XIP_MODE_DISABLE 0x00000000U

§ OSPI_CONFIG_ENTER_XIP_MODE_ENABLE

#define OSPI_CONFIG_ENTER_XIP_MODE_ENABLE 0x00020000U

§ OSPI_CONFIG_ENTER_XIP_MODE_IMM

#define OSPI_CONFIG_ENTER_XIP_MODE_IMM 0x00040000U

§ OSPI_CONFIG_ENTER_XIP_MODE_IMM_M

#define OSPI_CONFIG_ENTER_XIP_MODE_IMM_M 0x00040000U

§ OSPI_CONFIG_ENTER_XIP_MODE_IMM_S

#define OSPI_CONFIG_ENTER_XIP_MODE_IMM_S 18U

§ OSPI_CONFIG_ENTER_XIP_MODE_IMM_DISABLE

#define OSPI_CONFIG_ENTER_XIP_MODE_IMM_DISABLE 0x00000000U

§ OSPI_CONFIG_ENTER_XIP_MODE_IMM_ENABLE

#define OSPI_CONFIG_ENTER_XIP_MODE_IMM_ENABLE 0x00040000U

§ OSPI_CONFIG_MSTR_BAUD_DIV_W

#define OSPI_CONFIG_MSTR_BAUD_DIV_W 4U

§ OSPI_CONFIG_MSTR_BAUD_DIV_M

#define OSPI_CONFIG_MSTR_BAUD_DIV_M 0x00780000U

§ OSPI_CONFIG_MSTR_BAUD_DIV_S

#define OSPI_CONFIG_MSTR_BAUD_DIV_S 19U

§ OSPI_CONFIG_MSTR_BAUD_DIV_MINIMUM

#define OSPI_CONFIG_MSTR_BAUD_DIV_MINIMUM 0x00000000U

§ OSPI_CONFIG_MSTR_BAUD_DIV_MAXIMUM

#define OSPI_CONFIG_MSTR_BAUD_DIV_MAXIMUM 0x00780000U

§ OSPI_CONFIG_ENABLE_AHB_DECODER

#define OSPI_CONFIG_ENABLE_AHB_DECODER 0x00800000U

§ OSPI_CONFIG_ENABLE_AHB_DECODER_M

#define OSPI_CONFIG_ENABLE_AHB_DECODER_M 0x00800000U

§ OSPI_CONFIG_ENABLE_AHB_DECODER_S

#define OSPI_CONFIG_ENABLE_AHB_DECODER_S 23U

§ OSPI_CONFIG_ENABLE_AHB_DECODER_DISABLE

#define OSPI_CONFIG_ENABLE_AHB_DECODER_DISABLE 0x00000000U

§ OSPI_CONFIG_ENABLE_AHB_DECODER_ENABLE

#define OSPI_CONFIG_ENABLE_AHB_DECODER_ENABLE 0x00800000U

§ OSPI_CONFIG_ENABLE_DTR_PROTOCOL

#define OSPI_CONFIG_ENABLE_DTR_PROTOCOL 0x01000000U

§ OSPI_CONFIG_ENABLE_DTR_PROTOCOL_M

#define OSPI_CONFIG_ENABLE_DTR_PROTOCOL_M 0x01000000U

§ OSPI_CONFIG_ENABLE_DTR_PROTOCOL_S

#define OSPI_CONFIG_ENABLE_DTR_PROTOCOL_S 24U

§ OSPI_CONFIG_ENABLE_DTR_PROTOCOL_DISABLE

#define OSPI_CONFIG_ENABLE_DTR_PROTOCOL_DISABLE 0x00000000U

§ OSPI_CONFIG_ENABLE_DTR_PROTOCOL_ENABLE

#define OSPI_CONFIG_ENABLE_DTR_PROTOCOL_ENABLE 0x01000000U

§ OSPI_CONFIG_PIPELINE_PHY

#define OSPI_CONFIG_PIPELINE_PHY 0x02000000U

§ OSPI_CONFIG_PIPELINE_PHY_M

#define OSPI_CONFIG_PIPELINE_PHY_M 0x02000000U

§ OSPI_CONFIG_PIPELINE_PHY_S

#define OSPI_CONFIG_PIPELINE_PHY_S 25U

§ OSPI_CONFIG_PIPELINE_PHY_DISABLE

#define OSPI_CONFIG_PIPELINE_PHY_DISABLE 0x00000000U

§ OSPI_CONFIG_PIPELINE_PHY_ENABLE

#define OSPI_CONFIG_PIPELINE_PHY_ENABLE 0x02000000U

§ OSPI_CONFIG_CRC_ENABLE

#define OSPI_CONFIG_CRC_ENABLE 0x20000000U

§ OSPI_CONFIG_CRC_ENABLE_M

#define OSPI_CONFIG_CRC_ENABLE_M 0x20000000U

§ OSPI_CONFIG_CRC_ENABLE_S

#define OSPI_CONFIG_CRC_ENABLE_S 29U

§ OSPI_CONFIG_CRC_ENABLE_DISABLE

#define OSPI_CONFIG_CRC_ENABLE_DISABLE 0x00000000U

§ OSPI_CONFIG_CRC_ENABLE_ENABLE

#define OSPI_CONFIG_CRC_ENABLE_ENABLE 0x20000000U

§ OSPI_CONFIG_DUAL_BYTE_OPCODE_EN

#define OSPI_CONFIG_DUAL_BYTE_OPCODE_EN 0x40000000U

§ OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_M

#define OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_M 0x40000000U

§ OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_S

#define OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_S 30U

§ OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_DISABLE

#define OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_DISABLE 0x00000000U

§ OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_ENABLE

#define OSPI_CONFIG_DUAL_BYTE_OPCODE_EN_ENABLE 0x40000000U

§ OSPI_CONFIG_IDLE

#define OSPI_CONFIG_IDLE 0x80000000U

§ OSPI_CONFIG_IDLE_M

#define OSPI_CONFIG_IDLE_M 0x80000000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_CONFIG_IDLE_S

#define OSPI_CONFIG_IDLE_S 31U

§ OSPI_CONFIG_IDLE_DISABLE

#define OSPI_CONFIG_IDLE_DISABLE 0x00000000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_CONFIG_IDLE_ENABLE

#define OSPI_CONFIG_IDLE_ENABLE 0x80000000U

§ OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_W

#define OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_W 8U

§ OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_M

#define OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_M 0x000000FFU

§ OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_S

#define OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_S 0U

§ OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_MINIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_MAXIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_RD_OPCODE_NON_XIP_MAXIMUM 0x000000FFU

§ OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_W

#define OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_W 2U

§ OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_M

#define OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_M 0x00000300U

§ OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_S

#define OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_S 8U

§ OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_MINIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_MAXIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_INSTR_TYPE_MAXIMUM 0x00000300U

§ OSPI_DEV_INSTR_RD_CONFIG_DDR_EN

#define OSPI_DEV_INSTR_RD_CONFIG_DDR_EN 0x00000400U

§ OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_M

#define OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_M 0x00000400U

§ OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_S

#define OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_S 10U

§ OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_DISABLE

#define OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_DISABLE 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_ENABLE

#define OSPI_DEV_INSTR_RD_CONFIG_DDR_EN_ENABLE 0x00000400U

§ OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS

#define OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS 0x00000800U

§ OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_M

#define OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_M 0x00000800U

§ OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_S

#define OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_S 11U

§ OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_DISABLE

#define OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_DISABLE 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_ENABLE

#define OSPI_DEV_INSTR_RD_CONFIG_PRED_DIS_ENABLE 0x00000800U

§ OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_W

#define OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_W 2U

§ OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_M

#define OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_M 0x00003000U

§ OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_S

#define OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_S 12U

§ OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_MINIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_MAXIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_ADDR_XFER_TYPE_STD_MODE_MAXIMUM 0x00003000U

§ OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_W

#define OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_W 2U

§ OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_M

#define OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_M 0x00030000U

§ OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_S

#define OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_S 16U

§ OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_MINIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_MAXIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_DATA_XFER_TYPE_EXT_MODE_MAXIMUM 0x00030000U

§ OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE

#define OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE 0x00100000U

§ OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_M

#define OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_M 0x00100000U

§ OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_S

#define OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_S 20U

§ OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_DISABLE

#define OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_DISABLE 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_ENABLE

#define OSPI_DEV_INSTR_RD_CONFIG_MODE_BIT_ENABLE_ENABLE 0x00100000U

§ OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_W

#define OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_W 5U

§ OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_M

#define OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_M 0x1F000000U

§ OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_S

#define OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_S 24U

§ OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_MINIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_MAXIMUM

#define OSPI_DEV_INSTR_RD_CONFIG_DUMMY_RD_CLK_CYCLES_MAXIMUM 0x1F000000U

§ OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_W

#define OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_W 8U

§ OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_M

#define OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_M 0x000000FFU

§ OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_S

#define OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_S 0U

§ OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_MINIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_MAXIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_WR_OPCODE_MAXIMUM 0x000000FFU

§ OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS

#define OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS 0x00000100U

§ OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_M

#define OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_M 0x00000100U

§ OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_S

#define OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_S 8U

§ OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_DISABLE

#define OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_DISABLE 0x00000000U

§ OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_ENABLE

#define OSPI_DEV_INSTR_WR_CONFIG_WEL_DIS_ENABLE 0x00000100U

§ OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_W

#define OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_W 2U

§ OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_M

#define OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_M 0x00003000U

§ OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_S

#define OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_S 12U

§ OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_MINIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_MAXIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_ADDR_XFER_TYPE_STD_MODE_MAXIMUM 0x00003000U

§ OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_W

#define OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_W 2U

§ OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_M

#define OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_M 0x00030000U

§ OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_S

#define OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_S 16U

§ OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_MINIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_MAXIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_DATA_XFER_TYPE_EXT_MODE_MAXIMUM 0x00030000U

§ OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_W

#define OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_W 5U

§ OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_M

#define OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_M 0x1F000000U

§ OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_S

#define OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_S 24U

§ OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_MINIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_MINIMUM 0x00000000U

§ OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_MAXIMUM

#define OSPI_DEV_INSTR_WR_CONFIG_DUMMY_WR_CLK_CYCLES_MAXIMUM 0x1F000000U

§ OSPI_DEV_DELAY_D_INIT_W

#define OSPI_DEV_DELAY_D_INIT_W 8U

§ OSPI_DEV_DELAY_D_INIT_M

#define OSPI_DEV_DELAY_D_INIT_M 0x000000FFU

§ OSPI_DEV_DELAY_D_INIT_S

#define OSPI_DEV_DELAY_D_INIT_S 0U

§ OSPI_DEV_DELAY_D_INIT_MINIMUM

#define OSPI_DEV_DELAY_D_INIT_MINIMUM 0x00000000U

§ OSPI_DEV_DELAY_D_INIT_MAXIMUM

#define OSPI_DEV_DELAY_D_INIT_MAXIMUM 0x000000FFU

§ OSPI_DEV_DELAY_D_AFTER_W

#define OSPI_DEV_DELAY_D_AFTER_W 8U

§ OSPI_DEV_DELAY_D_AFTER_M

#define OSPI_DEV_DELAY_D_AFTER_M 0x0000FF00U

§ OSPI_DEV_DELAY_D_AFTER_S

#define OSPI_DEV_DELAY_D_AFTER_S 8U

§ OSPI_DEV_DELAY_D_AFTER_MINIMUM

#define OSPI_DEV_DELAY_D_AFTER_MINIMUM 0x00000000U

§ OSPI_DEV_DELAY_D_AFTER_MAXIMUM

#define OSPI_DEV_DELAY_D_AFTER_MAXIMUM 0x0000FF00U

§ OSPI_DEV_DELAY_D_BTWN_W

#define OSPI_DEV_DELAY_D_BTWN_W 8U

§ OSPI_DEV_DELAY_D_BTWN_M

#define OSPI_DEV_DELAY_D_BTWN_M 0x00FF0000U

§ OSPI_DEV_DELAY_D_BTWN_S

#define OSPI_DEV_DELAY_D_BTWN_S 16U

§ OSPI_DEV_DELAY_D_BTWN_MINIMUM

#define OSPI_DEV_DELAY_D_BTWN_MINIMUM 0x00000000U

§ OSPI_DEV_DELAY_D_BTWN_MAXIMUM

#define OSPI_DEV_DELAY_D_BTWN_MAXIMUM 0x00FF0000U

§ OSPI_DEV_DELAY_D_NSS_W

#define OSPI_DEV_DELAY_D_NSS_W 8U

§ OSPI_DEV_DELAY_D_NSS_M

#define OSPI_DEV_DELAY_D_NSS_M 0xFF000000U

§ OSPI_DEV_DELAY_D_NSS_S

#define OSPI_DEV_DELAY_D_NSS_S 24U

§ OSPI_DEV_DELAY_D_NSS_MINIMUM

#define OSPI_DEV_DELAY_D_NSS_MINIMUM 0x00000000U

§ OSPI_DEV_DELAY_D_NSS_MAXIMUM

#define OSPI_DEV_DELAY_D_NSS_MAXIMUM 0xFF000000U

§ OSPI_RD_DATA_CAPTURE_BYPASS

#define OSPI_RD_DATA_CAPTURE_BYPASS 0x00000001U

§ OSPI_RD_DATA_CAPTURE_BYPASS_M

#define OSPI_RD_DATA_CAPTURE_BYPASS_M 0x00000001U

§ OSPI_RD_DATA_CAPTURE_BYPASS_S

#define OSPI_RD_DATA_CAPTURE_BYPASS_S 0U

§ OSPI_RD_DATA_CAPTURE_BYPASS_DISABLE

#define OSPI_RD_DATA_CAPTURE_BYPASS_DISABLE 0x00000000U

§ OSPI_RD_DATA_CAPTURE_BYPASS_ENABLE

#define OSPI_RD_DATA_CAPTURE_BYPASS_ENABLE 0x00000001U

§ OSPI_RD_DATA_CAPTURE_DELAY_W

#define OSPI_RD_DATA_CAPTURE_DELAY_W 4U

§ OSPI_RD_DATA_CAPTURE_DELAY_M

#define OSPI_RD_DATA_CAPTURE_DELAY_M 0x0000001EU

§ OSPI_RD_DATA_CAPTURE_DELAY_S

#define OSPI_RD_DATA_CAPTURE_DELAY_S 1U

§ OSPI_RD_DATA_CAPTURE_DELAY_MINIMUM

#define OSPI_RD_DATA_CAPTURE_DELAY_MINIMUM 0x00000000U

§ OSPI_RD_DATA_CAPTURE_DELAY_MAXIMUM

#define OSPI_RD_DATA_CAPTURE_DELAY_MAXIMUM 0x0000001EU

§ OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL

#define OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL 0x00000020U

§ OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_M

#define OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_M 0x00000020U

§ OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_S

#define OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_S 5U

§ OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_DISABLE

#define OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_DISABLE 0x00000000U

§ OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_ENABLE

#define OSPI_RD_DATA_CAPTURE_SAMPLE_EDGE_SEL_ENABLE 0x00000020U

§ OSPI_RD_DATA_CAPTURE_DQS_ENABLE

#define OSPI_RD_DATA_CAPTURE_DQS_ENABLE 0x00000100U

§ OSPI_RD_DATA_CAPTURE_DQS_ENABLE_M

#define OSPI_RD_DATA_CAPTURE_DQS_ENABLE_M 0x00000100U

§ OSPI_RD_DATA_CAPTURE_DQS_ENABLE_S

#define OSPI_RD_DATA_CAPTURE_DQS_ENABLE_S 8U

§ OSPI_RD_DATA_CAPTURE_DQS_ENABLE_DISABLE

#define OSPI_RD_DATA_CAPTURE_DQS_ENABLE_DISABLE 0x00000000U

§ OSPI_RD_DATA_CAPTURE_DQS_ENABLE_ENABLE

#define OSPI_RD_DATA_CAPTURE_DQS_ENABLE_ENABLE 0x00000100U

§ OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_W

#define OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_W 4U

§ OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_M

#define OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_M 0x000F0000U

§ OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_S

#define OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_S 16U

§ OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_MINIMUM

#define OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_MINIMUM 0x00000000U

§ OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_MAXIMUM

#define OSPI_RD_DATA_CAPTURE_DDR_READ_DELAY_MAXIMUM 0x000F0000U

§ OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_W

#define OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_W 4U

§ OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_M

#define OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_M 0x0000000FU

§ OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_S

#define OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_S 0U

§ OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_NUM_ADDR_BYTES_MAXIMUM 0x0000000FU

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_W

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_W 12U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_M

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_M 0x0000FFF0U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_S

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_S 4U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_DEVICE_PAGE_MAXIMUM 0x0000FFF0U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_W

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_W 5U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_M

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_M 0x001F0000U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_S

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_S 16U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_BYTES_PER_SUBSECTOR_MAXIMUM 0x001F0000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_W

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_W 2U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_M

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_M 0x00600000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_S

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_S 21U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS0_MAXIMUM 0x00600000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_W

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_W 2U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_M

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_M 0x01800000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_S

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_S 23U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS1_MAXIMUM 0x01800000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_W

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_W 2U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_M

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_M 0x06000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_S

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_S 25U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS2_MAXIMUM 0x06000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_W

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_W 2U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_M

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_M 0x18000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_S

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_S 27U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_MINIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_MINIMUM 0x00000000U

§ OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_MAXIMUM

#define OSPI_DEV_SIZE_CONFIG_MEM_SIZE_ON_CS3_MAXIMUM 0x18000000U

§ OSPI_SRAM_PARTITION_CFG_THRESHOLD_W

#define OSPI_SRAM_PARTITION_CFG_THRESHOLD_W 8U

§ OSPI_SRAM_PARTITION_CFG_THRESHOLD_M

#define OSPI_SRAM_PARTITION_CFG_THRESHOLD_M 0x000000FFU

§ OSPI_SRAM_PARTITION_CFG_THRESHOLD_S

#define OSPI_SRAM_PARTITION_CFG_THRESHOLD_S 0U

§ OSPI_IND_AHB_ADDR_TRIGGER_ADDR_W

#define OSPI_IND_AHB_ADDR_TRIGGER_ADDR_W 32U

§ OSPI_IND_AHB_ADDR_TRIGGER_ADDR_M

#define OSPI_IND_AHB_ADDR_TRIGGER_ADDR_M 0xFFFFFFFFU

§ OSPI_IND_AHB_ADDR_TRIGGER_ADDR_S

#define OSPI_IND_AHB_ADDR_TRIGGER_ADDR_S 0U

§ OSPI_IND_AHB_ADDR_TRIGGER_ADDR_MINIMUM

#define OSPI_IND_AHB_ADDR_TRIGGER_ADDR_MINIMUM 0x00000000U

§ OSPI_IND_AHB_ADDR_TRIGGER_ADDR_MAXIMUM

#define OSPI_IND_AHB_ADDR_TRIGGER_ADDR_MAXIMUM 0xFFFFFFFFU

§ OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_W

#define OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_W 4U

§ OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_M

#define OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_M 0x0000000FU

§ OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_S

#define OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_S 0U

§ OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_MINIMUM

#define OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_MINIMUM 0x00000000U

§ OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_MAXIMUM

#define OSPI_DMA_PERIPH_CONFIG_NUM_SINGLE_REQ_BYTES_MAXIMUM 0x0000000FU

§ OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_W

#define OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_W 4U

§ OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_M

#define OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_M 0x00000F00U

§ OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_S

#define OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_S 8U

§ OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_MINIMUM

#define OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_MINIMUM 0x00000000U

§ OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_MAXIMUM

#define OSPI_DMA_PERIPH_CONFIG_NUM_BURST_REQ_BYTES_MAXIMUM 0x00000F00U

§ OSPI_REMAP_ADDR_VALUE_W

#define OSPI_REMAP_ADDR_VALUE_W 32U

§ OSPI_REMAP_ADDR_VALUE_M

#define OSPI_REMAP_ADDR_VALUE_M 0xFFFFFFFFU

§ OSPI_REMAP_ADDR_VALUE_S

#define OSPI_REMAP_ADDR_VALUE_S 0U

§ OSPI_REMAP_ADDR_VALUE_MINIMUM

#define OSPI_REMAP_ADDR_VALUE_MINIMUM 0x00000000U

§ OSPI_REMAP_ADDR_VALUE_MAXIMUM

#define OSPI_REMAP_ADDR_VALUE_MAXIMUM 0xFFFFFFFFU

§ OSPI_MODE_BIT_CONFIG_MODE_W

#define OSPI_MODE_BIT_CONFIG_MODE_W 8U

§ OSPI_MODE_BIT_CONFIG_MODE_M

#define OSPI_MODE_BIT_CONFIG_MODE_M 0x000000FFU

§ OSPI_MODE_BIT_CONFIG_MODE_S

#define OSPI_MODE_BIT_CONFIG_MODE_S 0U

§ OSPI_MODE_BIT_CONFIG_MODE_MINIMUM

#define OSPI_MODE_BIT_CONFIG_MODE_MINIMUM 0x00000000U

§ OSPI_MODE_BIT_CONFIG_MODE_MAXIMUM

#define OSPI_MODE_BIT_CONFIG_MODE_MAXIMUM 0x000000FFU

§ OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_W

#define OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_W 3U

§ OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_M

#define OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_M 0x00000700U

§ OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_S

#define OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_S 8U

§ OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_MINIMUM

#define OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_MINIMUM 0x00000000U

§ OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_MAXIMUM

#define OSPI_MODE_BIT_CONFIG_CHUNK_SIZE_MAXIMUM 0x00000700U

§ OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE

#define OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE 0x00008000U

§ OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_M

#define OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_M 0x00008000U

§ OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_S

#define OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_S 15U

§ OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_DISABLE

#define OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_DISABLE 0x00000000U

§ OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_ENABLE

#define OSPI_MODE_BIT_CONFIG_CRC_OUT_ENABLE_ENABLE 0x00008000U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_W

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_W 8U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_M

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_M 0x00FF0000U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_S

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_S 16U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_MINIMUM

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_MINIMUM 0x00000000U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_MAXIMUM

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_UP_MAXIMUM 0x00FF0000U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_W

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_W 8U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_M

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_M 0xFF000000U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_S

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_S 24U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_MINIMUM

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_MINIMUM 0x00000000U

§ OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_MAXIMUM

#define OSPI_MODE_BIT_CONFIG_RX_CRC_DATA_LOW_MAXIMUM 0xFF000000U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_W

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_W 16U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_M

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_M 0x0000FFFFU

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_S

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_S 0U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_MINIMUM

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_MINIMUM 0x00000000U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_MAXIMUM

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_READ_MAXIMUM 0x0000FFFFU

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_W

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_W 16U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_M

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_M 0xFFFF0000U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_S

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_S 16U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_MINIMUM

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_MINIMUM 0x00000000U

§ OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_MAXIMUM

#define OSPI_SRAM_FILL_SRAM_FILL_INDAC_WRITE_MAXIMUM 0xFFFF0000U

§ OSPI_TX_THRESH_LEVEL_W

#define OSPI_TX_THRESH_LEVEL_W 5U

§ OSPI_TX_THRESH_LEVEL_M

#define OSPI_TX_THRESH_LEVEL_M 0x0000001FU

§ OSPI_TX_THRESH_LEVEL_S

#define OSPI_TX_THRESH_LEVEL_S 0U

§ OSPI_TX_THRESH_LEVEL_MINIMUM

#define OSPI_TX_THRESH_LEVEL_MINIMUM 0x00000000U

§ OSPI_TX_THRESH_LEVEL_MAXIMUM

#define OSPI_TX_THRESH_LEVEL_MAXIMUM 0x0000001FU

§ OSPI_RX_THRESH_LEVEL_W

#define OSPI_RX_THRESH_LEVEL_W 5U

§ OSPI_RX_THRESH_LEVEL_M

#define OSPI_RX_THRESH_LEVEL_M 0x0000001FU

§ OSPI_RX_THRESH_LEVEL_S

#define OSPI_RX_THRESH_LEVEL_S 0U

§ OSPI_RX_THRESH_LEVEL_MINIMUM

#define OSPI_RX_THRESH_LEVEL_MINIMUM 0x00000000U

§ OSPI_RX_THRESH_LEVEL_MAXIMUM

#define OSPI_RX_THRESH_LEVEL_MAXIMUM 0x0000001FU

§ OSPI_WRITE_COMPLETION_CTRL_OPCODE_W

#define OSPI_WRITE_COMPLETION_CTRL_OPCODE_W 8U

§ OSPI_WRITE_COMPLETION_CTRL_OPCODE_M

#define OSPI_WRITE_COMPLETION_CTRL_OPCODE_M 0x000000FFU

§ OSPI_WRITE_COMPLETION_CTRL_OPCODE_S

#define OSPI_WRITE_COMPLETION_CTRL_OPCODE_S 0U

§ OSPI_WRITE_COMPLETION_CTRL_OPCODE_MINIMUM

#define OSPI_WRITE_COMPLETION_CTRL_OPCODE_MINIMUM 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_OPCODE_MAXIMUM

#define OSPI_WRITE_COMPLETION_CTRL_OPCODE_MAXIMUM 0x000000FFU

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_W

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_W 3U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_M

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_M 0x00000700U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_S

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_S 8U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_MINIMUM

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_MINIMUM 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_MAXIMUM

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_BIT_INDEX_MAXIMUM 0x00000700U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN 0x00000800U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_M

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_M 0x00000800U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_S

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_S 11U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_DISABLE

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_DISABLE 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_ENABLE

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_ADDR_EN_ENABLE 0x00000800U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY 0x00002000U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_M

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_M 0x00002000U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_S

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_S 13U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_DISABLE

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_DISABLE 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_ENABLE

#define OSPI_WRITE_COMPLETION_CTRL_POLLING_POLARITY_ENABLE 0x00002000U

§ OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING

#define OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING 0x00004000U

§ OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_M

#define OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_M 0x00004000U

§ OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_S

#define OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_S 14U

§ OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_DISABLE

#define OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_DISABLE 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_ENABLE

#define OSPI_WRITE_COMPLETION_CTRL_DISABLE_POLLING_ENABLE 0x00004000U

§ OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP

#define OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP 0x00008000U

§ OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_M

#define OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_M 0x00008000U

§ OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_S

#define OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_S 15U

§ OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_DISABLE

#define OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_DISABLE 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_ENABLE

#define OSPI_WRITE_COMPLETION_CTRL_ENABLE_POLLING_EXP_ENABLE 0x00008000U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_W

#define OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_W 8U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_M

#define OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_M 0x00FF0000U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_S

#define OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_S 16U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_MINIMUM

#define OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_MINIMUM 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_MAXIMUM

#define OSPI_WRITE_COMPLETION_CTRL_POLL_COUNT_MAXIMUM 0x00FF0000U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_W

#define OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_W 8U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_M

#define OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_M 0xFF000000U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_S

#define OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_S 24U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_MINIMUM

#define OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_MINIMUM 0x00000000U

§ OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_MAXIMUM

#define OSPI_WRITE_COMPLETION_CTRL_POLL_REP_DELAY_MAXIMUM 0xFF000000U

§ OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_W

#define OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_W 32U

§ OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_M

#define OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_M 0xFFFFFFFFU

§ OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_S

#define OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_S 0U

§ OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_MINIMUM

#define OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_MINIMUM 0x00000000U

§ OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_MAXIMUM

#define OSPI_NO_OF_POLLS_BEF_EXP_NO_OF_POLLS_BEF_EXP_MAXIMUM 0xFFFFFFFFU

§ OSPI_IRQ_STATUS_MODE_M_FAIL

#define OSPI_IRQ_STATUS_MODE_M_FAIL 0x00000001U

§ OSPI_IRQ_STATUS_MODE_M_FAIL_M

#define OSPI_IRQ_STATUS_MODE_M_FAIL_M 0x00000001U

§ OSPI_IRQ_STATUS_MODE_M_FAIL_S

#define OSPI_IRQ_STATUS_MODE_M_FAIL_S 0U

§ OSPI_IRQ_STATUS_MODE_M_FAIL_DISABLE

#define OSPI_IRQ_STATUS_MODE_M_FAIL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_MODE_M_FAIL_ENABLE

#define OSPI_IRQ_STATUS_MODE_M_FAIL_ENABLE 0x00000001U

§ OSPI_IRQ_STATUS_UNDERFLOW_DET

#define OSPI_IRQ_STATUS_UNDERFLOW_DET 0x00000002U

§ OSPI_IRQ_STATUS_UNDERFLOW_DET_M

#define OSPI_IRQ_STATUS_UNDERFLOW_DET_M 0x00000002U

§ OSPI_IRQ_STATUS_UNDERFLOW_DET_S

#define OSPI_IRQ_STATUS_UNDERFLOW_DET_S 1U

§ OSPI_IRQ_STATUS_UNDERFLOW_DET_DISABLE

#define OSPI_IRQ_STATUS_UNDERFLOW_DET_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_UNDERFLOW_DET_ENABLE

#define OSPI_IRQ_STATUS_UNDERFLOW_DET_ENABLE 0x00000002U

§ OSPI_IRQ_STATUS_INDIRECT_OP_DONE

#define OSPI_IRQ_STATUS_INDIRECT_OP_DONE 0x00000004U

§ OSPI_IRQ_STATUS_INDIRECT_OP_DONE_M

#define OSPI_IRQ_STATUS_INDIRECT_OP_DONE_M 0x00000004U

§ OSPI_IRQ_STATUS_INDIRECT_OP_DONE_S

#define OSPI_IRQ_STATUS_INDIRECT_OP_DONE_S 2U

§ OSPI_IRQ_STATUS_INDIRECT_OP_DONE_DISABLE

#define OSPI_IRQ_STATUS_INDIRECT_OP_DONE_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_INDIRECT_OP_DONE_ENABLE

#define OSPI_IRQ_STATUS_INDIRECT_OP_DONE_ENABLE 0x00000004U

§ OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT

#define OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT 0x00000008U

§ OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_M

#define OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_M 0x00000008U

§ OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_S

#define OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_S 3U

§ OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_DISABLE

#define OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_ENABLE

#define OSPI_IRQ_STATUS_INDIRECT_TRANSFER_REJECT_ENABLE 0x00000008U

§ OSPI_IRQ_STATUS_PROT_WR_ATTEMPT

#define OSPI_IRQ_STATUS_PROT_WR_ATTEMPT 0x00000010U

§ OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_M

#define OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_M 0x00000010U

§ OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_S

#define OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_S 4U

§ OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_DISABLE

#define OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_ENABLE

#define OSPI_IRQ_STATUS_PROT_WR_ATTEMPT_ENABLE 0x00000010U

§ OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET

#define OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET 0x00000020U

§ OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_M

#define OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_M 0x00000020U

§ OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_S

#define OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_S 5U

§ OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_DISABLE

#define OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_ENABLE

#define OSPI_IRQ_STATUS_ILLEGAL_ACCESS_DET_ENABLE 0x00000020U

§ OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH

#define OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH 0x00000040U

§ OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_M

#define OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_M 0x00000040U

§ OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_S

#define OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_S 6U

§ OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_DISABLE

#define OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_ENABLE

#define OSPI_IRQ_STATUS_INDIRECT_XFER_LEVEL_BREACH_ENABLE 0x00000040U

§ OSPI_IRQ_STATUS_RECV_OVERFLOW

#define OSPI_IRQ_STATUS_RECV_OVERFLOW 0x00000080U

§ OSPI_IRQ_STATUS_RECV_OVERFLOW_M

#define OSPI_IRQ_STATUS_RECV_OVERFLOW_M 0x00000080U

§ OSPI_IRQ_STATUS_RECV_OVERFLOW_S

#define OSPI_IRQ_STATUS_RECV_OVERFLOW_S 7U

§ OSPI_IRQ_STATUS_RECV_OVERFLOW_DISABLE

#define OSPI_IRQ_STATUS_RECV_OVERFLOW_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_RECV_OVERFLOW_ENABLE

#define OSPI_IRQ_STATUS_RECV_OVERFLOW_ENABLE 0x00000080U

§ OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL

#define OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL 0x00000100U

§ OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_M

#define OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_M 0x00000100U

§ OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_S

#define OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_S 8U

§ OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_DISABLE

#define OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_ENABLE

#define OSPI_IRQ_STATUS_TX_FIFO_NOT_FULL_ENABLE 0x00000100U

§ OSPI_IRQ_STATUS_TX_FIFO_FULL

#define OSPI_IRQ_STATUS_TX_FIFO_FULL 0x00000200U

§ OSPI_IRQ_STATUS_TX_FIFO_FULL_M

#define OSPI_IRQ_STATUS_TX_FIFO_FULL_M 0x00000200U

§ OSPI_IRQ_STATUS_TX_FIFO_FULL_S

#define OSPI_IRQ_STATUS_TX_FIFO_FULL_S 9U

§ OSPI_IRQ_STATUS_TX_FIFO_FULL_DISABLE

#define OSPI_IRQ_STATUS_TX_FIFO_FULL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_TX_FIFO_FULL_ENABLE

#define OSPI_IRQ_STATUS_TX_FIFO_FULL_ENABLE 0x00000200U

§ OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY

#define OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY 0x00000400U

§ OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_M

#define OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_M 0x00000400U

§ OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_S

#define OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_S 10U

§ OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_DISABLE

#define OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_ENABLE

#define OSPI_IRQ_STATUS_RX_FIFO_NOT_EMPTY_ENABLE 0x00000400U

§ OSPI_IRQ_STATUS_RX_FIFO_FULL

#define OSPI_IRQ_STATUS_RX_FIFO_FULL 0x00000800U

§ OSPI_IRQ_STATUS_RX_FIFO_FULL_M

#define OSPI_IRQ_STATUS_RX_FIFO_FULL_M 0x00000800U

§ OSPI_IRQ_STATUS_RX_FIFO_FULL_S

#define OSPI_IRQ_STATUS_RX_FIFO_FULL_S 11U

§ OSPI_IRQ_STATUS_RX_FIFO_FULL_DISABLE

#define OSPI_IRQ_STATUS_RX_FIFO_FULL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_RX_FIFO_FULL_ENABLE

#define OSPI_IRQ_STATUS_RX_FIFO_FULL_ENABLE 0x00000800U

§ OSPI_IRQ_STATUS_INDRD_SRAM_FULL

#define OSPI_IRQ_STATUS_INDRD_SRAM_FULL 0x00001000U

§ OSPI_IRQ_STATUS_INDRD_SRAM_FULL_M

#define OSPI_IRQ_STATUS_INDRD_SRAM_FULL_M 0x00001000U

§ OSPI_IRQ_STATUS_INDRD_SRAM_FULL_S

#define OSPI_IRQ_STATUS_INDRD_SRAM_FULL_S 12U

§ OSPI_IRQ_STATUS_INDRD_SRAM_FULL_DISABLE

#define OSPI_IRQ_STATUS_INDRD_SRAM_FULL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_INDRD_SRAM_FULL_ENABLE

#define OSPI_IRQ_STATUS_INDRD_SRAM_FULL_ENABLE 0x00001000U

§ OSPI_IRQ_STATUS_POLL_EXP_INT

#define OSPI_IRQ_STATUS_POLL_EXP_INT 0x00002000U

§ OSPI_IRQ_STATUS_POLL_EXP_INT_M

#define OSPI_IRQ_STATUS_POLL_EXP_INT_M 0x00002000U

§ OSPI_IRQ_STATUS_POLL_EXP_INT_S

#define OSPI_IRQ_STATUS_POLL_EXP_INT_S 13U

§ OSPI_IRQ_STATUS_POLL_EXP_INT_DISABLE

#define OSPI_IRQ_STATUS_POLL_EXP_INT_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_POLL_EXP_INT_ENABLE

#define OSPI_IRQ_STATUS_POLL_EXP_INT_ENABLE 0x00002000U

§ OSPI_IRQ_STATUS_STIG_REQ_INT

#define OSPI_IRQ_STATUS_STIG_REQ_INT 0x00004000U

§ OSPI_IRQ_STATUS_STIG_REQ_INT_M

#define OSPI_IRQ_STATUS_STIG_REQ_INT_M 0x00004000U

§ OSPI_IRQ_STATUS_STIG_REQ_INT_S

#define OSPI_IRQ_STATUS_STIG_REQ_INT_S 14U

§ OSPI_IRQ_STATUS_STIG_REQ_INT_DISABLE

#define OSPI_IRQ_STATUS_STIG_REQ_INT_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_STIG_REQ_INT_ENABLE

#define OSPI_IRQ_STATUS_STIG_REQ_INT_ENABLE 0x00004000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_ERR

#define OSPI_IRQ_STATUS_RX_CRC_DATA_ERR 0x00010000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_M

#define OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_M 0x00010000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_S

#define OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_S 16U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_DISABLE

#define OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_ENABLE

#define OSPI_IRQ_STATUS_RX_CRC_DATA_ERR_ENABLE 0x00010000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_VAL

#define OSPI_IRQ_STATUS_RX_CRC_DATA_VAL 0x00020000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_M

#define OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_M 0x00020000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_S

#define OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_S 17U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_DISABLE

#define OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_ENABLE

#define OSPI_IRQ_STATUS_RX_CRC_DATA_VAL_ENABLE 0x00020000U

§ OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK

#define OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK 0x00040000U

§ OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_M

#define OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_M 0x00040000U

§ OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_S

#define OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_S 18U

§ OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_DISABLE

#define OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_ENABLE

#define OSPI_IRQ_STATUS_TX_CRC_CHUNK_BRK_ENABLE 0x00040000U

§ OSPI_IRQ_STATUS_ECC_FAIL

#define OSPI_IRQ_STATUS_ECC_FAIL 0x00080000U

§ OSPI_IRQ_STATUS_ECC_FAIL_M

#define OSPI_IRQ_STATUS_ECC_FAIL_M 0x00080000U

§ OSPI_IRQ_STATUS_ECC_FAIL_S

#define OSPI_IRQ_STATUS_ECC_FAIL_S 19U

§ OSPI_IRQ_STATUS_ECC_FAIL_DISABLE

#define OSPI_IRQ_STATUS_ECC_FAIL_DISABLE 0x00000000U

§ OSPI_IRQ_STATUS_ECC_FAIL_ENABLE

#define OSPI_IRQ_STATUS_ECC_FAIL_ENABLE 0x00080000U

§ OSPI_IRQ_MASK_MODE_M_FAIL_MASK

#define OSPI_IRQ_MASK_MODE_M_FAIL_MASK 0x00000001U

§ OSPI_IRQ_MASK_MODE_M_FAIL_MASK_M

#define OSPI_IRQ_MASK_MODE_M_FAIL_MASK_M 0x00000001U

§ OSPI_IRQ_MASK_MODE_M_FAIL_MASK_S

#define OSPI_IRQ_MASK_MODE_M_FAIL_MASK_S 0U

§ OSPI_IRQ_MASK_MODE_M_FAIL_MASK_DISABLE

#define OSPI_IRQ_MASK_MODE_M_FAIL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_MODE_M_FAIL_MASK_ENABLE

#define OSPI_IRQ_MASK_MODE_M_FAIL_MASK_ENABLE 0x00000001U

§ OSPI_IRQ_MASK_UNDERFLOW_DET_MASK

#define OSPI_IRQ_MASK_UNDERFLOW_DET_MASK 0x00000002U

§ OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_M

#define OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_M 0x00000002U

§ OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_S

#define OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_S 1U

§ OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_DISABLE

#define OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_ENABLE

#define OSPI_IRQ_MASK_UNDERFLOW_DET_MASK_ENABLE 0x00000002U

§ OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK

#define OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK 0x00000004U

§ OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_M

#define OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_M 0x00000004U

§ OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_S

#define OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_S 2U

§ OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_DISABLE

#define OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_ENABLE

#define OSPI_IRQ_MASK_INDIRECT_OP_DONE_MASK_ENABLE 0x00000004U

§ OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK

#define OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK 0x00000008U

§ OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_M

#define OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_M 0x00000008U

§ OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_S

#define OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_S 3U

§ OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_DISABLE

#define OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_ENABLE

#define OSPI_IRQ_MASK_INDIRECT_TRANSFER_REJECT_MASK_ENABLE 0x00000008U

§ OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK

#define OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK 0x00000010U

§ OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_M

#define OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_M 0x00000010U

§ OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_S

#define OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_S 4U

§ OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_DISABLE

#define OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_ENABLE

#define OSPI_IRQ_MASK_PROT_WR_ATTEMPT_MASK_ENABLE 0x00000010U

§ OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK

#define OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK 0x00000020U

§ OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_M

#define OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_M 0x00000020U

§ OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_S

#define OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_S 5U

§ OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_DISABLE

#define OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_ENABLE

#define OSPI_IRQ_MASK_ILLEGAL_ACCESS_DET_MASK_ENABLE 0x00000020U

§ OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK

#define OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK 0x00000040U

§ OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_M

#define OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_M 0x00000040U

§ OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_S

#define OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_S 6U

§ OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_DISABLE

#define OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_ENABLE

#define OSPI_IRQ_MASK_INDIRECT_XFER_LEVEL_BREACH_MASK_ENABLE 0x00000040U

§ OSPI_IRQ_MASK_RECV_OVERFLOW_MASK

#define OSPI_IRQ_MASK_RECV_OVERFLOW_MASK 0x00000080U

§ OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_M

#define OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_M 0x00000080U

§ OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_S

#define OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_S 7U

§ OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_DISABLE

#define OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_ENABLE

#define OSPI_IRQ_MASK_RECV_OVERFLOW_MASK_ENABLE 0x00000080U

§ OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK

#define OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK 0x00000100U

§ OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_M

#define OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_M 0x00000100U

§ OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_S

#define OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_S 8U

§ OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_DISABLE

#define OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_ENABLE

#define OSPI_IRQ_MASK_TX_FIFO_NOT_FULL_MASK_ENABLE 0x00000100U

§ OSPI_IRQ_MASK_TX_FIFO_FULL_MASK

#define OSPI_IRQ_MASK_TX_FIFO_FULL_MASK 0x00000200U

§ OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_M

#define OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_M 0x00000200U

§ OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_S

#define OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_S 9U

§ OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_DISABLE

#define OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_ENABLE

#define OSPI_IRQ_MASK_TX_FIFO_FULL_MASK_ENABLE 0x00000200U

§ OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK

#define OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK 0x00000400U

§ OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_M

#define OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_M 0x00000400U

§ OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_S

#define OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_S 10U

§ OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_DISABLE

#define OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_ENABLE

#define OSPI_IRQ_MASK_RX_FIFO_NOT_EMPTY_MASK_ENABLE 0x00000400U

§ OSPI_IRQ_MASK_RX_FIFO_FULL_MASK

#define OSPI_IRQ_MASK_RX_FIFO_FULL_MASK 0x00000800U

§ OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_M

#define OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_M 0x00000800U

§ OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_S

#define OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_S 11U

§ OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_DISABLE

#define OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_ENABLE

#define OSPI_IRQ_MASK_RX_FIFO_FULL_MASK_ENABLE 0x00000800U

§ OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK

#define OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK 0x00001000U

§ OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_M

#define OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_M 0x00001000U

§ OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_S

#define OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_S 12U

§ OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_DISABLE

#define OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_ENABLE

#define OSPI_IRQ_MASK_INDRD_SRAM_FULL_MASK_ENABLE 0x00001000U

§ OSPI_IRQ_MASK_POLL_EXP_INT_MASK

#define OSPI_IRQ_MASK_POLL_EXP_INT_MASK 0x00002000U

§ OSPI_IRQ_MASK_POLL_EXP_INT_MASK_M

#define OSPI_IRQ_MASK_POLL_EXP_INT_MASK_M 0x00002000U

§ OSPI_IRQ_MASK_POLL_EXP_INT_MASK_S

#define OSPI_IRQ_MASK_POLL_EXP_INT_MASK_S 13U

§ OSPI_IRQ_MASK_POLL_EXP_INT_MASK_DISABLE

#define OSPI_IRQ_MASK_POLL_EXP_INT_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_POLL_EXP_INT_MASK_ENABLE

#define OSPI_IRQ_MASK_POLL_EXP_INT_MASK_ENABLE 0x00002000U

§ OSPI_IRQ_MASK_STIG_REQ_MASK

#define OSPI_IRQ_MASK_STIG_REQ_MASK 0x00004000U

§ OSPI_IRQ_MASK_STIG_REQ_MASK_M

#define OSPI_IRQ_MASK_STIG_REQ_MASK_M 0x00004000U

§ OSPI_IRQ_MASK_STIG_REQ_MASK_S

#define OSPI_IRQ_MASK_STIG_REQ_MASK_S 14U

§ OSPI_IRQ_MASK_STIG_REQ_MASK_DISABLE

#define OSPI_IRQ_MASK_STIG_REQ_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_STIG_REQ_MASK_ENABLE

#define OSPI_IRQ_MASK_STIG_REQ_MASK_ENABLE 0x00004000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK

#define OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK 0x00010000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_M

#define OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_M 0x00010000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_S

#define OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_S 16U

§ OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_DISABLE

#define OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_ENABLE

#define OSPI_IRQ_MASK_RX_CRC_DATA_ERR_MASK_ENABLE 0x00010000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK

#define OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK 0x00020000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_M

#define OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_M 0x00020000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_S

#define OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_S 17U

§ OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_DISABLE

#define OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_ENABLE

#define OSPI_IRQ_MASK_RX_CRC_DATA_VAL_MASK_ENABLE 0x00020000U

§ OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK

#define OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK 0x00040000U

§ OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_M

#define OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_M 0x00040000U

§ OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_S

#define OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_S 18U

§ OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_DISABLE

#define OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_ENABLE

#define OSPI_IRQ_MASK_TX_CRC_CHUNK_BRK_MASK_ENABLE 0x00040000U

§ OSPI_IRQ_MASK_ECC_FAIL_MASK

#define OSPI_IRQ_MASK_ECC_FAIL_MASK 0x00080000U

§ OSPI_IRQ_MASK_ECC_FAIL_MASK_M

#define OSPI_IRQ_MASK_ECC_FAIL_MASK_M 0x00080000U

§ OSPI_IRQ_MASK_ECC_FAIL_MASK_S

#define OSPI_IRQ_MASK_ECC_FAIL_MASK_S 19U

§ OSPI_IRQ_MASK_ECC_FAIL_MASK_DISABLE

#define OSPI_IRQ_MASK_ECC_FAIL_MASK_DISABLE 0x00000000U

§ OSPI_IRQ_MASK_ECC_FAIL_MASK_ENABLE

#define OSPI_IRQ_MASK_ECC_FAIL_MASK_ENABLE 0x00080000U

§ OSPI_LOWER_WR_PROT_SUBSECTOR_W

#define OSPI_LOWER_WR_PROT_SUBSECTOR_W 32U

§ OSPI_LOWER_WR_PROT_SUBSECTOR_M

#define OSPI_LOWER_WR_PROT_SUBSECTOR_M 0xFFFFFFFFU

§ OSPI_LOWER_WR_PROT_SUBSECTOR_S

#define OSPI_LOWER_WR_PROT_SUBSECTOR_S 0U

§ OSPI_LOWER_WR_PROT_SUBSECTOR_MINIMUM

#define OSPI_LOWER_WR_PROT_SUBSECTOR_MINIMUM 0x00000000U

§ OSPI_LOWER_WR_PROT_SUBSECTOR_MAXIMUM

#define OSPI_LOWER_WR_PROT_SUBSECTOR_MAXIMUM 0xFFFFFFFFU

§ OSPI_UPPER_WR_PROT_SUBSECTOR_W

#define OSPI_UPPER_WR_PROT_SUBSECTOR_W 32U

§ OSPI_UPPER_WR_PROT_SUBSECTOR_M

#define OSPI_UPPER_WR_PROT_SUBSECTOR_M 0xFFFFFFFFU

§ OSPI_UPPER_WR_PROT_SUBSECTOR_S

#define OSPI_UPPER_WR_PROT_SUBSECTOR_S 0U

§ OSPI_UPPER_WR_PROT_SUBSECTOR_MINIMUM

#define OSPI_UPPER_WR_PROT_SUBSECTOR_MINIMUM 0x00000000U

§ OSPI_UPPER_WR_PROT_SUBSECTOR_MAXIMUM

#define OSPI_UPPER_WR_PROT_SUBSECTOR_MAXIMUM 0xFFFFFFFFU

§ OSPI_WR_PROT_CTRL_INV

#define OSPI_WR_PROT_CTRL_INV 0x00000001U

§ OSPI_WR_PROT_CTRL_INV_M

#define OSPI_WR_PROT_CTRL_INV_M 0x00000001U

§ OSPI_WR_PROT_CTRL_INV_S

#define OSPI_WR_PROT_CTRL_INV_S 0U

§ OSPI_WR_PROT_CTRL_INV_DISABLE

#define OSPI_WR_PROT_CTRL_INV_DISABLE 0x00000000U

§ OSPI_WR_PROT_CTRL_INV_ENABLE

#define OSPI_WR_PROT_CTRL_INV_ENABLE 0x00000001U

§ OSPI_WR_PROT_CTRL_ENB

#define OSPI_WR_PROT_CTRL_ENB 0x00000002U

§ OSPI_WR_PROT_CTRL_ENB_M

#define OSPI_WR_PROT_CTRL_ENB_M 0x00000002U

§ OSPI_WR_PROT_CTRL_ENB_S

#define OSPI_WR_PROT_CTRL_ENB_S 1U

§ OSPI_WR_PROT_CTRL_ENB_DISABLE

#define OSPI_WR_PROT_CTRL_ENB_DISABLE 0x00000000U

§ OSPI_WR_PROT_CTRL_ENB_ENABLE

#define OSPI_WR_PROT_CTRL_ENB_ENABLE 0x00000002U

§ OSPI_INDIRECT_READ_XFER_CTRL_START

#define OSPI_INDIRECT_READ_XFER_CTRL_START 0x00000001U

§ OSPI_INDIRECT_READ_XFER_CTRL_START_M

#define OSPI_INDIRECT_READ_XFER_CTRL_START_M 0x00000001U

§ OSPI_INDIRECT_READ_XFER_CTRL_START_S

#define OSPI_INDIRECT_READ_XFER_CTRL_START_S 0U

§ OSPI_INDIRECT_READ_XFER_CTRL_START_DISABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_START_DISABLE 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_START_ENABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_START_ENABLE 0x00000001U

§ OSPI_INDIRECT_READ_XFER_CTRL_CANCEL

#define OSPI_INDIRECT_READ_XFER_CTRL_CANCEL 0x00000002U

§ OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_M

#define OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_M 0x00000002U

§ OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_S

#define OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_S 1U

§ OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_DISABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_DISABLE 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_ENABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_CANCEL_ENABLE 0x00000002U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS 0x00000004U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_M

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_M 0x00000004U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_S

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_S 2U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_DISABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_DISABLE 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_ENABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_STATUS_ENABLE 0x00000004U

§ OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL

#define OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL 0x00000008U

§ OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_M

#define OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_M 0x00000008U

§ OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_S

#define OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_S 3U

§ OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_DISABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_DISABLE 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_ENABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_SRAM_FULL_ENABLE 0x00000008U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED 0x00000010U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_M

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_M 0x00000010U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_S

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_S 4U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_DISABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_DISABLE 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_ENABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_RD_QUEUED_ENABLE 0x00000010U

§ OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS

#define OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS 0x00000020U

§ OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_M

#define OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_M 0x00000020U

§ OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_S

#define OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_S 5U

§ OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_DISABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_DISABLE 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_ENABLE

#define OSPI_INDIRECT_READ_XFER_CTRL_IND_OPS_DONE_STATUS_ENABLE 0x00000020U

§ OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_W

#define OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_W 2U

§ OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_M

#define OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_M 0x000000C0U

§ OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_S

#define OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_S 6U

§ OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_MINIMUM

#define OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_MINIMUM 0x00000000U

§ OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_MAXIMUM

#define OSPI_INDIRECT_READ_XFER_CTRL_NUM_IND_OPS_DONE_MAXIMUM 0x000000C0U

§ OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_W

#define OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_W 32U

§ OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_M

#define OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_M 0xFFFFFFFFU

§ OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_S

#define OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_S 0U

§ OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_MINIMUM

#define OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_MINIMUM 0x00000000U

§ OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_MAXIMUM

#define OSPI_INDIRECT_READ_XFER_WATERMARK_LEVEL_MAXIMUM 0xFFFFFFFFU

§ OSPI_INDIRECT_READ_XFER_START_ADDR_W

#define OSPI_INDIRECT_READ_XFER_START_ADDR_W 32U

§ OSPI_INDIRECT_READ_XFER_START_ADDR_M

#define OSPI_INDIRECT_READ_XFER_START_ADDR_M 0xFFFFFFFFU

§ OSPI_INDIRECT_READ_XFER_START_ADDR_S

#define OSPI_INDIRECT_READ_XFER_START_ADDR_S 0U

§ OSPI_INDIRECT_READ_XFER_START_ADDR_MINIMUM

#define OSPI_INDIRECT_READ_XFER_START_ADDR_MINIMUM 0x00000000U

§ OSPI_INDIRECT_READ_XFER_START_ADDR_MAXIMUM

#define OSPI_INDIRECT_READ_XFER_START_ADDR_MAXIMUM 0xFFFFFFFFU

§ OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_W

#define OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_W 32U

§ OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_M

#define OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_M 0xFFFFFFFFU

§ OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_S

#define OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_S 0U

§ OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_MINIMUM

#define OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_MINIMUM 0x00000000U

§ OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_MAXIMUM

#define OSPI_INDIRECT_READ_XFER_NUM_BYTES_VALUE_MAXIMUM 0xFFFFFFFFU

§ OSPI_INDIRECT_WRITE_XFER_CTRL_START

#define OSPI_INDIRECT_WRITE_XFER_CTRL_START 0x00000001U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_START_M

#define OSPI_INDIRECT_WRITE_XFER_CTRL_START_M 0x00000001U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_START_S

#define OSPI_INDIRECT_WRITE_XFER_CTRL_START_S 0U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_START_DISABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_START_DISABLE 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_START_ENABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_START_ENABLE 0x00000001U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL

#define OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL 0x00000002U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_M

#define OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_M 0x00000002U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_S

#define OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_S 1U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_DISABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_DISABLE 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_ENABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_CANCEL_ENABLE 0x00000002U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS 0x00000004U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_M

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_M 0x00000004U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_S

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_S 2U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_DISABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_DISABLE 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_ENABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_STATUS_ENABLE 0x00000004U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED 0x00000010U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_M

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_M 0x00000010U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_S

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_S 4U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_DISABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_DISABLE 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_ENABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_WR_QUEUED_ENABLE 0x00000010U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS

#define OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS 0x00000020U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_M

#define OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_M 0x00000020U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_S

#define OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_S 5U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_DISABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_DISABLE 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_ENABLE

#define OSPI_INDIRECT_WRITE_XFER_CTRL_IND_OPS_DONE_STATUS_ENABLE 0x00000020U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_W

#define OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_W 2U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_M

#define OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_M 0x000000C0U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_S

#define OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_S 6U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_MINIMUM

#define OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_MINIMUM 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_MAXIMUM

#define OSPI_INDIRECT_WRITE_XFER_CTRL_NUM_IND_OPS_DONE_MAXIMUM 0x000000C0U

§ OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_W

#define OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_W 32U

§ OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_M

#define OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_M 0xFFFFFFFFU

§ OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_S

#define OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_S 0U

§ OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_MINIMUM

#define OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_MINIMUM 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_MAXIMUM

#define OSPI_INDIRECT_WRITE_XFER_WATERMARK_LEVEL_MAXIMUM 0xFFFFFFFFU

§ OSPI_INDIRECT_WRITE_XFER_START_ADDR_W

#define OSPI_INDIRECT_WRITE_XFER_START_ADDR_W 32U

§ OSPI_INDIRECT_WRITE_XFER_START_ADDR_M

#define OSPI_INDIRECT_WRITE_XFER_START_ADDR_M 0xFFFFFFFFU

§ OSPI_INDIRECT_WRITE_XFER_START_ADDR_S

#define OSPI_INDIRECT_WRITE_XFER_START_ADDR_S 0U

§ OSPI_INDIRECT_WRITE_XFER_START_ADDR_MINIMUM

#define OSPI_INDIRECT_WRITE_XFER_START_ADDR_MINIMUM 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_START_ADDR_MAXIMUM

#define OSPI_INDIRECT_WRITE_XFER_START_ADDR_MAXIMUM 0xFFFFFFFFU

§ OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_W

#define OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_W 32U

§ OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_M

#define OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_M 0xFFFFFFFFU

§ OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_S

#define OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_S 0U

§ OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_MINIMUM

#define OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_MINIMUM 0x00000000U

§ OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_MAXIMUM

#define OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_VALUE_MAXIMUM 0xFFFFFFFFU

§ OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_W

#define OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_W 4U

§ OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_M

#define OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_M 0x0000000FU

§ OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_S

#define OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_S 0U

§ OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_MINIMUM

#define OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_MINIMUM 0x00000000U

§ OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_MAXIMUM

#define OSPI_INDIRECT_TRIGGER_ADDR_RANGE_IND_RANGE_WIDTH_MAXIMUM 0x0000000FU

§ OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ

#define OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ 0x00000001U

§ OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_M

#define OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_M 0x00000001U

§ OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_S

#define OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_S 0U

§ OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_DISABLE

#define OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_DISABLE 0x00000000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_ENABLE

#define OSPI_FLASH_COMMAND_CTRL_MEM_TRIGGER_MEM_BANK_REQ_ENABLE 0x00000001U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS 0x00000002U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_M

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_M 0x00000002U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_S

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_S 1U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_DISABLE

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_DISABLE 0x00000000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_ENABLE

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_REQ_IN_PROGRESS_ENABLE 0x00000002U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_W

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_W 8U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_M

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_M 0x0000FF00U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_S

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_S 8U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_MINIMUM

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_MINIMUM 0x00000000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_MAXIMUM

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_READ_DATA_MAXIMUM 0x0000FF00U

§ OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_W

#define OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_W 3U

§ OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_M

#define OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_M 0x00070000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_S

#define OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_S 16U

§ OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_MINIMUM

#define OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_MINIMUM 0x00000000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_MAXIMUM

#define OSPI_FLASH_COMMAND_CTRL_MEM_NB_OF_STIG_READ_BYTES_MAXIMUM 0x00070000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_W

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_W 9U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_M

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_M 0x1FF00000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_S

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_S 20U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_MINIMUM

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_MINIMUM 0x00000000U

§ OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_MAXIMUM

#define OSPI_FLASH_COMMAND_CTRL_MEM_MEM_BANK_ADDR_MAXIMUM 0x1FF00000U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC 0x00000001U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_M

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_M 0x00000001U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_S

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_S 0U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_DISABLE

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_ENABLE

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_ENABLE 0x00000001U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS 0x00000002U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_M

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_M 0x00000002U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_S

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_S 1U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_DISABLE

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_ENABLE

#define OSPI_FLASH_CMD_CTRL_CMD_EXEC_STATUS_ENABLE 0x00000002U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN

#define OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN 0x00000004U

§ OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_M

#define OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_M 0x00000004U

§ OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_S

#define OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_S 2U

§ OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_DISABLE

#define OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_ENABLE

#define OSPI_FLASH_CMD_CTRL_STIG_MEM_BANK_EN_ENABLE 0x00000004U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_W

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_W 4U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_M

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_M 0x00000078U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_S

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_S 3U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_IDLE

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_IDLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_ADDR_BYTES

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_ADDR_BYTES 0x00000008U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_STIG_MODE_BYTE

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_STIG_MODE_BYTE 0x00000010U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_STIG_DUMMY_BYTES

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_STIG_DUMMY_BYTES 0x00000018U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_DATA

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_DATA 0x00000020U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_STIG_DATA_LOWER

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_STIG_DATA_LOWER 0x00000028U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_STIG_DATA_UPPER

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_STIG_DATA_UPPER 0x00000030U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_AFTER_WRITE

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_AFTER_WRITE 0x00000038U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_AFTER_WRITE2

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_AFTER_WRITE2 0x00000040U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_LET_TXFIFO_EMPTY

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_LET_TXFIFO_EMPTY 0x00000050U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_WAIT

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_POLL_STATUS_WAIT 0x00000058U

§ OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_DATA_PIPE

#define OSPI_FLASH_CMD_CTRL_CMD_GEN_FSM_STATE_SEND_DATA_PIPE 0x00000060U

§ OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_W

#define OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_W 5U

§ OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_M

#define OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_M 0x00000F80U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_S

#define OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_S 7U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_MINIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_MINIMUM 0x00000000U

§ OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_MAXIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_DUMMY_CYCLES_MAXIMUM 0x00000F80U

§ OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_W

#define OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_W 3U

§ OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_M

#define OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_M 0x00007000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_S

#define OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_S 12U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_MINIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_MINIMUM 0x00000000U

§ OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_MAXIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_WR_DATA_BYTES_MAXIMUM 0x00007000U

§ OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA

#define OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA 0x00008000U

§ OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_M

#define OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_M 0x00008000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_S

#define OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_S 15U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_DISABLE

#define OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_ENABLE

#define OSPI_FLASH_CMD_CTRL_ENB_WRITE_DATA_ENABLE 0x00008000U

§ OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_W

#define OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_W 2U

§ OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_M

#define OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_M 0x00030000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_S

#define OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_S 16U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_MINIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_MINIMUM 0x00000000U

§ OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_MAXIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_ADDR_BYTES_MAXIMUM 0x00030000U

§ OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT

#define OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT 0x00040000U

§ OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_M

#define OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_M 0x00040000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_S

#define OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_S 18U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_DISABLE

#define OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_ENABLE

#define OSPI_FLASH_CMD_CTRL_ENB_MODE_BIT_ENABLE 0x00040000U

§ OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR

#define OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR 0x00080000U

§ OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_M

#define OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_M 0x00080000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_S

#define OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_S 19U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_DISABLE

#define OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_ENABLE

#define OSPI_FLASH_CMD_CTRL_ENB_COMD_ADDR_ENABLE 0x00080000U

§ OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_W

#define OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_W 3U

§ OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_M

#define OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_M 0x00700000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_S

#define OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_S 20U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_MINIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_MINIMUM 0x00000000U

§ OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_MAXIMUM

#define OSPI_FLASH_CMD_CTRL_NUM_RD_DATA_BYTES_MAXIMUM 0x00700000U

§ OSPI_FLASH_CMD_CTRL_ENB_READ_DATA

#define OSPI_FLASH_CMD_CTRL_ENB_READ_DATA 0x00800000U

§ OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_M

#define OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_M 0x00800000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_S

#define OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_S 23U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_DISABLE

#define OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_DISABLE 0x00000000U

§ OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_ENABLE

#define OSPI_FLASH_CMD_CTRL_ENB_READ_DATA_ENABLE 0x00800000U

§ OSPI_FLASH_CMD_CTRL_CMD_OPCODE_W

#define OSPI_FLASH_CMD_CTRL_CMD_OPCODE_W 8U

§ OSPI_FLASH_CMD_CTRL_CMD_OPCODE_M

#define OSPI_FLASH_CMD_CTRL_CMD_OPCODE_M 0xFF000000U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_CMD_OPCODE_S

#define OSPI_FLASH_CMD_CTRL_CMD_OPCODE_S 24U

Referenced by OSPISetSTIGDataRegister().

§ OSPI_FLASH_CMD_CTRL_CMD_OPCODE_MINIMUM

#define OSPI_FLASH_CMD_CTRL_CMD_OPCODE_MINIMUM 0x00000000U

§ OSPI_FLASH_CMD_CTRL_CMD_OPCODE_MAXIMUM

#define OSPI_FLASH_CMD_CTRL_CMD_OPCODE_MAXIMUM 0xFF000000U

§ OSPI_FLASH_CMD_ADDR_ADDR_W

#define OSPI_FLASH_CMD_ADDR_ADDR_W 32U

§ OSPI_FLASH_CMD_ADDR_ADDR_M

#define OSPI_FLASH_CMD_ADDR_ADDR_M 0xFFFFFFFFU

§ OSPI_FLASH_CMD_ADDR_ADDR_S

#define OSPI_FLASH_CMD_ADDR_ADDR_S 0U

§ OSPI_FLASH_CMD_ADDR_ADDR_MINIMUM

#define OSPI_FLASH_CMD_ADDR_ADDR_MINIMUM 0x00000000U

§ OSPI_FLASH_CMD_ADDR_ADDR_MAXIMUM

#define OSPI_FLASH_CMD_ADDR_ADDR_MAXIMUM 0xFFFFFFFFU

§ OSPI_FLASH_RD_DATA_LOWER_DATA_W

#define OSPI_FLASH_RD_DATA_LOWER_DATA_W 32U

§ OSPI_FLASH_RD_DATA_LOWER_DATA_M

#define OSPI_FLASH_RD_DATA_LOWER_DATA_M 0xFFFFFFFFU

§ OSPI_FLASH_RD_DATA_LOWER_DATA_S

#define OSPI_FLASH_RD_DATA_LOWER_DATA_S 0U

§ OSPI_FLASH_RD_DATA_LOWER_DATA_MINIMUM

#define OSPI_FLASH_RD_DATA_LOWER_DATA_MINIMUM 0x00000000U

§ OSPI_FLASH_RD_DATA_LOWER_DATA_MAXIMUM

#define OSPI_FLASH_RD_DATA_LOWER_DATA_MAXIMUM 0xFFFFFFFFU

§ OSPI_FLASH_RD_DATA_UPPER_DATA_W

#define OSPI_FLASH_RD_DATA_UPPER_DATA_W 32U

§ OSPI_FLASH_RD_DATA_UPPER_DATA_M

#define OSPI_FLASH_RD_DATA_UPPER_DATA_M 0xFFFFFFFFU

§ OSPI_FLASH_RD_DATA_UPPER_DATA_S

#define OSPI_FLASH_RD_DATA_UPPER_DATA_S 0U

§ OSPI_FLASH_RD_DATA_UPPER_DATA_MINIMUM

#define OSPI_FLASH_RD_DATA_UPPER_DATA_MINIMUM 0x00000000U

§ OSPI_FLASH_RD_DATA_UPPER_DATA_MAXIMUM

#define OSPI_FLASH_RD_DATA_UPPER_DATA_MAXIMUM 0xFFFFFFFFU

§ OSPI_FLASH_WR_DATA_LOWER_DATA_W

#define OSPI_FLASH_WR_DATA_LOWER_DATA_W 32U

§ OSPI_FLASH_WR_DATA_LOWER_DATA_M

#define OSPI_FLASH_WR_DATA_LOWER_DATA_M 0xFFFFFFFFU

§ OSPI_FLASH_WR_DATA_LOWER_DATA_S

#define OSPI_FLASH_WR_DATA_LOWER_DATA_S 0U

§ OSPI_FLASH_WR_DATA_LOWER_DATA_MINIMUM

#define OSPI_FLASH_WR_DATA_LOWER_DATA_MINIMUM 0x00000000U

§ OSPI_FLASH_WR_DATA_LOWER_DATA_MAXIMUM

#define OSPI_FLASH_WR_DATA_LOWER_DATA_MAXIMUM 0xFFFFFFFFU

§ OSPI_FLASH_WR_DATA_UPPER_DATA_W

#define OSPI_FLASH_WR_DATA_UPPER_DATA_W 32U

§ OSPI_FLASH_WR_DATA_UPPER_DATA_M

#define OSPI_FLASH_WR_DATA_UPPER_DATA_M 0xFFFFFFFFU

§ OSPI_FLASH_WR_DATA_UPPER_DATA_S

#define OSPI_FLASH_WR_DATA_UPPER_DATA_S 0U

§ OSPI_FLASH_WR_DATA_UPPER_DATA_MINIMUM

#define OSPI_FLASH_WR_DATA_UPPER_DATA_MINIMUM 0x00000000U

§ OSPI_FLASH_WR_DATA_UPPER_DATA_MAXIMUM

#define OSPI_FLASH_WR_DATA_UPPER_DATA_MAXIMUM 0xFFFFFFFFU

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_W

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_W 8U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_M

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_M 0x000000FFU

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_S

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_S 0U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_MINIMUM

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_MINIMUM 0x00000000U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_MAXIMUM

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_MAXIMUM 0x000000FFU

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID 0x00000100U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_M

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_M 0x00000100U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_S

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_S 8U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_DISABLE

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_DISABLE 0x00000000U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_ENABLE

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_VALID_ENABLE 0x00000100U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_W

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_W 5U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_M

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_M 0x001F0000U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_S

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_S 16U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_MINIMUM

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_MINIMUM 0x00000000U

§ OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_MAXIMUM

#define OSPI_POLLING_FLASH_STATUS_DEVICE_STATUS_NB_DUMMY_MAXIMUM 0x001F0000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_W

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_W 7U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_M

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_M 0x0000007FU

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_S

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_S 0U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_MINIMUM

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_MINIMUM 0x00000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_MAXIMUM

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_DELAY_MAXIMUM 0x0000007FU

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_W

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_W 7U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_M

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_M 0x007F0000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_S

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_S 16U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_MINIMUM

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_MINIMUM 0x00000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_MAXIMUM

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_TX_DLL_DELAY_MAXIMUM 0x007F0000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS 0x20000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_M

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_M 0x20000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_S

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_S 29U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_DISABLE

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_DISABLE 0x00000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_ENABLE

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RX_DLL_BYPASS_ENABLE 0x20000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET 0x40000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_M

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_M 0x40000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_S

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_S 30U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_DISABLE

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_DISABLE 0x00000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_ENABLE

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESET_ENABLE 0x40000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC 0x80000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_M

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_M 0x80000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_S

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_S 31U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_DISABLE

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_DISABLE 0x00000000U

§ OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_ENABLE

#define OSPI_PHY_CONFIGURATION_PHY_CONFIG_RESYNC_ENABLE 0x80000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_W

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_W 7U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_M

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_M 0x0000007FU

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_S

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_S 0U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_MINIMUM

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_MINIMUM 0x00000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_MAXIMUM

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_INITIAL_DELAY_MAXIMUM 0x0000007FU

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_W

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_W 3U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_M

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_M 0x00070000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_S

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_S 16U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_MINIMUM

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_MINIMUM 0x00000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_MAXIMUM

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_NB_INDICATIONS_MAXIMUM 0x00070000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_W

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_W 3U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_M

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_M 0x00700000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_S

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_S 20U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_MINIMUM

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_MINIMUM 0x00000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_MAXIMUM

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_PHASE_DETECT_SELECTOR_MAXIMUM 0x00700000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE 0x00800000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_M

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_M 0x00800000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_S

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_S 23U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_DISABLE

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_DISABLE 0x00000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_ENABLE

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_BYPASS_MODE_ENABLE 0x00800000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE 0x01000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_M

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_M 0x01000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_S

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_S 24U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_DISABLE

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_DISABLE 0x00000000U

§ OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_ENABLE

#define OSPI_PHY_MASTER_CONTROL_PHY_MASTER_LOCK_MODE_ENABLE 0x01000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK 0x00000001U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_M 0x00000001U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_S 0U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DISABLE

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DISABLE 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_ENABLE

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_ENABLE 0x00000001U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_W

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_W 2U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_M 0x00000006U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_S 1U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_MINIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_MAXIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_MODE_MAXIMUM 0x00000006U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_W

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_W 5U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_M 0x000000F8U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_S 3U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_MINIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_MAXIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_MAXIMUM 0x000000F8U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_W

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_W 7U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_M 0x00007F00U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_S 8U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_MINIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_MAXIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOCK_VALUE_MAXIMUM 0x00007F00U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK 0x00008000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_M 0x00008000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_S 15U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_DISABLE

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_DISABLE 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_ENABLE

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_ENABLE 0x00008000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_W

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_W 8U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_M 0x00FF0000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_S 16U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_MINIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_MAXIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_MAXIMUM 0x00FF0000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_W

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_W 8U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_M

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_M 0xFF000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_S

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_S 24U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_MINIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_MAXIMUM

#define OSPI_DLL_OBSERVABLE_LOWER_DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_MAXIMUM 0xFF000000U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_W

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_W 7U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_M

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_M 0x0000007FU

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_S

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_S 0U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_MINIMUM

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_MAXIMUM

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_MAXIMUM 0x0000007FU

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_W

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_W 7U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_M

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_M 0x007F0000U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_S

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_S 16U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_MINIMUM

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_MINIMUM 0x00000000U

§ OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_MAXIMUM

#define OSPI_DLL_OBSERVABLE_UPPER_DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_MAXIMUM 0x007F0000U

§ OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_W

#define OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_W 8U

§ OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_M

#define OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_M 0x000000FFU

§ OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_S

#define OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_S 0U

§ OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_MINIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_MINIMUM 0x00000000U

§ OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_MAXIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_STIG_OPCODE_MAXIMUM 0x000000FFU

§ OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_W

#define OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_W 8U

§ OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_M

#define OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_M 0x0000FF00U

§ OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_S

#define OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_S 8U

§ OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_MINIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_MINIMUM 0x00000000U

§ OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_MAXIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_POLL_OPCODE_MAXIMUM 0x0000FF00U

§ OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_W

#define OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_W 8U

§ OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_M

#define OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_M 0x00FF0000U

§ OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_S

#define OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_S 16U

§ OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_MINIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_MINIMUM 0x00000000U

§ OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_MAXIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_WRITE_OPCODE_MAXIMUM 0x00FF0000U

§ OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_W

#define OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_W 8U

§ OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_M

#define OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_M 0xFF000000U

§ OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_S

#define OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_S 24U

§ OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_MINIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_MINIMUM 0x00000000U

§ OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_MAXIMUM

#define OSPI_OPCODE_EXT_LOWER_EXT_READ_OPCODE_MAXIMUM 0xFF000000U

§ OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_W

#define OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_W 8U

§ OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_M

#define OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_M 0x00FF0000U

§ OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_S

#define OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_S 16U

§ OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_MINIMUM

#define OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_MINIMUM 0x00000000U

§ OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_MAXIMUM

#define OSPI_OPCODE_EXT_UPPER_EXT_WEL_OPCODE_MAXIMUM 0x00FF0000U

§ OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_W

#define OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_W 8U

§ OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_M

#define OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_M 0xFF000000U

§ OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_S

#define OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_S 24U

§ OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_MINIMUM

#define OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_MINIMUM 0x00000000U

§ OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_MAXIMUM

#define OSPI_OPCODE_EXT_UPPER_WEL_OPCODE_MAXIMUM 0xFF000000U

§ OSPI_MODULE_ID_CONF_W

#define OSPI_MODULE_ID_CONF_W 2U

§ OSPI_MODULE_ID_CONF_M

#define OSPI_MODULE_ID_CONF_M 0x00000003U

§ OSPI_MODULE_ID_CONF_S

#define OSPI_MODULE_ID_CONF_S 0U

§ OSPI_MODULE_ID_CONF_MINIMUM

#define OSPI_MODULE_ID_CONF_MINIMUM 0x00000000U

§ OSPI_MODULE_ID_CONF_MAXIMUM

#define OSPI_MODULE_ID_CONF_MAXIMUM 0x00000003U

§ OSPI_MODULE_ID_MODULE_ID_W

#define OSPI_MODULE_ID_MODULE_ID_W 16U

§ OSPI_MODULE_ID_MODULE_ID_M

#define OSPI_MODULE_ID_MODULE_ID_M 0x00FFFF00U

§ OSPI_MODULE_ID_MODULE_ID_S

#define OSPI_MODULE_ID_MODULE_ID_S 8U

§ OSPI_MODULE_ID_MODULE_ID_MINIMUM

#define OSPI_MODULE_ID_MODULE_ID_MINIMUM 0x00000000U

§ OSPI_MODULE_ID_MODULE_ID_MAXIMUM

#define OSPI_MODULE_ID_MODULE_ID_MAXIMUM 0x00FFFF00U

§ OSPI_MODULE_ID_FIX_PATCH_W

#define OSPI_MODULE_ID_FIX_PATCH_W 8U

§ OSPI_MODULE_ID_FIX_PATCH_M

#define OSPI_MODULE_ID_FIX_PATCH_M 0xFF000000U

§ OSPI_MODULE_ID_FIX_PATCH_S

#define OSPI_MODULE_ID_FIX_PATCH_S 24U

§ OSPI_MODULE_ID_FIX_PATCH_MINIMUM

#define OSPI_MODULE_ID_FIX_PATCH_MINIMUM 0x00000000U

§ OSPI_MODULE_ID_FIX_PATCH_MAXIMUM

#define OSPI_MODULE_ID_FIX_PATCH_MAXIMUM 0xFF000000U

Macros

Macro Definition Documentation

§ OSPI_O_CONFIG

§ OSPI_O_DEV_INSTR_RD_CONFIG

§ OSPI_O_DEV_INSTR_WR_CONFIG

§ OSPI_O_DEV_DELAY

§ OSPI_O_RD_DATA_CAPTURE

§ OSPI_O_DEV_SIZE_CONFIG

§ OSPI_O_SRAM_PARTITION_CFG

§ OSPI_O_IND_AHB_ADDR_TRIGGER

§ OSPI_O_DMA_PERIPH_CONFIG

§ OSPI_O_REMAP_ADDR

§ OSPI_O_MODE_BIT_CONFIG

§ OSPI_O_SRAM_FILL

§ OSPI_O_TX_THRESH

§ OSPI_O_RX_THRESH

§ OSPI_O_WRITE_COMPLETION_CTRL

§ OSPI_O_NO_OF_POLLS_BEF_EXP

§ OSPI_O_IRQ_STATUS

§ OSPI_O_IRQ_MASK

§ OSPI_O_LOWER_WR_PROT

§ OSPI_O_UPPER_WR_PROT

§ OSPI_O_WR_PROT_CTRL

§ OSPI_O_INDIRECT_READ_XFER_CTRL

§ OSPI_O_INDIRECT_READ_XFER_WATERMARK

§ OSPI_O_INDIRECT_READ_XFER_START

§ OSPI_O_INDIRECT_READ_XFER_NUM_BYTES

§ OSPI_O_INDIRECT_WRITE_XFER_CTRL

§ OSPI_O_INDIRECT_WRITE_XFER_WATERMARK

§ OSPI_O_INDIRECT_WRITE_XFER_START

§ OSPI_O_INDIRECT_WRITE_XFER_NUM_BYTES

§ OSPI_O_INDIRECT_TRIGGER_ADDR_RANGE

§ OSPI_O_FLASH_COMMAND_CTRL_MEM

§ OSPI_O_FLASH_CMD_CTRL

§ OSPI_O_FLASH_CMD_ADDR

§ OSPI_O_FLASH_RD_DATA_LOWER

§ OSPI_O_FLASH_RD_DATA_UPPER

§ OSPI_O_FLASH_WR_DATA_LOWER

§ OSPI_O_FLASH_WR_DATA_UPPER

§ OSPI_O_POLLING_FLASH_STATUS

§ OSPI_O_PHY_CONFIGURATION

§ OSPI_O_PHY_MASTER_CONTROL

§ OSPI_O_DLL_OBSERVABLE_LOWER

§ OSPI_O_DLL_OBSERVABLE_UPPER

§ OSPI_O_OPCODE_EXT_LOWER

§ OSPI_O_OPCODE_EXT_UPPER

§ OSPI_O_MODULE_ID

§ OSPI_CONFIG_ENB_SPI

§ OSPI_CONFIG_ENB_SPI_M

§ OSPI_CONFIG_ENB_SPI_S

§ OSPI_CONFIG_ENB_SPI_DISABLE

§ OSPI_CONFIG_ENB_SPI_ENABLE

§ OSPI_CONFIG_SEL_CLK_POL

§ OSPI_CONFIG_SEL_CLK_POL_M

§ OSPI_CONFIG_SEL_CLK_POL_S

§ OSPI_CONFIG_SEL_CLK_POL_DISABLE

§ OSPI_CONFIG_SEL_CLK_POL_ENABLE

§ OSPI_CONFIG_SEL_CLK_PHASE

§ OSPI_CONFIG_SEL_CLK_PHASE_M

§ OSPI_CONFIG_SEL_CLK_PHASE_S

§ OSPI_CONFIG_SEL_CLK_PHASE_DISABLE

§ OSPI_CONFIG_SEL_CLK_PHASE_ENABLE

§ OSPI_CONFIG_PHY_MODE_ENABLE

§ OSPI_CONFIG_PHY_MODE_ENABLE_M

§ OSPI_CONFIG_PHY_MODE_ENABLE_S

§ OSPI_CONFIG_PHY_MODE_ENABLE_DISABLE

§ OSPI_CONFIG_PHY_MODE_ENABLE_ENABLE

§ OSPI_CONFIG_HOLD_PIN

§ OSPI_CONFIG_HOLD_PIN_M

§ OSPI_CONFIG_HOLD_PIN_S

§ OSPI_CONFIG_HOLD_PIN_DISABLE

§ OSPI_CONFIG_HOLD_PIN_ENABLE

§ OSPI_CONFIG_RESET_PIN

§ OSPI_CONFIG_RESET_PIN_M

§ OSPI_CONFIG_RESET_PIN_S

§ OSPI_CONFIG_RESET_PIN_DISABLE

§ OSPI_CONFIG_RESET_PIN_ENABLE

§ OSPI_CONFIG_RESET_CFG

§ OSPI_CONFIG_RESET_CFG_M

§ OSPI_CONFIG_RESET_CFG_S