CC35xxDriverLibrary
hw_memmap.h
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1 /******************************************************************************
2  * Filename: hw_memmap_h
3  *
4  * Description: Device memory map macros.
5  *
6  * Copyright (c) 2022-2025 Texas Instruments Incorporated
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35 
36 #ifndef __HW_MEMMAP_H__
37 #define __HW_MEMMAP_H__
38 
39 //*****************************************************************************
40 //
41 // The following are defines for the base address of the memories and
42 // peripherals on the CPU_MMAP interface
43 //
44 //*****************************************************************************
45 #define HOSTMCU_TGT_BASE 0x00000000
46 #define TCM_CRAM_BASE 0x00000000
47 #define TCM_CRAM_SEC_BASE 0x04000000
48 #define CRAM_BASE 0x08000000
49 #define CRAM_SEC_BASE 0x0C000000
50 #define EXT_FLASH_BASE 0x10000000
51 #define EXT_FLASH_SEC_BASE 0x14000000
52 #define TCM_DRAM_BASE 0x20000000
53 #define TCM_DRAM_SEC_BASE 0x24000000
54 #define DRAM_BASE 0x28000000
55 #define DRAM_SEC_BASE 0x2C000000
56 #define EXT_PSRAM_BASE 0x60000000
57 #define EXT_PSRAM_SEC_BASE 0x64000000
58 #define HOST_MCU_BASE 0x41900000
59 #define ICACHE_BASE 0x41902000
60 #define DCACHE_BASE 0x41902400
61 #define HOST_MCU_SEC_BASE 0x41903000
62 #define OSPI_REGS_BASE 0x41910000
63 #define OSPI_INDAC_BASE 0x41911000
64 #define HOST_XIP_REGS_BASE 0x41912000
65 #define HIF_BASE 0x408A0000
66 #define COEX_BASE 0x40850000
67 #define IOMUX_BASE 0x41140000
68 #define PRCM_BASE 0x41090000
69 #define PRCM_AON_BASE 0x41090000
70 #define PRCM_SCRATCHPAD_BASE 0x4109F000
71 #define PLL_SHARING_BASE 0x410A0000
72 #define CKM_BASE 0x410a0000
73 #define SOC_DEBUGSS_BASE 0x410d0000
74 #define SOC_DEBUGSS_DSSM_BASE 0x410d0000
75 #define SOC_IC_REGS_BASE 0x410f0000
76 #define SOC_AON_BASE 0x41100000
77 #define SOC_AAON_BASE 0x41104000
78 #define RTC_BASE 0x41108000
79 #define WSOC_OCLA_BASE 0x411C0000
80 #define MEMSS_BASE 0x41C00000
81 #define HOSTMCU_AON_BASE 0x411D0000
82 #define SYSRESOURCES_BASE 0x411E0000
83 #define SYSTIM_BASE 0x411E2000
84 #define HOST_DMA_TGT_BASE 0x41A00000
85 #define HSM_BASE 0x41B00000
86 #define HSM_NON_SEC_BASE 0x41B04000
87 #define HSM_SEC_BASE 0x41B05000
88 #define I2C0_BASE 0x41200000
89 #define I2C1_BASE 0x41210000
90 #define SPI0_BASE 0x41220000
91 #define SPI1_BASE 0x41230000
92 #define UARTLIN0_BASE 0x41240000
93 #define UARTLIN1_BASE 0x41250000
94 #define UARTLIN2_BASE 0x41300000
95 #define GPTIMER0_BASE 0x41260000
96 #define GPTIMER1_BASE 0x41268000
97 #define I2S_BASE 0x41270000
98 #define PDM_BASE 0x41280000
99 #define DCAN_BASE 0x412A0000
100 #define ADC_BASE 0x412B0000
101 #define SDMMC_BASE 0x412C0000
102 #define SDIO_CARD_FN1_BASE 0x412D0000
103 #define SDIO_CORE_BASE 0x412E0000
104 #define CORE_AON_BASE 0x41E00000
105 
106 // TODO: Review presence of commented IPs
107 #define CPU_ITM_BASE 0xE0000000 // CPU_ITM
108 #define CPU_DWT_BASE 0xE0001000 // CPU_DWT
109 #define CPU_ICB_BASE 0xE000E000 // CPU_ICB
110 #define CPU_SYSTICK_BASE 0xE000E010 // CPU_SYSTICK
111 #define CPU_NVIC_BASE 0xE000E100 // CPU_NVIC
112 #define CPU_MPU_BASE 0xE000EDC0 // CPU_MPU
113 #define CPU_SAU_BASE 0xE000EDD0 // CPU_SAU
114 #define CPU_FPU_BASE 0xE000EF30 // CPU_FPU
115 
116 #endif // __HW_MEMMAP__