Macros
#define	ICACHE_O_MOD_VERSION 0x00000000U

#define	ICACHE_O_CTRL 0x00000004U

#define	ICACHE_O_STATUS 0x00000008U

#define	ICACHE_O_CACHE_ADDRESS_LOW 0x00000010U

#define	ICACHE_O_CACHE_ADDRESS_HIGH 0x00000018U

#define	ICACHE_O_REGISTER_ADDRESS 0x00000020U

#define	ICACHE_O_HIT_COUNTER 0x00000040U

#define	ICACHE_O_MISS_COUNTER 0x00000044U

#define	ICACHE_O_IRQ_STATUS_RAW 0x00000080U

#define	ICACHE_O_IRQ_STATUS_MASK 0x00000084U

#define	ICACHE_O_IRQ_ENABLE_SET 0x00000088U

#define	ICACHE_O_IRQ_ENABLE_CLR 0x0000008CU

#define	ICACHE_MOD_VERSION_MINOR_REVISION_W 6U

#define	ICACHE_MOD_VERSION_MINOR_REVISION_M 0x0000003FU

#define	ICACHE_MOD_VERSION_MINOR_REVISION_S 0U

#define	ICACHE_MOD_VERSION_CUSTOM_REVISION_W 2U

#define	ICACHE_MOD_VERSION_CUSTOM_REVISION_M 0x000000C0U

#define	ICACHE_MOD_VERSION_CUSTOM_REVISION_S 6U

#define	ICACHE_MOD_VERSION_MAJOR_REVISION_W 3U

#define	ICACHE_MOD_VERSION_MAJOR_REVISION_M 0x00000700U

#define	ICACHE_MOD_VERSION_MAJOR_REVISION_S 8U

#define	ICACHE_MOD_VERSION_RTL_VERSION_W 5U

#define	ICACHE_MOD_VERSION_RTL_VERSION_M 0x0000F800U

#define	ICACHE_MOD_VERSION_RTL_VERSION_S 11U

#define	ICACHE_MOD_VERSION_MODULE_ID_W 12U

#define	ICACHE_MOD_VERSION_MODULE_ID_M 0x0FFF0000U

#define	ICACHE_MOD_VERSION_MODULE_ID_S 16U

#define	ICACHE_MOD_VERSION_BU_W 2U

#define	ICACHE_MOD_VERSION_BU_M 0x30000000U

#define	ICACHE_MOD_VERSION_BU_S 28U

#define	ICACHE_MOD_VERSION_SCHEME_W 2U

#define	ICACHE_MOD_VERSION_SCHEME_M 0xC0000000U

#define	ICACHE_MOD_VERSION_SCHEME_S 30U

#define	ICACHE_CTRL_MEM_RENABLE 0x40000000U

#define	ICACHE_CTRL_MEM_RENABLE_M 0x40000000U

#define	ICACHE_CTRL_MEM_RENABLE_S 30U

#define	ICACHE_CTRL_MEM_CENABLE 0x80000000U

#define	ICACHE_CTRL_MEM_CENABLE_M 0x80000000U

#define	ICACHE_CTRL_MEM_CENABLE_S 31U

#define	ICACHE_STATUS_OK_TO_GO 0x80000000U

#define	ICACHE_STATUS_OK_TO_GO_M 0x80000000U

#define	ICACHE_STATUS_OK_TO_GO_S 31U

#define	ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_W 20U

#define	ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_M 0xFFFFF000U

#define	ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_S 12U

#define	ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_W 20U

#define	ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_M 0xFFFFF000U

#define	ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_S 12U

#define	ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_W 17U

#define	ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_M 0xFFFF8000U

#define	ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_S 15U

#define	ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_W 32U

#define	ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_M 0xFFFFFFFFU

#define	ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_S 0U

#define	ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_W 32U

#define	ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_M 0xFFFFFFFFU

#define	ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_S 0U

#define	ICACHE_IRQ_STATUS_RAW_WR_ERR 0x00000001U

#define	ICACHE_IRQ_STATUS_RAW_WR_ERR_M 0x00000001U

#define	ICACHE_IRQ_STATUS_RAW_WR_ERR_S 0U

#define	ICACHE_IRQ_STATUS_RAW_WR_HIT 0x00000002U

#define	ICACHE_IRQ_STATUS_RAW_WR_HIT_M 0x00000002U

#define	ICACHE_IRQ_STATUS_RAW_WR_HIT_S 1U

#define	ICACHE_IRQ_STATUS_MASK_MEM_ERR 0x00000001U

#define	ICACHE_IRQ_STATUS_MASK_MEM_ERR_M 0x00000001U

#define	ICACHE_IRQ_STATUS_MASK_MEM_ERR_S 0U

#define	ICACHE_IRQ_STATUS_MASK_MEM_HIT 0x00000002U

#define	ICACHE_IRQ_STATUS_MASK_MEM_HIT_M 0x00000002U

#define	ICACHE_IRQ_STATUS_MASK_MEM_HIT_S 1U

#define	ICACHE_IRQ_ENABLE_SET_EN_WR_ERR 0x00000001U

#define	ICACHE_IRQ_ENABLE_SET_EN_WR_ERR_M 0x00000001U

#define	ICACHE_IRQ_ENABLE_SET_EN_WR_ERR_S 0U

#define	ICACHE_IRQ_ENABLE_SET_EN_WR_HIT 0x00000002U

#define	ICACHE_IRQ_ENABLE_SET_EN_WR_HIT_M 0x00000002U

#define	ICACHE_IRQ_ENABLE_SET_EN_WR_HIT_S 1U

#define	ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR 0x00000001U

#define	ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR_M 0x00000001U

#define	ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR_S 0U

#define	ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT 0x00000002U

#define	ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT_M 0x00000002U

#define	ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT_S 1U

Macro Definition Documentation

§ ICACHE_O_MOD_VERSION

#define ICACHE_O_MOD_VERSION 0x00000000U

§ ICACHE_O_CTRL

#define ICACHE_O_CTRL 0x00000004U

§ ICACHE_O_STATUS

#define ICACHE_O_STATUS 0x00000008U

§ ICACHE_O_CACHE_ADDRESS_LOW

#define ICACHE_O_CACHE_ADDRESS_LOW 0x00000010U

§ ICACHE_O_CACHE_ADDRESS_HIGH

#define ICACHE_O_CACHE_ADDRESS_HIGH 0x00000018U

§ ICACHE_O_REGISTER_ADDRESS

#define ICACHE_O_REGISTER_ADDRESS 0x00000020U

§ ICACHE_O_HIT_COUNTER

#define ICACHE_O_HIT_COUNTER 0x00000040U

§ ICACHE_O_MISS_COUNTER

#define ICACHE_O_MISS_COUNTER 0x00000044U

§ ICACHE_O_IRQ_STATUS_RAW

#define ICACHE_O_IRQ_STATUS_RAW 0x00000080U

§ ICACHE_O_IRQ_STATUS_MASK

#define ICACHE_O_IRQ_STATUS_MASK 0x00000084U

§ ICACHE_O_IRQ_ENABLE_SET

#define ICACHE_O_IRQ_ENABLE_SET 0x00000088U

§ ICACHE_O_IRQ_ENABLE_CLR

#define ICACHE_O_IRQ_ENABLE_CLR 0x0000008CU

§ ICACHE_MOD_VERSION_MINOR_REVISION_W

#define ICACHE_MOD_VERSION_MINOR_REVISION_W 6U

§ ICACHE_MOD_VERSION_MINOR_REVISION_M

#define ICACHE_MOD_VERSION_MINOR_REVISION_M 0x0000003FU

§ ICACHE_MOD_VERSION_MINOR_REVISION_S

#define ICACHE_MOD_VERSION_MINOR_REVISION_S 0U

§ ICACHE_MOD_VERSION_CUSTOM_REVISION_W

#define ICACHE_MOD_VERSION_CUSTOM_REVISION_W 2U

§ ICACHE_MOD_VERSION_CUSTOM_REVISION_M

#define ICACHE_MOD_VERSION_CUSTOM_REVISION_M 0x000000C0U

§ ICACHE_MOD_VERSION_CUSTOM_REVISION_S

#define ICACHE_MOD_VERSION_CUSTOM_REVISION_S 6U

§ ICACHE_MOD_VERSION_MAJOR_REVISION_W

#define ICACHE_MOD_VERSION_MAJOR_REVISION_W 3U

§ ICACHE_MOD_VERSION_MAJOR_REVISION_M

#define ICACHE_MOD_VERSION_MAJOR_REVISION_M 0x00000700U

§ ICACHE_MOD_VERSION_MAJOR_REVISION_S

#define ICACHE_MOD_VERSION_MAJOR_REVISION_S 8U

§ ICACHE_MOD_VERSION_RTL_VERSION_W

#define ICACHE_MOD_VERSION_RTL_VERSION_W 5U

§ ICACHE_MOD_VERSION_RTL_VERSION_M

#define ICACHE_MOD_VERSION_RTL_VERSION_M 0x0000F800U

§ ICACHE_MOD_VERSION_RTL_VERSION_S

#define ICACHE_MOD_VERSION_RTL_VERSION_S 11U

§ ICACHE_MOD_VERSION_MODULE_ID_W

#define ICACHE_MOD_VERSION_MODULE_ID_W 12U

§ ICACHE_MOD_VERSION_MODULE_ID_M

#define ICACHE_MOD_VERSION_MODULE_ID_M 0x0FFF0000U

§ ICACHE_MOD_VERSION_MODULE_ID_S

#define ICACHE_MOD_VERSION_MODULE_ID_S 16U

§ ICACHE_MOD_VERSION_BU_W

#define ICACHE_MOD_VERSION_BU_W 2U

§ ICACHE_MOD_VERSION_BU_M

#define ICACHE_MOD_VERSION_BU_M 0x30000000U

§ ICACHE_MOD_VERSION_BU_S

#define ICACHE_MOD_VERSION_BU_S 28U

§ ICACHE_MOD_VERSION_SCHEME_W

#define ICACHE_MOD_VERSION_SCHEME_W 2U

§ ICACHE_MOD_VERSION_SCHEME_M

#define ICACHE_MOD_VERSION_SCHEME_M 0xC0000000U

§ ICACHE_MOD_VERSION_SCHEME_S

#define ICACHE_MOD_VERSION_SCHEME_S 30U

§ ICACHE_CTRL_MEM_RENABLE

#define ICACHE_CTRL_MEM_RENABLE 0x40000000U

§ ICACHE_CTRL_MEM_RENABLE_M

#define ICACHE_CTRL_MEM_RENABLE_M 0x40000000U

§ ICACHE_CTRL_MEM_RENABLE_S

#define ICACHE_CTRL_MEM_RENABLE_S 30U

§ ICACHE_CTRL_MEM_CENABLE

#define ICACHE_CTRL_MEM_CENABLE 0x80000000U

§ ICACHE_CTRL_MEM_CENABLE_M

#define ICACHE_CTRL_MEM_CENABLE_M 0x80000000U

§ ICACHE_CTRL_MEM_CENABLE_S

#define ICACHE_CTRL_MEM_CENABLE_S 31U

§ ICACHE_STATUS_OK_TO_GO

#define ICACHE_STATUS_OK_TO_GO 0x80000000U

§ ICACHE_STATUS_OK_TO_GO_M

#define ICACHE_STATUS_OK_TO_GO_M 0x80000000U

§ ICACHE_STATUS_OK_TO_GO_S

#define ICACHE_STATUS_OK_TO_GO_S 31U

§ ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_W

#define ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_W 20U

§ ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_M

#define ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_M 0xFFFFF000U

§ ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_S

#define ICACHE_CACHE_ADDRESS_LOW_MEM_ADDR_LOW_S 12U

§ ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_W

#define ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_W 20U

§ ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_M

#define ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_M 0xFFFFF000U

§ ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_S

#define ICACHE_CACHE_ADDRESS_HIGH_MEM_ADDR_HIGH_S 12U

§ ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_W

#define ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_W 17U

§ ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_M

#define ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_M 0xFFFF8000U

§ ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_S

#define ICACHE_REGISTER_ADDRESS_MEM_SEG_ADDR_S 15U

§ ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_W

#define ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_W 32U

§ ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_M

#define ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_M 0xFFFFFFFFU

§ ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_S

#define ICACHE_HIT_COUNTER_MEM_HIT_COUNTER_S 0U

§ ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_W

#define ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_W 32U

§ ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_M

#define ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_M 0xFFFFFFFFU

§ ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_S

#define ICACHE_MISS_COUNTER_MEM_MISS_COUNTER_S 0U

§ ICACHE_IRQ_STATUS_RAW_WR_ERR

#define ICACHE_IRQ_STATUS_RAW_WR_ERR 0x00000001U

§ ICACHE_IRQ_STATUS_RAW_WR_ERR_M

#define ICACHE_IRQ_STATUS_RAW_WR_ERR_M 0x00000001U

§ ICACHE_IRQ_STATUS_RAW_WR_ERR_S

#define ICACHE_IRQ_STATUS_RAW_WR_ERR_S 0U

§ ICACHE_IRQ_STATUS_RAW_WR_HIT

#define ICACHE_IRQ_STATUS_RAW_WR_HIT 0x00000002U

§ ICACHE_IRQ_STATUS_RAW_WR_HIT_M

#define ICACHE_IRQ_STATUS_RAW_WR_HIT_M 0x00000002U

§ ICACHE_IRQ_STATUS_RAW_WR_HIT_S

#define ICACHE_IRQ_STATUS_RAW_WR_HIT_S 1U

§ ICACHE_IRQ_STATUS_MASK_MEM_ERR

#define ICACHE_IRQ_STATUS_MASK_MEM_ERR 0x00000001U

§ ICACHE_IRQ_STATUS_MASK_MEM_ERR_M

#define ICACHE_IRQ_STATUS_MASK_MEM_ERR_M 0x00000001U

§ ICACHE_IRQ_STATUS_MASK_MEM_ERR_S

#define ICACHE_IRQ_STATUS_MASK_MEM_ERR_S 0U

§ ICACHE_IRQ_STATUS_MASK_MEM_HIT

#define ICACHE_IRQ_STATUS_MASK_MEM_HIT 0x00000002U

§ ICACHE_IRQ_STATUS_MASK_MEM_HIT_M

#define ICACHE_IRQ_STATUS_MASK_MEM_HIT_M 0x00000002U

§ ICACHE_IRQ_STATUS_MASK_MEM_HIT_S

#define ICACHE_IRQ_STATUS_MASK_MEM_HIT_S 1U

§ ICACHE_IRQ_ENABLE_SET_EN_WR_ERR

#define ICACHE_IRQ_ENABLE_SET_EN_WR_ERR 0x00000001U

§ ICACHE_IRQ_ENABLE_SET_EN_WR_ERR_M

#define ICACHE_IRQ_ENABLE_SET_EN_WR_ERR_M 0x00000001U

§ ICACHE_IRQ_ENABLE_SET_EN_WR_ERR_S

#define ICACHE_IRQ_ENABLE_SET_EN_WR_ERR_S 0U

§ ICACHE_IRQ_ENABLE_SET_EN_WR_HIT

#define ICACHE_IRQ_ENABLE_SET_EN_WR_HIT 0x00000002U

§ ICACHE_IRQ_ENABLE_SET_EN_WR_HIT_M

#define ICACHE_IRQ_ENABLE_SET_EN_WR_HIT_M 0x00000002U

§ ICACHE_IRQ_ENABLE_SET_EN_WR_HIT_S

#define ICACHE_IRQ_ENABLE_SET_EN_WR_HIT_S 1U

§ ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR

#define ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR 0x00000001U

§ ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR_M

#define ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR_M 0x00000001U

§ ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR_S

#define ICACHE_IRQ_ENABLE_CLR_EN_WR_ERR_S 0U

§ ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT

#define ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT 0x00000002U

§ ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT_M

#define ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT_M 0x00000002U

§ ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT_S

#define ICACHE_IRQ_ENABLE_CLR_EN_WR_HIT_S 1U

Macros