CC35xxDriverLibrary
hw_i2s.h
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1 /******************************************************************************
2 * Filename: hw_i2s.h
3 *
4 * Description: Defines and prototypes for the I2S peripheral.
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36 #ifndef __HW_I2S_H__
37 #define __HW_I2S_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the I2S component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //WCLK Source Selection
45 #define I2S_O_AIFWCLKSRC 0x00000000U
46 
47 //DMA Buffer Size Configuration
48 #define I2S_O_AIFDMACFG 0x00000004U
49 
50 //Pin Direction
51 #define I2S_O_AIFDIRCFG 0x00000008U
52 
53 //Serial Interface Format Configuration
54 #define I2S_O_AIFFMTCFG 0x0000000CU
55 
56 //Word Selection Bit Mask for Pin 0
57 #define I2S_O_AIFWMASK0 0x00000010U
58 
59 //Word Selection Bit Mask for Pin 1
60 #define I2S_O_AIFWMASK1 0x00000014U
61 
62 //DMA Input Buffer Next Pointer
63 #define I2S_O_AIFINPTNXT 0x00000020U
64 
65 //DMA Input Buffer Current Pointer
66 #define I2S_O_AIFINPTR 0x00000024U
67 
68 //DMA Output Buffer Next Pointer
69 #define I2S_O_AIFOPTNXT 0x00000028U
70 
71 //DMA Output Buffer Current Pointer
72 #define I2S_O_AIFOUTPTR 0x0000002CU
73 
74 //Samplestamp Generator Control Register
75 #define I2S_O_STMPCTL 0x00000034U
76 
77 //Captured **XOSC** Counter Value, Capture Channel 0
78 #define I2S_O_STMPXCPT0 0x00000038U
79 
80 //XOSC Period Value
81 #define I2S_O_STMPXPER 0x0000003CU
82 
83 //Captured **WCLK** Counter Value, Capture Channel 0
84 #define I2S_O_STMPWCPT0 0x00000040U
85 
86 //**WCLK** Counter Period Value
87 #define I2S_O_STMPWPER 0x00000044U
88 
89 //WCLK Counter Trigger Value for Input Pins
90 #define I2S_O_STMPINTRIG 0x00000048U
91 
92 //WCLK Counter Trigger Value for Output Pins
93 #define I2S_O_STMPOTRIG 0x0000004CU
94 
95 //WCLK Counter Set Operation
96 #define I2S_O_STMPWSET 0x00000050U
97 
98 //WCLK Counter Add Operation
99 #define I2S_O_STMPWADD 0x00000054U
100 
101 //XOSC Minimum Period Value
102 #define I2S_O_STMPXPRMIN 0x00000058U
103 
104 //Current Value of WCNT
105 #define I2S_O_STMPWCNT 0x0000005CU
106 
107 //Current Value of XCNT
108 #define I2S_O_STMPXCNT 0x00000060U
109 
110 //Interrupt Mask Register
111 #define I2S_O_IRQMASK 0x00000070U
112 
113 //Raw Interrupt Status Register
114 #define I2S_O_IRQFLAGS 0x00000074U
115 
116 //Interrupt Set Register
117 #define I2S_O_IRQSET 0x00000078U
118 
119 //Interrupt Clear Register
120 #define I2S_O_IRQCLR 0x0000007CU
121 
122 //**MCLK** Division Ratio
123 #define I2S_O_AIFMCLKDIV 0x00000080U
124 
125 //**BCLK** Division Ratio
126 #define I2S_O_AIFBCLKDIV 0x00000084U
127 
128 //**WCLK** Division Ratio
129 #define I2S_O_AIFWCLKDIV 0x00000088U
130 
131 //Internal Audio Clock Control
132 #define I2S_O_AIFCLKCTL 0x0000008CU
133 
134 //Audio clock source selection and **I2S** enable register
135 #define I2S_O_CLKCFG 0x00001000U
136 
137 //ADFS TREF control register
138 #define I2S_O_ADFSCTRL1 0x00001004U
139 
140 //ADFS general configuration register
141 #define I2S_O_ADFSCTRL2 0x00001008U
142 
143 
144 
145 /*-----------------------------------REGISTER------------------------------------
146  Register name: AIFWCLKSRC
147  Offset name: I2S_O_AIFWCLKSRC
148  Relative address: 0x0
149  Description: WCLK Source Selection
150  Default Value: 0x00000000
151 
152  Field: WBCLKSRC
153  From..to bits: 0...1
154  DefaultValue: 0x0
155  Access type: read-write
156  Description: Selects **WCLK** / **BCLK** source for **AIF**.
157 
158  ENUMs:
159  NONE: None ('0')
160  EXT: External **WCLK** generator, from pad
161  INT: Internal **WCLK** generator, from module PRCM
162  RESERVED: Not supported. Will give same **WCLK** as 'NONE' ('00')
163 */
164 #define I2S_AIFWCLKSRC_WBCLKSRC_W 2U
165 #define I2S_AIFWCLKSRC_WBCLKSRC_M 0x00000003U
166 #define I2S_AIFWCLKSRC_WBCLKSRC_S 0U
167 #define I2S_AIFWCLKSRC_WBCLKSRC_NONE 0x00000000U
168 #define I2S_AIFWCLKSRC_WBCLKSRC_EXT 0x00000001U
169 #define I2S_AIFWCLKSRC_WBCLKSRC_INT 0x00000002U
170 #define I2S_AIFWCLKSRC_WBCLKSRC_RESERVED 0x00000003U
171 /*
172 
173  Field: WCLKINV
174  From..to bits: 2...2
175  DefaultValue: 0x0
176  Access type: read-write
177  Description: Inverts **WCLK** source (pad or internal) when set.
178 
179  0: Not inverted
180  1: Inverted
181 
182 */
183 #define I2S_AIFWCLKSRC_WCLKINV 0x00000004U
184 #define I2S_AIFWCLKSRC_WCLKINV_M 0x00000004U
185 #define I2S_AIFWCLKSRC_WCLKINV_S 2U
186 
187 
188 /*-----------------------------------REGISTER------------------------------------
189  Register name: AIFDMACFG
190  Offset name: I2S_O_AIFDMACFG
191  Relative address: 0x4
192  Description: DMA Buffer Size Configuration
193  Default Value: 0x00000000
194 
195  Field: ENDFRAMIDX
196  From..to bits: 0...7
197  DefaultValue: 0x0
198  Access type: read-write
199  Description: Defines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes AIF. Note that before doing so, all other configuration must have been done, and [AIFINPTRNEXT.*]/[AIFOUTPTRNEXT.*] must have been loaded.
200 
201 */
202 #define I2S_AIFDMACFG_ENDFRAMIDX_W 8U
203 #define I2S_AIFDMACFG_ENDFRAMIDX_M 0x000000FFU
204 #define I2S_AIFDMACFG_ENDFRAMIDX_S 0U
205 
206 
207 /*-----------------------------------REGISTER------------------------------------
208  Register name: AIFDIRCFG
209  Offset name: I2S_O_AIFDIRCFG
210  Relative address: 0x8
211  Description: Pin Direction
212  Default Value: 0x00000000
213 
214  Field: AD0
215  From..to bits: 0...1
216  DefaultValue: 0x0
217  Access type: read-write
218  Description: Configures the **AD0** audio data pin usage:
219 
220  0x3: Reserved
221 
222  ENUMs:
223  DIS: Not in use (disabled)
224  IN: Input mode
225  OUT: Output mode
226 */
227 #define I2S_AIFDIRCFG_AD0_W 2U
228 #define I2S_AIFDIRCFG_AD0_M 0x00000003U
229 #define I2S_AIFDIRCFG_AD0_S 0U
230 #define I2S_AIFDIRCFG_AD0_DIS 0x00000000U
231 #define I2S_AIFDIRCFG_AD0_IN 0x00000001U
232 #define I2S_AIFDIRCFG_AD0_OUT 0x00000002U
233 /*
234 
235  Field: AD1
236  From..to bits: 4...5
237  DefaultValue: 0x0
238  Access type: read-write
239  Description: Configures the **AD1** audio data pin usage:
240 
241  0x3: Reserved
242 
243  ENUMs:
244  DIS: Not in use (disabled)
245  IN: Input mode
246  OUT: Output mode
247 */
248 #define I2S_AIFDIRCFG_AD1_W 2U
249 #define I2S_AIFDIRCFG_AD1_M 0x00000030U
250 #define I2S_AIFDIRCFG_AD1_S 4U
251 #define I2S_AIFDIRCFG_AD1_DIS 0x00000000U
252 #define I2S_AIFDIRCFG_AD1_IN 0x00000010U
253 #define I2S_AIFDIRCFG_AD1_OUT 0x00000020U
254 
255 
256 /*-----------------------------------REGISTER------------------------------------
257  Register name: AIFFMTCFG
258  Offset name: I2S_O_AIFFMTCFG
259  Relative address: 0xC
260  Description: Serial Interface Format Configuration
261  Default Value: 0x00000010
262 
263  Field: WORDLEN
264  From..to bits: 0...4
265  DefaultValue: 0x10
266  Access type: read-write
267  Description: Number of bits per word (8-24):
268  In single-phase format, this is the exact number of bits per word.
269  In dual-phase format, this is the maximum number of bits per word.
270 
271  Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by [MEM_LEN_24]. Bit widths that differ from this alignment will either be truncated or zero padded.
272 
273 
274 */
275 #define I2S_AIFFMTCFG_WORDLEN_W 5U
276 #define I2S_AIFFMTCFG_WORDLEN_M 0x0000001FU
277 #define I2S_AIFFMTCFG_WORDLEN_S 0U
278 /*
279 
280  Field: DUALPHASE
281  From..to bits: 5...5
282  DefaultValue: 0x0
283  Access type: read-write
284  Description: Selects dual- or single-phase format.
285 
286  0: Single-phase: **DSP** format
287  1: Dual-phase: **I2S**, **LJF** and **RJF** formats
288 
289 */
290 #define I2S_AIFFMTCFG_DUALPHASE 0x00000020U
291 #define I2S_AIFFMTCFG_DUALPHASE_M 0x00000020U
292 #define I2S_AIFFMTCFG_DUALPHASE_S 5U
293 /*
294 
295  Field: SMPLEDGE
296  From..to bits: 6...6
297  DefaultValue: 0x0
298  Access type: read-write
299  Description: On the serial audio interface, data (and wclk) is sampled and clocked out on opposite edges of BCLK.
300 
301  ENUMs:
302  NEG: Data is sampled on the negative edge and clocked out on the positive edge.
303  POS: Data is sampled on the positive edge and clocked out on the negative edge.
304 */
305 #define I2S_AIFFMTCFG_SMPLEDGE 0x00000040U
306 #define I2S_AIFFMTCFG_SMPLEDGE_M 0x00000040U
307 #define I2S_AIFFMTCFG_SMPLEDGE_S 6U
308 #define I2S_AIFFMTCFG_SMPLEDGE_NEG 0x00000000U
309 #define I2S_AIFFMTCFG_SMPLEDGE_POS 0x00000040U
310 /*
311 
312  Field: LEN32
313  From..to bits: 7...7
314  DefaultValue: 0x0
315  Access type: read-write
316  Description: The size of each word stored to or loaded from memory:
317 
318  ENUMs:
319  _16BIT: 16-bit (one 16 bit access per sample)
320  _32BIT: 32-bit(one 32-bit access per sample)
321 */
322 #define I2S_AIFFMTCFG_LEN32 0x00000080U
323 #define I2S_AIFFMTCFG_LEN32_M 0x00000080U
324 #define I2S_AIFFMTCFG_LEN32_S 7U
325 #define I2S_AIFFMTCFG_LEN32__16BIT 0x00000000U
326 #define I2S_AIFFMTCFG_LEN32__32BIT 0x00000080U
327 /*
328 
329  Field: DATADELAY
330  From..to bits: 8...15
331  DefaultValue: 0x0
332  Access type: read-write
333  Description: The number of **BCLK** periods between a **WCLK** edge and **MSB** of the first word in a phase:
334 
335  0x00: **LJF** and **DSP** format
336  0x01: **I2S** and **DSP** format
337  0x02: **RJF** format
338  ...
339  0xFF: **RJF** format
340 
341  Note: When 0, **MSB** of the next word will be output in the idle period between **LSB** of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.
342 
343 */
344 #define I2S_AIFFMTCFG_DATADELAY_W 8U
345 #define I2S_AIFFMTCFG_DATADELAY_M 0x0000FF00U
346 #define I2S_AIFFMTCFG_DATADELAY_S 8U
347 
348 
349 /*-----------------------------------REGISTER------------------------------------
350  Register name: AIFWMASK0
351  Offset name: I2S_O_AIFWMASK0
352  Relative address: 0x10
353  Description: Word Selection Bit Mask for Pin 0
354  Default Value: 0x00000003
355 
356  Field: MASK
357  From..to bits: 0...7
358  DefaultValue: 0x3
359  Access type: read-write
360  Description: Bit-mask indicating valid channels in a frame on AD0.
361 
362  In single-phase mode, each bit represents one channel, starting with **LSB** for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
363 
364  In dual-phase mode, only the two **LSB**s are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
365 
366  In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
367 
368  If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when **PWM** debug output is desired without any actively used output pins.
369 
370 
371 */
372 #define I2S_AIFWMASK0_MASK_W 8U
373 #define I2S_AIFWMASK0_MASK_M 0x000000FFU
374 #define I2S_AIFWMASK0_MASK_S 0U
375 
376 
377 /*-----------------------------------REGISTER------------------------------------
378  Register name: AIFWMASK1
379  Offset name: I2S_O_AIFWMASK1
380  Relative address: 0x14
381  Description: Word Selection Bit Mask for Pin 1
382  Default Value: 0x00000003
383 
384  Field: MASK
385  From..to bits: 0...7
386  DefaultValue: 0x3
387  Access type: read-write
388  Description: Bit-mask indicating valid channels in a frame on AD1.
389 
390  In single-phase mode, each bit represents one channel, starting with **LSB** for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'.
391 
392  In dual-phase mode, only the two **LSB**s are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out.
393 
394  In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out.
395 
396  If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when **PWM** debug output is desired without any actively used output pins.
397 
398 */
399 #define I2S_AIFWMASK1_MASK_W 8U
400 #define I2S_AIFWMASK1_MASK_M 0x000000FFU
401 #define I2S_AIFWMASK1_MASK_S 0U
402 
403 
404 /*-----------------------------------REGISTER------------------------------------
405  Register name: AIFINPTNXT
406  Offset name: I2S_O_AIFINPTNXT
407  Relative address: 0x20
408  Description: DMA Input Buffer Next Pointer
409  Default Value: 0x00000000
410 
411  Field: PTR
412  From..to bits: 0...31
413  DefaultValue: 0x0
414  Access type: read-write
415  Description: Pointer to the first byte in the next **DMA** input buffer.
416 
417  The read value equals the last written value until the currently used **DMA** input buffer is completed, and then becomes null when the last written value is transferred to the **DMA** controller to start on the next buffer. This event is signalized by [IRQFLAGS-AIF_DMA_IN].
418 
419  At startup, the value must be written once before and once after configuring the **DMA** buffer size in [AIFDMACFG.*].
420 
421  The next pointer must be written to this register while the **DMA** function uses the previously written pointer. If not written in time, [IRQFLAGS.PTR_ERR] will be raised and all input pins will be disabled.
422 
423 */
424 #define I2S_AIFINPTNXT_PTR_W 32U
425 #define I2S_AIFINPTNXT_PTR_M 0xFFFFFFFFU
426 #define I2S_AIFINPTNXT_PTR_S 0U
427 
428 
429 /*-----------------------------------REGISTER------------------------------------
430  Register name: AIFINPTR
431  Offset name: I2S_O_AIFINPTR
432  Relative address: 0x24
433  Description: DMA Input Buffer Current Pointer
434  Default Value: 0x00000000
435 
436  Field: PTR
437  From..to bits: 0...31
438  DefaultValue: 0x0
439  Access type: read-only
440  Description: Value of the **DMA** input buffer pointer currently used by the **DMA** controller. Incremented by 1 (byte) or 2 (word) for each **AHB** access.
441 
442 */
443 #define I2S_AIFINPTR_PTR_W 32U
444 #define I2S_AIFINPTR_PTR_M 0xFFFFFFFFU
445 #define I2S_AIFINPTR_PTR_S 0U
446 
447 
448 /*-----------------------------------REGISTER------------------------------------
449  Register name: AIFOPTNXT
450  Offset name: I2S_O_AIFOPTNXT
451  Relative address: 0x28
452  Description: DMA Output Buffer Next Pointer
453  Default Value: 0x00000000
454 
455  Field: PTR
456  From..to bits: 0...31
457  DefaultValue: 0x0
458  Access type: read-write
459  Description: Pointer to the first byte in the next **DMA** output buffer.
460 
461  The read value equals the last written value until the currently used **DMA** output buffer is completed, and then becomes null when the last written value is transferred to the **DMA** controller to start on the next buffer. This event is signalized by [IRQFLAGS.AIF_DMA_OUT].
462 
463  At startup, the value must be written once before and once after configuring the **DMA** buffer size in [AIFDMACFG.*]. At this time, the first two samples will be fetched from memory.
464 
465  The next pointer must be written to this register while the **DMA** function uses the previously written pointer. If not written in time, [IRQFLAGS.PTR_ERR] will be raised and all output pins will be disabled.
466 
467 */
468 #define I2S_AIFOPTNXT_PTR_W 32U
469 #define I2S_AIFOPTNXT_PTR_M 0xFFFFFFFFU
470 #define I2S_AIFOPTNXT_PTR_S 0U
471 
472 
473 /*-----------------------------------REGISTER------------------------------------
474  Register name: AIFOUTPTR
475  Offset name: I2S_O_AIFOUTPTR
476  Relative address: 0x2C
477  Description: DMA Output Buffer Current Pointer
478  Default Value: 0x00000000
479 
480  Field: PTR
481  From..to bits: 0...31
482  DefaultValue: 0x0
483  Access type: read-only
484  Description: Value of the **DMA** output buffer pointer currently used by the **DMA** controller Incremented by 1 (byte) or 2 (word) for each **AHB** access.
485 
486 */
487 #define I2S_AIFOUTPTR_PTR_W 32U
488 #define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFFU
489 #define I2S_AIFOUTPTR_PTR_S 0U
490 
491 
492 /*-----------------------------------REGISTER------------------------------------
493  Register name: STMPCTL
494  Offset name: I2S_O_STMPCTL
495  Relative address: 0x34
496  Description: Samplestamp Generator Control Register
497  Default Value: 0x00000000
498 
499  Field: STMPEN
500  From..to bits: 0...0
501  DefaultValue: 0x0
502  Access type: read-write
503  Description: Enables the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.
504  When cleared, all samplestamp generator counters and capture values are cleared.
505 
506 
507 */
508 #define I2S_STMPCTL_STMPEN 0x00000001U
509 #define I2S_STMPCTL_STMPEN_M 0x00000001U
510 #define I2S_STMPCTL_STMPEN_S 0U
511 /*
512 
513  Field: INRDY
514  From..to bits: 1...1
515  DefaultValue: 0x0
516  Access type: read-only
517  Description: Low until the input pins are ready to be started by the samplestamp generator. When started (that is [STMPINTRIG.*] equals the **WCLK** counter) the bit goes back low.
518 
519 */
520 #define I2S_STMPCTL_INRDY 0x00000002U
521 #define I2S_STMPCTL_INRDY_M 0x00000002U
522 #define I2S_STMPCTL_INRDY_S 1U
523 /*
524 
525  Field: OUTRDY
526  From..to bits: 2...2
527  DefaultValue: 0x0
528  Access type: read-only
529  Description: Low until the output pins are ready to be started by the samplestamp generator. When started (that is [STMPOUTTRIG.*] equals the **WCLK** counter) the bit goes back low.
530 
531 */
532 #define I2S_STMPCTL_OUTRDY 0x00000004U
533 #define I2S_STMPCTL_OUTRDY_M 0x00000004U
534 #define I2S_STMPCTL_OUTRDY_S 2U
535 
536 
537 /*-----------------------------------REGISTER------------------------------------
538  Register name: STMPXCPT0
539  Offset name: I2S_O_STMPXCPT0
540  Relative address: 0x38
541  Description: Captured **XOSC** Counter Value, Capture Channel 0
542  Default Value: 0x00000000
543 
544  Field: CAPTVAL
545  From..to bits: 0...15
546  DefaultValue: 0x0
547  Access type: read-only
548  Description: The value of the samplestamp **XOSC** counter ([STMPXCNT.CURR_VALUE]) last time an event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected **WCLK**.
549  The value is cleared when [STMPCTL.STMP_EN] = 0.
550  Note: Due to buffering and synchronization, **WCLK** is delayed by a small number of **BCLK** periods and clk periods.
551  Note: When calculating the fractional part of the sample stamp, [STMPXPER.*] may be less than this bit field.
552 
553 
554 */
555 #define I2S_STMPXCPT0_CAPTVAL_W 16U
556 #define I2S_STMPXCPT0_CAPTVAL_M 0x0000FFFFU
557 #define I2S_STMPXCPT0_CAPTVAL_S 0U
558 
559 
560 /*-----------------------------------REGISTER------------------------------------
561  Register name: STMPXPER
562  Offset name: I2S_O_STMPXPER
563  Relative address: 0x3C
564  Description: XOSC Period Value
565  Default Value: 0x00000000
566 
567  Field: VALUE
568  From..to bits: 0...15
569  DefaultValue: 0x0
570  Access type: read-only
571  Description: The number of 24 MHz clock cycles in the previous **WCLK** period (that is - the next value of the **XOSC** counter at the positive **WCLK** edge, had it not been reset to 0).
572  The value is cleared when [STMPCTL.STMP_EN] = 0.
573 
574 
575 */
576 #define I2S_STMPXPER_VALUE_W 16U
577 #define I2S_STMPXPER_VALUE_M 0x0000FFFFU
578 #define I2S_STMPXPER_VALUE_S 0U
579 
580 
581 /*-----------------------------------REGISTER------------------------------------
582  Register name: STMPWCPT0
583  Offset name: I2S_O_STMPWCPT0
584  Relative address: 0x40
585  Description: Captured **WCLK** Counter Value, Capture Channel 0
586  Default Value: 0x00000000
587 
588  Field: CAPTVAL
589  From..to bits: 0...15
590  DefaultValue: 0x0
591  Access type: read-only
592  Description: The value of the samplestamp **WCLK** counter ([STMPWCNT.CURR_VALUE]) last time an event was pulsed (event source selected in [EVENT:I2SSTMPSEL0.EV] for channel 0). This number corresponds to the number of positive **WCLK** edges since the samplestamp generator was enabled (not taking modification through [STMPWADD.*]/[STMPWSET.*] into account).
593  The value is cleared when [STMPCTL.STMP_EN] = 0.
594 
595 
596 */
597 #define I2S_STMPWCPT0_CAPTVAL_W 16U
598 #define I2S_STMPWCPT0_CAPTVAL_M 0x0000FFFFU
599 #define I2S_STMPWCPT0_CAPTVAL_S 0U
600 
601 
602 /*-----------------------------------REGISTER------------------------------------
603  Register name: STMPWPER
604  Offset name: I2S_O_STMPWPER
605  Relative address: 0x44
606  Description: **WCLK** Counter Period Value
607  Default Value: 0x00000000
608 
609  Field: VALUE
610  From..to bits: 0...15
611  DefaultValue: 0x0
612  Access type: read-write
613  Description: Used to define when [STMPWCNT.*] is to be reset so number of **WCLK** edges are found for the size of the sample buffer. This is thus a modulo value for the **WCLK** counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).
614 
615 */
616 #define I2S_STMPWPER_VALUE_W 16U
617 #define I2S_STMPWPER_VALUE_M 0x0000FFFFU
618 #define I2S_STMPWPER_VALUE_S 0U
619 
620 
621 /*-----------------------------------REGISTER------------------------------------
622  Register name: STMPINTRIG
623  Offset name: I2S_O_STMPINTRIG
624  Relative address: 0x48
625  Description: WCLK Counter Trigger Value for Input Pins
626  Default Value: 0x00000000
627 
628  Field: INSTRTWCNT
629  From..to bits: 0...15
630  DefaultValue: 0x0
631  Access type: read-write
632  Description: Compare value used to start the incoming audio streams.
633  This bit field shall equal the **WCLK** counter value during the **WCLK** period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first **DMA** input buffer).
634 
635  The value of this register takes effect when the following conditions are met:
636  - One or more pins are configured as inputs in [AIFDIRCFG.*].
637  - [AIFDMACFG.*] has been configured for the correct buffer size, and at least 32 **BCLK** cycle ticks have happened.
638 
639  Note: To avoid false triggers, this bit field should be set higher than [STMPWPER.VALUE].
640 
641 
642 */
643 #define I2S_STMPINTRIG_INSTRTWCNT_W 16U
644 #define I2S_STMPINTRIG_INSTRTWCNT_M 0x0000FFFFU
645 #define I2S_STMPINTRIG_INSTRTWCNT_S 0U
646 
647 
648 /*-----------------------------------REGISTER------------------------------------
649  Register name: STMPOTRIG
650  Offset name: I2S_O_STMPOTRIG
651  Relative address: 0x4C
652  Description: WCLK Counter Trigger Value for Output Pins
653  Default Value: 0x00000000
654 
655  Field: OSTRTWCNT
656  From..to bits: 0...15
657  DefaultValue: 0x0
658  Access type: read-write
659  Description: OUT START WCNT:
660  Compare value used to start the outgoing audio streams.
661 
662  This bit field must equal the **WCLK** counter value during the **WCLK** period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first **DMA** output buffer).
663 
664  The value of this register takes effect when the following conditions are met:
665  - One or more pins are configured as outputs in [AIFDIRCFG.*].
666  - [AIFDMACFG.*] has been configured for the correct buffer size, and 32 **BCLK** cycle ticks have happened.
667  - 2 samples have been preloaded from memory (examine the [AIFOUTPTR.*] register if necessary).
668  Note: The memory read access is only performed when required, that is channels 0/1 must be selected in [AIFWMASK0.*]/[AIFWMASK1.*].
669 
670  Note: To avoid false triggers, this bit field should be set higher than [STMPWPER.VALUE].
671 
672 
673 */
674 #define I2S_STMPOTRIG_OSTRTWCNT_W 16U
675 #define I2S_STMPOTRIG_OSTRTWCNT_M 0x0000FFFFU
676 #define I2S_STMPOTRIG_OSTRTWCNT_S 0U
677 
678 
679 /*-----------------------------------REGISTER------------------------------------
680  Register name: STMPWSET
681  Offset name: I2S_O_STMPWSET
682  Relative address: 0x50
683  Description: WCLK Counter Set Operation
684  Default Value: 0x00000000
685 
686  Field: VALUE
687  From..to bits: 0...15
688  DefaultValue: 0x0
689  Access type: write-only
690  Description: **WCLK** counter modification: Sets the running **WCLK** counter equal to the written value.
691 
692 */
693 #define I2S_STMPWSET_VALUE_W 16U
694 #define I2S_STMPWSET_VALUE_M 0x0000FFFFU
695 #define I2S_STMPWSET_VALUE_S 0U
696 
697 
698 /*-----------------------------------REGISTER------------------------------------
699  Register name: STMPWADD
700  Offset name: I2S_O_STMPWADD
701  Relative address: 0x54
702  Description: WCLK Counter Add Operation
703  Default Value: 0x00000000
704 
705  Field: VALINC
706  From..to bits: 0...15
707  DefaultValue: 0x0
708  Access type: write-only
709  Description: **WCLK** counter modification: Adds the written value to the running **WCLK** counter. If a positive edge of **WCLK** occurs at the same time as the operation, this will be taken into account.
710  To add a negative value, write "[STMPWPER.VALUE] - value".
711 
712 
713 */
714 #define I2S_STMPWADD_VALINC_W 16U
715 #define I2S_STMPWADD_VALINC_M 0x0000FFFFU
716 #define I2S_STMPWADD_VALINC_S 0U
717 
718 
719 /*-----------------------------------REGISTER------------------------------------
720  Register name: STMPXPRMIN
721  Offset name: I2S_O_STMPXPRMIN
722  Relative address: 0x58
723  Description: XOSC Minimum Period Value
724  Minimum Value of [STMPXPER.*]
725  Default Value: 0x0000FFFF
726 
727  Field: VALUE
728  From..to bits: 0...15
729  DefaultValue: 0xFFFF
730  Access type: read-write
731  Description: Each time [STMPXPER.*] is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register.
732  When written, the register is reset to 0xFFFF (65535), regardless of the value written.
733  The minimum value can be used to detect extra **WCLK** pulses (this registers value will be significantly smaller than [STMPXPER.VALUE]).
734 
735 
736 */
737 #define I2S_STMPXPRMIN_VALUE_W 16U
738 #define I2S_STMPXPRMIN_VALUE_M 0x0000FFFFU
739 #define I2S_STMPXPRMIN_VALUE_S 0U
740 
741 
742 /*-----------------------------------REGISTER------------------------------------
743  Register name: STMPWCNT
744  Offset name: I2S_O_STMPWCNT
745  Relative address: 0x5C
746  Description: Current Value of WCNT
747  Default Value: 0x00000000
748 
749  Field: CURRVAL
750  From..to bits: 0...15
751  DefaultValue: 0x0
752  Access type: read-only
753  Description: Current value of the **WCLK** counter
754 
755 */
756 #define I2S_STMPWCNT_CURRVAL_W 16U
757 #define I2S_STMPWCNT_CURRVAL_M 0x0000FFFFU
758 #define I2S_STMPWCNT_CURRVAL_S 0U
759 
760 
761 /*-----------------------------------REGISTER------------------------------------
762  Register name: STMPXCNT
763  Offset name: I2S_O_STMPXCNT
764  Relative address: 0x60
765  Description: Current Value of XCNT
766  Default Value: 0x00000000
767 
768  Field: CURRVAL
769  From..to bits: 0...15
770  DefaultValue: 0x0
771  Access type: read-only
772  Description: Current value of the **XOSC** counter, latched when reading [STMPWCNT.*].
773 
774 */
775 #define I2S_STMPXCNT_CURRVAL_W 16U
776 #define I2S_STMPXCNT_CURRVAL_M 0x0000FFFFU
777 #define I2S_STMPXCNT_CURRVAL_S 0U
778 
779 
780 /*-----------------------------------REGISTER------------------------------------
781  Register name: IRQMASK
782  Offset name: I2S_O_IRQMASK
783  Relative address: 0x70
784  Description: Interrupt Mask Register
785 
786  Selects mask states of the flags in [IRQFLAGS.*] that contribute to the **I2S_IRQ** event.
787  Default Value: 0x00000000
788 
789  Field: PTRERR
790  From..to bits: 0...0
791  DefaultValue: 0x0
792  Access type: read-write
793  Description: [IRQFLAGS.PTR_ERR] interrupt mask.
794 
795  0: Disable
796  1: Enable
797 
798 */
799 #define I2S_IRQMASK_PTRERR 0x00000001U
800 #define I2S_IRQMASK_PTRERR_M 0x00000001U
801 #define I2S_IRQMASK_PTRERR_S 0U
802 /*
803 
804  Field: WCLKERR
805  From..to bits: 1...1
806  DefaultValue: 0x0
807  Access type: read-write
808  Description: [IRQFLAGS.WCLK_ERR] interrupt mask
809 
810  0: Disable
811  1: Enable
812 
813 */
814 #define I2S_IRQMASK_WCLKERR 0x00000002U
815 #define I2S_IRQMASK_WCLKERR_M 0x00000002U
816 #define I2S_IRQMASK_WCLKERR_S 1U
817 /*
818 
819  Field: BUSERR
820  From..to bits: 2...2
821  DefaultValue: 0x0
822  Access type: read-write
823  Description: [IRQFLAGS.BUS_ERR] interrupt mask
824 
825  0: Disable
826  1: Enable
827 
828 */
829 #define I2S_IRQMASK_BUSERR 0x00000004U
830 #define I2S_IRQMASK_BUSERR_M 0x00000004U
831 #define I2S_IRQMASK_BUSERR_S 2U
832 /*
833 
834  Field: WCLKTOUT
835  From..to bits: 3...3
836  DefaultValue: 0x0
837  Access type: read-write
838  Description: [IRQFLAGS.WCLK_TIMEOUT] interrupt mask
839 
840  0: Disable
841  1: Enable
842 
843 */
844 #define I2S_IRQMASK_WCLKTOUT 0x00000008U
845 #define I2S_IRQMASK_WCLKTOUT_M 0x00000008U
846 #define I2S_IRQMASK_WCLKTOUT_S 3U
847 /*
848 
849  Field: AIFDMAOUT
850  From..to bits: 4...4
851  DefaultValue: 0x0
852  Access type: read-write
853  Description: [IRQFLAGS.AIF_DMA_OUT] interrupt mask
854 
855  0: Disable
856  1: Enable
857 
858 */
859 #define I2S_IRQMASK_AIFDMAOUT 0x00000010U
860 #define I2S_IRQMASK_AIFDMAOUT_M 0x00000010U
861 #define I2S_IRQMASK_AIFDMAOUT_S 4U
862 /*
863 
864  Field: AIFDMAIN
865  From..to bits: 5...5
866  DefaultValue: 0x0
867  Access type: read-write
868  Description: [IRQFLAGS.AIF_DMA_IN] interrupt mask
869 
870  0: Disable
871  1: Enable
872 
873 */
874 #define I2S_IRQMASK_AIFDMAIN 0x00000020U
875 #define I2S_IRQMASK_AIFDMAIN_M 0x00000020U
876 #define I2S_IRQMASK_AIFDMAIN_S 5U
877 /*
878 
879  Field: XCNTCPT
880  From..to bits: 6...6
881  DefaultValue: 0x0
882  Access type: read-write
883  Description: [IRQFLAGS.XCNT_CAPTURE] interrupt mask
884 
885  0: Disable
886  1: Enable
887 
888 */
889 #define I2S_IRQMASK_XCNTCPT 0x00000040U
890 #define I2S_IRQMASK_XCNTCPT_M 0x00000040U
891 #define I2S_IRQMASK_XCNTCPT_S 6U
892 
893 
894 /*-----------------------------------REGISTER------------------------------------
895  Register name: IRQFLAGS
896  Offset name: I2S_O_IRQFLAGS
897  Relative address: 0x74
898  Description: Raw Interrupt Status Register
899  Default Value: 0x00000000
900 
901  Field: PTRERR
902  From..to bits: 0...0
903  DefaultValue: 0x0
904  Access type: read-only
905  Description: Set when [AIFINPTRNEXT.*] or [AIFOUTPTRNEXT.*] has not been loaded with the next block address in time.
906  This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.PTR_ERR]).
907 
908 
909 */
910 #define I2S_IRQFLAGS_PTRERR 0x00000001U
911 #define I2S_IRQFLAGS_PTRERR_M 0x00000001U
912 #define I2S_IRQFLAGS_PTRERR_S 0U
913 /*
914 
915  Field: WCLKERR
916  From..to bits: 1...1
917  DefaultValue: 0x0
918  Access type: read-only
919  Description: Set when:
920  - An unexpected **WCLK** edge occurs during the data delay period of a phase. Note unexpected **WCLK** edges during the word and idle periods of the phase are not detected.
921  - In dual-phase mode, when two **WCLK** edges are less than 4 **BCLK** cycles apart.
922  - In single-phase mode, when a **WCLK** pulse occurs before the last channel.
923  This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.WCLK_ERR]).
924 
925 */
926 #define I2S_IRQFLAGS_WCLKERR 0x00000002U
927 #define I2S_IRQFLAGS_WCLKERR_M 0x00000002U
928 #define I2S_IRQFLAGS_WCLKERR_S 1U
929 /*
930 
931  Field: BUSERR
932  From..to bits: 2...2
933  DefaultValue: 0x0
934  Access type: read-only
935  Description: Set when a **DMA** operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow).
936  This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.BUS_ERR]).
937 
938  Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined.
939 
940  INTERNAL_NOTE:
941  The I2S module is not monitoring the AHB bus error response, hence bus faults resulting from access to illegal addresses are not generated. It is best practice to detect and report such errors and, therefore, a ticket has been entered into the CDDS bug tracking database for the I2S module. The reference is CC26_I2S--BUG00011.
942  All versions of CC13xx/CC26xx Chameleon and Lizard are impacted, and there is no plans to change this behavior.
943 
944 
945 */
946 #define I2S_IRQFLAGS_BUSERR 0x00000004U
947 #define I2S_IRQFLAGS_BUSERR_M 0x00000004U
948 #define I2S_IRQFLAGS_BUSERR_S 2U
949 /*
950 
951  Field: WCLKTOUT
952  From..to bits: 3...3
953  DefaultValue: 0x0
954  Access type: read-only
955  Description: Set when the sample stamp generator does not detect a positive **WCLK** edge for 65535 clk periods. This signalizes that the internal or external **BCLK** and **WCLK** generator source has been disabled.
956 
957  The bit is sticky and may only be cleared by software (by writing '1' to [IRQCLR.WCLK_TIMEOUT]).
958 
959 */
960 #define I2S_IRQFLAGS_WCLKTOUT 0x00000008U
961 #define I2S_IRQFLAGS_WCLKTOUT_M 0x00000008U
962 #define I2S_IRQFLAGS_WCLKTOUT_S 3U
963 /*
964 
965  Field: AIFDMAOUT
966  From..to bits: 4...4
967  DefaultValue: 0x0
968  Access type: read-only
969  Description: Set when condition for this bit field event occurs (auto cleared when output pointer is updated - [AIFOUTPTRNEXT.*]), see description of [AIFOUTPTRNEXT.*] register for details
970 
971 */
972 #define I2S_IRQFLAGS_AIFDMAOUT 0x00000010U
973 #define I2S_IRQFLAGS_AIFDMAOUT_M 0x00000010U
974 #define I2S_IRQFLAGS_AIFDMAOUT_S 4U
975 /*
976 
977  Field: AIFDMAIN
978  From..to bits: 5...5
979  DefaultValue: 0x0
980  Access type: read-only
981  Description: Set when condition for this bit field event occurs (auto cleared when input pointer is updated - [AIFINPTRNEXT.*]), see description of [AIFINPTRNEXT.*] register for details.
982 
983 */
984 #define I2S_IRQFLAGS_AIFDMAIN 0x00000020U
985 #define I2S_IRQFLAGS_AIFDMAIN_M 0x00000020U
986 #define I2S_IRQFLAGS_AIFDMAIN_S 5U
987 /*
988 
989  Field: XCNTCPT
990  From..to bits: 6...6
991  DefaultValue: 0x0
992  Access type: read-only
993  Description: Will be set when xcnt counter is captured either by events or software.
994  Needs to be cleared by software.
995 
996 */
997 #define I2S_IRQFLAGS_XCNTCPT 0x00000040U
998 #define I2S_IRQFLAGS_XCNTCPT_M 0x00000040U
999 #define I2S_IRQFLAGS_XCNTCPT_S 6U
1000 
1001 
1002 /*-----------------------------------REGISTER------------------------------------
1003  Register name: IRQSET
1004  Offset name: I2S_O_IRQSET
1005  Relative address: 0x78
1006  Description: Interrupt Set Register
1007  Default Value: 0x00000000
1008 
1009  Field: PTRERR
1010  From..to bits: 0...0
1011  DefaultValue: 0x0
1012  Access type: write-only
1013  Description: 1: Sets the interrupt of [IRQFLAGS.PTR_ERR]
1014 
1015 */
1016 #define I2S_IRQSET_PTRERR 0x00000001U
1017 #define I2S_IRQSET_PTRERR_M 0x00000001U
1018 #define I2S_IRQSET_PTRERR_S 0U
1019 /*
1020 
1021  Field: WCLKERR
1022  From..to bits: 1...1
1023  DefaultValue: 0x0
1024  Access type: write-only
1025  Description: 1: Sets the interrupt of [IRQFLAGS.WCLK_ERR]
1026 
1027 */
1028 #define I2S_IRQSET_WCLKERR 0x00000002U
1029 #define I2S_IRQSET_WCLKERR_M 0x00000002U
1030 #define I2S_IRQSET_WCLKERR_S 1U
1031 /*
1032 
1033  Field: BUSERR
1034  From..to bits: 2...2
1035  DefaultValue: 0x0
1036  Access type: write-only
1037  Description: 1: Sets the interrupt of [IRQFLAGS.BUS_ERR]
1038 
1039 */
1040 #define I2S_IRQSET_BUSERR 0x00000004U
1041 #define I2S_IRQSET_BUSERR_M 0x00000004U
1042 #define I2S_IRQSET_BUSERR_S 2U
1043 /*
1044 
1045  Field: WCLKTOUT
1046  From..to bits: 3...3
1047  DefaultValue: 0x0
1048  Access type: write-only
1049  Description: 1: Sets the interrupt of [IRQFLAGS.WCLK_TIMEOUT]
1050 
1051 */
1052 #define I2S_IRQSET_WCLKTOUT 0x00000008U
1053 #define I2S_IRQSET_WCLKTOUT_M 0x00000008U
1054 #define I2S_IRQSET_WCLKTOUT_S 3U
1055 /*
1056 
1057  Field: AIFDMAOUT
1058  From..to bits: 4...4
1059  DefaultValue: 0x0
1060  Access type: write-only
1061  Description: 1: Sets the interrupt of [IRQFLAGS.AIF_DMA_OUT] (unless a auto clear criteria was given at the same time, in which the set will be ignored)
1062 
1063 */
1064 #define I2S_IRQSET_AIFDMAOUT 0x00000010U
1065 #define I2S_IRQSET_AIFDMAOUT_M 0x00000010U
1066 #define I2S_IRQSET_AIFDMAOUT_S 4U
1067 /*
1068 
1069  Field: AIFDMAIN
1070  From..to bits: 5...5
1071  DefaultValue: 0x0
1072  Access type: write-only
1073  Description: 1: Sets the interrupt of [IRQFLAGS.AIF_DMA_IN] (unless a auto clear criteria was given at the same time, in which the set will be ignored)
1074 
1075 */
1076 #define I2S_IRQSET_AIFDMAIN 0x00000020U
1077 #define I2S_IRQSET_AIFDMAIN_M 0x00000020U
1078 #define I2S_IRQSET_AIFDMAIN_S 5U
1079 /*
1080 
1081  Field: XCNTCPT
1082  From..to bits: 6...6
1083  DefaultValue: 0x0
1084  Access type: write-only
1085  Description: 1: Sets the interrupt of [IRQFLAGS.XCNT_CAPTURE] (unless a auto clear criteria was given at the same time, in which the set will be ignored)
1086 
1087 */
1088 #define I2S_IRQSET_XCNTCPT 0x00000040U
1089 #define I2S_IRQSET_XCNTCPT_M 0x00000040U
1090 #define I2S_IRQSET_XCNTCPT_S 6U
1091 
1092 
1093 /*-----------------------------------REGISTER------------------------------------
1094  Register name: IRQCLR
1095  Offset name: I2S_O_IRQCLR
1096  Relative address: 0x7C
1097  Description: Interrupt Clear Register
1098  Default Value: 0x00000000
1099 
1100  Field: PTRERR
1101  From..to bits: 0...0
1102  DefaultValue: 0x0
1103  Access type: write-only
1104  Description: 1: Clears the interrupt of [IRQFLAGS.PTR_ERR] (unless a set criteria was given at the same time in which the clear will be ignored)
1105 
1106 */
1107 #define I2S_IRQCLR_PTRERR 0x00000001U
1108 #define I2S_IRQCLR_PTRERR_M 0x00000001U
1109 #define I2S_IRQCLR_PTRERR_S 0U
1110 /*
1111 
1112  Field: WCLKERR
1113  From..to bits: 1...1
1114  DefaultValue: 0x0
1115  Access type: write-only
1116  Description: 1: Clears the interrupt of [IRQFLAGS.WCLK_ERR] (unless a set criteria was given at the same time in which the clear will be ignored)
1117 
1118 */
1119 #define I2S_IRQCLR_WCLKERR 0x00000002U
1120 #define I2S_IRQCLR_WCLKERR_M 0x00000002U
1121 #define I2S_IRQCLR_WCLKERR_S 1U
1122 /*
1123 
1124  Field: BUSERR
1125  From..to bits: 2...2
1126  DefaultValue: 0x0
1127  Access type: write-only
1128  Description: 1: Clears the interrupt of [IRQFLAGS.BUS_ERR] (unless a set criteria was given at the same time in which the clear will be ignored)
1129 
1130 */
1131 #define I2S_IRQCLR_BUSERR 0x00000004U
1132 #define I2S_IRQCLR_BUSERR_M 0x00000004U
1133 #define I2S_IRQCLR_BUSERR_S 2U
1134 /*
1135 
1136  Field: WCLKTOUT
1137  From..to bits: 3...3
1138  DefaultValue: 0x0
1139  Access type: write-only
1140  Description: 1: Clears the interrupt of [IRQFLAGS.WCLK_TIMEOUT] (unless a set criteria was given at the same time in which the clear will be ignored)
1141 
1142 */
1143 #define I2S_IRQCLR_WCLKTOUT 0x00000008U
1144 #define I2S_IRQCLR_WCLKTOUT_M 0x00000008U
1145 #define I2S_IRQCLR_WCLKTOUT_S 3U
1146 /*
1147 
1148  Field: AIFDMAOUT
1149  From..to bits: 4...4
1150  DefaultValue: 0x0
1151  Access type: write-only
1152  Description: 1: Clears the interrupt of [IRQFLAGS.AIF_DMA_OUT] (unless a set criteria was given at the same time in which the clear will be ignored)
1153 
1154 */
1155 #define I2S_IRQCLR_AIFDMAOUT 0x00000010U
1156 #define I2S_IRQCLR_AIFDMAOUT_M 0x00000010U
1157 #define I2S_IRQCLR_AIFDMAOUT_S 4U
1158 /*
1159 
1160  Field: AIFDMAIN
1161  From..to bits: 5...5
1162  DefaultValue: 0x0
1163  Access type: write-only
1164  Description: 1: Clears the interrupt of [IRQFLAGS.AIF_DMA_IN] (unless a set criteria was given at the same time in which the clear will be ignored)
1165 
1166 */
1167 #define I2S_IRQCLR_AIFDMAIN 0x00000020U
1168 #define I2S_IRQCLR_AIFDMAIN_M 0x00000020U
1169 #define I2S_IRQCLR_AIFDMAIN_S 5U
1170 /*
1171 
1172  Field: XCNTCPT
1173  From..to bits: 6...6
1174  DefaultValue: 0x0
1175  Access type: write-only
1176  Description: 1: Clears the interrupt of [IRQFLAGS.XCNT_CAPTURE] (unless a set criteria was given at the same time in which the clear will be ignored)
1177 
1178 */
1179 #define I2S_IRQCLR_XCNTCPT 0x00000040U
1180 #define I2S_IRQCLR_XCNTCPT_M 0x00000040U
1181 #define I2S_IRQCLR_XCNTCPT_S 6U
1182 
1183 
1184 /*-----------------------------------REGISTER------------------------------------
1185  Register name: AIFMCLKDIV
1186  Offset name: I2S_O_AIFMCLKDIV
1187  Relative address: 0x80
1188  Description: **MCLK** Division Ratio
1189  Default Value: 0x00000000
1190 
1191  Field: MDIV
1192  From..to bits: 0...9
1193  DefaultValue: 0x0
1194  Access type: read-write
1195  Description: An unsigned factor of the division ratio used to generate **MCLK** [2-1024]:
1196  **MCLK** = MCUCLK/MDIV[Hz] **MCUCLK** is upto 96MHz.
1197  A value of 0 is interpreted as 1024.
1198  A value of 1 is invalid.
1199  If MDIV is odd the low phase of the clock is one **MCUCLK** period longer than the high phase.
1200 
1201 */
1202 #define I2S_AIFMCLKDIV_MDIV_W 10U
1203 #define I2S_AIFMCLKDIV_MDIV_M 0x000003FFU
1204 #define I2S_AIFMCLKDIV_MDIV_S 0U
1205 
1206 
1207 /*-----------------------------------REGISTER------------------------------------
1208  Register name: AIFBCLKDIV
1209  Offset name: I2S_O_AIFBCLKDIV
1210  Relative address: 0x84
1211  Description: **BCLK** Division Ratio
1212  Default Value: 0x00000000
1213 
1214  Field: BDIV
1215  From..to bits: 0...9
1216  DefaultValue: 0x0
1217  Access type: read-write
1218  Description: An unsigned factor of the division ratio used to generate **BCLK** [2-1024]:
1219  **BCLK** = MCUCLK/BDIV[Hz] **MCUCLK** can be upto 96MHz.
1220  A value of 0 is interpreted as 1024.
1221  A value of 1 is invalid.
1222  If BDIV is odd and [AIFCLKCTL.SMPL_ON_POSEDGE.*] = 0, the low phase of the clock is one **MCUCLK** period longer than the high phase.
1223  If BDIV is odd and [AIFCLKCTL.SMPL_ON_POSEDGE.*] = 1 , the high phase of the clock is one **MCUCLK** period longer than the low phase.
1224 
1225 */
1226 #define I2S_AIFBCLKDIV_BDIV_W 10U
1227 #define I2S_AIFBCLKDIV_BDIV_M 0x000003FFU
1228 #define I2S_AIFBCLKDIV_BDIV_S 0U
1229 
1230 
1231 /*-----------------------------------REGISTER------------------------------------
1232  Register name: AIFWCLKDIV
1233  Offset name: I2S_O_AIFWCLKDIV
1234  Relative address: 0x88
1235  Description: **WCLK** Division Ratio
1236  Default Value: 0x00000000
1237 
1238  Field: WDIV
1239  From..to bits: 0...15
1240  DefaultValue: 0x0
1241  Access type: read-write
1242  Description: If [AIFCLKCTL.WCLK_PHASE.*] = 0, Single phase. **WCLK** is high one **BCLK** period and low WDIV[9:0] (unsigned, [1-1023]) **BCLK** periods.
1243  **WCLK** = **MCUCLK** / BDIV*(WDIV[9:0] + 1) [Hz] **MCUCLK** upto 96MHz.
1244  If [AIFCLKCTL.WCLK_PHASE.*] = 1, Dual phase. Each phase on **WCLK** (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) **BCLK** periods.
1245  **WCLK **= **MCUCLK ** / BDIV*(2*WDIV[9:0]) [Hz]
1246  If [AIFCLKCTL.WCLK_PHASE.*] = 2, User defined. **WCLK** is high WDIV[7:0] (unsigned, [1-255]) **BCLK** periods and low WDIV[15:8] (unsigned, [1-255]) **BCLK** periods.
1247  **WCLK** = **MCUCLK ** / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]
1248 
1249 */
1250 #define I2S_AIFWCLKDIV_WDIV_W 16U
1251 #define I2S_AIFWCLKDIV_WDIV_M 0x0000FFFFU
1252 #define I2S_AIFWCLKDIV_WDIV_S 0U
1253 
1254 
1255 /*-----------------------------------REGISTER------------------------------------
1256  Register name: AIFCLKCTL
1257  Offset name: I2S_O_AIFCLKCTL
1258  Relative address: 0x8C
1259  Description: Internal Audio Clock Control
1260  Default Value: 0x00000000
1261 
1262  Field: WBEN
1263  From..to bits: 0...0
1264  DefaultValue: 0x0
1265  Access type: read-write
1266  Description: 0: WCLK/BCLK geneartion disabled, 1: WCLK/BCLK generation enabled
1267 
1268 */
1269 #define I2S_AIFCLKCTL_WBEN 0x00000001U
1270 #define I2S_AIFCLKCTL_WBEN_M 0x00000001U
1271 #define I2S_AIFCLKCTL_WBEN_S 0U
1272 /*
1273 
1274  Field: WCLKPHASE
1275  From..to bits: 1...2
1276  DefaultValue: 0x0
1277  Access type: read-write
1278  Description: Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See [AIFWCLKDIV.WDIV.*]).
1279 
1280 */
1281 #define I2S_AIFCLKCTL_WCLKPHASE_W 2U
1282 #define I2S_AIFCLKCTL_WCLKPHASE_M 0x00000006U
1283 #define I2S_AIFCLKCTL_WCLKPHASE_S 1U
1284 /*
1285 
1286  Field: MEN
1287  From..to bits: 3...3
1288  DefaultValue: 0x0
1289  Access type: read-write
1290  Description: 0: **MCLK** geneartion disabled, 1: **MCLK** generation enabled
1291 
1292 */
1293 #define I2S_AIFCLKCTL_MEN 0x00000008U
1294 #define I2S_AIFCLKCTL_MEN_M 0x00000008U
1295 #define I2S_AIFCLKCTL_MEN_S 3U
1296 
1297 
1298 /*-----------------------------------REGISTER------------------------------------
1299  Register name: CLKCFG
1300  Offset name: I2S_O_CLKCFG
1301  Relative address: 0x1000
1302  Description: Audio clock source selection and **I2S** enable register
1303  Note: Disable the [CLKCFG.MEM_CLK_EN] and [CLKCFG.ADFS_EN] to change [CLK_CFG.MEM_CLK_SEL]
1304  After changing [CLK_CFG.MEM_CLK_SEL], enable [CLKCFG.ADFS_EN] followed by [CLKCFG.MEM_CLK_EN]
1305 
1306  Default Value: 0x00000000
1307 
1308  Field: EN
1309  From..to bits: 0...0
1310  DefaultValue: 0x0
1311  Access type: read-write
1312  Description: 0: **I2S** clock disabled
1313  1: **I2S** clock enabled
1314 
1315 */
1316 #define I2S_CLKCFG_EN 0x00000001U
1317 #define I2S_CLKCFG_EN_M 0x00000001U
1318 #define I2S_CLKCFG_EN_S 0U
1319 /*
1320 
1321  Field: CLKSEL
1322  From..to bits: 4...6
1323  DefaultValue: 0x0
1324  Access type: read-write
1325  Description: Audio clock selection
1326 
1327  ENUMs:
1328  SEL_0: No Clock
1329  SEL_1: SOC Clock(80MHz)
1330  SEL_2: SOC PLL Clock(un-swallowed 80MHz)
1331  SEL_3: HFXT
1332 */
1333 #define I2S_CLKCFG_CLKSEL_W 3U
1334 #define I2S_CLKCFG_CLKSEL_M 0x00000070U
1335 #define I2S_CLKCFG_CLKSEL_S 4U
1336 #define I2S_CLKCFG_CLKSEL_SEL_0 0x00000000U
1337 #define I2S_CLKCFG_CLKSEL_SEL_1 0x00000010U
1338 #define I2S_CLKCFG_CLKSEL_SEL_2 0x00000020U
1339 #define I2S_CLKCFG_CLKSEL_SEL_3 0x00000030U
1340 /*
1341 
1342  Field: ADFSEN
1343  From..to bits: 7...7
1344  DefaultValue: 0x0
1345  Access type: read-write
1346  Description: ADFS enable field
1347 
1348 */
1349 #define I2S_CLKCFG_ADFSEN 0x00000080U
1350 #define I2S_CLKCFG_ADFSEN_M 0x00000080U
1351 #define I2S_CLKCFG_ADFSEN_S 7U
1352 
1353 
1354 /*-----------------------------------REGISTER------------------------------------
1355  Register name: ADFSCTRL1
1356  Offset name: I2S_O_ADFSCTRL1
1357  Relative address: 0x1004
1358  Description: ADFS TREF control register
1359  Default Value: 0x00000000
1360 
1361  Field: TREF
1362  From..to bits: 0...20
1363  DefaultValue: 0x0
1364  Access type: read-write
1365  Description: TREF value for ADFS
1366 
1367 */
1368 #define I2S_ADFSCTRL1_TREF_W 21U
1369 #define I2S_ADFSCTRL1_TREF_M 0x001FFFFFU
1370 #define I2S_ADFSCTRL1_TREF_S 0U
1371 
1372 
1373 /*-----------------------------------REGISTER------------------------------------
1374  Register name: ADFSCTRL2
1375  Offset name: I2S_O_ADFSCTRL2
1376  Relative address: 0x1008
1377  Description: ADFS general configuration register
1378  Default Value: 0x00000000
1379 
1380  Field: DELTA
1381  From..to bits: 0...16
1382  DefaultValue: 0x0
1383  Access type: read-write
1384  Description: ADFS delta value field
1385 
1386 */
1387 #define I2S_ADFSCTRL2_DELTA_W 17U
1388 #define I2S_ADFSCTRL2_DELTA_M 0x0001FFFFU
1389 #define I2S_ADFSCTRL2_DELTA_S 0U
1390 /*
1391 
1392  Field: DELTASIGN
1393  From..to bits: 17...17
1394  DefaultValue: 0x0
1395  Access type: read-write
1396  Description: ADFS delta sign field
1397 
1398 */
1399 #define I2S_ADFSCTRL2_DELTASIGN 0x00020000U
1400 #define I2S_ADFSCTRL2_DELTASIGN_M 0x00020000U
1401 #define I2S_ADFSCTRL2_DELTASIGN_S 17U
1402 /*
1403 
1404  Field: DIV
1405  From..to bits: 20...29
1406  DefaultValue: 0x0
1407  Access type: read-write
1408  Description: ADFS div value field
1409 
1410 */
1411 #define I2S_ADFSCTRL2_DIV_W 10U
1412 #define I2S_ADFSCTRL2_DIV_M 0x3FF00000U
1413 #define I2S_ADFSCTRL2_DIV_S 20U
1414 
1415 #endif /* __HW_I2S_H__*/