CC35xxDriverLibrary
hw_hsm_non_sec.h
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1 /******************************************************************************
2 * Filename: hw_hsm_non_sec.h
3 *
4 * Description: Defines and prototypes for the HSM_NON_SEC peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
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13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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22 *
23  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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35 ******************************************************************************/
36 #ifndef __HW_HSM_NON_SEC_H__
37 #define __HW_HSM_NON_SEC_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HSM_NON_SEC component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //This register is used for enabling clock to the module
45 #define HSM_NON_SEC_O_CLK_MEM_CTRL 0x00000000U
46 
47 //This register is used for aborting PKA operation
48 #define HSM_NON_SEC_O_PKA_ABORT_CTRL 0x00000004U
49 
50 //This register provides EIP130 status
51 #define HSM_NON_SEC_O_HSM_STA_REG 0x00000008U
52 
53 //This register stores status of asset clear indication
54 #define HSM_NON_SEC_O_RAM_CLR_STA 0x0000000CU
55 
56 
57 
58 /*-----------------------------------REGISTER------------------------------------
59  Register name: CLK_MEM_CTRL
60  Offset name: HSM_NON_SEC_O_CLK_MEM_CTRL
61  Relative address: 0x0
62  Description: This register is used for enabling clock to the module
63 
64  Default Value: 0x00000000
65 
66  Field: MEM_CLK_GO
67  From..to bits: 0...0
68  DefaultValue: 0x0
69  Access type: read-write
70  Description: Write this bit to enable clock to the module
71 
72 
73 
74 
75  ENUMs:
76  EN: Write 1b to enable clock
77  DIS: Write 0b to disable clock
78 
79 */
80 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO 0x00000001U
81 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M 0x00000001U
82 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_S 0U
83 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_EN 0x00000001U
84 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_DIS 0x00000000U
85 /*
86 
87  Field: MEM_SLV_CLK_GO
88  From..to bits: 1...1
89  DefaultValue: 0x0
90  Access type: read-write
91  Description: Write this bit to enable host interface clock
92 
93 
94 
95  ENUMs:
96  EN: Write 1b to enable clock
97  DIS: Write 0b to disable clock
98 
99 */
100 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO 0x00000002U
101 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M 0x00000002U
102 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_S 1U
103 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_EN 0x00000002U
104 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_DIS 0x00000000U
105 /*
106 
107  Field: MEM_CTR_CLK_GO
108  From..to bits: 2...2
109  DefaultValue: 0x0
110  Access type: read-write
111  Description: Write this bit to enable counter clock
112 
113  ENUMs:
114  DIS: Write 0b to disable clock
115 
116  EN: Write 1b to enable clock
117 */
118 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO 0x00000004U
119 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M 0x00000004U
120 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_S 2U
121 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_DIS 0x00000000U
122 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_EN 0x00000004U
123 /*
124 
125  Field: MEM_CLK_GO_M3
126  From..to bits: 3...3
127  DefaultValue: 0x0
128  Access type: read-write
129  Description: M3 writes this bit to enable clock to the module
130 
131  ENUMs:
132  DIS: Write 0b to disable clock
133 
134  EN: Write 1b to enable clock
135 */
136 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3 0x00000008U
137 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M 0x00000008U
138 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_S 3U
139 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_DIS 0x00000000U
140 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_EN 0x00000008U
141 /*
142 
143  Field: MEM_SLV_CLK_GO_M3
144  From..to bits: 4...4
145  DefaultValue: 0x0
146  Access type: read-write
147  Description: Write this bit to enable host interface clock
148 
149  ENUMs:
150  EN: Write 1b to enable clock
151  DIS: Write 0b to disable clock
152 
153 */
154 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3 0x00000010U
155 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M 0x00000010U
156 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_S 4U
157 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_EN 0x00000010U
158 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_DIS 0x00000000U
159 /*
160 
161  Field: MEM_CTR_CLK_GO_M3
162  From..to bits: 5...5
163  DefaultValue: 0x0
164  Access type: read-write
165  Description: Write this bit to enable counter clock
166 
167  ENUMs:
168  DIS: Write 0b to disable clock
169 
170  EN: Write 1b to enable clock
171 */
172 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3 0x00000020U
173 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M 0x00000020U
174 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_S 5U
175 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_DIS 0x00000000U
176 #define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_EN 0x00000020U
177 /*
178 
179  Field: CLK_BUSY
180  From..to bits: 6...6
181  DefaultValue: 0x0
182  Access type: read-only
183  Description: when 1b, indicates that the module is active and busy with processing data and tokens.
184 
185 */
186 #define HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY 0x00000040U
187 #define HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_M 0x00000040U
188 #define HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_S 6U
189 /*
190 
191  Field: SLV_CLK_BUSY
192  From..to bits: 7...7
193  DefaultValue: 0x0
194  Access type: read-only
195  Description: When 1b indicates the Host interface is active and busy with Host bus transfers.
196 
197 */
198 #define HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY 0x00000080U
199 #define HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_M 0x00000080U
200 #define HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_S 7U
201 /*
202 
203  Field: CTR_CLK_BUSY
204  From..to bits: 8...8
205  DefaultValue: 0x0
206  Access type: read-only
207  Description: When 1b, indicates that the counter clock domain is active. This signal is always asserted (set to '1'), except when the
208  counter module is in reset (ctr_reset_n set to '0').
209 
210 */
211 #define HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY 0x00000100U
212 #define HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_M 0x00000100U
213 #define HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_S 8U
214 
215 
216 /*-----------------------------------REGISTER------------------------------------
217  Register name: PKA_ABORT_CTRL
218  Offset name: HSM_NON_SEC_O_PKA_ABORT_CTRL
219  Relative address: 0x4
220  Description: This register is used for aborting PKA operation.
221  Default Value: 0x00000000
222 
223  Field: MEM_PKA_ABORT_NS
224  From..to bits: 0...0
225  DefaultValue: 0x0
226  Access type: read-write
227  Description: Write 1 to this bit to abort PKA operation
228 
229 
230  ENUMs:
231  ABORT: Set to 1, to abort PKA operation
232 */
233 #define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS 0x00000001U
234 #define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_M 0x00000001U
235 #define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_S 0U
236 #define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_ABORT 0x00000001U
237 
238 
239 /*-----------------------------------REGISTER------------------------------------
240  Register name: HSM_STA_REG
241  Offset name: HSM_NON_SEC_O_HSM_STA_REG
242  Relative address: 0x8
243  Description: This register provides EIP130 status
244 
245  Default Value: 0x00000000
246 
247  Field: FIPS_MODE
248  From..to bits: 0...0
249  DefaultValue: 0x0
250  Access type: read-only
251  Description: If active (set to 1b), EIP130 is in FIPS mode
252 
253 
254 */
255 #define HSM_NON_SEC_HSM_STA_REG_FIPS_MODE 0x00000001U
256 #define HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_M 0x00000001U
257 #define HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_S 0U
258 /*
259 
260  Field: NON_FIPS_MODE
261  From..to bits: 1...1
262  DefaultValue: 0x0
263  Access type: read-only
264  Description: If active (set to 1b), EIP130 is in NON-FIPS mode
265 
266 */
267 #define HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE 0x00000002U
268 #define HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_M 0x00000002U
269 #define HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_S 1U
270 /*
271 
272  Field: FATAL_ERROR
273  From..to bits: 2...2
274  DefaultValue: 0x0
275  Access type: read-only
276  Description: If active (set to 1b), EIP130 detected a fatal error and stops operation. fatal error can happen when CRC on firmware ROM fails or selftest fails.
277 
278 */
279 #define HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR 0x00000004U
280 #define HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_M 0x00000004U
281 #define HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_S 2U
282 /*
283 
284  Field: POWER_MODE
285  From..to bits: 3...3
286  DefaultValue: 0x0
287  Access type: read-only
288  Description: Power mode value 1'b1 indicates hsm is in sleep and value 1'b0 indicates hsm is out of sleep.
289 
290 */
291 #define HSM_NON_SEC_HSM_STA_REG_POWER_MODE 0x00000008U
292 #define HSM_NON_SEC_HSM_STA_REG_POWER_MODE_M 0x00000008U
293 #define HSM_NON_SEC_HSM_STA_REG_POWER_MODE_S 3U
294 
295 
296 /*-----------------------------------REGISTER------------------------------------
297  Register name: RAM_CLR_STA
298  Offset name: HSM_NON_SEC_O_RAM_CLR_STA
299  Relative address: 0xC
300  Description: This register stores status of asset clear indication.
301 
302  Default Value: 0x00000000
303 
304  Field: OTP_CLR_DONE
305  From..to bits: 0...0
306  DefaultValue: 0x0
307  Access type: read-only
308  Description: If active (set to 1b), it indicates that auto clear of OTP on reset release has been completed.
309 
310 */
311 #define HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE 0x00000001U
312 #define HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_M 0x00000001U
313 #define HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_S 0U
314 /*
315 
316  Field: DATARAM_CLR_DONE
317  From..to bits: 1...1
318  DefaultValue: 0x0
319  Access type: read-only
320  Description: If active (set to 1b), it indicates that auto clear of Dataram on reset release has been completed.
321 
322 */
323 #define HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE 0x00000002U
324 #define HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_M 0x00000002U
325 #define HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_S 1U
326 
327 #endif /* __HW_HSM_NON_SEC_H__*/