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#define	HSM_NON_SEC_O_CLK_MEM_CTRL 0x00000000U

#define	HSM_NON_SEC_O_PKA_ABORT_CTRL 0x00000004U

#define	HSM_NON_SEC_O_HSM_STA_REG 0x00000008U

#define	HSM_NON_SEC_O_RAM_CLR_STA 0x0000000CU

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO 0x00000001U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M 0x00000001U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_S 0U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_EN 0x00000001U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_DIS 0x00000000U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO 0x00000002U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M 0x00000002U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_S 1U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_EN 0x00000002U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_DIS 0x00000000U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO 0x00000004U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M 0x00000004U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_S 2U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_DIS 0x00000000U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_EN 0x00000004U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3 0x00000008U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M 0x00000008U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_S 3U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_DIS 0x00000000U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_EN 0x00000008U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3 0x00000010U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M 0x00000010U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_S 4U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_EN 0x00000010U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_DIS 0x00000000U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3 0x00000020U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M 0x00000020U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_S 5U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_DIS 0x00000000U

#define	HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_EN 0x00000020U

#define	HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY 0x00000040U

#define	HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_M 0x00000040U

#define	HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_S 6U

#define	HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY 0x00000080U

#define	HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_M 0x00000080U

#define	HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_S 7U

#define	HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY 0x00000100U

#define	HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_M 0x00000100U

#define	HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_S 8U

#define	HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS 0x00000001U

#define	HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_M 0x00000001U

#define	HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_S 0U

#define	HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_ABORT 0x00000001U

#define	HSM_NON_SEC_HSM_STA_REG_FIPS_MODE 0x00000001U

#define	HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_M 0x00000001U

#define	HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_S 0U

#define	HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE 0x00000002U

#define	HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_M 0x00000002U

#define	HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_S 1U

#define	HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR 0x00000004U

#define	HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_M 0x00000004U

#define	HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_S 2U

#define	HSM_NON_SEC_HSM_STA_REG_POWER_MODE 0x00000008U

#define	HSM_NON_SEC_HSM_STA_REG_POWER_MODE_M 0x00000008U

#define	HSM_NON_SEC_HSM_STA_REG_POWER_MODE_S 3U

#define	HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE 0x00000001U

#define	HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_M 0x00000001U

#define	HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_S 0U

#define	HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE 0x00000002U

#define	HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_M 0x00000002U

#define	HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_S 1U

Macro Definition Documentation

§ HSM_NON_SEC_O_CLK_MEM_CTRL

#define HSM_NON_SEC_O_CLK_MEM_CTRL 0x00000000U

§ HSM_NON_SEC_O_PKA_ABORT_CTRL

#define HSM_NON_SEC_O_PKA_ABORT_CTRL 0x00000004U

§ HSM_NON_SEC_O_HSM_STA_REG

#define HSM_NON_SEC_O_HSM_STA_REG 0x00000008U

§ HSM_NON_SEC_O_RAM_CLR_STA

#define HSM_NON_SEC_O_RAM_CLR_STA 0x0000000CU

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO 0x00000001U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M 0x00000001U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_S

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_S 0U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_EN

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_EN 0x00000001U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_DIS

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_DIS 0x00000000U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO 0x00000002U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M 0x00000002U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_S

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_S 1U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_EN

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_EN 0x00000002U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_DIS

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_DIS 0x00000000U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO 0x00000004U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M 0x00000004U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_S

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_S 2U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_DIS

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_DIS 0x00000000U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_EN

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_EN 0x00000004U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3 0x00000008U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_M 0x00000008U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_S

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_S 3U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_DIS

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_DIS 0x00000000U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_EN

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CLK_GO_M3_EN 0x00000008U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3 0x00000010U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_M 0x00000010U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_S

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_S 4U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_EN

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_EN 0x00000010U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_DIS

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_SLV_CLK_GO_M3_DIS 0x00000000U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3 0x00000020U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_M 0x00000020U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_S

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_S 5U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_DIS

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_DIS 0x00000000U

§ HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_EN

#define HSM_NON_SEC_CLK_MEM_CTRL_MEM_CTR_CLK_GO_M3_EN 0x00000020U

§ HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY

#define HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY 0x00000040U

§ HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_M

#define HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_M 0x00000040U

§ HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_S

#define HSM_NON_SEC_CLK_MEM_CTRL_CLK_BUSY_S 6U

§ HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY

#define HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY 0x00000080U

§ HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_M

#define HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_M 0x00000080U

§ HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_S

#define HSM_NON_SEC_CLK_MEM_CTRL_SLV_CLK_BUSY_S 7U

§ HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY

#define HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY 0x00000100U

§ HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_M

#define HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_M 0x00000100U

§ HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_S

#define HSM_NON_SEC_CLK_MEM_CTRL_CTR_CLK_BUSY_S 8U

§ HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS

#define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS 0x00000001U

§ HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_M

#define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_M 0x00000001U

§ HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_S

#define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_S 0U

§ HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_ABORT

#define HSM_NON_SEC_PKA_ABORT_CTRL_MEM_PKA_ABORT_NS_ABORT 0x00000001U

§ HSM_NON_SEC_HSM_STA_REG_FIPS_MODE

#define HSM_NON_SEC_HSM_STA_REG_FIPS_MODE 0x00000001U

§ HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_M

#define HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_M 0x00000001U

§ HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_S

#define HSM_NON_SEC_HSM_STA_REG_FIPS_MODE_S 0U

§ HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE

#define HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE 0x00000002U

§ HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_M

#define HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_M 0x00000002U

§ HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_S

#define HSM_NON_SEC_HSM_STA_REG_NON_FIPS_MODE_S 1U

§ HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR

#define HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR 0x00000004U

§ HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_M

#define HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_M 0x00000004U

§ HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_S

#define HSM_NON_SEC_HSM_STA_REG_FATAL_ERROR_S 2U

§ HSM_NON_SEC_HSM_STA_REG_POWER_MODE

#define HSM_NON_SEC_HSM_STA_REG_POWER_MODE 0x00000008U

§ HSM_NON_SEC_HSM_STA_REG_POWER_MODE_M

#define HSM_NON_SEC_HSM_STA_REG_POWER_MODE_M 0x00000008U

§ HSM_NON_SEC_HSM_STA_REG_POWER_MODE_S

#define HSM_NON_SEC_HSM_STA_REG_POWER_MODE_S 3U

§ HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE

#define HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE 0x00000001U

§ HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_M

#define HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_M 0x00000001U

§ HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_S

#define HSM_NON_SEC_RAM_CLR_STA_OTP_CLR_DONE_S 0U

§ HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE

#define HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE 0x00000002U

§ HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_M

#define HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_M 0x00000002U

§ HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_S

#define HSM_NON_SEC_RAM_CLR_STA_DATARAM_CLR_DONE_S 1U

Macros