CC35xxDriverLibrary
hw_hsm.h
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1 /******************************************************************************
2 * Filename: hw_hsm.h
3 *
4 * Description: Defines and prototypes for the HSM peripheral.
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36 #ifndef __HW_HSM_H__
37 #define __HW_HSM_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HSM component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Input MAILBOX1
45 #define HSM_O_EIP130_072_MAILBOX1_IN 0x00000000U
46 
47 //Input MAILBOX2
48 #define HSM_O_EIP130_072_MAILBOX2_IN 0x00000400U
49 
50 //AIC Polarity Control Register
51 #define HSM_O_AICPOLCTL 0x00003E00U
52 
53 //AIC Type Control Register
54 #define HSM_O_AICTYPCTL 0x00003E04U
55 
56 //AIC Enable Control Register
57 #define HSM_O_AICENCTL 0x00003E08U
58 
59 //AIC Raw Source Status Register
60 #define HSM_O_AICRAWCTL 0x00003E0CU
61 
62 //AIC Enable Set Registers
63 #define HSM_O_AICENSET 0x00003E0CU
64 
65 //AIC Enabled Status Register
66 #define HSM_O_AICENSTA 0x00003E10U
67 
68 //AIC Acknowledge Register
69 #define HSM_O_AICACK 0x00003E10U
70 
71 //AIC Enable Clear Register
72 #define HSM_O_AICENCLR 0x00003E14U
73 
74 //AIC Options Register
75 #define HSM_O_AICOPTS 0x00003E18U
76 
77 //AIC Version Register
78 #define HSM_O_AICVER 0x00003E1CU
79 
80 //Mailbox Status Register
81 #define HSM_O_MBXSTA 0x00003F00U
82 
83 //Mailbox Control Register
84 #define HSM_O_MBXCTL 0x00003F00U
85 
86 //Raw (unmasked) Mailbox Status Register
87 #define HSM_O_MBXRAWSTA 0x00003F04U
88 
89 //Mailbox Reset Register
90 #define HSM_O_MBXRST 0x00003F04U
91 
92 //Mailbox Status - linked Host IDs Register
93 #define HSM_O_MBXLINKID 0x00003F08U
94 
95 //Mailbox Status - output Host IDs Register
96 #define HSM_O_MBXOUTID 0x00003F0CU
97 
98 //Host/Mailbox1-4 lockout control Register
99 #define HSM_O_MBXLCKOUT 0x00003F10U
100 
101 //Module Status Register
102 #define HSM_O_MODULESTA 0x00003FE0U
103 
104 //VaultIP configured options(2)
105 #define HSM_O_EIPOPTS2 0x00003FF4U
106 
107 //VaultIP configured options(1)
108 #define HSM_O_EIPOPTS1 0x00003FF8U
109 
110 //Standard EIP version register
111 #define HSM_O_EIPVER 0x00003FFCU
112 
113 
114 
115 /*-----------------------------------REGISTER------------------------------------
116  Register name: EIP130_072_MAILBOX1_IN
117  Offset name: HSM_O_EIP130_072_MAILBOX1_IN
118  Relative address: 0x0
119  Description: Input MAILBOX1
120  Default Value: 0x00000000
121 
122 */
123 
124 /*-----------------------------------REGISTER------------------------------------
125  Register name: EIP130_072_MAILBOX2_IN
126  Offset name: HSM_O_EIP130_072_MAILBOX2_IN
127  Relative address: 0x400
128  Description: Input MAILBOX2
129  Default Value: 0x00000000
130 
131 */
132 
133 /*-----------------------------------REGISTER------------------------------------
134  Register name: AICPOLCTL
135  Offset name: HSM_O_AICPOLCTL
136  Relative address: 0x3E00
137  Description: AIC Polarity Control Register
138  Default Value: 0x00000000
139 
140  Field: CTL0
141  From..to bits: 0...0
142  DefaultValue: 0x0
143  Access type: read-write
144  Description: Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.
145 
146 */
147 #define HSM_AICPOLCTL_CTL0 0x00000001U
148 #define HSM_AICPOLCTL_CTL0_M 0x00000001U
149 #define HSM_AICPOLCTL_CTL0_S 0U
150 /*
151 
152  Field: CTL1
153  From..to bits: 1...1
154  DefaultValue: 0x0
155  Access type: read-write
156  Description: Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.
157 
158 */
159 #define HSM_AICPOLCTL_CTL1 0x00000002U
160 #define HSM_AICPOLCTL_CTL1_M 0x00000002U
161 #define HSM_AICPOLCTL_CTL1_S 1U
162 /*
163 
164  Field: CTL2
165  From..to bits: 2...2
166  DefaultValue: 0x0
167  Access type: read-write
168  Description: Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.
169 
170 */
171 #define HSM_AICPOLCTL_CTL2 0x00000004U
172 #define HSM_AICPOLCTL_CTL2_M 0x00000004U
173 #define HSM_AICPOLCTL_CTL2_S 2U
174 /*
175 
176  Field: CTL3
177  From..to bits: 3...3
178  DefaultValue: 0x0
179  Access type: read-write
180  Description: Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.
181 
182 */
183 #define HSM_AICPOLCTL_CTL3 0x00000008U
184 #define HSM_AICPOLCTL_CTL3_M 0x00000008U
185 #define HSM_AICPOLCTL_CTL3_S 3U
186 /*
187 
188  Field: CTL4
189  From..to bits: 4...4
190  DefaultValue: 0x0
191  Access type: read-write
192  Description: Individual polarity (high level/rising edge or low level/falling edge) control bits per interrupt input: 0b = Low level/falling edge 1b = High level/rising edge.
193 
194 */
195 #define HSM_AICPOLCTL_CTL4 0x00000010U
196 #define HSM_AICPOLCTL_CTL4_M 0x00000010U
197 #define HSM_AICPOLCTL_CTL4_S 4U
198 
199 
200 /*-----------------------------------REGISTER------------------------------------
201  Register name: AICTYPCTL
202  Offset name: HSM_O_AICTYPCTL
203  Relative address: 0x3E04
204  Description: AIC Type Control Register
205  Default Value: 0x00000000
206 
207  Field: CTL0
208  From..to bits: 0...0
209  DefaultValue: 0x0
210  Access type: read-write
211  Description: Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).
212 
213 */
214 #define HSM_AICTYPCTL_CTL0 0x00000001U
215 #define HSM_AICTYPCTL_CTL0_M 0x00000001U
216 #define HSM_AICTYPCTL_CTL0_S 0U
217 /*
218 
219  Field: CTL1
220  From..to bits: 1...1
221  DefaultValue: 0x0
222  Access type: read-write
223  Description: Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).
224 
225 */
226 #define HSM_AICTYPCTL_CTL1 0x00000002U
227 #define HSM_AICTYPCTL_CTL1_M 0x00000002U
228 #define HSM_AICTYPCTL_CTL1_S 1U
229 /*
230 
231  Field: CTL2
232  From..to bits: 2...2
233  DefaultValue: 0x0
234  Access type: read-write
235  Description: Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).
236 
237 */
238 #define HSM_AICTYPCTL_CTL2 0x00000004U
239 #define HSM_AICTYPCTL_CTL2_M 0x00000004U
240 #define HSM_AICTYPCTL_CTL2_S 2U
241 /*
242 
243  Field: CTL3
244  From..to bits: 3...3
245  DefaultValue: 0x0
246  Access type: read-write
247  Description: Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).
248 
249 */
250 #define HSM_AICTYPCTL_CTL3 0x00000008U
251 #define HSM_AICTYPCTL_CTL3_M 0x00000008U
252 #define HSM_AICTYPCTL_CTL3_S 3U
253 /*
254 
255  Field: CTL4
256  From..to bits: 4...4
257  DefaultValue: 0x0
258  Access type: read-write
259  Description: Signal type (level or edge) control bits for each interrupt input: 0b = level (the interrupt source level determines the raw status). 1b = edge (the interrupt source is connected to an edge detector and the edge detector output determines the raw status).
260 
261 */
262 #define HSM_AICTYPCTL_CTL4 0x00000010U
263 #define HSM_AICTYPCTL_CTL4_M 0x00000010U
264 #define HSM_AICTYPCTL_CTL4_S 4U
265 
266 
267 /*-----------------------------------REGISTER------------------------------------
268  Register name: AICENCTL
269  Offset name: HSM_O_AICENCTL
270  Relative address: 0x3E08
271  Description: AIC Enable Control Register
272  Default Value: 0x00000000
273 
274  Field: CTL
275  From..to bits: 0...4
276  DefaultValue: 0x0
277  Access type: read-write
278  Description: Individual enable control bits per interrupt input: 0b = Disabled. 1b = Enabled
279 
280 */
281 #define HSM_AICENCTL_CTL_W 5U
282 #define HSM_AICENCTL_CTL_M 0x0000001FU
283 #define HSM_AICENCTL_CTL_S 0U
284 
285 
286 /*-----------------------------------REGISTER------------------------------------
287  Register name: AICRAWCTL
288  Offset name: HSM_O_AICRAWCTL
289  Relative address: 0x3E0C
290  Description: AIC Raw Source Status Register
291  Default Value: 0x0000000F
292 
293  Field: STA0
294  From..to bits: 0...0
295  DefaultValue: 0x1
296  Access type: read-only
297  Description: Individual interrupt status bit before masking with enable_ctrl_r[0] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.
298 
299 */
300 #define HSM_AICRAWCTL_STA0 0x00000001U
301 #define HSM_AICRAWCTL_STA0_M 0x00000001U
302 #define HSM_AICRAWCTL_STA0_S 0U
303 /*
304 
305  Field: STA1
306  From..to bits: 1...1
307  DefaultValue: 0x1
308  Access type: read-only
309  Description: Individual interrupt status bit before masking with enable_ctrl_r[1] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.
310 
311 */
312 #define HSM_AICRAWCTL_STA1 0x00000002U
313 #define HSM_AICRAWCTL_STA1_M 0x00000002U
314 #define HSM_AICRAWCTL_STA1_S 1U
315 /*
316 
317  Field: STA2
318  From..to bits: 2...2
319  DefaultValue: 0x1
320  Access type: read-only
321  Description: Individual interrupt status bit before masking with enable_ctrl_r[2] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.
322 
323 */
324 #define HSM_AICRAWCTL_STA2 0x00000004U
325 #define HSM_AICRAWCTL_STA2_M 0x00000004U
326 #define HSM_AICRAWCTL_STA2_S 2U
327 /*
328 
329  Field: STA3
330  From..to bits: 3...3
331  DefaultValue: 0x1
332  Access type: read-only
333  Description: Individual interrupt status bit before masking with enable_ctrl_r[3] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.
334 
335 */
336 #define HSM_AICRAWCTL_STA3 0x00000008U
337 #define HSM_AICRAWCTL_STA3_M 0x00000008U
338 #define HSM_AICRAWCTL_STA3_S 3U
339 /*
340 
341  Field: STA4
342  From..to bits: 4...4
343  DefaultValue: 0x0
344  Access type: read-only
345  Description: Individual interrupt status bit before masking with enable_ctrl_r[4] (programmable, reset to 'low level' mode): 0b = Inactive, 1b = Pending.
346 
347 */
348 #define HSM_AICRAWCTL_STA4 0x00000010U
349 #define HSM_AICRAWCTL_STA4_M 0x00000010U
350 #define HSM_AICRAWCTL_STA4_S 4U
351 
352 
353 /*-----------------------------------REGISTER------------------------------------
354  Register name: AICENSET
355  Offset name: HSM_O_AICENSET
356  Relative address: 0x3E0C
357  Description: AIC Enable Set Registers
358  Default Value: NA
359 
360  Field: ENSET
361  From..to bits: 0...4
362  DefaultValue: NA
363  Access type: write-only
364  Description: Individual interrupt enable bits per interrupt input: 0b = No effect. 1b = Set the corresponding bit in the AIC_ENABLE_CTRL register, enabling the interrupt. After writing a 1b, there is no need to write a 0b.
365 
366 */
367 #define HSM_AICENSET_ENSET_W 5U
368 #define HSM_AICENSET_ENSET_M 0x0000001FU
369 #define HSM_AICENSET_ENSET_S 0U
370 
371 
372 /*-----------------------------------REGISTER------------------------------------
373  Register name: AICENSTA
374  Offset name: HSM_O_AICENSTA
375  Relative address: 0x3E10
376  Description: AIC Enabled Status Register
377  Default Value: 0x00000000
378 
379  Field: STA
380  From..to bits: 0...4
381  DefaultValue: 0x0
382  Access type: read-only
383  Description: These bits reflect the status of the interrupts after polarity control and optional edge detection, gated with bits in AIC_ENABLE_CTRL register: 0b = Inactive. 1b = Pending.
384 
385 */
386 #define HSM_AICENSTA_STA_W 5U
387 #define HSM_AICENSTA_STA_M 0x0000001FU
388 #define HSM_AICENSTA_STA_S 0U
389 
390 
391 /*-----------------------------------REGISTER------------------------------------
392  Register name: AICACK
393  Offset name: HSM_O_AICACK
394  Relative address: 0x3E10
395  Description: AIC Acknowledge Register
396  Default Value: NA
397 
398  Field: ACK0
399  From..to bits: 0...0
400  DefaultValue: NA
401  Access type: read-write
402  Description: Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [0] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.
403 
404 */
405 #define HSM_AICACK_ACK0 0x00000001U
406 #define HSM_AICACK_ACK0_M 0x00000001U
407 #define HSM_AICACK_ACK0_S 0U
408 /*
409 
410  Field: ACK1
411  From..to bits: 1...1
412  DefaultValue: NA
413  Access type: read-write
414  Description: Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [1] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.
415 
416 */
417 #define HSM_AICACK_ACK1 0x00000002U
418 #define HSM_AICACK_ACK1_M 0x00000002U
419 #define HSM_AICACK_ACK1_S 1U
420 /*
421 
422  Field: ACK2
423  From..to bits: 2...2
424  DefaultValue: NA
425  Access type: read-write
426  Description: Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [2] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.
427 
428 */
429 #define HSM_AICACK_ACK2 0x00000004U
430 #define HSM_AICACK_ACK2_M 0x00000004U
431 #define HSM_AICACK_ACK2_S 2U
432 /*
433 
434  Field: ACK3
435  From..to bits: 3...3
436  DefaultValue: NA
437  Access type: read-write
438  Description: Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [3] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.
439 
440 */
441 #define HSM_AICACK_ACK3 0x00000008U
442 #define HSM_AICACK_ACK3_M 0x00000008U
443 #define HSM_AICACK_ACK3_S 3U
444 /*
445 
446  Field: ACK4
447  From..to bits: 4...4
448  DefaultValue: NA
449  Access type: read-write
450  Description: Used to clear edge-detect interrupts: 0b = No effect. 1b = Acknowledge the interrupt signal, clears the edge detector and status bit when in edge detect mode (bit [4] of TYPE_CTRL == 1b). After writing a 1b, there is no need to write a 0b.
451 
452 */
453 #define HSM_AICACK_ACK4 0x00000010U
454 #define HSM_AICACK_ACK4_M 0x00000010U
455 #define HSM_AICACK_ACK4_S 4U
456 
457 
458 /*-----------------------------------REGISTER------------------------------------
459  Register name: AICENCLR
460  Offset name: HSM_O_AICENCLR
461  Relative address: 0x3E14
462  Description: AIC Enable Clear Register
463  Default Value: 0x00000000
464 
465  Field: CLR
466  From..to bits: 0...4
467  DefaultValue: 0x0
468  Access type: write-only
469  Description: Individual interrupt disable bits per interrupt input: 0b = No effect. 1b = Clear the corresponding bit in the AIC_ENABLE_CTRL register, disabling the interrupt. After writing a 1b, there is no need to write a 0b.
470 
471 */
472 #define HSM_AICENCLR_CLR_W 5U
473 #define HSM_AICENCLR_CLR_M 0x0000001FU
474 #define HSM_AICENCLR_CLR_S 0U
475 
476 
477 /*-----------------------------------REGISTER------------------------------------
478  Register name: AICOPTS
479  Offset name: HSM_O_AICOPTS
480  Relative address: 0x3E18
481  Description: AIC Options Register
482  Default Value: 0x00000005
483 
484  Field: NUMOFIN
485  From..to bits: 0...5
486  DefaultValue: 0x5
487  Access type: read-only
488  Description: The number of interrupt request inputs.
489 
490 */
491 #define HSM_AICOPTS_NUMOFIN_W 6U
492 #define HSM_AICOPTS_NUMOFIN_M 0x0000003FU
493 #define HSM_AICOPTS_NUMOFIN_S 0U
494 /*
495 
496  Field: EXTMAP
497  From..to bits: 7...7
498  DefaultValue: 0x0
499  Access type: read-only
500  Description: Extended register map.
501 
502 */
503 #define HSM_AICOPTS_EXTMAP 0x00000080U
504 #define HSM_AICOPTS_EXTMAP_M 0x00000080U
505 #define HSM_AICOPTS_EXTMAP_S 7U
506 /*
507 
508  Field: MINIMAP
509  From..to bits: 8...8
510  DefaultValue: 0x0
511  Access type: read-only
512  Description: Mini register map.
513 
514 */
515 #define HSM_AICOPTS_MINIMAP 0x00000100U
516 #define HSM_AICOPTS_MINIMAP_M 0x00000100U
517 #define HSM_AICOPTS_MINIMAP_S 8U
518 
519 
520 /*-----------------------------------REGISTER------------------------------------
521  Register name: AICVER
522  Offset name: HSM_O_AICVER
523  Relative address: 0x3E1C
524  Description: AIC Version Register
525  Default Value: 0x014036C9
526 
527  Field: EIPNUM
528  From..to bits: 0...7
529  DefaultValue: 0xC9
530  Access type: read-only
531  Description: These bits encode the Rambus EIP number.
532 
533 */
534 #define HSM_AICVER_EIPNUM_W 8U
535 #define HSM_AICVER_EIPNUM_M 0x000000FFU
536 #define HSM_AICVER_EIPNUM_S 0U
537 /*
538 
539  Field: EIPNUMCOMP
540  From..to bits: 8...15
541  DefaultValue: 0x36
542  Access type: read-only
543  Description: These bits simply contain the complement of bits [7:0], used by a driver to ascertain that this version register is indeed read.
544 
545 */
546 #define HSM_AICVER_EIPNUMCOMP_W 8U
547 #define HSM_AICVER_EIPNUMCOMP_M 0x0000FF00U
548 #define HSM_AICVER_EIPNUMCOMP_S 8U
549 /*
550 
551  Field: PATCHLVL
552  From..to bits: 16...19
553  DefaultValue: 0x0
554  Access type: read-only
555  Description: These bits encode the hardware patch level for the EIP-201 module, starting at value 0 on the first release.
556 
557 */
558 #define HSM_AICVER_PATCHLVL_W 4U
559 #define HSM_AICVER_PATCHLVL_M 0x000F0000U
560 #define HSM_AICVER_PATCHLVL_S 16U
561 /*
562 
563  Field: MINORVER
564  From..to bits: 20...23
565  DefaultValue: 0x4
566  Access type: read-only
567  Description: These bits encode the minor version number for the EIP-201 module.
568 
569 */
570 #define HSM_AICVER_MINORVER_W 4U
571 #define HSM_AICVER_MINORVER_M 0x00F00000U
572 #define HSM_AICVER_MINORVER_S 20U
573 /*
574 
575  Field: MAJORVER
576  From..to bits: 24...27
577  DefaultValue: 0x1
578  Access type: read-only
579  Description: These bits encode the major version number for the EIP-201 module.
580 
581 */
582 #define HSM_AICVER_MAJORVER_W 4U
583 #define HSM_AICVER_MAJORVER_M 0x0F000000U
584 #define HSM_AICVER_MAJORVER_S 24U
585 
586 
587 /*-----------------------------------REGISTER------------------------------------
588  Register name: MBXSTA
589  Offset name: HSM_O_MBXSTA
590  Relative address: 0x3F00
591  Description: Mailbox Status Register
592  Default Value: 0x00000088
593 
594  Field: INFULL1
595  From..to bits: 0...0
596  DefaultValue: 0x0
597  Access type: read-only
598  Description: (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox is ready to rceive new token
599 
600 */
601 #define HSM_MBXSTA_INFULL1 0x00000001U
602 #define HSM_MBXSTA_INFULL1_M 0x00000001U
603 #define HSM_MBXSTA_INFULL1_S 0U
604 /*
605 
606  Field: OUTFULL1
607  From..to bits: 1...1
608  DefaultValue: 0x0
609  Access type: read-only
610  Description: (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox is empty
611 
612 */
613 #define HSM_MBXSTA_OUTFULL1 0x00000002U
614 #define HSM_MBXSTA_OUTFULL1_M 0x00000002U
615 #define HSM_MBXSTA_OUTFULL1_S 1U
616 /*
617 
618  Field: LINKED1
619  From..to bits: 2...2
620  DefaultValue: 0x0
621  Access type: read-only
622  Description: (set)-This Host is linked to Mailbox, (Clear)-This Host is not linked to Mailbox
623 
624 */
625 #define HSM_MBXSTA_LINKED1 0x00000004U
626 #define HSM_MBXSTA_LINKED1_M 0x00000004U
627 #define HSM_MBXSTA_LINKED1_S 2U
628 /*
629 
630  Field: AVAIL1
631  From..to bits: 3...3
632  DefaultValue: 0x1
633  Access type: read-only
634  Description: (set)-Input Mailbox is linked to a Host or is filled, (Clear)- Input Mailbox is available for linking by this Host
635 
636 */
637 #define HSM_MBXSTA_AVAIL1 0x00000008U
638 #define HSM_MBXSTA_AVAIL1_M 0x00000008U
639 #define HSM_MBXSTA_AVAIL1_S 3U
640 /*
641 
642  Field: INFULL2
643  From..to bits: 4...4
644  DefaultValue: 0x0
645  Access type: read-only
646  Description: (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox is ready to rceive new token
647 
648 */
649 #define HSM_MBXSTA_INFULL2 0x00000010U
650 #define HSM_MBXSTA_INFULL2_M 0x00000010U
651 #define HSM_MBXSTA_INFULL2_S 4U
652 /*
653 
654  Field: OUTFULL2
655  From..to bits: 5...5
656  DefaultValue: 0x0
657  Access type: read-only
658  Description: (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox is empty
659 
660 */
661 #define HSM_MBXSTA_OUTFULL2 0x00000020U
662 #define HSM_MBXSTA_OUTFULL2_M 0x00000020U
663 #define HSM_MBXSTA_OUTFULL2_S 5U
664 /*
665 
666  Field: LINKED2
667  From..to bits: 6...6
668  DefaultValue: 0x0
669  Access type: read-only
670  Description: (set)-This Host is linked to Mailbox, (Clear)-This Host is not linked to Mailbox
671 
672 */
673 #define HSM_MBXSTA_LINKED2 0x00000040U
674 #define HSM_MBXSTA_LINKED2_M 0x00000040U
675 #define HSM_MBXSTA_LINKED2_S 6U
676 /*
677 
678  Field: AVAIL2
679  From..to bits: 7...7
680  DefaultValue: 0x1
681  Access type: read-only
682  Description: (set)-Input Mailbox is linked to a Host or is filled, (Clear)- Input Mailbox is available for linking by this Host
683 
684 */
685 #define HSM_MBXSTA_AVAIL2 0x00000080U
686 #define HSM_MBXSTA_AVAIL2_M 0x00000080U
687 #define HSM_MBXSTA_AVAIL2_S 7U
688 
689 
690 /*-----------------------------------REGISTER------------------------------------
691  Register name: MBXCTL
692  Offset name: HSM_O_MBXCTL
693  Relative address: 0x3F00
694  Description: Mailbox Control Register
695  Default Value: NA
696 
697  Field: INFULL1
698  From..to bits: 0...0
699  DefaultValue: NA
700  Access type: write-only
701  Description: Set only - The Host linked to mailbox can set the mbx_in_full bit in MAILBOX_STAT by writing 1b here.
702 
703 */
704 #define HSM_MBXCTL_INFULL1 0x00000001U
705 #define HSM_MBXCTL_INFULL1_M 0x00000001U
706 #define HSM_MBXCTL_INFULL1_S 0U
707 /*
708 
709  Field: OUTEMP1
710  From..to bits: 1...1
711  DefaultValue: NA
712  Access type: write-only
713  Description: Set only - The Host for whom the token in Output Mailbox is meant can clear the mbx_out_full bit in MAILBOX_STAT by writing 1b here.
714 
715 */
716 #define HSM_MBXCTL_OUTEMP1 0x00000002U
717 #define HSM_MBXCTL_OUTEMP1_M 0x00000002U
718 #define HSM_MBXCTL_OUTEMP1_S 1U
719 /*
720 
721  Field: LINK1
722  From..to bits: 2...2
723  DefaultValue: NA
724  Access type: write-only
725  Description: Writing a 1b here links Mailbox to this Host - only if Mailbox not filled and not linked to another host
726 
727 */
728 #define HSM_MBXCTL_LINK1 0x00000004U
729 #define HSM_MBXCTL_LINK1_M 0x00000004U
730 #define HSM_MBXCTL_LINK1_S 2U
731 /*
732 
733  Field: UNLINK1
734  From..to bits: 3...3
735  DefaultValue: NA
736  Access type: write-only
737  Description: Set only - Writing a 1b here unlinks the MAilbox from this HOST and clears the mbx_linked bit in MAILBOX_STAT
738 
739 */
740 #define HSM_MBXCTL_UNLINK1 0x00000008U
741 #define HSM_MBXCTL_UNLINK1_M 0x00000008U
742 #define HSM_MBXCTL_UNLINK1_S 3U
743 /*
744 
745  Field: INFULL2
746  From..to bits: 4...4
747  DefaultValue: NA
748  Access type: write-only
749  Description: Set only - The Host linked to mailbox can set the mbx_in_full bit in MAILBOX_STAT by writing 1b here.
750 
751 */
752 #define HSM_MBXCTL_INFULL2 0x00000010U
753 #define HSM_MBXCTL_INFULL2_M 0x00000010U
754 #define HSM_MBXCTL_INFULL2_S 4U
755 /*
756 
757  Field: OUTEMP2
758  From..to bits: 5...5
759  DefaultValue: NA
760  Access type: write-only
761  Description: Set only - The Host for whom the token in Output Mailbox is meant can clear the mbx_out_full bit in MAILBOX_STAT by writing 1b here.
762 
763 */
764 #define HSM_MBXCTL_OUTEMP2 0x00000020U
765 #define HSM_MBXCTL_OUTEMP2_M 0x00000020U
766 #define HSM_MBXCTL_OUTEMP2_S 5U
767 /*
768 
769  Field: LINK2
770  From..to bits: 6...6
771  DefaultValue: NA
772  Access type: write-only
773  Description: Writing a 1b here links Mailbox to this Host - only if Mailbox not filled and not linked to another host
774 
775 */
776 #define HSM_MBXCTL_LINK2 0x00000040U
777 #define HSM_MBXCTL_LINK2_M 0x00000040U
778 #define HSM_MBXCTL_LINK2_S 6U
779 /*
780 
781  Field: UNLINK2
782  From..to bits: 7...7
783  DefaultValue: NA
784  Access type: write-only
785  Description: Set only - Writing a 1b here unlinks the MAilbox from this HOST and clears the mbx_linked bit in MAILBOX_STAT
786 
787 */
788 #define HSM_MBXCTL_UNLINK2 0x00000080U
789 #define HSM_MBXCTL_UNLINK2_M 0x00000080U
790 #define HSM_MBXCTL_UNLINK2_S 7U
791 
792 
793 /*-----------------------------------REGISTER------------------------------------
794  Register name: MBXRAWSTA
795  Offset name: HSM_O_MBXRAWSTA
796  Relative address: 0x3F04
797  Description: Raw (unmasked) Mailbox Status Register
798  Default Value: 0x00000000
799 
800  Field: INFULL1
801  From..to bits: 0...0
802  DefaultValue: 0x0
803  Access type: read-only
804  Description: (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox mbx%d is ready to rceive new token
805 
806 */
807 #define HSM_MBXRAWSTA_INFULL1 0x00000001U
808 #define HSM_MBXRAWSTA_INFULL1_M 0x00000001U
809 #define HSM_MBXRAWSTA_INFULL1_S 0U
810 /*
811 
812  Field: OUTFULL1
813  From..to bits: 1...1
814  DefaultValue: 0x0
815  Access type: read-only
816  Description: (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox mbx%d is empty
817 
818 */
819 #define HSM_MBXRAWSTA_OUTFULL1 0x00000002U
820 #define HSM_MBXRAWSTA_OUTFULL1_M 0x00000002U
821 #define HSM_MBXRAWSTA_OUTFULL1_S 1U
822 /*
823 
824  Field: LINKED1
825  From..to bits: 2...2
826  DefaultValue: 0x0
827  Access type: read-only
828  Description: (set)-This Host is linked to Mailbox mbx%d , (Clear)-This Host is not linked to Mailbox mbx%d
829 
830 */
831 #define HSM_MBXRAWSTA_LINKED1 0x00000004U
832 #define HSM_MBXRAWSTA_LINKED1_M 0x00000004U
833 #define HSM_MBXRAWSTA_LINKED1_S 2U
834 /*
835 
836  Field: INFULL2
837  From..to bits: 4...4
838  DefaultValue: 0x0
839  Access type: read-only
840  Description: (set)-Input Mailbox contains a token that is handed over to Internal Controller, (Clear)-Input Mailbox mbx%d is ready to rceive new token
841 
842 */
843 #define HSM_MBXRAWSTA_INFULL2 0x00000010U
844 #define HSM_MBXRAWSTA_INFULL2_M 0x00000010U
845 #define HSM_MBXRAWSTA_INFULL2_S 4U
846 /*
847 
848  Field: OUTFULL2
849  From..to bits: 5...5
850  DefaultValue: 0x0
851  Access type: read-only
852  Description: (set)-Output Mailbox contains an output token, (Clear)-Output Mailbox mbx%d is empty
853 
854 */
855 #define HSM_MBXRAWSTA_OUTFULL2 0x00000020U
856 #define HSM_MBXRAWSTA_OUTFULL2_M 0x00000020U
857 #define HSM_MBXRAWSTA_OUTFULL2_S 5U
858 /*
859 
860  Field: LINKED2
861  From..to bits: 6...6
862  DefaultValue: 0x0
863  Access type: read-only
864  Description: (set)-This Host is linked to Mailbox mbx%d , (Clear)-This Host is not linked to Mailbox mbx%d
865 
866 */
867 #define HSM_MBXRAWSTA_LINKED2 0x00000040U
868 #define HSM_MBXRAWSTA_LINKED2_M 0x00000040U
869 #define HSM_MBXRAWSTA_LINKED2_S 6U
870 
871 
872 /*-----------------------------------REGISTER------------------------------------
873  Register name: MBXRST
874  Offset name: HSM_O_MBXRST
875  Relative address: 0x3F04
876  Description: Mailbox Reset Register
877  Default Value: NA
878 
879  Field: OUTEMP1
880  From..to bits: 1...1
881  DefaultValue: NA
882  Access type: write-only
883  Description: Set only - Master Host can clear mbx_out_full bit in MAILBOX_STAT by writing 1b here.
884 
885 */
886 #define HSM_MBXRST_OUTEMP1 0x00000002U
887 #define HSM_MBXRST_OUTEMP1_M 0x00000002U
888 #define HSM_MBXRST_OUTEMP1_S 1U
889 /*
890 
891  Field: UNLINK1
892  From..to bits: 3...3
893  DefaultValue: NA
894  Access type: write-only
895  Description: Set only - Master Host can unlink mbx from it's current Host by writing 1b here.
896 
897 */
898 #define HSM_MBXRST_UNLINK1 0x00000008U
899 #define HSM_MBXRST_UNLINK1_M 0x00000008U
900 #define HSM_MBXRST_UNLINK1_S 3U
901 /*
902 
903  Field: OUTEMP2
904  From..to bits: 5...5
905  DefaultValue: NA
906  Access type: write-only
907  Description: Set only - Master Host can clear mbx_out_full bit in MAILBOX_STAT by writing 1b here.
908 
909 */
910 #define HSM_MBXRST_OUTEMP2 0x00000020U
911 #define HSM_MBXRST_OUTEMP2_M 0x00000020U
912 #define HSM_MBXRST_OUTEMP2_S 5U
913 /*
914 
915  Field: UNLINK2
916  From..to bits: 7...7
917  DefaultValue: NA
918  Access type: write-only
919  Description: Set only - Master Host can unlink mbx from it's current Host by writing 1b here.
920 
921 */
922 #define HSM_MBXRST_UNLINK2 0x00000080U
923 #define HSM_MBXRST_UNLINK2_M 0x00000080U
924 #define HSM_MBXRST_UNLINK2_S 7U
925 
926 
927 /*-----------------------------------REGISTER------------------------------------
928  Register name: MBXLINKID
929  Offset name: HSM_O_MBXLINKID
930  Relative address: 0x3F08
931  Description: Mailbox Status - linked Host IDs Register
932  Default Value: 0x00000000
933 
934  Field: LINKID1
935  From..to bits: 0...2
936  DefaultValue: 0x0
937  Access type: read-only
938  Description: Bits[1:0]Host cpu_id of the Host linked to the Mailbox, bit[2] Set - Mailbox is only accessible if Host uses protected access, Clear - Mailbox accessed with protected of non-protected access
939 
940 */
941 #define HSM_MBXLINKID_LINKID1_W 3U
942 #define HSM_MBXLINKID_LINKID1_M 0x00000007U
943 #define HSM_MBXLINKID_LINKID1_S 0U
944 /*
945 
946  Field: PROTACC1
947  From..to bits: 3...3
948  DefaultValue: 0x0
949  Access type: read-only
950  Description: 0: Mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Mailbox 1 is only accessible if the Host uses protected access.
951 
952 */
953 #define HSM_MBXLINKID_PROTACC1 0x00000008U
954 #define HSM_MBXLINKID_PROTACC1_M 0x00000008U
955 #define HSM_MBXLINKID_PROTACC1_S 3U
956 /*
957 
958  Field: LINKID2
959  From..to bits: 4...6
960  DefaultValue: 0x0
961  Access type: read-only
962  Description: Bits[1:0]Host cpu_id of the Host linked to the Mailbox, bit[2] Set - Mailbox is only accessible if Host uses protected access, Clear - Mailbox accessed with protected of non-protected access
963 
964 */
965 #define HSM_MBXLINKID_LINKID2_W 3U
966 #define HSM_MBXLINKID_LINKID2_M 0x00000070U
967 #define HSM_MBXLINKID_LINKID2_S 4U
968 /*
969 
970  Field: PORTACC2
971  From..to bits: 7...7
972  DefaultValue: 0x0
973  Access type: read-only
974  Description: 0: Mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Mailbox 2 is only accessible if the Host uses protected access.
975 
976 */
977 #define HSM_MBXLINKID_PORTACC2 0x00000080U
978 #define HSM_MBXLINKID_PORTACC2_M 0x00000080U
979 #define HSM_MBXLINKID_PORTACC2_S 7U
980 
981 
982 /*-----------------------------------REGISTER------------------------------------
983  Register name: MBXOUTID
984  Offset name: HSM_O_MBXOUTID
985  Relative address: 0x3F0C
986  Description: Mailbox Status - output Host IDs Register
987  Default Value: 0x00000000
988 
989  Field: OUTID1
990  From..to bits: 0...2
991  DefaultValue: 0x0
992  Access type: read-only
993  Description: Bit[1,0] Host cpu_id of the Host allowed to read a result from the Mailbox, bit[2] Set - Out Mailbox is only accessible if Host uses protected access, Clear - Output Mailbox accessed with protected of non-protected access
994 
995 */
996 #define HSM_MBXOUTID_OUTID1_W 3U
997 #define HSM_MBXOUTID_OUTID1_M 0x00000007U
998 #define HSM_MBXOUTID_OUTID1_S 0U
999 /*
1000 
1001  Field: PROTACC1
1002  From..to bits: 3...3
1003  DefaultValue: 0x0
1004  Access type: read-only
1005  Description: 0: Output mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 1 is only accessible if the Host uses protected access.
1006 
1007 */
1008 #define HSM_MBXOUTID_PROTACC1 0x00000008U
1009 #define HSM_MBXOUTID_PROTACC1_M 0x00000008U
1010 #define HSM_MBXOUTID_PROTACC1_S 3U
1011 /*
1012 
1013  Field: OUTID2
1014  From..to bits: 4...6
1015  DefaultValue: 0x0
1016  Access type: read-only
1017  Description: Bit[1,0] Host cpu_id of the Host allowed to read a result from the Mailbox, bit[2] Set - Out Mailbox is only accessible if Host uses protected access, Clear - Output Mailbox accessed with protected of non-protected access
1018 
1019 */
1020 #define HSM_MBXOUTID_OUTID2_W 3U
1021 #define HSM_MBXOUTID_OUTID2_M 0x00000070U
1022 #define HSM_MBXOUTID_OUTID2_S 4U
1023 /*
1024 
1025  Field: PORTACC2
1026  From..to bits: 7...7
1027  DefaultValue: 0x0
1028  Access type: read-only
1029  Description: 0: Output mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 2 is only accessible if the Host uses protected access.
1030 
1031 */
1032 #define HSM_MBXOUTID_PORTACC2 0x00000080U
1033 #define HSM_MBXOUTID_PORTACC2_M 0x00000080U
1034 #define HSM_MBXOUTID_PORTACC2_S 7U
1035 
1036 
1037 /*-----------------------------------REGISTER------------------------------------
1038  Register name: MBXLCKOUT
1039  Offset name: HSM_O_MBXLCKOUT
1040  Relative address: 0x3F10
1041  Description: Host/Mailbox1-4 lockout control Register
1042  Default Value: 0x00000E0E
1043 
1044  Field: LOCKOUT1
1045  From..to bits: 0...7
1046  DefaultValue: 0xE
1047  Access type: read-write
1048  Description: Bit map indicates which Hosts are blocked from accessing mailbox
1049 
1050 */
1051 #define HSM_MBXLCKOUT_LOCKOUT1_W 8U
1052 #define HSM_MBXLCKOUT_LOCKOUT1_M 0x000000FFU
1053 #define HSM_MBXLCKOUT_LOCKOUT1_S 0U
1054 /*
1055 
1056  Field: LOCKOUT2
1057  From..to bits: 8...15
1058  DefaultValue: 0xE
1059  Access type: read-write
1060  Description: Bit map indicates which Hosts are blocked from accessing mailbox
1061 
1062 */
1063 #define HSM_MBXLCKOUT_LOCKOUT2_W 8U
1064 #define HSM_MBXLCKOUT_LOCKOUT2_M 0x0000FF00U
1065 #define HSM_MBXLCKOUT_LOCKOUT2_S 8U
1066 
1067 
1068 /*-----------------------------------REGISTER------------------------------------
1069  Register name: MODULESTA
1070  Offset name: HSM_O_MODULESTA
1071  Relative address: 0x3FE0
1072  Description: Module Status Register
1073  Default Value: 0x00000100
1074 
1075  Field: FIPSMOD
1076  From..to bits: 0...0
1077  DefaultValue: 0x0
1078  Access type: read-only
1079  Description: Read-Only. Set if VaultIP is in FIPS mode
1080 
1081 */
1082 #define HSM_MODULESTA_FIPSMOD 0x00000001U
1083 #define HSM_MODULESTA_FIPSMOD_M 0x00000001U
1084 #define HSM_MODULESTA_FIPSMOD_S 0U
1085 /*
1086 
1087  Field: NFIPSMOD
1088  From..to bits: 1...1
1089  DefaultValue: 0x0
1090  Access type: read-only
1091  Description: Read-Only. Set if VaultIP is in non-FIPS mode
1092 
1093 */
1094 #define HSM_MODULESTA_NFIPSMOD 0x00000002U
1095 #define HSM_MODULESTA_NFIPSMOD_M 0x00000002U
1096 #define HSM_MODULESTA_NFIPSMOD_S 1U
1097 /*
1098 
1099  Field: CRCBUSY
1100  From..to bits: 8...8
1101  DefaultValue: 0x1
1102  Access type: read-only
1103  Description: Read-Only. Set if CRC on ProgramROM is busy
1104 
1105 */
1106 #define HSM_MODULESTA_CRCBUSY 0x00000100U
1107 #define HSM_MODULESTA_CRCBUSY_M 0x00000100U
1108 #define HSM_MODULESTA_CRCBUSY_S 8U
1109 /*
1110 
1111  Field: CRCOK
1112  From..to bits: 9...9
1113  DefaultValue: 0x0
1114  Access type: read-only
1115  Description: Read-Only. Set if CRC on ProgramROM is passes
1116 
1117 */
1118 #define HSM_MODULESTA_CRCOK 0x00000200U
1119 #define HSM_MODULESTA_CRCOK_M 0x00000200U
1120 #define HSM_MODULESTA_CRCOK_S 9U
1121 /*
1122 
1123  Field: CRCERR
1124  From..to bits: 10...10
1125  DefaultValue: 0x0
1126  Access type: read-only
1127  Description: Read-Only. Set if CRC on ProgramROM is fails
1128 
1129 */
1130 #define HSM_MODULESTA_CRCERR 0x00000400U
1131 #define HSM_MODULESTA_CRCERR_M 0x00000400U
1132 #define HSM_MODULESTA_CRCERR_S 10U
1133 /*
1134 
1135  Field: FATALERR
1136  From..to bits: 31...31
1137  DefaultValue: 0x0
1138  Access type: read-only
1139  Description: Read-Only. Set if fatal error occured
1140 
1141 */
1142 #define HSM_MODULESTA_FATALERR 0x80000000U
1143 #define HSM_MODULESTA_FATALERR_M 0x80000000U
1144 #define HSM_MODULESTA_FATALERR_S 31U
1145 
1146 
1147 /*-----------------------------------REGISTER------------------------------------
1148  Register name: EIPOPTS2
1149  Offset name: HSM_O_EIPOPTS2
1150  Relative address: 0x3FF4
1151  Description: VaultIP configured options(2)
1152  Default Value: 0x0020003C
1153 
1154  Field: DESAES
1155  From..to bits: 0...0
1156  DefaultValue: 0x0
1157  Access type: read-only
1158  Description: Set - (3)DES/AES combination crypto core available
1159 
1160 */
1161 #define HSM_EIPOPTS2_DESAES 0x00000001U
1162 #define HSM_EIPOPTS2_DESAES_M 0x00000001U
1163 #define HSM_EIPOPTS2_DESAES_S 0U
1164 /*
1165 
1166  Field: SHA
1167  From..to bits: 2...2
1168  DefaultValue: 0x1
1169  Access type: read-only
1170  Description: Set - SHA1/SHA2 combination core available
1171 
1172 */
1173 #define HSM_EIPOPTS2_SHA 0x00000004U
1174 #define HSM_EIPOPTS2_SHA_M 0x00000004U
1175 #define HSM_EIPOPTS2_SHA_S 2U
1176 /*
1177 
1178  Field: TRNG
1179  From..to bits: 3...3
1180  DefaultValue: 0x1
1181  Access type: read-only
1182  Description: Set - TRNG engine available
1183 
1184 */
1185 #define HSM_EIPOPTS2_TRNG 0x00000008U
1186 #define HSM_EIPOPTS2_TRNG_M 0x00000008U
1187 #define HSM_EIPOPTS2_TRNG_S 3U
1188 /*
1189 
1190  Field: CRC
1191  From..to bits: 4...4
1192  DefaultValue: 0x1
1193  Access type: read-only
1194  Description: CRC calculation available
1195 
1196 */
1197 #define HSM_EIPOPTS2_CRC 0x00000010U
1198 #define HSM_EIPOPTS2_CRC_M 0x00000010U
1199 #define HSM_EIPOPTS2_CRC_S 4U
1200 /*
1201 
1202  Field: PKCP
1203  From..to bits: 5...5
1204  DefaultValue: 0x1
1205  Access type: read-only
1206  Description: PKCP Engine available
1207 
1208 */
1209 #define HSM_EIPOPTS2_PKCP 0x00000020U
1210 #define HSM_EIPOPTS2_PKCP_M 0x00000020U
1211 #define HSM_EIPOPTS2_PKCP_S 5U
1212 /*
1213 
1214  Field: CCPU
1215  From..to bits: 8...8
1216  DefaultValue: 0x0
1217  Access type: read-only
1218  Description: C capable local cpu available
1219 
1220 */
1221 #define HSM_EIPOPTS2_CCPU 0x00000100U
1222 #define HSM_EIPOPTS2_CCPU_M 0x00000100U
1223 #define HSM_EIPOPTS2_CCPU_S 8U
1224 /*
1225 
1226  Field: PRAM
1227  From..to bits: 9...9
1228  DefaultValue: 0x0
1229  Access type: read-only
1230  Description: 1b = downloadable RAM based firmware program memory. 0b = ROM only firmware program memory.
1231 
1232 */
1233 #define HSM_EIPOPTS2_PRAM 0x00000200U
1234 #define HSM_EIPOPTS2_PRAM_M 0x00000200U
1235 #define HSM_EIPOPTS2_PRAM_S 9U
1236 /*
1237 
1238  Field: BUSIF
1239  From..to bits: 12...12
1240  DefaultValue: 0x0
1241  Access type: read-only
1242  Description: Bus interface type, for both Master and Slave: 0b = 32-bit AHB, 1b = 32-bit AXI
1243 
1244 */
1245 #define HSM_EIPOPTS2_BUSIF 0x00001000U
1246 #define HSM_EIPOPTS2_BUSIF_M 0x00001000U
1247 #define HSM_EIPOPTS2_BUSIF_S 12U
1248 /*
1249 
1250  Field: ADDCE1
1251  From..to bits: 16...16
1252  DefaultValue: 0x0
1253  Access type: read-only
1254  Description: Set - an additional crypto engine is available in hardware as custom engine1
1255 
1256 */
1257 #define HSM_EIPOPTS2_ADDCE1 0x00010000U
1258 #define HSM_EIPOPTS2_ADDCE1_M 0x00010000U
1259 #define HSM_EIPOPTS2_ADDCE1_S 16U
1260 /*
1261 
1262  Field: ADDCE2
1263  From..to bits: 17...17
1264  DefaultValue: 0x0
1265  Access type: read-only
1266  Description: Set - an additional crypto engine is available in hardware as custom engine2
1267 
1268 */
1269 #define HSM_EIPOPTS2_ADDCE2 0x00020000U
1270 #define HSM_EIPOPTS2_ADDCE2_M 0x00020000U
1271 #define HSM_EIPOPTS2_ADDCE2_S 17U
1272 /*
1273 
1274  Field: ADDCE3
1275  From..to bits: 18...18
1276  DefaultValue: 0x0
1277  Access type: read-only
1278  Description: Set - an additional crypto engine is available in hardware as custom engine3
1279 
1280 */
1281 #define HSM_EIPOPTS2_ADDCE3 0x00040000U
1282 #define HSM_EIPOPTS2_ADDCE3_M 0x00040000U
1283 #define HSM_EIPOPTS2_ADDCE3_S 18U
1284 /*
1285 
1286  Field: ADDCE4
1287  From..to bits: 19...19
1288  DefaultValue: 0x0
1289  Access type: read-only
1290  Description: Set - an additional crypto engine is available in hardware as custom engine4
1291 
1292 */
1293 #define HSM_EIPOPTS2_ADDCE4 0x00080000U
1294 #define HSM_EIPOPTS2_ADDCE4_M 0x00080000U
1295 #define HSM_EIPOPTS2_ADDCE4_S 19U
1296 /*
1297 
1298  Field: ADDCE5
1299  From..to bits: 20...20
1300  DefaultValue: 0x0
1301  Access type: read-only
1302  Description: Set - an additional crypto engine is available in hardware as custom engine5
1303 
1304 */
1305 #define HSM_EIPOPTS2_ADDCE5 0x00100000U
1306 #define HSM_EIPOPTS2_ADDCE5_M 0x00100000U
1307 #define HSM_EIPOPTS2_ADDCE5_S 20U
1308 /*
1309 
1310  Field: ADDCE6
1311  From..to bits: 21...21
1312  DefaultValue: 0x1
1313  Access type: read-only
1314  Description: Set - an additional crypto engine is available in hardware as custom engine6
1315 
1316 */
1317 #define HSM_EIPOPTS2_ADDCE6 0x00200000U
1318 #define HSM_EIPOPTS2_ADDCE6_M 0x00200000U
1319 #define HSM_EIPOPTS2_ADDCE6_S 21U
1320 /*
1321 
1322  Field: ADDCE7
1323  From..to bits: 22...22
1324  DefaultValue: 0x0
1325  Access type: read-only
1326  Description: Set - an additional crypto engine is available in hardware as custom engine7
1327 
1328 */
1329 #define HSM_EIPOPTS2_ADDCE7 0x00400000U
1330 #define HSM_EIPOPTS2_ADDCE7_M 0x00400000U
1331 #define HSM_EIPOPTS2_ADDCE7_S 22U
1332 /*
1333 
1334  Field: ADDCE8
1335  From..to bits: 23...23
1336  DefaultValue: 0x0
1337  Access type: read-only
1338  Description: Set - an additional crypto engine is available in hardware as custom engine8
1339 
1340 */
1341 #define HSM_EIPOPTS2_ADDCE8 0x00800000U
1342 #define HSM_EIPOPTS2_ADDCE8_M 0x00800000U
1343 #define HSM_EIPOPTS2_ADDCE8_S 23U
1344 /*
1345 
1346  Field: ADDCE9
1347  From..to bits: 24...24
1348  DefaultValue: 0x0
1349  Access type: read-only
1350  Description: Set - an additional crypto engine is available in hardware as custom engine9
1351 
1352 */
1353 #define HSM_EIPOPTS2_ADDCE9 0x01000000U
1354 #define HSM_EIPOPTS2_ADDCE9_M 0x01000000U
1355 #define HSM_EIPOPTS2_ADDCE9_S 24U
1356 /*
1357 
1358  Field: ADDCE10
1359  From..to bits: 25...25
1360  DefaultValue: 0x0
1361  Access type: read-only
1362  Description: Set - an additional crypto engine is available in hardware as custom engine10
1363 
1364 */
1365 #define HSM_EIPOPTS2_ADDCE10 0x02000000U
1366 #define HSM_EIPOPTS2_ADDCE10_M 0x02000000U
1367 #define HSM_EIPOPTS2_ADDCE10_S 25U
1368 
1369 
1370 /*-----------------------------------REGISTER------------------------------------
1371  Register name: EIPOPTS1
1372  Offset name: HSM_O_EIPOPTS1
1373  Relative address: 0x3FF8
1374  Description: VaultIP configured options(1)
1375  Default Value: 0x01800F12
1376 
1377  Field: NUMOFMBX
1378  From..to bits: 0...3
1379  DefaultValue: 0x2
1380  Access type: read-only
1381  Description: Number of Input/Output Mailbox pairs
1382 
1383 */
1384 #define HSM_EIPOPTS1_NUMOFMBX_W 4U
1385 #define HSM_EIPOPTS1_NUMOFMBX_M 0x0000000FU
1386 #define HSM_EIPOPTS1_NUMOFMBX_S 0U
1387 /*
1388 
1389  Field: MBXSIZE
1390  From..to bits: 4...5
1391  DefaultValue: 0x1
1392  Access type: read-only
1393  Description: Implemented size of Mailbox pairs - 00b-128bytes, 01b-256bytes, 10b-512bytes, 11b-1Kbyte
1394 
1395 */
1396 #define HSM_EIPOPTS1_MBXSIZE_W 2U
1397 #define HSM_EIPOPTS1_MBXSIZE_M 0x00000030U
1398 #define HSM_EIPOPTS1_MBXSIZE_S 4U
1399 /*
1400 
1401  Field: HOSTID
1402  From..to bits: 8...15
1403  DefaultValue: 0xF
1404  Access type: read-only
1405  Description: Bits to indicate which of the 8 possible cpu_id codes on the bus interface are active
1406 
1407 */
1408 #define HSM_EIPOPTS1_HOSTID_W 8U
1409 #define HSM_EIPOPTS1_HOSTID_M 0x0000FF00U
1410 #define HSM_EIPOPTS1_HOSTID_S 8U
1411 /*
1412 
1413  Field: MASID
1414  From..to bits: 16...18
1415  DefaultValue: 0x0
1416  Access type: read-only
1417  Description: Value of the cpu_id that designates the Master Host
1418 
1419 */
1420 #define HSM_EIPOPTS1_MASID_W 3U
1421 #define HSM_EIPOPTS1_MASID_M 0x00070000U
1422 #define HSM_EIPOPTS1_MASID_S 16U
1423 /*
1424 
1425  Field: MYID
1426  From..to bits: 20...22
1427  DefaultValue: 0x0
1428  Access type: read-only
1429  Description: Slave & Master interface support protection bit (secure/non-secure) accesses
1430 
1431 */
1432 #define HSM_EIPOPTS1_MYID_W 3U
1433 #define HSM_EIPOPTS1_MYID_M 0x00700000U
1434 #define HSM_EIPOPTS1_MYID_S 20U
1435 /*
1436 
1437  Field: MYIDSEC
1438  From..to bits: 23...23
1439  DefaultValue: 0x1
1440  Access type: read-only
1441  Description: Indicates the current protection bit values of the Host actually reading the register
1442 
1443 */
1444 #define HSM_EIPOPTS1_MYIDSEC 0x00800000U
1445 #define HSM_EIPOPTS1_MYIDSEC_M 0x00800000U
1446 #define HSM_EIPOPTS1_MYIDSEC_S 23U
1447 /*
1448 
1449  Field: HOSTIDSEC
1450  From..to bits: 24...31
1451  DefaultValue: 0x1
1452  Access type: read-only
1453  Description: Bits to indicate which of the 8 possible cpu_id codes on the bus interface are active Hosts with secure access
1454 
1455 */
1456 #define HSM_EIPOPTS1_HOSTIDSEC_W 8U
1457 #define HSM_EIPOPTS1_HOSTIDSEC_M 0xFF000000U
1458 #define HSM_EIPOPTS1_HOSTIDSEC_S 24U
1459 
1460 
1461 /*-----------------------------------REGISTER------------------------------------
1462  Register name: EIPVER
1463  Offset name: HSM_O_EIPVER
1464  Relative address: 0x3FFC
1465  Description: Standard EIP version register
1466  Default Value: 0x04007D82
1467 
1468  Field: EIPNUM
1469  From..to bits: 0...7
1470  DefaultValue: 0x82
1471  Access type: read-only
1472  Description: RAMBUS EIP number - EIP130
1473 
1474 */
1475 #define HSM_EIPVER_EIPNUM_W 8U
1476 #define HSM_EIPVER_EIPNUM_M 0x000000FFU
1477 #define HSM_EIPVER_EIPNUM_S 0U
1478 /*
1479 
1480  Field: EIPNUMCOMP
1481  From..to bits: 8...15
1482  DefaultValue: 0x7D
1483  Access type: read-only
1484  Description: Bit by Bit compliment of EIP Number
1485 
1486 */
1487 #define HSM_EIPVER_EIPNUMCOMP_W 8U
1488 #define HSM_EIPVER_EIPNUMCOMP_M 0x0000FF00U
1489 #define HSM_EIPVER_EIPNUMCOMP_S 8U
1490 /*
1491 
1492  Field: PATCHLVL
1493  From..to bits: 16...19
1494  DefaultValue: 0x0
1495  Access type: read-only
1496  Description: Hardware Patch Level for this module
1497 
1498 */
1499 #define HSM_EIPVER_PATCHLVL_W 4U
1500 #define HSM_EIPVER_PATCHLVL_M 0x000F0000U
1501 #define HSM_EIPVER_PATCHLVL_S 16U
1502 /*
1503 
1504  Field: MINORVER
1505  From..to bits: 20...23
1506  DefaultValue: 0x0
1507  Access type: read-only
1508  Description: Minor Version release number for this module
1509 
1510 */
1511 #define HSM_EIPVER_MINORVER_W 4U
1512 #define HSM_EIPVER_MINORVER_M 0x00F00000U
1513 #define HSM_EIPVER_MINORVER_S 20U
1514 /*
1515 
1516  Field: MAJORVER
1517  From..to bits: 24...27
1518  DefaultValue: 0x4
1519  Access type: read-only
1520  Description: Major Version release number for this module
1521 
1522 */
1523 #define HSM_EIPVER_MAJORVER_W 4U
1524 #define HSM_EIPVER_MAJORVER_M 0x0F000000U
1525 #define HSM_EIPVER_MAJORVER_S 24U
1526 
1527 #endif /* __HW_HSM_H__*/