CC35xxDriverLibrary
hw_hostmcu_aon.h
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1 /******************************************************************************
2 * Filename: hw_hostmcu_aon.h
3 *
4 * Description: Defines and prototypes for the HOSTMCU_AON peripheral.
5 *
6 * Copyright (c) 2023-2025, Texas Instruments Incorporated
7 * All rights reserved.
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35 ******************************************************************************/
36 #ifndef __HW_HOSTMCU_AON_H__
37 #define __HW_HOSTMCU_AON_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HOSTMCU_AON component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Wake up Control Skip Configuration
45 #define HOSTMCU_AON_O_WUCSKPCFG 0x00000004U
46 
47 //Configure WIC SENSE
48 #define HOSTMCU_AON_O_CFGWICSNS 0x00000008U
49 
50 //ELP Wake-up Type Configuration
51 #define HOSTMCU_AON_O_CFGWUTP 0x0000000CU
52 
53 //ELP Timer Enable
54 #define HOSTMCU_AON_O_ELPTMREN 0x00000010U
55 
56 //Timer Wake-up Configuration
57 #define HOSTMCU_AON_O_CFGTMRWU 0x00000014U
58 
59 //Timer Wake-up Request Clear
60 #define HOSTMCU_AON_O_TMRWUREQ 0x00000018U
61 
62 //Watch Dog Timer Configuration
63 #define HOSTMCU_AON_O_CFGWDT 0x0000001CU
64 
65 //Watch Dog Timer Request Clear
66 #define HOSTMCU_AON_O_WDTREQ 0x00000020U
67 
68 //GPIO Wake-up AND IRQ Configuration
69 #define HOSTMCU_AON_O_GPWUAND 0x00000028U
70 
71 //GPIO Wake-up OR IRQ Configuration
72 #define HOSTMCU_AON_O_GPWUOR 0x0000002CU
73 
74 //GPIO Wake-up AND IRQ Configuration
75 #define HOSTMCU_AON_O_GPWUAND1 0x00000030U
76 
77 //GPIO Wake-up OR IRQ Configuration
78 #define HOSTMCU_AON_O_GPWUOR1 0x00000034U
79 
80 //Fast Clock From ARM Command
81 #define HOSTMCU_AON_O_FCLKARM 0x00000038U
82 
83 //Sleep Time Slow Clock
84 #define HOSTMCU_AON_O_SLPTIMES 0x0000003CU
85 
86 //Sleep Time Fast Clock
87 #define HOSTMCU_AON_O_SLPTIMEF 0x00000040U
88 
89 //Wake up Request Status
90 #define HOSTMCU_AON_O_WUREQ 0x0000004CU
91 
92 //OSPI Reference Clock
93 #define HOSTMCU_AON_O_OREFCLK 0x00000050U
94 
95 //Wake-up Control State
96 #define HOSTMCU_AON_O_WUC 0x0000005CU
97 
98 
99 
100 /*-----------------------------------REGISTER------------------------------------
101  Register name: WUCSKPCFG
102  Offset name: HOSTMCU_AON_O_WUCSKPCFG
103  Relative address: 0x4
104  Description: Wake up Control Skip Configuration
105  Default Value: 0x00000000
106 
107  Field: SKPPRCMVLD
108  From..to bits: 0...0
109  DefaultValue: 0x0
110  Access type: read-write
111  Description: SKIP PRCM VALID
112 
113  Enable skip precise duration for PRCM Shared UP if wake up event type is '0':
114  '0' - don't skip
115  '1' - skip
116 
117  ENUMs:
118  DIS: Don't Skip
119  EN: Skip
120 */
121 #define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD 0x00000001U
122 #define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_M 0x00000001U
123 #define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_S 0U
124 #define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_DIS 0x00000000U
125 #define HOSTMCU_AON_WUCSKPCFG_SKPPRCMVLD_EN 0x00000001U
126 /*
127 
128  Field: SKPPDVLD
129  From..to bits: 1...1
130  DefaultValue: 0x0
131  Access type: read-write
132  Description: SKIP POWER DOMAIN VALID
133 
134  Enable skip precise duration for Power Domain if wake up event type is '0':
135  '0' - don't skip
136  '1' - skip
137 
138  ENUMs:
139  DIS: Don't skip
140  EN: Skip
141 */
142 #define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD 0x00000002U
143 #define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_M 0x00000002U
144 #define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_S 1U
145 #define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_DIS 0x00000000U
146 #define HOSTMCU_AON_WUCSKPCFG_SKPPDVLD_EN 0x00000002U
147 
148 
149 /*-----------------------------------REGISTER------------------------------------
150  Register name: CFGWICSNS
151  Offset name: HOSTMCU_AON_O_CFGWICSNS
152  Relative address: 0x8
153  Description: Configure WIC SENSE
154  Default Value: 0x00000000
155 
156  Field: VAL
157  From..to bits: 0...17
158  DefaultValue: 0x0
159  Access type: read-write
160  Description: Field to control wake up source
161 
162  Set 1 - Enable wake up source.
163  Set 0 - Disable wake up source.
164 
165  Bit 0 : ELP TMR Wake up request
166  Bit 1 : GPIO wake up src 0
167  Bit 2 : GPIO wake up src 1
168  Bit 3 : doorbell 0
169  Bit 4 : doorbell 1
170  Bit 5 : doorbell 2
171  Bit 6 : doorbell 3
172  Bit 7 : doorbell 4
173  Bit 8 : doorbell 5
174  Bit 9 : doorbell 6
175  Bit 10 : doorbell 7
176  Bit 11 : nab_host_irq
177  Bit 12 : ble_rfc_gpo_8_irq
178  Bit 13 : RTC
179  Bit 14 : DebugSS Csyspwrupreq
180  Bit 15 : DebugSS Forceactive
181  Bit 16 : secured_error_irq
182  Bit 17 : core wdt irq
183 
184  Note: GPIO wakeup src 0 is AND of wakeup sources and GPIO wakup src 1 is OR of wakeup sources
185 
186  ENUMs:
187  DIS: Disable wakeup source
188  TMRREQ_EN: ELP timer wakeup request
189  WUSRC0_EN: AND of wakeup sources
190  WUSRC1_EN: OR of wakeup sources
191  DRBL0_EN: Doorbell 0
192  DRBL1_EN: Doorbell 1
193  DRBL2_EN: Doorbell 2
194  DRBL3_EN: Doorbell 3
195  DRBL4_EN: Doorbell 4
196  DRBL5_EN: Doorbell 5
197  DRBL6_EN: Doorbell 6
198  DRBL7_EN: Doorbell 7
199  NAB_EN: NAB host irq
200  BLERFCGPO_EN: BLE RFC GPO 9 irq
201  RTC_EN: RTC
202  DBGPWRUP_EN: Debugss Csyspwrupreq
203  DBGFRCACT_EN: Debugss forecactive
204  SECERR_EN: Secure error irq
205  COREWDT_EN: Core WDT request
206 */
207 #define HOSTMCU_AON_CFGWICSNS_VAL_W 18U
208 #define HOSTMCU_AON_CFGWICSNS_VAL_M 0x0003FFFFU
209 #define HOSTMCU_AON_CFGWICSNS_VAL_S 0U
210 #define HOSTMCU_AON_CFGWICSNS_VAL_DIS 0x00000000U
211 #define HOSTMCU_AON_CFGWICSNS_VAL_TMRREQ_EN 0x00000001U
212 #define HOSTMCU_AON_CFGWICSNS_VAL_WUSRC0_EN 0x00000002U
213 #define HOSTMCU_AON_CFGWICSNS_VAL_WUSRC1_EN 0x00000004U
214 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL0_EN 0x00000008U
215 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL1_EN 0x00000010U
216 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL2_EN 0x00000020U
217 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL3_EN 0x00000040U
218 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL4_EN 0x00000080U
219 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL5_EN 0x00000100U
220 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL6_EN 0x00000200U
221 #define HOSTMCU_AON_CFGWICSNS_VAL_DRBL7_EN 0x00000400U
222 #define HOSTMCU_AON_CFGWICSNS_VAL_NAB_EN 0x00000800U
223 #define HOSTMCU_AON_CFGWICSNS_VAL_BLERFCGPO_EN 0x00001000U
224 #define HOSTMCU_AON_CFGWICSNS_VAL_RTC_EN 0x00002000U
225 #define HOSTMCU_AON_CFGWICSNS_VAL_DBGPWRUP_EN 0x00004000U
226 #define HOSTMCU_AON_CFGWICSNS_VAL_DBGFRCACT_EN 0x00008000U
227 #define HOSTMCU_AON_CFGWICSNS_VAL_SECERR_EN 0x00010000U
228 #define HOSTMCU_AON_CFGWICSNS_VAL_COREWDT_EN 0x00020000U
229 
230 
231 /*-----------------------------------REGISTER------------------------------------
232  Register name: CFGWUTP
233  Offset name: HOSTMCU_AON_O_CFGWUTP
234  Relative address: 0xC
235  Description: ELP Wake-up Type Configuration.
236 
237  Register to configure wake up type
238  Default Value: 0x00000000
239 
240  Field: VAL
241  From..to bits: 0...17
242  DefaultValue: 0x0
243  Access type: read-write
244  Description: Field to configure wake up type
245 
246  Set 0 - Slow Wake up (precise WU).
247  Set 1 - Fast Wake up (assume system is already active when event is triggered).
248 
249  Bit 0 : ELP TMR Wake up request
250  Bit 1 : GPIO wake up src 0
251  Bit 2 : GPIO wake up src 1
252  Bit 3 : doorbell 0
253  Bit 4 : doorbell 1
254  Bit 5 : doorbell 2
255  Bit 6 : doorbell 3
256  Bit 7 : doorbell 4
257  Bit 8 : doorbell 5
258  Bit 9 : doorbell 6
259  Bit 10 : doorbell 7
260  Bit 11 : nab_host_irq
261  Bit 12 : ble_rfc_gpo_8_irq
262  Bit 13 : RTC
263  Bit 14 : DebugSS Csyspwrupreq
264  Bit 15 : DebugSS Forceactive
265  Bit 16 : secured_error_irq
266  Bit 17 : core wdt irq
267 
268  Note: GPIO wakeup src 0 is AND of wakeup sources and GPIO wakup src 1 is OR of wakeup sources
269 
270  ENUMs:
271  SLOW: Slow wakeup(precise wakup)
272  TMRREQ: Fast Wake up
273  WUSRC0: Fast Wake up
274  WUSRC1: Fast Wake up
275  DRBL0: Fast Wake up
276  DRBL1: Fast Wake up
277  DRBL2: Fast Wake up
278  DRBL3: Fast Wake up
279  DRBL4: Fast Wake up
280  DRBL5: Fast Wake up
281  DRBL6: Fast Wake up
282  DRBL7: Fast Wake up
283  NAB: Fast Wake up
284  BLERFCGPO: Fast Wake up
285  RTC: Fast Wake up
286  DBGPWRUP: Fast Wake up
287  DBGFRCACT: Fast Wake up
288  SECERR: Fast Wake up
289  COREWDT: Fast Wake up
290 */
291 #define HOSTMCU_AON_CFGWUTP_VAL_W 18U
292 #define HOSTMCU_AON_CFGWUTP_VAL_M 0x0003FFFFU
293 #define HOSTMCU_AON_CFGWUTP_VAL_S 0U
294 #define HOSTMCU_AON_CFGWUTP_VAL_SLOW 0x00000000U
295 #define HOSTMCU_AON_CFGWUTP_VAL_TMRREQ 0x00000001U
296 #define HOSTMCU_AON_CFGWUTP_VAL_WUSRC0 0x00000002U
297 #define HOSTMCU_AON_CFGWUTP_VAL_WUSRC1 0x00000004U
298 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL0 0x00000008U
299 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL1 0x00000010U
300 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL2 0x00000020U
301 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL3 0x00000040U
302 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL4 0x00000080U
303 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL5 0x00000100U
304 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL6 0x00000200U
305 #define HOSTMCU_AON_CFGWUTP_VAL_DRBL7 0x00000400U
306 #define HOSTMCU_AON_CFGWUTP_VAL_NAB 0x00000800U
307 #define HOSTMCU_AON_CFGWUTP_VAL_BLERFCGPO 0x00001000U
308 #define HOSTMCU_AON_CFGWUTP_VAL_RTC 0x00002000U
309 #define HOSTMCU_AON_CFGWUTP_VAL_DBGPWRUP 0x00004000U
310 #define HOSTMCU_AON_CFGWUTP_VAL_DBGFRCACT 0x00008000U
311 #define HOSTMCU_AON_CFGWUTP_VAL_SECERR 0x00010000U
312 #define HOSTMCU_AON_CFGWUTP_VAL_COREWDT 0x00020000U
313 
314 
315 /*-----------------------------------REGISTER------------------------------------
316  Register name: ELPTMREN
317  Offset name: HOSTMCU_AON_O_ELPTMREN
318  Relative address: 0x10
319  Description: ELP Timer Enable.
320 
321  Register to configure ELP Timer enable
322  Default Value: 0x00000002
323 
324  Field: VAL
325  From..to bits: 0...0
326  DefaultValue: 0x0
327  Access type: read-only
328  Description: Field to enable ELP Timer
329 
330  ENUMs:
331  DIS: Disable
332  EN: Enable
333 */
334 #define HOSTMCU_AON_ELPTMREN_VAL 0x00000001U
335 #define HOSTMCU_AON_ELPTMREN_VAL_M 0x00000001U
336 #define HOSTMCU_AON_ELPTMREN_VAL_S 0U
337 #define HOSTMCU_AON_ELPTMREN_VAL_DIS 0x00000000U
338 #define HOSTMCU_AON_ELPTMREN_VAL_EN 0x00000001U
339 /*
340 
341  Field: TMRSWCTL
342  From..to bits: 1...1
343  DefaultValue: 0x1
344  Access type: read-write
345  Description: Field to configure the type of timer control
346 
347  ENUMs:
348  HW: Hardware control
349  SW: Software control
350 */
351 #define HOSTMCU_AON_ELPTMREN_TMRSWCTL 0x00000002U
352 #define HOSTMCU_AON_ELPTMREN_TMRSWCTL_M 0x00000002U
353 #define HOSTMCU_AON_ELPTMREN_TMRSWCTL_S 1U
354 #define HOSTMCU_AON_ELPTMREN_TMRSWCTL_HW 0x00000000U
355 #define HOSTMCU_AON_ELPTMREN_TMRSWCTL_SW 0x00000002U
356 /*
357 
358  Field: ELPTMRSET
359  From..to bits: 2...2
360  DefaultValue: 0x0
361  Access type: read-write
362  Description: ELP TIMER SET
363 
364  starts the timer
365 
366 */
367 #define HOSTMCU_AON_ELPTMREN_ELPTMRSET 0x00000004U
368 #define HOSTMCU_AON_ELPTMREN_ELPTMRSET_M 0x00000004U
369 #define HOSTMCU_AON_ELPTMREN_ELPTMRSET_S 2U
370 /*
371 
372  Field: ELPTMRRST
373  From..to bits: 3...3
374  DefaultValue: 0x0
375  Access type: read-write
376  Description: ELP TIMER RESET
377 
378  setting this bit will stop the timer
379 
380 */
381 #define HOSTMCU_AON_ELPTMREN_ELPTMRRST 0x00000008U
382 #define HOSTMCU_AON_ELPTMREN_ELPTMRRST_M 0x00000008U
383 #define HOSTMCU_AON_ELPTMREN_ELPTMRRST_S 3U
384 /*
385 
386  Field: ELPTMRLD
387  From..to bits: 16...16
388  DefaultValue: 0x0
389  Access type: write-only
390  Description: ELP TIMER LOAD
391 
392  setting this bit will load the value 2 to the timer
393 
394 */
395 #define HOSTMCU_AON_ELPTMREN_ELPTMRLD 0x00010000U
396 #define HOSTMCU_AON_ELPTMREN_ELPTMRLD_M 0x00010000U
397 #define HOSTMCU_AON_ELPTMREN_ELPTMRLD_S 16U
398 
399 
400 /*-----------------------------------REGISTER------------------------------------
401  Register name: CFGTMRWU
402  Offset name: HOSTMCU_AON_O_CFGTMRWU
403  Relative address: 0x14
404  Description: Timer Wake-up Configuration.
405 
406  Register to configure Timer wake up
407  Default Value: 0x00000000
408 
409  Field: THR
410  From..to bits: 0...30
411  DefaultValue: 0x0
412  Access type: read-write
413  Description: Field to configure the Threshold of timer wake up
414 
415  Upon reaching this value wake up event is generated towards the WUC (if not masked in WICSENSE).
416  Resolution slow clock cycles.
417 
418  value must be greater than 1
419 
420 */
421 #define HOSTMCU_AON_CFGTMRWU_THR_W 31U
422 #define HOSTMCU_AON_CFGTMRWU_THR_M 0x7FFFFFFFU
423 #define HOSTMCU_AON_CFGTMRWU_THR_S 0U
424 /*
425 
426  Field: EN
427  From..to bits: 31...31
428  DefaultValue: 0x0
429  Access type: read-write
430  Description: Field to enable timer wake up
431 
432  Set 1 - Enable BCN threshold IRQ.
433  Set 0 - Otherwise.
434 
435  Timer is kicked upon moving from ACTIVE to POWER DOWN.
436 
437  ENUMs:
438  DIS: otherwise
439  EN: Enable BCN threshold IRQ
440 */
441 #define HOSTMCU_AON_CFGTMRWU_EN 0x80000000U
442 #define HOSTMCU_AON_CFGTMRWU_EN_M 0x80000000U
443 #define HOSTMCU_AON_CFGTMRWU_EN_S 31U
444 #define HOSTMCU_AON_CFGTMRWU_EN_DIS 0x00000000U
445 #define HOSTMCU_AON_CFGTMRWU_EN_EN 0x80000000U
446 
447 
448 /*-----------------------------------REGISTER------------------------------------
449  Register name: TMRWUREQ
450  Offset name: HOSTMCU_AON_O_TMRWUREQ
451  Relative address: 0x18
452  Description: Timer Wake-up Request Clear.
453 
454  Register to configure timer wake up request
455  Default Value: 0x00000000
456 
457  Field: CLR
458  From..to bits: 0...0
459  DefaultValue: 0x0
460  Access type: write-only
461  Description: Field to clear timer wake up request. Set this bit to clear
462 
463 */
464 #define HOSTMCU_AON_TMRWUREQ_CLR 0x00000001U
465 #define HOSTMCU_AON_TMRWUREQ_CLR_M 0x00000001U
466 #define HOSTMCU_AON_TMRWUREQ_CLR_S 0U
467 
468 
469 /*-----------------------------------REGISTER------------------------------------
470  Register name: CFGWDT
471  Offset name: HOSTMCU_AON_O_CFGWDT
472  Relative address: 0x1C
473  Description: Watch Dog Timer Configuration.
474 
475  Register to configure watchdog timer
476  Default Value: 0x800EA600
477 
478  Field: THR
479  From..to bits: 8...30
480  DefaultValue: 0xEA6
481  Access type: read-write
482  Description: Field to configure watchdog timer threshold
483 
484  Upon reaching this value wake up event is generated towards the WUC (if not masked in WICSENSE).
485  Resolution slow clock cycles (min val ~8ms).
486 
487  value must be greater than 1
488 
489 */
490 #define HOSTMCU_AON_CFGWDT_THR_W 23U
491 #define HOSTMCU_AON_CFGWDT_THR_M 0x7FFFFF00U
492 #define HOSTMCU_AON_CFGWDT_THR_S 8U
493 /*
494 
495  Field: EN
496  From..to bits: 31...31
497  DefaultValue: 0x1
498  Access type: read-write
499  Description: Field to enable watchdog timer
500 
501  ENUMs:
502  DIS:
503  EN:
504 */
505 #define HOSTMCU_AON_CFGWDT_EN 0x80000000U
506 #define HOSTMCU_AON_CFGWDT_EN_M 0x80000000U
507 #define HOSTMCU_AON_CFGWDT_EN_S 31U
508 #define HOSTMCU_AON_CFGWDT_EN_DIS 0x00000000U
509 #define HOSTMCU_AON_CFGWDT_EN_EN 0x80000000U
510 
511 
512 /*-----------------------------------REGISTER------------------------------------
513  Register name: WDTREQ
514  Offset name: HOSTMCU_AON_O_WDTREQ
515  Relative address: 0x20
516  Description: Watch Dog Timer Request Clear.
517 
518  Register to clear watchdog timer request
519  Default Value: 0x00000000
520 
521  Field: CLR
522  From..to bits: 0...0
523  DefaultValue: 0x0
524  Access type: write-only
525  Description: Field to clear watchdog timer request. Set this bet to clear
526 
527 */
528 #define HOSTMCU_AON_WDTREQ_CLR 0x00000001U
529 #define HOSTMCU_AON_WDTREQ_CLR_M 0x00000001U
530 #define HOSTMCU_AON_WDTREQ_CLR_S 0U
531 
532 
533 /*-----------------------------------REGISTER------------------------------------
534  Register name: GPWUAND
535  Offset name: HOSTMCU_AON_O_GPWUAND
536  Relative address: 0x28
537  Description: GPIO Wake-up AND IRQ Configuration.
538 
539  Field to configure *GPIO* wake up AND *IRQ* 0 to 31
540  Default Value: 0xFFFFFFFF
541 
542  Field: BM0T31
543  From..to bits: 0...31
544  DefaultValue: 0xFFFFFFFF
545  Access type: read-write
546  Description: Field to bit mask GPIO 0 to 31
547 
548  select 0-31 GPIOs as wake up source.
549 
550 */
551 #define HOSTMCU_AON_GPWUAND_BM0T31_W 32U
552 #define HOSTMCU_AON_GPWUAND_BM0T31_M 0xFFFFFFFFU
553 #define HOSTMCU_AON_GPWUAND_BM0T31_S 0U
554 
555 
556 /*-----------------------------------REGISTER------------------------------------
557  Register name: GPWUOR
558  Offset name: HOSTMCU_AON_O_GPWUOR
559  Relative address: 0x2C
560  Description: GPIO Wake-up OR IRQ Configuration.
561 
562  Field to configure *GPIO* wake up OR gate *IRQ*
563  Default Value: 0xFFFFFFFF
564 
565  Field: BM0T31
566  From..to bits: 0...31
567  DefaultValue: 0xFFFFFFFF
568  Access type: read-write
569  Description: Field to bit mask GPIO 0 to 31
570 
571  select 0-31 GPIOs as wake up source.
572 
573 */
574 #define HOSTMCU_AON_GPWUOR_BM0T31_W 32U
575 #define HOSTMCU_AON_GPWUOR_BM0T31_M 0xFFFFFFFFU
576 #define HOSTMCU_AON_GPWUOR_BM0T31_S 0U
577 
578 
579 /*-----------------------------------REGISTER------------------------------------
580  Register name: GPWUAND1
581  Offset name: HOSTMCU_AON_O_GPWUAND1
582  Relative address: 0x30
583  Description: GPIO Wake-up AND IRQ Configuration.
584 
585  Field to configure *GPIO* wake up AND *IRQ* 32 to 44
586  Default Value: 0x000FFFFF
587 
588  Field: BM32T44
589  From..to bits: 0...12
590  DefaultValue: 0x1FFF
591  Access type: read-write
592  Description: Field to bit mask 32 to 44
593 
594  select 32-44 GPIOs as wake up source.
595 
596 */
597 #define HOSTMCU_AON_GPWUAND1_BM32T44_W 13U
598 #define HOSTMCU_AON_GPWUAND1_BM32T44_M 0x00001FFFU
599 #define HOSTMCU_AON_GPWUAND1_BM32T44_S 0U
600 
601 
602 /*-----------------------------------REGISTER------------------------------------
603  Register name: GPWUOR1
604  Offset name: HOSTMCU_AON_O_GPWUOR1
605  Relative address: 0x34
606  Description: GPIO Wake-up OR IRQ Configuration.
607 
608  Field to configure *GPIO* wake up OR *IRQ* 32 to 44
609  Default Value: 0x000FFFFF
610 
611  Field: BM32T44
612  From..to bits: 0...12
613  DefaultValue: 0x1FFF
614  Access type: read-write
615  Description: Field to bit mask 32 to 44
616 
617  select 32-44 GPIOs as wake up source.
618 
619 */
620 #define HOSTMCU_AON_GPWUOR1_BM32T44_W 13U
621 #define HOSTMCU_AON_GPWUOR1_BM32T44_M 0x00001FFFU
622 #define HOSTMCU_AON_GPWUOR1_BM32T44_S 0U
623 
624 
625 /*-----------------------------------REGISTER------------------------------------
626  Register name: FCLKARM
627  Offset name: HOSTMCU_AON_O_FCLKARM
628  Relative address: 0x38
629  Description: Fast Clock From ARM Command
630  Default Value: 0x00000000
631 
632  Field: CMD
633  From..to bits: 0...15
634  DefaultValue: 0x0
635  Access type: read-only
636  Description: Command
637  Latched counter value reflecting the number of fast clocks (host_clk) from rise of SLEEPDEEP indication until ELP WUC start power down sequence.
638  This value should capture the uncertainty of 2-3 slow clocks of synchronization of ARM CMD
639 
640 */
641 #define HOSTMCU_AON_FCLKARM_CMD_W 16U
642 #define HOSTMCU_AON_FCLKARM_CMD_M 0x0000FFFFU
643 #define HOSTMCU_AON_FCLKARM_CMD_S 0U
644 
645 
646 /*-----------------------------------REGISTER------------------------------------
647  Register name: SLPTIMES
648  Offset name: HOSTMCU_AON_O_SLPTIMES
649  Relative address: 0x3C
650  Description: Sleep Time Slow Clock.
651 
652  Register for sleep time on slow clock
653  Default Value: 0x00000000
654 
655  Field: CLK
656  From..to bits: 0...31
657  DefaultValue: 0x0
658  Access type: read-only
659  Description: Sleep time value from last ELP sleep entry (slow clock synced ARM CMD).
660  Slow Clock - Reflects the number of slow clocks in ELP timer.
661 
662 */
663 #define HOSTMCU_AON_SLPTIMES_CLK_W 32U
664 #define HOSTMCU_AON_SLPTIMES_CLK_M 0xFFFFFFFFU
665 #define HOSTMCU_AON_SLPTIMES_CLK_S 0U
666 
667 
668 /*-----------------------------------REGISTER------------------------------------
669  Register name: SLPTIMEF
670  Offset name: HOSTMCU_AON_O_SLPTIMEF
671  Relative address: 0x40
672  Description: Sleep Time Fast Clock.
673 
674  Register for sleep time on fast clock
675  Default Value: 0x00000000
676 
677  Field: CLK
678  From..to bits: 0...10
679  DefaultValue: 0x0
680  Access type: read-only
681  Description: Sleep time value from last ELP sleep entry (slow clock synced ARM CMD).
682  Fast Clock - Reflects the number of fast clocks from last Slow clock rise until OCP Read.
683  Note, fast counter value is latched upon OCP Read of ELP_SLEEP_TIME_SLOW.
684  Counts up t0 51 microsecond.
685 
686 */
687 #define HOSTMCU_AON_SLPTIMEF_CLK_W 11U
688 #define HOSTMCU_AON_SLPTIMEF_CLK_M 0x000007FFU
689 #define HOSTMCU_AON_SLPTIMEF_CLK_S 0U
690 
691 
692 /*-----------------------------------REGISTER------------------------------------
693  Register name: WUREQ
694  Offset name: HOSTMCU_AON_O_WUREQ
695  Relative address: 0x4C
696  Description: Wake up Request Status
697  Default Value: 0x00000000
698 
699  Field: VAL
700  From..to bits: 0...17
701  DefaultValue: 0x0
702  Access type: read-only
703  Description: Field to show the event request
704 
705  Bit 0 : ELP TMR Wake up request
706  Bit 1 : GPIO wake up src 0
707  Bit 2 : GPIO wake up src 1
708  Bit 3 : doorbell 0
709  Bit 4 : doorbell 1
710  Bit 5 : doorbell 2
711  Bit 6 : doorbell 3
712  Bit 7 : doorbell 4
713  Bit 8 : doorbell 5
714  Bit 9 : doorbell 6
715  Bit 10 : doorbell 7
716  Bit 11 : nab_host_irq
717  Bit 12 : ble_rfc_gpo_8_irq
718  Bit 13 : RTC
719  Bit 14 : DebugSS Csyspwrupreq
720  Bit 15 : DebugSS Force-active
721  Bit 16 : secured_error_irq
722  Bit 17 : core wdt irq
723  Note: GPIO wakeup src 0 is AND of wakeup sources and GPIO wakup src 1 is OR of wakeup sources
724 
725  ENUMs:
726  CLEAR: No event request
727  TMRREQ: ELP timer wakeup request
728  WUSRC0: AND of wakeup sources
729  WUSRC1: OR of wakeup sources
730  DRBL0: Doorbell 0
731  DRBL1: Doorbell 1
732  DRBL2: Doorbell 2
733  DRBL3: Doorbell 3
734  DRBL4: Doorbell 4
735  DRBL5: Doorbell 5
736  DRBL6: Doorbell 6
737  DRBL7: Doorbell 7
738  NAB: NAB host irq
739  BLERFCGPO: BLE RFC GPO 9 irq
740  RTC: RTC
741  DBGPWRUP: Debugss Csyspwrupreq
742  DBGFRCACT: Debugss forecactive
743  SECERR: Secure error irq
744  COREWDT: Core WDT request
745 */
746 #define HOSTMCU_AON_WUREQ_VAL_W 18U
747 #define HOSTMCU_AON_WUREQ_VAL_M 0x0003FFFFU
748 #define HOSTMCU_AON_WUREQ_VAL_S 0U
749 #define HOSTMCU_AON_WUREQ_VAL_CLEAR 0x00000000U
750 #define HOSTMCU_AON_WUREQ_VAL_TMRREQ 0x00000001U
751 #define HOSTMCU_AON_WUREQ_VAL_WUSRC0 0x00000002U
752 #define HOSTMCU_AON_WUREQ_VAL_WUSRC1 0x00000004U
753 #define HOSTMCU_AON_WUREQ_VAL_DRBL0 0x00000008U
754 #define HOSTMCU_AON_WUREQ_VAL_DRBL1 0x00000010U
755 #define HOSTMCU_AON_WUREQ_VAL_DRBL2 0x00000020U
756 #define HOSTMCU_AON_WUREQ_VAL_DRBL3 0x00000040U
757 #define HOSTMCU_AON_WUREQ_VAL_DRBL4 0x00000080U
758 #define HOSTMCU_AON_WUREQ_VAL_DRBL5 0x00000100U
759 #define HOSTMCU_AON_WUREQ_VAL_DRBL6 0x00000200U
760 #define HOSTMCU_AON_WUREQ_VAL_DRBL7 0x00000400U
761 #define HOSTMCU_AON_WUREQ_VAL_NAB 0x00000800U
762 #define HOSTMCU_AON_WUREQ_VAL_BLERFCGPO 0x00001000U
763 #define HOSTMCU_AON_WUREQ_VAL_RTC 0x00002000U
764 #define HOSTMCU_AON_WUREQ_VAL_DBGPWRUP 0x00004000U
765 #define HOSTMCU_AON_WUREQ_VAL_DBGFRCACT 0x00008000U
766 #define HOSTMCU_AON_WUREQ_VAL_SECERR 0x00010000U
767 #define HOSTMCU_AON_WUREQ_VAL_COREWDT 0x00020000U
768 
769 
770 /*-----------------------------------REGISTER------------------------------------
771  Register name: OREFCLK
772  Offset name: HOSTMCU_AON_O_OREFCLK
773  Relative address: 0x50
774  Description: OSPI Reference Clock.
775 
776  Field to select the OSPI reference clock
777  Default Value: 0x00000012
778 
779  Field: SEL
780  From..to bits: 0...0
781  DefaultValue: 0x0
782  Access type: read-write
783  Description: SELECTOR
784 
785  '0' - default host clk div2
786  '1' host clk div 4
787 
788  ENUMs:
789  SEL_0: Host clock div2
790  SEL_1: Host clock div4
791 */
792 #define HOSTMCU_AON_OREFCLK_SEL 0x00000001U
793 #define HOSTMCU_AON_OREFCLK_SEL_M 0x00000001U
794 #define HOSTMCU_AON_OREFCLK_SEL_S 0U
795 #define HOSTMCU_AON_OREFCLK_SEL_SEL_0 0x00000000U
796 #define HOSTMCU_AON_OREFCLK_SEL_SEL_1 0x00000001U
797 
798 
799 /*-----------------------------------REGISTER------------------------------------
800  Register name: WUC
801  Offset name: HOSTMCU_AON_O_WUC
802  Relative address: 0x5C
803  Description: Wake-up Control State.
804 
805  Register for Host wake up state
806  Default Value: 0x00000004
807 
808  Field: STA
809  From..to bits: 0...2
810  DefaultValue: 0x4
811  Access type: read-only
812  Description: Field showing the host wake up state
813 
814  3'b000 - PD_PWR_DN
815  3'b001 - SHARED_UP
816  3'b010 - PD_PWR_UP
817  3'b011 - ACTIVE
818  3'b100 - DEEPSLEEP
819 
820  ENUMs:
821  RD_0: PD power down
822  RD_1: Shared domain up
823  RD_2: PD power up
824  RD_3: Active
825 */
826 #define HOSTMCU_AON_WUC_STA_W 3U
827 #define HOSTMCU_AON_WUC_STA_M 0x00000007U
828 #define HOSTMCU_AON_WUC_STA_S 0U
829 #define HOSTMCU_AON_WUC_STA_RD_0 0x00000000U
830 #define HOSTMCU_AON_WUC_STA_RD_1 0x00000001U
831 #define HOSTMCU_AON_WUC_STA_RD_2 0x00000002U
832 #define HOSTMCU_AON_WUC_STA_RD_3 0x00000003U
833 
834 #endif /* __HW_HOSTMCU_AON_H__*/