CC35xxDriverLibrary
hw_host_mcu.h
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1 /******************************************************************************
2 * Filename: hw_host_mcu.h
3 *
4 * Description: Defines and prototypes for the HOST_MCU peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
11 *
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13 * this list of conditions and the following disclaimer.
14 *
15 * 2) Redistributions in binary form must reproduce the above copyright notice,
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18 *
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22 *
23  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 ******************************************************************************/
36 #ifndef __HW_HOST_MCU_H__
37 #define __HW_HOST_MCU_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the HOST_MCU component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Trace Configuration
45 #define HOST_MCU_O_TRACECFG 0x00000000U
46 
47 //Spare
48 #define HOST_MCU_O_SPARE 0x00000004U
49 
50 //WRR Arbiter Enable Register
51 #define HOST_MCU_O_WRRARB 0x00000008U
52 
53 //WRR Arbiter - Agent 0 Configuration
54 #define HOST_MCU_O_AGENT0CFG 0x00000010U
55 
56 //WRR Arbiter - Agent 1 Configuration
57 #define HOST_MCU_O_AGENT1CFG 0x00000014U
58 
59 //Software Timestamp Interrupt Register
60 #define HOST_MCU_O_SWIRQ 0x00000018U
61 
62 //Non Secure Software Interrupt
63 #define HOST_MCU_O_NSSWIRQ 0x0000001CU
64 
65 //Software Interrupt to CM3
66 #define HOST_MCU_O_SWIRQCM3 0x00000020U
67 
68 //Arbiter Policy
69 #define HOST_MCU_O_ARBPOL 0x00000024U
70 
71 //DEBUGSS Control Register
72 #define HOST_MCU_O_DBGSS 0x00000028U
73 
74 //DEBUGSS Interface Lock
75 #define HOST_MCU_O_DBGSSLCK 0x0000002CU
76 
77 //DEBUGSS Interface Lock Condition Mask
78 #define HOST_MCU_O_DBGSSLM 0x00000030U
79 
80 //DEBUGSS Interface Lock Condition Status
81 #define HOST_MCU_O_DBGSSLS 0x00000034U
82 
83 
84 
85 /*-----------------------------------REGISTER------------------------------------
86  Register name: TRACECFG
87  Offset name: HOST_MCU_O_TRACECFG
88  Relative address: 0x0
89  Description: Trace Configuration.
90 
91  Configuration register for CortexM3-TPIU (TRACE ports i/o unit)
92  Default Value: 0x00000002
93 
94  Field: CLKDIVVAL
95  From..to bits: 0...1
96  DefaultValue: 0x2
97  Access type: read-write
98  Description: Configure TRACE-CLOCK divider value, for (TPIU - input clock)
99  [1] - Divide by 2 - 'tpiu_trace_clk_in' = 40MHz
100  [2] - Divide by 4 - 'tpiu_trace_clk_in' = 20MHz (Default)
101  [0,3] - are not supported (do not use)
102 
103  AFTER setting this value - set [CLKDIVEN] to active this value
104 
105  ENUMs:
106  DIV_2: Divide by 2
107  DIV_4: Divide by 4
108 */
109 #define HOST_MCU_TRACECFG_CLKDIVVAL_W 2U
110 #define HOST_MCU_TRACECFG_CLKDIVVAL_M 0x00000003U
111 #define HOST_MCU_TRACECFG_CLKDIVVAL_S 0U
112 #define HOST_MCU_TRACECFG_CLKDIVVAL_DIV_2 0x00000000U
113 #define HOST_MCU_TRACECFG_CLKDIVVAL_DIV_4 0x00000001U
114 /*
115 
116  Field: CLKDIVEN
117  From..to bits: 8...8
118  DefaultValue: 0x0
119  Access type: write-only
120  Description: Set this register to load [CLKDIVVAL]
121 
122  ENUMs:
123  DIS:
124  EN: Disable
125 */
126 #define HOST_MCU_TRACECFG_CLKDIVEN 0x00000100U
127 #define HOST_MCU_TRACECFG_CLKDIVEN_M 0x00000100U
128 #define HOST_MCU_TRACECFG_CLKDIVEN_S 8U
129 #define HOST_MCU_TRACECFG_CLKDIVEN_DIS 0x00000000U
130 #define HOST_MCU_TRACECFG_CLKDIVEN_EN 0x00000100U
131 
132 
133 /*-----------------------------------REGISTER------------------------------------
134  Register name: SPARE
135  Offset name: HOST_MCU_O_SPARE
136  Relative address: 0x4
137  Description: Spare
138  Default Value: 0x00000000
139 
140  Field: SBITS
141  From..to bits: 0...31
142  DefaultValue: 0x0
143  Access type: read-write
144  Description: Spare
145 
146 */
147 #define HOST_MCU_SPARE_SBITS_W 32U
148 #define HOST_MCU_SPARE_SBITS_M 0xFFFFFFFFU
149 #define HOST_MCU_SPARE_SBITS_S 0U
150 
151 
152 /*-----------------------------------REGISTER------------------------------------
153  Register name: WRRARB
154  Offset name: HOST_MCU_O_WRRARB
155  Relative address: 0x8
156  Description: WRR Arbiter Enable Register
157  Default Value: 0x00000002
158 
159  Field: EN
160  From..to bits: 0...0
161  DefaultValue: 0x0
162  Access type: read-write
163  Description: Field to enable/select the arbitration logic
164  0 - Disabled, use SIE-200 arbitration logic.
165  1 - Enable, use wrapper arbitration logic.
166 
167  ENUMs:
168  DIS: Use SIE-200 arbitration logic
169  EN: Use wrapper arbitration logic
170 */
171 #define HOST_MCU_WRRARB_EN 0x00000001U
172 #define HOST_MCU_WRRARB_EN_M 0x00000001U
173 #define HOST_MCU_WRRARB_EN_S 0U
174 #define HOST_MCU_WRRARB_EN_DIS 0x00000000U
175 #define HOST_MCU_WRRARB_EN_EN 0x00000001U
176 /*
177 
178  Field: POLICY
179  From..to bits: 1...1
180  DefaultValue: 0x1
181  Access type: read-write
182  Description: Field to configure the priority policy
183  0 - Fixed Priority
184  1 - Round Robin (Default)
185 
186  ENUMs:
187  FIXED: Fixed priority
188  ROUNDROBIN: Round Robin (Default)
189 */
190 #define HOST_MCU_WRRARB_POLICY 0x00000002U
191 #define HOST_MCU_WRRARB_POLICY_M 0x00000002U
192 #define HOST_MCU_WRRARB_POLICY_S 1U
193 #define HOST_MCU_WRRARB_POLICY_FIXED 0x00000000U
194 #define HOST_MCU_WRRARB_POLICY_ROUNDROBIN 0x00000002U
195 
196 
197 /*-----------------------------------REGISTER------------------------------------
198  Register name: AGENT0CFG
199  Offset name: HOST_MCU_O_AGENT0CFG
200  Relative address: 0x10
201  Description: WRR Arbiter - Agent 0 Configuration
202  Default Value: 0x00010004
203 
204  Field: NUMOFBLK
205  From..to bits: 0...12
206  DefaultValue: 0x4
207  Access type: read-write
208  Description: Number of words to be served in each arbitration grant.
209  Up to 8,192 words (32KB).
210  Value must be greater then 0.
211 
212 */
213 #define HOST_MCU_AGENT0CFG_NUMOFBLK_W 13U
214 #define HOST_MCU_AGENT0CFG_NUMOFBLK_M 0x00001FFFU
215 #define HOST_MCU_AGENT0CFG_NUMOFBLK_S 0U
216 /*
217 
218  Field: FIXPRI
219  From..to bits: 16...17
220  DefaultValue: 0x1
221  Access type: read-write
222  Description: Field to select the fixed priority level
223  0 - Highest
224  1 - Medium
225  2 - Lowest (default)
226  3 - Not in Use
227 
228  ENUMs:
229  SEL_0: Highest Priority
230  SEL_2: Lowest priority (default)
231  SEL_1: Medium Priority
232 */
233 #define HOST_MCU_AGENT0CFG_FIXPRI_W 2U
234 #define HOST_MCU_AGENT0CFG_FIXPRI_M 0x00030000U
235 #define HOST_MCU_AGENT0CFG_FIXPRI_S 16U
236 #define HOST_MCU_AGENT0CFG_FIXPRI_SEL_0 0x00000000U
237 #define HOST_MCU_AGENT0CFG_FIXPRI_SEL_2 0x00020000U
238 #define HOST_MCU_AGENT0CFG_FIXPRI_SEL_1 0x00010000U
239 /*
240 
241  Field: TRANSDLY
242  From..to bits: 24...28
243  DefaultValue: 0x0
244  Access type: read-write
245  Description: Number of cycle before starting to serve next agent in line.
246  Up to 32 cycles.
247 
248 */
249 #define HOST_MCU_AGENT0CFG_TRANSDLY_W 5U
250 #define HOST_MCU_AGENT0CFG_TRANSDLY_M 0x1F000000U
251 #define HOST_MCU_AGENT0CFG_TRANSDLY_S 24U
252 
253 
254 /*-----------------------------------REGISTER------------------------------------
255  Register name: AGENT1CFG
256  Offset name: HOST_MCU_O_AGENT1CFG
257  Relative address: 0x14
258  Description: WRR Arbiter - Agent 1 Configuration
259  Default Value: 0x00000004
260 
261  Field: NUMOFBLK
262  From..to bits: 0...12
263  DefaultValue: 0x4
264  Access type: read-write
265  Description: Number of words to be served in each arbitration grant.
266  Up to 8,192 words (32KB).
267  Value must be greater then 0.
268 
269 */
270 #define HOST_MCU_AGENT1CFG_NUMOFBLK_W 13U
271 #define HOST_MCU_AGENT1CFG_NUMOFBLK_M 0x00001FFFU
272 #define HOST_MCU_AGENT1CFG_NUMOFBLK_S 0U
273 /*
274 
275  Field: FIXPRI
276  From..to bits: 16...17
277  DefaultValue: 0x0
278  Access type: read-write
279  Description: Field to select the fixed priority level
280  0 - Highest
281  1 - Medium
282  2 - Lowest (default)
283  3 - Not in Use
284 
285  ENUMs:
286  SEL_0: Highest priority
287  SEL_1: Medium priority
288  SEL_2: Lowest priority (default)
289 */
290 #define HOST_MCU_AGENT1CFG_FIXPRI_W 2U
291 #define HOST_MCU_AGENT1CFG_FIXPRI_M 0x00030000U
292 #define HOST_MCU_AGENT1CFG_FIXPRI_S 16U
293 #define HOST_MCU_AGENT1CFG_FIXPRI_SEL_0 0x00000000U
294 #define HOST_MCU_AGENT1CFG_FIXPRI_SEL_1 0x00010000U
295 #define HOST_MCU_AGENT1CFG_FIXPRI_SEL_2 0x00020000U
296 /*
297 
298  Field: TRANSDLY
299  From..to bits: 24...28
300  DefaultValue: 0x0
301  Access type: read-write
302  Description: Number of cycle before starting to serve next agent in line.
303  Up to 32 cycles.
304 
305 */
306 #define HOST_MCU_AGENT1CFG_TRANSDLY_W 5U
307 #define HOST_MCU_AGENT1CFG_TRANSDLY_M 0x1F000000U
308 #define HOST_MCU_AGENT1CFG_TRANSDLY_S 24U
309 
310 
311 /*-----------------------------------REGISTER------------------------------------
312  Register name: SWIRQ
313  Offset name: HOST_MCU_O_SWIRQ
314  Relative address: 0x18
315  Description: Software Timestamp Interrupt Register
316  Default Value: 0x00000000
317 
318  Field: TIMESTAMP
319  From..to bits: 0...15
320  DefaultValue: 0x0
321  Access type: read-write
322  Description: Field to write timestamp for ET bus.
323 
324 */
325 #define HOST_MCU_SWIRQ_TIMESTAMP_W 16U
326 #define HOST_MCU_SWIRQ_TIMESTAMP_M 0x0000FFFFU
327 #define HOST_MCU_SWIRQ_TIMESTAMP_S 0U
328 
329 
330 /*-----------------------------------REGISTER------------------------------------
331  Register name: NSSWIRQ
332  Offset name: HOST_MCU_O_NSSWIRQ
333  Relative address: 0x1C
334  Description: Non Secure Software Interrupt
335  Default Value: 0x00000000
336 
337  Field: EN
338  From..to bits: 0...3
339  DefaultValue: 0x0
340  Access type: read-write
341  Description: Non Secure context of CM33 can use this register to interrupt secure context of CM33.
342 
343 */
344 #define HOST_MCU_NSSWIRQ_EN_W 4U
345 #define HOST_MCU_NSSWIRQ_EN_M 0x0000000FU
346 #define HOST_MCU_NSSWIRQ_EN_S 0U
347 
348 
349 /*-----------------------------------REGISTER------------------------------------
350  Register name: SWIRQCM3
351  Offset name: HOST_MCU_O_SWIRQCM3
352  Relative address: 0x20
353  Description: Software Interrupt to CM3
354  Default Value: 0x00000000
355 
356  Field: EN
357  From..to bits: 0...0
358  DefaultValue: 0x0
359  Access type: read-write
360  Description: Non Secure context of CM33 can use this register to interrupt CM3.
361 
362 */
363 #define HOST_MCU_SWIRQCM3_EN 0x00000001U
364 #define HOST_MCU_SWIRQCM3_EN_M 0x00000001U
365 #define HOST_MCU_SWIRQCM3_EN_S 0U
366 
367 
368 /*-----------------------------------REGISTER------------------------------------
369  Register name: ARBPOL
370  Offset name: HOST_MCU_O_ARBPOL
371  Relative address: 0x24
372  Description: Arbiter Policy.
373 
374  Arbiter Policy for the arbiters(x2) located just before MEMSS Portion A and Portion B
375  Default Value: 0x00000000
376 
377  Field: RNDRBNS0
378  From..to bits: 0...0
379  DefaultValue: 0x0
380  Access type: read-write
381  Description: Field to select the arbitration policy of second arbiter (MEMSS Portion A)
382  1 -> Round Robin is enabled
383  0 -> Fixed priority is enabled
384 
385  ENUMs:
386  FIXED: Fixed priority
387  ROUNDROBIN: Round Robin priority
388 */
389 #define HOST_MCU_ARBPOL_RNDRBNS0 0x00000001U
390 #define HOST_MCU_ARBPOL_RNDRBNS0_M 0x00000001U
391 #define HOST_MCU_ARBPOL_RNDRBNS0_S 0U
392 #define HOST_MCU_ARBPOL_RNDRBNS0_FIXED 0x00000000U
393 #define HOST_MCU_ARBPOL_RNDRBNS0_ROUNDROBIN 0x00000001U
394 /*
395 
396  Field: RNDRBNS1
397  From..to bits: 1...1
398  DefaultValue: 0x0
399  Access type: read-write
400  Description: Field to select the arbitration policy of second arbiter (MEMSS Portion )
401  1 -> Round Robin is enabled
402  0 -> Fixed priority is enabled
403 
404  ENUMs:
405  FIXED: Fixed priority
406  ROUNDROBIN: Round Robin priority
407 */
408 #define HOST_MCU_ARBPOL_RNDRBNS1 0x00000002U
409 #define HOST_MCU_ARBPOL_RNDRBNS1_M 0x00000002U
410 #define HOST_MCU_ARBPOL_RNDRBNS1_S 1U
411 #define HOST_MCU_ARBPOL_RNDRBNS1_FIXED 0x00000000U
412 #define HOST_MCU_ARBPOL_RNDRBNS1_ROUNDROBIN 0x00000002U
413 /*
414 
415  Field: S0PRIM0
416  From..to bits: 2...3
417  DefaultValue: 0x0
418  Access type: read-write
419  Description: This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion A. This field is used to configure the priority of udma/sahb.
420 
421 */
422 #define HOST_MCU_ARBPOL_S0PRIM0_W 2U
423 #define HOST_MCU_ARBPOL_S0PRIM0_M 0x0000000CU
424 #define HOST_MCU_ARBPOL_S0PRIM0_S 2U
425 /*
426 
427  Field: S0PRIM1
428  From..to bits: 4...5
429  DefaultValue: 0x0
430  Access type: read-write
431  Description: This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion A. This field is used to configure the priority of ocp.
432 
433 */
434 #define HOST_MCU_ARBPOL_S0PRIM1_W 2U
435 #define HOST_MCU_ARBPOL_S0PRIM1_M 0x00000030U
436 #define HOST_MCU_ARBPOL_S0PRIM1_S 4U
437 /*
438 
439  Field: S1PRIM0
440  From..to bits: 6...7
441  DefaultValue: 0x0
442  Access type: read-write
443  Description: This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion B. This field is used to configure the priority of udma/sahb.
444 
445 */
446 #define HOST_MCU_ARBPOL_S1PRIM0_W 2U
447 #define HOST_MCU_ARBPOL_S1PRIM0_M 0x000000C0U
448 #define HOST_MCU_ARBPOL_S1PRIM0_S 6U
449 /*
450 
451  Field: S1PRIM1
452  From..to bits: 8...9
453  DefaultValue: 0x0
454  Access type: read-write
455  Description: This bit field takes affect when Fixed Priority is selected for the arbiter before MEMSS Portion B. This field is used to configure the priority of ocp.
456 
457 */
458 #define HOST_MCU_ARBPOL_S1PRIM1_W 2U
459 #define HOST_MCU_ARBPOL_S1PRIM1_M 0x00000300U
460 #define HOST_MCU_ARBPOL_S1PRIM1_S 8U
461 
462 
463 /*-----------------------------------REGISTER------------------------------------
464  Register name: DBGSS
465  Offset name: HOST_MCU_O_DBGSS
466  Relative address: 0x28
467  Description: DEBUGSS Control Register.
468  Default Value: 0x00000000
469 
470  Field: EN
471  From..to bits: 0...0
472  DefaultValue: 0x0
473  Access type: read-write
474  Description: Non Secure context of CM33 can use this register to interrupt CM3.
475 
476 */
477 #define HOST_MCU_DBGSS_EN 0x00000001U
478 #define HOST_MCU_DBGSS_EN_M 0x00000001U
479 #define HOST_MCU_DBGSS_EN_S 0U
480 
481 
482 /*-----------------------------------REGISTER------------------------------------
483  Register name: DBGSSLCK
484  Offset name: HOST_MCU_O_DBGSSLCK
485  Relative address: 0x2C
486  Description: DEBUGSS Interface Lock.
487  Default Value: 0x00000000
488 
489  Field: LOCK
490  From..to bits: 0...0
491  DefaultValue: 0x0
492  Access type: read-write
493  Description: The method: Obtain lock by Read. Following are all s/w operation possibilities:
494  When reading '1' - lock is obtained. (i.e. no debugss request was active during the rd transaction).
495  When reading '0' - lock is not obtained. Try to read again. (i.e. at least debugss request event was active during the rd transaction).
496  when writing '1' - lock will be obtained regardless to debugss request status
497  when writing '0' - lock will be released.
498 
499  Type: Write/Read-Clear
500 
501 */
502 #define HOST_MCU_DBGSSLCK_LOCK 0x00000001U
503 #define HOST_MCU_DBGSSLCK_LOCK_M 0x00000001U
504 #define HOST_MCU_DBGSSLCK_LOCK_S 0U
505 
506 
507 /*-----------------------------------REGISTER------------------------------------
508  Register name: DBGSSLM
509  Offset name: HOST_MCU_O_DBGSSLM
510  Relative address: 0x30
511  Description: DEBUGSS Interface Lock Condition Mask
512  Default Value: 0x00000000
513 
514  Field: MASK
515  From..to bits: 1...1
516  DefaultValue: 0x0
517  Access type: read-write
518  Description: Masks Debugss Force-active
519 
520  Set 1 - Mask request during lock check.
521  Set 0 - O.W.
522 
523  ENUMs:
524  SET_0: O.W
525  SET_1: Mask request during lock check
526 */
527 #define HOST_MCU_DBGSSLM_MASK 0x00000002U
528 #define HOST_MCU_DBGSSLM_MASK_M 0x00000002U
529 #define HOST_MCU_DBGSSLM_MASK_S 1U
530 #define HOST_MCU_DBGSSLM_MASK_SET_0 0x00000000U
531 #define HOST_MCU_DBGSSLM_MASK_SET_1 0x00000002U
532 
533 
534 /*-----------------------------------REGISTER------------------------------------
535  Register name: DBGSSLS
536  Offset name: HOST_MCU_O_DBGSSLS
537  Relative address: 0x34
538  Description: DEBUGSS Interface Lock Condition Status
539  Default Value: 0x00000000
540 
541  Field: CSYSPWRREQ
542  From..to bits: 0...0
543  DefaultValue: 0x0
544  Access type: read-only
545  Description: DEBUGSS HOST C SYS Power Request
546 
547  ENUMs:
548  CLR: Not in use
549  SET: Debugss host c sys power requested
550 */
551 #define HOST_MCU_DBGSSLS_CSYSPWRREQ 0x00000001U
552 #define HOST_MCU_DBGSSLS_CSYSPWRREQ_M 0x00000001U
553 #define HOST_MCU_DBGSSLS_CSYSPWRREQ_S 0U
554 #define HOST_MCU_DBGSSLS_CSYSPWRREQ_CLR 0x00000000U
555 #define HOST_MCU_DBGSSLS_CSYSPWRREQ_SET 0x00000001U
556 /*
557 
558  Field: FRCACT
559  From..to bits: 1...1
560  DefaultValue: 0x0
561  Access type: read-only
562  Description: DEBUGSS HOST Force Active
563 
564  ENUMs:
565  CLR: Not in use
566  SET: Debugss host force active is set
567 */
568 #define HOST_MCU_DBGSSLS_FRCACT 0x00000002U
569 #define HOST_MCU_DBGSSLS_FRCACT_M 0x00000002U
570 #define HOST_MCU_DBGSSLS_FRCACT_S 1U
571 #define HOST_MCU_DBGSSLS_FRCACT_CLR 0x00000000U
572 #define HOST_MCU_DBGSSLS_FRCACT_SET 0x00000002U
573 
574 #endif /* __HW_HOST_MCU_H__*/