CC35xxDriverLibrary
hw_gptimer.h
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1 /******************************************************************************
2 * Filename: hw_gptimer.h
3 *
4 * Description: Defines and prototypes for the GPTIMER peripheral.
5 *
6 * Copyright (c) 2023, Texas Instruments Incorporated
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36 #ifndef __HW_GPTIMER_H__
37 #define __HW_GPTIMER_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the GPTIMER component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //Description Register
45 #define GPTIMER_O_DESC 0x00000000U
46 
47 //Description Extended
48 #define GPTIMER_O_DESCEX 0x00000004U
49 
50 //Start Configuration
51 #define GPTIMER_O_STARTCFG 0x00000008U
52 
53 //Timer Control
54 #define GPTIMER_O_CTL 0x0000000CU
55 
56 //Output Control
57 #define GPTIMER_O_OUTCTL 0x00000010U
58 
59 //Counter
60 #define GPTIMER_O_CNTR 0x00000014U
61 
62 //Clock Prescaler Configuration
63 #define GPTIMER_O_PRECFG 0x00000018U
64 
65 //Prescaler Event
66 #define GPTIMER_O_PREEVENT 0x0000001CU
67 
68 //Channel Input Filter
69 #define GPTIMER_O_CHFILT 0x00000020U
70 
71 //Fault
72 #define GPTIMER_O_FAULT 0x00000024U
73 
74 //Park
75 #define GPTIMER_O_PARK 0x00000028U
76 
77 //Dead Band Delay
78 #define GPTIMER_O_DBDLY 0x0000002CU
79 
80 //Dead Band Control
81 #define GPTIMER_O_DBCTL 0x00000030U
82 
83 //Quadrature Decoder Status
84 #define GPTIMER_O_QDECSTAT 0x00000034U
85 
86 //IR Generation
87 #define GPTIMER_O_IRGEN 0x00000038U
88 
89 //Direct Memory Access
90 #define GPTIMER_O_DMA 0x0000003CU
91 
92 //Direct Memory Access
93 #define GPTIMER_O_DMARW 0x00000040U
94 
95 //ADC Trigger
96 #define GPTIMER_O_ADCTRG 0x00000044U
97 
98 //IO Controller
99 #define GPTIMER_O_IOCTL 0x00000048U
100 
101 //Interrupt mask
102 #define GPTIMER_O_IMASK 0x00000068U
103 
104 //Raw interrupt status
105 #define GPTIMER_O_RIS 0x0000006CU
106 
107 //Masked interrupt status
108 #define GPTIMER_O_MIS 0x00000070U
109 
110 //Interrupt set register
111 #define GPTIMER_O_ISET 0x00000074U
112 
113 //Interrupt clear register
114 #define GPTIMER_O_ICLR 0x00000078U
115 
116 //Interrupt mask set register
117 #define GPTIMER_O_IMSET 0x0000007CU
118 
119 //Interrupt mask clear register
120 #define GPTIMER_O_IMCLR 0x00000080U
121 
122 //Debug control
123 #define GPTIMER_O_EMU 0x00000084U
124 
125 //Channel 0 Configuration
126 #define GPTIMER_O_C0CFG 0x000000C0U
127 
128 //Channel 1 Configuration
129 #define GPTIMER_O_C1CFG 0x000000C4U
130 
131 //Channel 2 Configuration
132 #define GPTIMER_O_C2CFG 0x000000C8U
133 
134 //Channel 3 Configuration
135 #define GPTIMER_O_C3CFG 0x000000CCU
136 
137 //Pipeline Target
138 #define GPTIMER_O_PTGT 0x000000FCU
139 
140 //Pipeline Channel 0 Capture Compare
141 #define GPTIMER_O_PC0CC 0x00000100U
142 
143 //Pipeline Channel 1 Capture Compare
144 #define GPTIMER_O_PC1CC 0x00000104U
145 
146 //Pipeline Channel 2 Capture Compare
147 #define GPTIMER_O_PC2CC 0x00000108U
148 
149 //Pipeline Channel 3 Capture Compare
150 #define GPTIMER_O_PC3CC 0x0000010CU
151 
152 //Target
153 #define GPTIMER_O_TGT 0x0000013CU
154 
155 //Channel 0 Capture Compare
156 #define GPTIMER_O_C0CC 0x00000140U
157 
158 //Channel 1 Capture Compare
159 #define GPTIMER_O_C1CC 0x00000144U
160 
161 //Channel 2 Capture Compare
162 #define GPTIMER_O_C2CC 0x00000148U
163 
164 //Channel 3 Capture Compare
165 #define GPTIMER_O_C3CC 0x0000014CU
166 
167 //Pipeline Target No Clear
168 #define GPTIMER_O_PTGTNC 0x0000017CU
169 
170 //Pipeline Channel 0 Capture Compare No Clear
171 #define GPTIMER_O_PC0CCNC 0x00000180U
172 
173 //Pipeline Channel 1 Capture Compare No Clear
174 #define GPTIMER_O_PC1CCNC 0x00000184U
175 
176 //Pipeline Channel 2 Capture Compare No Clear
177 #define GPTIMER_O_PC2CCNC 0x00000188U
178 
179 //Pipeline Channel 3 Capture Compare No Clear
180 #define GPTIMER_O_PC3CCNC 0x0000018CU
181 
182 //Target No Clear
183 #define GPTIMER_O_TGTNC 0x000001BCU
184 
185 //Channel 0 Capture Compare No Clear
186 #define GPTIMER_O_C0CCNC 0x000001C0U
187 
188 //Channel 1 Capture Compare No Clear
189 #define GPTIMER_O_C1CCNC 0x000001C4U
190 
191 //Channel 2 Capture Compare No Clear
192 #define GPTIMER_O_C2CCNC 0x000001C8U
193 
194 //Channel 3 Capture Compare No Clear
195 #define GPTIMER_O_C3CCNC 0x000001CCU
196 
197 //Clock Enable Register
198 #define GPTIMER_O_CLKCFG 0x00001000U
199 
200 
201 
202 /*-----------------------------------REGISTER------------------------------------
203  Register name: DESC
204  Offset name: GPTIMER_O_DESC
205  Relative address: 0x0
206  Description: Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
207  Default Value: 0xDE491000
208 
209  Field: MINREV
210  From..to bits: 0...3
211  DefaultValue: 0x0
212  Access type: read-only
213  Description: Minor revision of IP.
214 
215 */
216 #define GPTIMER_DESC_MINREV_W 4U
217 #define GPTIMER_DESC_MINREV_M 0x0000000FU
218 #define GPTIMER_DESC_MINREV_S 0U
219 /*
220 
221  Field: MAJREV
222  From..to bits: 4...7
223  DefaultValue: 0x0
224  Access type: read-only
225  Description: Major revision of IP.
226 
227 */
228 #define GPTIMER_DESC_MAJREV_W 4U
229 #define GPTIMER_DESC_MAJREV_M 0x000000F0U
230 #define GPTIMER_DESC_MAJREV_S 4U
231 /*
232 
233  Field: INSTIDX
234  From..to bits: 8...11
235  DefaultValue: 0x0
236  Access type: read-only
237  Description: IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number.
238 
239 */
240 #define GPTIMER_DESC_INSTIDX_W 4U
241 #define GPTIMER_DESC_INSTIDX_M 0x00000F00U
242 #define GPTIMER_DESC_INSTIDX_S 8U
243 /*
244 
245  Field: STDIPOFF
246  From..to bits: 12...15
247  DefaultValue: 0x1
248  Access type: read-only
249  Description: Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
250 
251  0: Standard IP MMRs do not exist
252 
253  0x1-0xF: Standard IP MMRs begin at offset of (64*[STDIPOFF] from the base IP address)
254 
255 */
256 #define GPTIMER_DESC_STDIPOFF_W 4U
257 #define GPTIMER_DESC_STDIPOFF_M 0x0000F000U
258 #define GPTIMER_DESC_STDIPOFF_S 12U
259 /*
260 
261  Field: MODID
262  From..to bits: 16...31
263  DefaultValue: 0xDE49
264  Access type: read-only
265  Description: Module identifier used to uniquely identify this IP.
266 
267 */
268 #define GPTIMER_DESC_MODID_W 16U
269 #define GPTIMER_DESC_MODID_M 0xFFFF0000U
270 #define GPTIMER_DESC_MODID_S 16U
271 
272 
273 /*-----------------------------------REGISTER------------------------------------
274  Register name: DESCEX
275  Offset name: GPTIMER_O_DESCEX
276  Relative address: 0x4
277  Description: Description Extended
278 
279  This register describes the parameters of the LGPT.
280  Default Value: 0x00000000
281 
282  Field: NCH
283  From..to bits: 0...3
284  DefaultValue: 0x0
285  Access type: read-only
286  Description: Number of channels.
287 
288 */
289 #define GPTIMER_DESCEX_NCH_W 4U
290 #define GPTIMER_DESCEX_NCH_M 0x0000000FU
291 #define GPTIMER_DESCEX_NCH_S 0U
292 /*
293 
294  Field: CNTRW
295  From..to bits: 4...5
296  DefaultValue: 0x0
297  Access type: read-only
298  Description: Counter bit-width.
299  The maximum counter value is equal to 2^[CNTRW]-1.
300 
301  ENUMs:
302  CNTR16: 16-bit counter.
303  CNTR24: 24-bit counter.
304  CNTR32: 32-bit counter.
305  RESERVED: RESERVED
306 */
307 #define GPTIMER_DESCEX_CNTRW_W 2U
308 #define GPTIMER_DESCEX_CNTRW_M 0x00000030U
309 #define GPTIMER_DESCEX_CNTRW_S 4U
310 #define GPTIMER_DESCEX_CNTRW_CNTR16 0x00000000U
311 #define GPTIMER_DESCEX_CNTRW_CNTR24 0x00000010U
312 #define GPTIMER_DESCEX_CNTRW_CNTR32 0x00000020U
313 #define GPTIMER_DESCEX_CNTRW_RESERVED 0x00000030U
314 /*
315 
316  Field: HINT
317  From..to bits: 6...6
318  DefaultValue: 0x0
319  Access type: read-only
320  Description: Has interrupt output and logic.
321 
322 */
323 #define GPTIMER_DESCEX_HINT 0x00000040U
324 #define GPTIMER_DESCEX_HINT_M 0x00000040U
325 #define GPTIMER_DESCEX_HINT_S 6U
326 /*
327 
328  Field: HDMA
329  From..to bits: 7...7
330  DefaultValue: 0x0
331  Access type: read-only
332  Description: Has uDMA output and logic.
333 
334 */
335 #define GPTIMER_DESCEX_HDMA 0x00000080U
336 #define GPTIMER_DESCEX_HDMA_M 0x00000080U
337 #define GPTIMER_DESCEX_HDMA_S 7U
338 /*
339 
340  Field: CIFS
341  From..to bits: 8...11
342  DefaultValue: 0x0
343  Access type: read-only
344  Description: Channel input filter size. The prevailing state filter can maximum be configured to 2^[CIFS]-1.
345 
346 */
347 #define GPTIMER_DESCEX_CIFS_W 4U
348 #define GPTIMER_DESCEX_CIFS_M 0x00000F00U
349 #define GPTIMER_DESCEX_CIFS_S 8U
350 /*
351 
352  Field: HCIF
353  From..to bits: 12...12
354  DefaultValue: 0x0
355  Access type: read-only
356  Description: Has channel input filter.
357 
358 */
359 #define GPTIMER_DESCEX_HCIF 0x00001000U
360 #define GPTIMER_DESCEX_HCIF_M 0x00001000U
361 #define GPTIMER_DESCEX_HCIF_S 12U
362 /*
363 
364  Field: HQDEC
365  From..to bits: 13...13
366  DefaultValue: 0x0
367  Access type: read-only
368  Description: Has Quadrature Decoder.
369 
370 */
371 #define GPTIMER_DESCEX_HQDEC 0x00002000U
372 #define GPTIMER_DESCEX_HQDEC_M 0x00002000U
373 #define GPTIMER_DESCEX_HQDEC_S 13U
374 /*
375 
376  Field: PREW
377  From..to bits: 14...17
378  DefaultValue: 0x0
379  Access type: read-only
380  Description: Prescaler width. The prescaler can maximum be configured to 2^[PREW]-1.
381 
382 */
383 #define GPTIMER_DESCEX_PREW_W 4U
384 #define GPTIMER_DESCEX_PREW_M 0x0003C000U
385 #define GPTIMER_DESCEX_PREW_S 14U
386 /*
387 
388  Field: HDBF
389  From..to bits: 18...18
390  DefaultValue: 0x0
391  Access type: read-only
392  Description: Has Dead-Band, Fault, and Park logic.
393 
394 */
395 #define GPTIMER_DESCEX_HDBF 0x00040000U
396 #define GPTIMER_DESCEX_HDBF_M 0x00040000U
397 #define GPTIMER_DESCEX_HDBF_S 18U
398 /*
399 
400  Field: HIR
401  From..to bits: 19...19
402  DefaultValue: 0x0
403  Access type: read-only
404  Description: Has IR logic.
405 
406 */
407 #define GPTIMER_DESCEX_HIR 0x00080000U
408 #define GPTIMER_DESCEX_HIR_M 0x00080000U
409 #define GPTIMER_DESCEX_HIR_S 19U
410 
411 
412 /*-----------------------------------REGISTER------------------------------------
413  Register name: STARTCFG
414  Offset name: GPTIMER_O_STARTCFG
415  Relative address: 0x8
416  Description: Start Configuration
417 
418  This register is only for when [CTL.MODE] is configured to one of the SYNC modes.
419  This register defines when this LGPT starts.
420  Default Value: 0x00000000
421 
422  Field: LGPT0
423  From..to bits: 0...1
424  DefaultValue: 0x0
425  Access type: read-write
426  Description: LGPT start
427 
428  ENUMs:
429  EV_SYNC: LGPT starts when synchronized event input is high. Configured here [EVTSVT:LGPTSYNCSEL].
430 */
431 #define GPTIMER_STARTCFG_LGPT0_W 2U
432 #define GPTIMER_STARTCFG_LGPT0_M 0x00000003U
433 #define GPTIMER_STARTCFG_LGPT0_S 0U
434 #define GPTIMER_STARTCFG_LGPT0_EV_SYNC 0x00000000U
435 
436 
437 /*-----------------------------------REGISTER------------------------------------
438  Register name: CTL
439  Offset name: GPTIMER_O_CTL
440  Relative address: 0xC
441  Description: Timer Control
442  Default Value: 0x00000000
443 
444  Field: MODE
445  From..to bits: 0...2
446  DefaultValue: 0x0
447  Access type: read-write
448  Description: Timer mode control
449 
450  The [CNTR.*] restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER.
451 
452  When writing MODE all internally queued updates to the channels and [TGT.*] is cleared.
453 
454  When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example [C0CFG.*].
455 
456  ENUMs:
457  DIS: Disable timer. Updates to counter, channels, and events stop.
458  UP_ONCE: Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS.
459  UP_PER: Count up periodically. The timer increments from 0 to target value, repeatedly.
460 
461  Period = (target value + 1) * timer clock period
462  UPDWN_PER: Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly.
463 
464  Period = (target value * 2) * timer clock period
465  QDEC: The timer functions as a quadrature decoder. IOC input 0, IOC input 1 and IOC input 2 are used respectively as PHA, PHB and IDX inputs. IDX can be turned off by setting [C2CFG.EDGE] = NONE.
466  The timer clock frequency sets the sample rate of the QDEC logic. This frequency can be configured in [PRECFG.*].
467  SYNC_UP_ONCE: Start counting up once synchronous to another LGPT, selected within [STARTCFG.*]. The timer is started by setting [CTL.MODE] = UP_ONCE automatically.
468  It then functions as a normal timer in [CTL.MODE] = UP_ONCE, incrementing from 0 to target value, then stops and sets MODE to DIS.
469  SYNC_UP_PER: Start counting up periodically synchronous to another LGPT, selected within [STARTCFG.*]. The timer is started by setting [CTL.MODE] = UP_PER automatically.
470  It then operates as a normal timer in [CTL.MODE] = UP_PER, incrementing from 0 to target value, repeatedly.
471 
472  Period = (target value * 2) * timer clock period
473  SYNC_UPDWN_PER: Start counting up and down periodically synchronous to another LGPT, selected within [STARTCFG.*]. The timer is started by setting [CTL.MODE] = UPDWN_PER automatically.
474  It then operates as a normal timer in [CTL.MODE] = UPDWN_PER, counting from 0 to target value and back to 0, repeatedly.
475 
476  Period = (target value * 2) * timer clock period
477 */
478 #define GPTIMER_CTL_MODE_W 3U
479 #define GPTIMER_CTL_MODE_M 0x00000007U
480 #define GPTIMER_CTL_MODE_S 0U
481 #define GPTIMER_CTL_MODE_DIS 0x00000000U
482 #define GPTIMER_CTL_MODE_UP_ONCE 0x00000001U
483 #define GPTIMER_CTL_MODE_UP_PER 0x00000002U
484 #define GPTIMER_CTL_MODE_UPDWN_PER 0x00000003U
485 #define GPTIMER_CTL_MODE_QDEC 0x00000004U
486 #define GPTIMER_CTL_MODE_SYNC_UP_ONCE 0x00000005U
487 #define GPTIMER_CTL_MODE_SYNC_UP_PER 0x00000006U
488 #define GPTIMER_CTL_MODE_SYNC_UPDWN_PER 0x00000007U
489 /*
490 
491  Field: CMPDIR
492  From..to bits: 3...4
493  DefaultValue: 0x0
494  Access type: read-write
495  Description: Compare direction.
496 
497  This bit field controls the direction the counter must have in order to set the [RIS.*] compare interrupts.
498 
499  ENUMs:
500  BOTH: Compare [RIS.*] fields are set on up count and down count.
501  UP: Compare [RIS.*] fields are only set on up count.
502  DOWN: Compare [RIS.*] fields are only set on down count.
503  RESERVED: RESERVED
504 */
505 #define GPTIMER_CTL_CMPDIR_W 2U
506 #define GPTIMER_CTL_CMPDIR_M 0x00000018U
507 #define GPTIMER_CTL_CMPDIR_S 3U
508 #define GPTIMER_CTL_CMPDIR_BOTH 0x00000000U
509 #define GPTIMER_CTL_CMPDIR_UP 0x00000008U
510 #define GPTIMER_CTL_CMPDIR_DOWN 0x00000010U
511 #define GPTIMER_CTL_CMPDIR_RESERVED 0x00000018U
512 /*
513 
514  Field: INTP
515  From..to bits: 5...5
516  DefaultValue: 0x0
517  Access type: read-write
518  Description: Interrupt Phase.
519  This bit field controls when the [RIS.TGT] and [RIS.ZERO] interrupts are set.
520 
521  ENUMs:
522  EARLY: [RIS.TGT] and [RIS.ZERO] are set one system clock cycle after [CNTR.*] = TARGET/ZERO.
523  LATE: [RIS.TGT] and [RIS.ZERO] are set one timer clock cycle after [CNTR.*] = TARGET/ZERO.
524 */
525 #define GPTIMER_CTL_INTP 0x00000020U
526 #define GPTIMER_CTL_INTP_M 0x00000020U
527 #define GPTIMER_CTL_INTP_S 5U
528 #define GPTIMER_CTL_INTP_EARLY 0x00000000U
529 #define GPTIMER_CTL_INTP_LATE 0x00000020U
530 /*
531 
532  Field: C0RST
533  From..to bits: 8...8
534  DefaultValue: 0x0
535  Access type: write-only
536  Description: Channel 0 reset.
537 
538  ENUMs:
539  NOEFF: No effect.
540  RST: Reset [C0CC], [PC0CC], and [C0CFG].
541 */
542 #define GPTIMER_CTL_C0RST 0x00000100U
543 #define GPTIMER_CTL_C0RST_M 0x00000100U
544 #define GPTIMER_CTL_C0RST_S 8U
545 #define GPTIMER_CTL_C0RST_NOEFF 0x00000000U
546 #define GPTIMER_CTL_C0RST_RST 0x00000100U
547 /*
548 
549  Field: C1RST
550  From..to bits: 9...9
551  DefaultValue: 0x0
552  Access type: write-only
553  Description: Channel 1 reset.
554 
555  ENUMs:
556  NOEFF: No effect.
557  RST: Reset [C1CC.*], [PC1CC.*], and [C1CFG.*].
558 */
559 #define GPTIMER_CTL_C1RST 0x00000200U
560 #define GPTIMER_CTL_C1RST_M 0x00000200U
561 #define GPTIMER_CTL_C1RST_S 9U
562 #define GPTIMER_CTL_C1RST_NOEFF 0x00000000U
563 #define GPTIMER_CTL_C1RST_RST 0x00000200U
564 /*
565 
566  Field: C2RST
567  From..to bits: 10...10
568  DefaultValue: 0x0
569  Access type: write-only
570  Description: Channel 2 reset.
571 
572  ENUMs:
573  NOEFF: No effect.
574  RST: Reset [C2CC.*], [PC2CC.*], and [C2CFG.*].
575 */
576 #define GPTIMER_CTL_C2RST 0x00000400U
577 #define GPTIMER_CTL_C2RST_M 0x00000400U
578 #define GPTIMER_CTL_C2RST_S 10U
579 #define GPTIMER_CTL_C2RST_NOEFF 0x00000000U
580 #define GPTIMER_CTL_C2RST_RST 0x00000400U
581 /*
582 
583  Field: C3RST
584  From..to bits: 11...11
585  DefaultValue: 0x0
586  Access type: write-only
587  Description: Channel 3 reset.
588 
589  ENUMs:
590  NOEFF: No effect.
591  RST: Reset [C3CC.*], [PC3CC.*], and [C3CFG.*].
592 */
593 #define GPTIMER_CTL_C3RST 0x00000800U
594 #define GPTIMER_CTL_C3RST_M 0x00000800U
595 #define GPTIMER_CTL_C3RST_S 11U
596 #define GPTIMER_CTL_C3RST_NOEFF 0x00000000U
597 #define GPTIMER_CTL_C3RST_RST 0x00000800U
598 
599 
600 /*-----------------------------------REGISTER------------------------------------
601  Register name: OUTCTL
602  Offset name: GPTIMER_O_OUTCTL
603  Relative address: 0x10
604  Description: Output Control
605 
606  Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected.
607 
608  An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time.
609 
610  All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an additional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see [IOCTL.*].
611  Default Value: 0x00000000
612 
613  Field: CLROUT0
614  From..to bits: 0...0
615  DefaultValue: 0x0
616  Access type: write-only
617  Description: Clear output 0.
618 
619  Write 1 to clear output 0.
620 
621 */
622 #define GPTIMER_OUTCTL_CLROUT0 0x00000001U
623 #define GPTIMER_OUTCTL_CLROUT0_M 0x00000001U
624 #define GPTIMER_OUTCTL_CLROUT0_S 0U
625 /*
626 
627  Field: SETOUT0
628  From..to bits: 1...1
629  DefaultValue: 0x0
630  Access type: write-only
631  Description: Set output 0.
632 
633  Write 1 to set output 0.
634 
635 */
636 #define GPTIMER_OUTCTL_SETOUT0 0x00000002U
637 #define GPTIMER_OUTCTL_SETOUT0_M 0x00000002U
638 #define GPTIMER_OUTCTL_SETOUT0_S 1U
639 /*
640 
641  Field: CLROUT1
642  From..to bits: 2...2
643  DefaultValue: 0x0
644  Access type: write-only
645  Description: Clear output 1.
646 
647  Write 1 to clear output 1.
648 
649 */
650 #define GPTIMER_OUTCTL_CLROUT1 0x00000004U
651 #define GPTIMER_OUTCTL_CLROUT1_M 0x00000004U
652 #define GPTIMER_OUTCTL_CLROUT1_S 2U
653 /*
654 
655  Field: SETOUT1
656  From..to bits: 3...3
657  DefaultValue: 0x0
658  Access type: write-only
659  Description: Set output 1.
660 
661  Write 1 to set output 1.
662 
663 */
664 #define GPTIMER_OUTCTL_SETOUT1 0x00000008U
665 #define GPTIMER_OUTCTL_SETOUT1_M 0x00000008U
666 #define GPTIMER_OUTCTL_SETOUT1_S 3U
667 /*
668 
669  Field: CLROUT2
670  From..to bits: 4...4
671  DefaultValue: 0x0
672  Access type: write-only
673  Description: Clear output 2.
674 
675  Write 1 to clear output 2.
676 
677 */
678 #define GPTIMER_OUTCTL_CLROUT2 0x00000010U
679 #define GPTIMER_OUTCTL_CLROUT2_M 0x00000010U
680 #define GPTIMER_OUTCTL_CLROUT2_S 4U
681 /*
682 
683  Field: SETOUT2
684  From..to bits: 5...5
685  DefaultValue: 0x0
686  Access type: write-only
687  Description: Set output 2.
688 
689  Write 1 to set output 2.
690 
691 */
692 #define GPTIMER_OUTCTL_SETOUT2 0x00000020U
693 #define GPTIMER_OUTCTL_SETOUT2_M 0x00000020U
694 #define GPTIMER_OUTCTL_SETOUT2_S 5U
695 /*
696 
697  Field: CLROUT3
698  From..to bits: 6...6
699  DefaultValue: 0x0
700  Access type: write-only
701  Description: Clear output 3.
702 
703  Write 1 to clear output 3.
704 
705 */
706 #define GPTIMER_OUTCTL_CLROUT3 0x00000040U
707 #define GPTIMER_OUTCTL_CLROUT3_M 0x00000040U
708 #define GPTIMER_OUTCTL_CLROUT3_S 6U
709 /*
710 
711  Field: SETOUT3
712  From..to bits: 7...7
713  DefaultValue: 0x0
714  Access type: write-only
715  Description: Set output 3.
716 
717  Write 1 to set output 3.
718 
719 */
720 #define GPTIMER_OUTCTL_SETOUT3 0x00000080U
721 #define GPTIMER_OUTCTL_SETOUT3_M 0x00000080U
722 #define GPTIMER_OUTCTL_SETOUT3_S 7U
723 
724 
725 /*-----------------------------------REGISTER------------------------------------
726  Register name: CNTR
727  Offset name: GPTIMER_O_CNTR
728  Relative address: 0x14
729  Description: Counter
730  The counter of this timer. After [CTL.MODE] is set the counter updates at the rate specified in [PRECFG.*].
731  Default Value: 0x00000000
732 
733  Field: VAL
734  From..to bits: 0...31
735  DefaultValue: 0x0
736  Access type: read-write
737  Description: Current counter value.
738  If [CTL.MODE] = QDEC this can be used to set the initial counter value during QDEC.
739 
740 */
741 #define GPTIMER_CNTR_VAL_W 32U
742 #define GPTIMER_CNTR_VAL_M 0xFFFFFFFFU
743 #define GPTIMER_CNTR_VAL_S 0U
744 
745 
746 /*-----------------------------------REGISTER------------------------------------
747  Register name: PRECFG
748  Offset name: GPTIMER_O_PRECFG
749  Relative address: 0x18
750  Description: Clock Prescaler Configuration
751 
752  This register is used to set the timer clock period. The prescaler is a counter which counts down from the value [TICKDIV]. When the prescaler counter reaches zero, [CNTR.*] is updated. The field [TICKDIV] effectively divides the prescaler tick source. The timer clock frequency can be calculated as [TICKSRC]/([TICKDIV]+1).
753  Default Value: 0x00000000
754 
755  Field: TICKSRC
756  From..to bits: 0...1
757  DefaultValue: 0x0
758  Access type: read-write
759  Description: Prescaler tick source.
760 
761  [TICKSRC] determines the source which decrements the prescaler.
762 
763  ENUMs:
764  CLK: Prescaler is updated at the system clock.
765  RISE_TICK: Prescaler is updated at the rising edge of TICKEN.
766  FALL_TICK: Prescaler is updated at the falling edge of TICKEN.
767  BOTH_TICK: Prescaler is updated at both edges of TICKEN.
768 */
769 #define GPTIMER_PRECFG_TICKSRC_W 2U
770 #define GPTIMER_PRECFG_TICKSRC_M 0x00000003U
771 #define GPTIMER_PRECFG_TICKSRC_S 0U
772 #define GPTIMER_PRECFG_TICKSRC_CLK 0x00000000U
773 #define GPTIMER_PRECFG_TICKSRC_RISE_TICK 0x00000001U
774 #define GPTIMER_PRECFG_TICKSRC_FALL_TICK 0x00000002U
775 #define GPTIMER_PRECFG_TICKSRC_BOTH_TICK 0x00000003U
776 /*
777 
778  Field: TICKDIV
779  From..to bits: 8...15
780  DefaultValue: 0x0
781  Access type: read-write
782  Description: Tick division.
783 
784  [TICKDIV] determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by [TICKSRC] divided by ([TICKDIV] + 1). This inverse is the timer clock period.
785 
786  0x00: Divide by 1.
787  0x01: Divide by 2.
788  ...
789  0xFF: Divide by 256.
790 
791 */
792 #define GPTIMER_PRECFG_TICKDIV_W 8U
793 #define GPTIMER_PRECFG_TICKDIV_M 0x0000FF00U
794 #define GPTIMER_PRECFG_TICKDIV_S 8U
795 
796 
797 /*-----------------------------------REGISTER------------------------------------
798  Register name: PREEVENT
799  Offset name: GPTIMER_O_PREEVENT
800  Relative address: 0x1C
801  Description: Prescaler Event
802 
803  This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC.
804  Default Value: 0x00000000
805 
806  Field: VAL
807  From..to bits: 0...7
808  DefaultValue: 0x0
809  Access type: read-write
810  Description: Sets the HIGH time of the prescaler event output.
811 
812  Event goes high when the prescaler counter equals [VAL]. Event goes low when prescaler counter is 0.
813 
814  Note:
815  - Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC.
816  - If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer.
817 
818 */
819 #define GPTIMER_PREEVENT_VAL_W 8U
820 #define GPTIMER_PREEVENT_VAL_M 0x000000FFU
821 #define GPTIMER_PREEVENT_VAL_S 0U
822 
823 
824 /*-----------------------------------REGISTER------------------------------------
825  Register name: CHFILT
826  Offset name: GPTIMER_O_CHFILT
827  Relative address: 0x20
828  Description: Channel Input Filter
829 
830  This register is used to configure the filter on the channel inputs. The configuration is for all inputs.
831  The filter is enabled when a channel is in capture mode.
832 
833  The input to the filter is passed to the edge detection logic if [LOAD] + 1 consecutive input samples are equal. The filter functions as a down counter, counting down every input sample.
834  If two consecutive samples are unequal, the filter counter restarts from [LOAD].
835  If the filter counter reaches zero, the input signal is valid and passed to the edge detection logic.
836 
837  The channel filter should only be configured while the [CTL.MODE] = DIS. Configuring the filter while the timer is running can result in unexpected behavior.
838  Default Value: 0x00000000
839 
840  Field: MODE
841  From..to bits: 0...1
842  DefaultValue: 0x0
843  Access type: read-write
844  Description: Channel filter mode
845 
846  ENUMs:
847  BYPASS: Filter is bypassed. No Filter is used.
848  CLK: Filter is clocked by system clock.
849  TICKSRC: Filter is clocked by [PRECFG.TICKSRC].
850  TIMERCLK: Filter is clocked by timer clock.
851 */
852 #define GPTIMER_CHFILT_MODE_W 2U
853 #define GPTIMER_CHFILT_MODE_M 0x00000003U
854 #define GPTIMER_CHFILT_MODE_S 0U
855 #define GPTIMER_CHFILT_MODE_BYPASS 0x00000000U
856 #define GPTIMER_CHFILT_MODE_CLK 0x00000001U
857 #define GPTIMER_CHFILT_MODE_TICKSRC 0x00000002U
858 #define GPTIMER_CHFILT_MODE_TIMERCLK 0x00000003U
859 /*
860 
861  Field: LOAD
862  From..to bits: 8...15
863  DefaultValue: 0x0
864  Access type: read-write
865  Description: The input of the channel filter is passed to the edge detection logic after [LOAD] + 1 consecutive equal samples.
866 
867 */
868 #define GPTIMER_CHFILT_LOAD_W 8U
869 #define GPTIMER_CHFILT_LOAD_M 0x0000FF00U
870 #define GPTIMER_CHFILT_LOAD_S 8U
871 
872 
873 /*-----------------------------------REGISTER------------------------------------
874  Register name: FAULT
875  Offset name: GPTIMER_O_FAULT
876  Relative address: 0x24
877  Description: Fault
878 
879  This register is used to configure the fault input logic.
880 
881  Primary use scenario is to select [CTL] before starting the timer. Follow these steps to configure [CTL] while [CTL.MODE] is different from DIS:
882  - Set [C0CFG.EDGE] to NONE.
883  - Configure [CTL].
884  - Wait for three system clock periods before setting [C0CFG.EDGE] different from NONE.
885  These steps prevent fault detection caused by expired signal values in synchronize and edge-detection circuit.
886  Default Value: 0x00000000
887 
888  Field: CTL
889  From..to bits: 0...1
890  DefaultValue: 0x0
891  Access type: read-write
892  Description: Fault control
893 
894  On active fault input the counter can optionally stop. If the counter stops this is done by hardware, software must then restart the timer if wanted. The fault input overrides channel 0 IOC input when [CTL] != DIS.
895  This means that channel 0 receives fault as input signal when [C0CFG.INPUT] = IO and [CTL] != DIS.
896 
897  [CHFILT.*] can be used to avoid glitching on the fault input. Fault is level triggered, the polarity is set by the [C0CFG.EDGE] field. Here [C0CFG.EDGE] = RISE gives active high and [C0CFG.EDGE] = FALL gives active low polarity.
898 
899  Fault is typically used together with [PARK.*] to stop the PWM signal to an external motor control circuit safely. Configure [PARK.*] to ensure predefined values of the PWM outputs.
900 
901  If [CTL] != DIS the [RIS.FAULT] interrupt is set immediately when the fault input is active while [CTL.MODE] != DIS.
902 
903  The three modes of fault is described below:
904 
905  [CTL] = IMMEDIATE
906  In this mode the counter stops immediately on an active fault input. This is done by hardware by setting [CTL.MODE] = DIS. To start the counter software must set [CTL.MODE] != DIS.
907  When the counter has stopped, the input synchronizers and the channel filter is not running. This means that if [RIS.FAULT] is cleared it will not be set again while [CTL.MODE] = DIS.
908 
909  [CTL] = ZEROCOND
910  In this mode the counter stops when [CNTR.*] = 0 after an active fault input. If the [RIS.FAULT] interrupt has been cleared by software before [CNTR.*] = 0, and the fault input is inactive, the counter will continue as normal.
911  When the counter stops on zero, it can be started again by clearing the [RIS.FAULT] interrupt if the fault input is inactive. To change the counter mode set [CTL.MODE] = DIS, clear the [RIS.FAULT] interrupt, then start timer in wanted mode.
912 
913  [CTL] = IRQ
914  In this mode only the [RIS.FAULT] flag is set on an active fault input.
915 
916 
917  ENUMs:
918  DIS: Disable. The timer ignores fault.
919  IMMEDIATE: Immediate reaction. The counter stops immediately on fault.
920  ZERCOND: Zero condition. The counter stops when [CNTR.*] = 0.
921  IRQ: Interrupt request. Only set [RIS.FAULT] on active fault.
922 */
923 #define GPTIMER_FAULT_CTL_W 2U
924 #define GPTIMER_FAULT_CTL_M 0x00000003U
925 #define GPTIMER_FAULT_CTL_S 0U
926 #define GPTIMER_FAULT_CTL_DIS 0x00000000U
927 #define GPTIMER_FAULT_CTL_IMMEDIATE 0x00000001U
928 #define GPTIMER_FAULT_CTL_ZERCOND 0x00000002U
929 #define GPTIMER_FAULT_CTL_IRQ 0x00000003U
930 /*
931 
932  Field: RES
933  From..to bits: 2...31
934  DefaultValue: 0x0
935  Access type: read-only
936  Description: Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
937 
938 */
939 #define GPTIMER_FAULT_RES_W 30U
940 #define GPTIMER_FAULT_RES_M 0xFFFFFFFCU
941 #define GPTIMER_FAULT_RES_S 2U
942 
943 
944 /*-----------------------------------REGISTER------------------------------------
945  Register name: PARK
946  Offset name: GPTIMER_O_PARK
947  Relative address: 0x28
948  Description: Park
949 
950  This register configures how the outputs should be set in Park mode. Park mode is either entered by debug halt or fault. Park mode is activated when the counter stops. Park mode is inactive when the counter starts. When park mode is active all outputs are set to their predefined states.
951 
952  For IO output signals which have enabled dead band, a dead band insertion will be done before switching to the predefined state.
953  Default Value: 0x00000000
954 
955  Field: CTL
956  From..to bits: 0...1
957  DefaultValue: 0x0
958  Access type: read-write
959  Description: Park Control.
960 
961  ENUMs:
962  DIS: Disable park mode.
963  FAULT: Enter park mode on fault.
964  DEBUG: Enter park mode on debug.
965  BOTH: Enter parkmode on fault or debug.
966 */
967 #define GPTIMER_PARK_CTL_W 2U
968 #define GPTIMER_PARK_CTL_M 0x00000003U
969 #define GPTIMER_PARK_CTL_S 0U
970 #define GPTIMER_PARK_CTL_DIS 0x00000000U
971 #define GPTIMER_PARK_CTL_FAULT 0x00000001U
972 #define GPTIMER_PARK_CTL_DEBUG 0x00000002U
973 #define GPTIMER_PARK_CTL_BOTH 0x00000003U
974 /*
975 
976  Field: IOPS0
977  From..to bits: 2...2
978  DefaultValue: 0x0
979  Access type: read-write
980  Description: IO Park State 0
981 
982  Park state for IO output 0.
983 
984  ENUMs:
985  HIGH: Output is set high in park mode.
986  LOW: Output is set low in park mode.
987 */
988 #define GPTIMER_PARK_IOPS0 0x00000004U
989 #define GPTIMER_PARK_IOPS0_M 0x00000004U
990 #define GPTIMER_PARK_IOPS0_S 2U
991 #define GPTIMER_PARK_IOPS0_HIGH 0x00000004U
992 #define GPTIMER_PARK_IOPS0_LOW 0x00000000U
993 /*
994 
995  Field: IOCPS0
996  From..to bits: 3...3
997  DefaultValue: 0x0
998  Access type: read-write
999  Description: IO Complementary Park State 0
1000 
1001  Park state for IO Complementary output 0.
1002 
1003  ENUMs:
1004  LOW: Output is set low in park mode.
1005  HIGH: Output is set high in park mode.
1006 */
1007 #define GPTIMER_PARK_IOCPS0 0x00000008U
1008 #define GPTIMER_PARK_IOCPS0_M 0x00000008U
1009 #define GPTIMER_PARK_IOCPS0_S 3U
1010 #define GPTIMER_PARK_IOCPS0_LOW 0x00000000U
1011 #define GPTIMER_PARK_IOCPS0_HIGH 0x00000008U
1012 /*
1013 
1014  Field: IOPS1
1015  From..to bits: 4...4
1016  DefaultValue: 0x0
1017  Access type: read-write
1018  Description: IO Park State 1
1019 
1020  Park state for IO output 1.
1021 
1022  ENUMs:
1023  LOW: Output is set low in park mode.
1024  HIGH: Output is set high in park mode.
1025 */
1026 #define GPTIMER_PARK_IOPS1 0x00000010U
1027 #define GPTIMER_PARK_IOPS1_M 0x00000010U
1028 #define GPTIMER_PARK_IOPS1_S 4U
1029 #define GPTIMER_PARK_IOPS1_LOW 0x00000000U
1030 #define GPTIMER_PARK_IOPS1_HIGH 0x00000010U
1031 /*
1032 
1033  Field: IOCPS1
1034  From..to bits: 5...5
1035  DefaultValue: 0x0
1036  Access type: read-write
1037  Description: IO Complementary Park State 1
1038 
1039  Park state for IO Complementary output 1.
1040 
1041  ENUMs:
1042  LOW: Output is set low in park mode.
1043  HIGH: Output is set high in park mode.
1044 */
1045 #define GPTIMER_PARK_IOCPS1 0x00000020U
1046 #define GPTIMER_PARK_IOCPS1_M 0x00000020U
1047 #define GPTIMER_PARK_IOCPS1_S 5U
1048 #define GPTIMER_PARK_IOCPS1_LOW 0x00000000U
1049 #define GPTIMER_PARK_IOCPS1_HIGH 0x00000020U
1050 /*
1051 
1052  Field: IOPS2
1053  From..to bits: 6...6
1054  DefaultValue: 0x0
1055  Access type: read-write
1056  Description: IO Park State 2
1057 
1058  Park state for IO output 2.
1059 
1060  ENUMs:
1061  LOW: Output is set low in park mode.
1062  HIGH: Output is set high in park mode.
1063 */
1064 #define GPTIMER_PARK_IOPS2 0x00000040U
1065 #define GPTIMER_PARK_IOPS2_M 0x00000040U
1066 #define GPTIMER_PARK_IOPS2_S 6U
1067 #define GPTIMER_PARK_IOPS2_LOW 0x00000000U
1068 #define GPTIMER_PARK_IOPS2_HIGH 0x00000040U
1069 /*
1070 
1071  Field: IOCPS2
1072  From..to bits: 7...7
1073  DefaultValue: 0x0
1074  Access type: read-write
1075  Description: IO Complementary Park State 2
1076 
1077  Park state for IO Complementary output 2.
1078 
1079  ENUMs:
1080  LOW: Output is set low in park mode.
1081  HIGH: Output is set high in park mode.
1082 */
1083 #define GPTIMER_PARK_IOCPS2 0x00000080U
1084 #define GPTIMER_PARK_IOCPS2_M 0x00000080U
1085 #define GPTIMER_PARK_IOCPS2_S 7U
1086 #define GPTIMER_PARK_IOCPS2_LOW 0x00000000U
1087 #define GPTIMER_PARK_IOCPS2_HIGH 0x00000080U
1088 /*
1089 
1090  Field: IOPS3
1091  From..to bits: 8...8
1092  DefaultValue: 0x0
1093  Access type: read-write
1094  Description: IO Park State 3
1095 
1096  Park state for IO output 3.
1097 
1098  ENUMs:
1099  LOW: Output is set low in park mode.
1100  HIGH: Output is set high in park mode.
1101 */
1102 #define GPTIMER_PARK_IOPS3 0x00000100U
1103 #define GPTIMER_PARK_IOPS3_M 0x00000100U
1104 #define GPTIMER_PARK_IOPS3_S 8U
1105 #define GPTIMER_PARK_IOPS3_LOW 0x00000000U
1106 #define GPTIMER_PARK_IOPS3_HIGH 0x00000100U
1107 /*
1108 
1109  Field: IOCPS3
1110  From..to bits: 9...9
1111  DefaultValue: 0x0
1112  Access type: read-write
1113  Description: IO Complementary Park State 3
1114 
1115  Park state for IO Complementary output 3.
1116 
1117  ENUMs:
1118  LOW: Output is set low in park mode.
1119  HIGH: Output is set high in park mode.
1120 */
1121 #define GPTIMER_PARK_IOCPS3 0x00000200U
1122 #define GPTIMER_PARK_IOCPS3_M 0x00000200U
1123 #define GPTIMER_PARK_IOCPS3_S 9U
1124 #define GPTIMER_PARK_IOCPS3_LOW 0x00000000U
1125 #define GPTIMER_PARK_IOCPS3_HIGH 0x00000200U
1126 
1127 
1128 /*-----------------------------------REGISTER------------------------------------
1129  Register name: DBDLY
1130  Offset name: GPTIMER_O_DBDLY
1131  Relative address: 0x2C
1132  Description: Dead Band Delay
1133 
1134  This register is used to insert a dead band delay when generating complementary PWM signals. To enable dead band, on for example IO output 0, create a reference PWM signal on Output 0, then set [DBCTL.IOC0] = EN.
1135 
1136  TBD: 12-bit width fall delay and rise delay may be excessive, if 8-bits are enough we can join DBDLY and DBCTL.
1137  Default Value: 0x00000000
1138 
1139  Field: RISEDLY
1140  From..to bits: 0...11
1141  DefaultValue: 0x0
1142  Access type: read-write
1143  Description: Rise delay.
1144 
1145  The number of system clock periods inserted between the rise of the dead band reference signal and the rise of the output signal.
1146 
1147 */
1148 #define GPTIMER_DBDLY_RISEDLY_W 12U
1149 #define GPTIMER_DBDLY_RISEDLY_M 0x00000FFFU
1150 #define GPTIMER_DBDLY_RISEDLY_S 0U
1151 /*
1152 
1153  Field: FALLDLY
1154  From..to bits: 16...27
1155  DefaultValue: 0x0
1156  Access type: read-write
1157  Description: Fall delay.
1158 
1159  The number of system clock periods inserted between the fall of the dead band reference signal and the rise of the inverted output signal.
1160 
1161 */
1162 #define GPTIMER_DBDLY_FALLDLY_W 12U
1163 #define GPTIMER_DBDLY_FALLDLY_M 0x0FFF0000U
1164 #define GPTIMER_DBDLY_FALLDLY_S 16U
1165 
1166 
1167 /*-----------------------------------REGISTER------------------------------------
1168  Register name: DBCTL
1169  Offset name: GPTIMER_O_DBCTL
1170  Relative address: 0x30
1171  Description: Dead Band Control
1172 
1173  This register is used to enable dead band for IOC outputs.
1174  Default Value: 0x00000000
1175 
1176  Field: IO0
1177  From..to bits: 0...0
1178  DefaultValue: 0x0
1179  Access type: read-write
1180  Description: Enable dead band on IO and IO complementary output 0.
1181 
1182  ENUMs:
1183  DIS: Disable
1184  EN: Enable
1185 */
1186 #define GPTIMER_DBCTL_IO0 0x00000001U
1187 #define GPTIMER_DBCTL_IO0_M 0x00000001U
1188 #define GPTIMER_DBCTL_IO0_S 0U
1189 #define GPTIMER_DBCTL_IO0_DIS 0x00000000U
1190 #define GPTIMER_DBCTL_IO0_EN 0x00000001U
1191 /*
1192 
1193  Field: IO1
1194  From..to bits: 1...1
1195  DefaultValue: 0x0
1196  Access type: read-write
1197  Description: Enable dead band on IO and IO complementary output 1.
1198 
1199  ENUMs:
1200  DIS: Disable
1201  EN: Enable
1202 */
1203 #define GPTIMER_DBCTL_IO1 0x00000002U
1204 #define GPTIMER_DBCTL_IO1_M 0x00000002U
1205 #define GPTIMER_DBCTL_IO1_S 1U
1206 #define GPTIMER_DBCTL_IO1_DIS 0x00000000U
1207 #define GPTIMER_DBCTL_IO1_EN 0x00000002U
1208 /*
1209 
1210  Field: IO2
1211  From..to bits: 2...2
1212  DefaultValue: 0x0
1213  Access type: read-write
1214  Description: Enable dead band on IO and IO complementary output 2.
1215 
1216  ENUMs:
1217  DIS: Disable
1218  EN: Enable
1219 */
1220 #define GPTIMER_DBCTL_IO2 0x00000004U
1221 #define GPTIMER_DBCTL_IO2_M 0x00000004U
1222 #define GPTIMER_DBCTL_IO2_S 2U
1223 #define GPTIMER_DBCTL_IO2_DIS 0x00000000U
1224 #define GPTIMER_DBCTL_IO2_EN 0x00000004U
1225 /*
1226 
1227  Field: IO3
1228  From..to bits: 3...3
1229  DefaultValue: 0x0
1230  Access type: read-write
1231  Description: Enable dead band on IO and IO complementary output 3.
1232 
1233  ENUMs:
1234  DIS: Disable
1235  EN: Enable
1236 */
1237 #define GPTIMER_DBCTL_IO3 0x00000008U
1238 #define GPTIMER_DBCTL_IO3_M 0x00000008U
1239 #define GPTIMER_DBCTL_IO3_S 3U
1240 #define GPTIMER_DBCTL_IO3_DIS 0x00000000U
1241 #define GPTIMER_DBCTL_IO3_EN 0x00000008U
1242 
1243 
1244 /*-----------------------------------REGISTER------------------------------------
1245  Register name: QDECSTAT
1246  Offset name: GPTIMER_O_QDECSTAT
1247  Relative address: 0x34
1248  Description: Quadrature Decoder Status
1249 
1250  This register can be used during QDEC mode to check the status of the quadrature decoder.
1251  Default Value: 0x00000000
1252 
1253  Field: QDIR
1254  From..to bits: 0...0
1255  DefaultValue: 0x0
1256  Access type: read-only
1257  Description: Direction of count during QDEC mode.
1258 
1259  ENUMs:
1260  UP: Up (PHA leads PHB)
1261  DOWN: Down (PHB leads PHA)
1262 */
1263 #define GPTIMER_QDECSTAT_QDIR 0x00000001U
1264 #define GPTIMER_QDECSTAT_QDIR_M 0x00000001U
1265 #define GPTIMER_QDECSTAT_QDIR_S 0U
1266 #define GPTIMER_QDECSTAT_QDIR_UP 0x00000000U
1267 #define GPTIMER_QDECSTAT_QDIR_DOWN 0x00000001U
1268 /*
1269 
1270  Field: DBLTRANS
1271  From..to bits: 1...1
1272  DefaultValue: 0x0
1273  Access type: read-only
1274  Description: Double transition
1275 
1276  ENUMs:
1277  NONE: Single or no transition on phase inputs.
1278  DBL: Double transition on phase inputs.
1279 */
1280 #define GPTIMER_QDECSTAT_DBLTRANS 0x00000002U
1281 #define GPTIMER_QDECSTAT_DBLTRANS_M 0x00000002U
1282 #define GPTIMER_QDECSTAT_DBLTRANS_S 1U
1283 #define GPTIMER_QDECSTAT_DBLTRANS_NONE 0x00000000U
1284 #define GPTIMER_QDECSTAT_DBLTRANS_DBL 0x00000002U
1285 
1286 
1287 /*-----------------------------------REGISTER------------------------------------
1288  Register name: IRGEN
1289  Offset name: GPTIMER_O_IRGEN
1290  Relative address: 0x38
1291  Description: IR Generation
1292 
1293  Use this register to generate IR codes. When [CTL] = 1, an AND gate is enabled between IO output 0 in LGPT0 and IC output 0 in LGPT1. The output of the gate overrides IO output 0 in LGPT0. See [OUTCTL.*] for explanation of outputs.
1294 
1295  To generate IR codes let LGPT0 generate the carrier wave on output 0. Set this output as tick input of LGPT1, with [PRECFG.TICKSRC] = FALL_TICK.
1296  Generate wanted IR codes by adjusting LGPT1 [PTGT.*] and [PC0CC.*].
1297  Default Value: 0x00000000
1298 
1299  Field: CTL
1300  From..to bits: 0...0
1301  DefaultValue: 0x0
1302  Access type: read-write
1303  Description: Control
1304 
1305 
1306  ENUMs:
1307  DIS: Disable.
1308  EN: Enable.
1309 */
1310 #define GPTIMER_IRGEN_CTL 0x00000001U
1311 #define GPTIMER_IRGEN_CTL_M 0x00000001U
1312 #define GPTIMER_IRGEN_CTL_S 0U
1313 #define GPTIMER_IRGEN_CTL_DIS 0x00000000U
1314 #define GPTIMER_IRGEN_CTL_EN 0x00000001U
1315 
1316 
1317 /*-----------------------------------REGISTER------------------------------------
1318  Register name: DMA
1319  Offset name: GPTIMER_O_DMA
1320  Relative address: 0x3C
1321  Description: Direct Memory Access
1322 
1323  This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write).
1324  Choose DMA request source by setting the [REQ] field. The setting of the corresponding interrupt in the [RIS.*] registers also sets the DMA request.
1325  Upon a DMA request defined by [REQ] an internal address pointer is set to [RWADDR]*4. Every access to [DMARW.*] will increment the internal pointer by 4 such that the next DMA access will be to the next register.
1326  The internal pointer will stop after [RWCNTR] increments. Further access will be ignored.
1327  Default Value: 0x00000000
1328 
1329  Field: REQ
1330  From..to bits: 0...2
1331  DefaultValue: 0x0
1332  Access type: read-write
1333  Description: DMA request trigger
1334 
1335  ENUMs:
1336  DIS: Disabled
1337  FAULT: Setting of [RIS.FAULT] generates a DMA request.
1338  TGT: Setting of [RIS.TGT] generates a DMA request.
1339  ZERO: Setting of [RIS.ZERO] generates a DMA request.
1340  C0CC: Setting of [RIS.C0CC] generates a DMA request.
1341  C1CC: Setting of [RIS.C1CC] generates a DMA request.
1342  C2CC: Setting of [RIS.C2CC] generates a DMA request.
1343  C3CC: Setting of [RIS.C3CC] generates a DMA request.
1344 */
1345 #define GPTIMER_DMA_REQ_W 3U
1346 #define GPTIMER_DMA_REQ_M 0x00000007U
1347 #define GPTIMER_DMA_REQ_S 0U
1348 #define GPTIMER_DMA_REQ_DIS 0x00000000U
1349 #define GPTIMER_DMA_REQ_FAULT 0x00000003U
1350 #define GPTIMER_DMA_REQ_TGT 0x00000001U
1351 #define GPTIMER_DMA_REQ_ZERO 0x00000002U
1352 #define GPTIMER_DMA_REQ_C0CC 0x00000004U
1353 #define GPTIMER_DMA_REQ_C1CC 0x00000005U
1354 #define GPTIMER_DMA_REQ_C2CC 0x00000006U
1355 #define GPTIMER_DMA_REQ_C3CC 0x00000007U
1356 /*
1357 
1358  Field: ADDRESS
1359  From..to bits: 8...14
1360  DefaultValue: 0x0
1361  Access type: read-write
1362  Description: The base address which the DMA access when reading/writing [DMARW]. The base address is set by taking the 9 LSB of the physical address and divide by 4.
1363  For example, if you wanted the [RWADDR] to point to the [PTGT] register you should set [RWADDR] = 0x0FC/4.
1364 
1365 */
1366 #define GPTIMER_DMA_ADDRESS_W 7U
1367 #define GPTIMER_DMA_ADDRESS_M 0x00007F00U
1368 #define GPTIMER_DMA_ADDRESS_S 8U
1369 /*
1370 
1371  Field: RWC
1372  From..to bits: 16...19
1373  DefaultValue: 0x0
1374  Access type: read-write
1375  Description: The read/write counter. RWCNTR+1 is the number of times the DMA can access (read/write) the [DMARW] register. For each DMA access to [DMARW] an internal counter is incremented, writing to the next address field. [RWADDR] + 4*[RWCNTR] is the final register address which can be accessed by the DMA.
1376 
1377 */
1378 #define GPTIMER_DMA_RWC_W 4U
1379 #define GPTIMER_DMA_RWC_M 0x000F0000U
1380 #define GPTIMER_DMA_RWC_S 16U
1381 
1382 
1383 /*-----------------------------------REGISTER------------------------------------
1384  Register name: DMARW
1385  Offset name: GPTIMER_O_DMARW
1386  Relative address: 0x40
1387  Description: Direct Memory Access
1388 
1389  This register is used by the DMA to access (read/write) register inside this LGPT module.
1390  Each access to this register will increment the internal DMA address counter. See [DMA.*] for description.
1391  Default Value: 0x00000000
1392 
1393  Field: VAL
1394  From..to bits: 0...31
1395  DefaultValue: 0x0
1396  Access type: read-write
1397  Description: DMA read write value.
1398 
1399  The value that is read/written from/to the registers.
1400 
1401 */
1402 #define GPTIMER_DMARW_VAL_W 32U
1403 #define GPTIMER_DMARW_VAL_M 0xFFFFFFFFU
1404 #define GPTIMER_DMARW_VAL_S 0U
1405 
1406 
1407 /*-----------------------------------REGISTER------------------------------------
1408  Register name: ADCTRG
1409  Offset name: GPTIMER_O_ADCTRG
1410  Relative address: 0x44
1411  Description: ADC Trigger
1412 
1413  This register is used to enable ADC trigger from the timer.
1414  Choose ADC trigger source by setting the [SRC] field. The setting of the corresponding interrupt in the [RIS.*] registers also sets the ADC trigger.
1415  Default Value: 0x00000000
1416 
1417  Field: SRC
1418  From..to bits: 0...2
1419  DefaultValue: 0x0
1420  Access type: read-write
1421  Description: ADC request trigger
1422 
1423  ENUMs:
1424  DIS: Disabled
1425  FAULT: Setting of [RIS.FAULT] generates an ADC trigger.
1426  TGT: Setting of [RIS.TGT] generates an ADC trigger.
1427 
1428  ZERO: Setting of [RIS.ZERO] generates an ADC trigger.
1429  C0CC: Setting of [RIS.C0CC] generates an ADC trigger.
1430  C1CC: Setting of [RIS.C1CC] generates an ADC trigger.
1431  C2CC: Setting of [RIS.C2CC] generates an ADC trigger.
1432  C3CC: Setting of [RIS.C3CC] generates an ADC trigger.
1433 */
1434 #define GPTIMER_ADCTRG_SRC_W 3U
1435 #define GPTIMER_ADCTRG_SRC_M 0x00000007U
1436 #define GPTIMER_ADCTRG_SRC_S 0U
1437 #define GPTIMER_ADCTRG_SRC_DIS 0x00000000U
1438 #define GPTIMER_ADCTRG_SRC_FAULT 0x00000003U
1439 #define GPTIMER_ADCTRG_SRC_TGT 0x00000001U
1440 #define GPTIMER_ADCTRG_SRC_ZERO 0x00000002U
1441 #define GPTIMER_ADCTRG_SRC_C0CC 0x00000004U
1442 #define GPTIMER_ADCTRG_SRC_C1CC 0x00000005U
1443 #define GPTIMER_ADCTRG_SRC_C2CC 0x00000006U
1444 #define GPTIMER_ADCTRG_SRC_C3CC 0x00000007U
1445 
1446 
1447 /*-----------------------------------REGISTER------------------------------------
1448  Register name: IOCTL
1449  Offset name: GPTIMER_O_IOCTL
1450  Relative address: 0x48
1451  Description: IO Controller
1452 
1453  This register controls the IO outputs.
1454  Default Value: 0x00000000
1455 
1456  Field: OUT0
1457  From..to bits: 0...1
1458  DefaultValue: 0x0
1459  Access type: read-write
1460  Description: IO output 0 control
1461 
1462  This bit field controls IO output 0.
1463 
1464  ENUMs:
1465  NRM: Normal output. The IO output is not changed.
1466  LOW: Driven low. The IO output is driven low.
1467  HIGH: Driven high. The IO output is driven high.
1468  INV: Inverted value. The IO output is inverted.
1469 */
1470 #define GPTIMER_IOCTL_OUT0_W 2U
1471 #define GPTIMER_IOCTL_OUT0_M 0x00000003U
1472 #define GPTIMER_IOCTL_OUT0_S 0U
1473 #define GPTIMER_IOCTL_OUT0_NRM 0x00000000U
1474 #define GPTIMER_IOCTL_OUT0_LOW 0x00000001U
1475 #define GPTIMER_IOCTL_OUT0_HIGH 0x00000002U
1476 #define GPTIMER_IOCTL_OUT0_INV 0x00000003U
1477 /*
1478 
1479  Field: COUT0
1480  From..to bits: 2...3
1481  DefaultValue: 0x0
1482  Access type: read-write
1483  Description: IO complementary output 0 control
1484 
1485  This bit field controls IO complementary output 0.
1486 
1487  ENUMs:
1488  NRM: Normal output. The IO complementary output is not changed.
1489  LOW: Driven low. The IO complementary output is driven low.
1490  HIGH: Driven high. The IO complementary output is driven high.
1491  INV: Inverted value. The IO complementary output is inverted.
1492 */
1493 #define GPTIMER_IOCTL_COUT0_W 2U
1494 #define GPTIMER_IOCTL_COUT0_M 0x0000000CU
1495 #define GPTIMER_IOCTL_COUT0_S 2U
1496 #define GPTIMER_IOCTL_COUT0_NRM 0x00000000U
1497 #define GPTIMER_IOCTL_COUT0_LOW 0x00000004U
1498 #define GPTIMER_IOCTL_COUT0_HIGH 0x00000008U
1499 #define GPTIMER_IOCTL_COUT0_INV 0x0000000CU
1500 /*
1501 
1502  Field: OUT1
1503  From..to bits: 4...5
1504  DefaultValue: 0x0
1505  Access type: read-write
1506  Description: IO output 1 control
1507 
1508  This bit field controls IO output 1.
1509 
1510  ENUMs:
1511  NRM: Normal output. The IO output is not changed.
1512  LOW: Driven low. The IO output is driven low.
1513  HIGH: Driven high. The IO output is driven high.
1514  INV: Inverted value. The IO output is inverted.
1515 */
1516 #define GPTIMER_IOCTL_OUT1_W 2U
1517 #define GPTIMER_IOCTL_OUT1_M 0x00000030U
1518 #define GPTIMER_IOCTL_OUT1_S 4U
1519 #define GPTIMER_IOCTL_OUT1_NRM 0x00000000U
1520 #define GPTIMER_IOCTL_OUT1_LOW 0x00000010U
1521 #define GPTIMER_IOCTL_OUT1_HIGH 0x00000020U
1522 #define GPTIMER_IOCTL_OUT1_INV 0x00000030U
1523 /*
1524 
1525  Field: COUT1
1526  From..to bits: 6...7
1527  DefaultValue: 0x0
1528  Access type: read-write
1529  Description: IO complementary output 1 control
1530 
1531  This bit field controls IO complementary output 1.
1532 
1533  ENUMs:
1534  NRM: Normal output. The IO complementary output is not changed.
1535  LOW: Driven low. The IO complementary output is driven low.
1536  HIGH: Driven high. The IO complementary output is driven high.
1537  INV: Inverted value. The IO complementary output is inverted.
1538 */
1539 #define GPTIMER_IOCTL_COUT1_W 2U
1540 #define GPTIMER_IOCTL_COUT1_M 0x000000C0U
1541 #define GPTIMER_IOCTL_COUT1_S 6U
1542 #define GPTIMER_IOCTL_COUT1_NRM 0x00000000U
1543 #define GPTIMER_IOCTL_COUT1_LOW 0x00000040U
1544 #define GPTIMER_IOCTL_COUT1_HIGH 0x00000080U
1545 #define GPTIMER_IOCTL_COUT1_INV 0x000000C0U
1546 /*
1547 
1548  Field: OUT2
1549  From..to bits: 8...9
1550  DefaultValue: 0x0
1551  Access type: read-write
1552  Description: IO output 2 control
1553 
1554  This bit field controls IO output 2.
1555 
1556  ENUMs:
1557  NRM: Normal output. The IO output is not changed.
1558  LOW: Driven low. The IO output is driven low.
1559  HIGH: Driven high. The IO output is driven high.
1560  INV: Inverted value. The IO output is inverted.
1561 */
1562 #define GPTIMER_IOCTL_OUT2_W 2U
1563 #define GPTIMER_IOCTL_OUT2_M 0x00000300U
1564 #define GPTIMER_IOCTL_OUT2_S 8U
1565 #define GPTIMER_IOCTL_OUT2_NRM 0x00000000U
1566 #define GPTIMER_IOCTL_OUT2_LOW 0x00000100U
1567 #define GPTIMER_IOCTL_OUT2_HIGH 0x00000200U
1568 #define GPTIMER_IOCTL_OUT2_INV 0x00000300U
1569 /*
1570 
1571  Field: COUT2
1572  From..to bits: 10...11
1573  DefaultValue: 0x0
1574  Access type: read-write
1575  Description: IO complementary output 2 control
1576 
1577  This bit field controls IO complementary output 2.
1578 
1579  ENUMs:
1580  NRM: Normal output. The IO complementary output is not changed.
1581  LOW: Driven low. The IO complementary output is driven low.
1582  HIGH: Driven high. The IO complementary output is driven high.
1583  INV: Inverted value. The IO complementary output is inverted.
1584 */
1585 #define GPTIMER_IOCTL_COUT2_W 2U
1586 #define GPTIMER_IOCTL_COUT2_M 0x00000C00U
1587 #define GPTIMER_IOCTL_COUT2_S 10U
1588 #define GPTIMER_IOCTL_COUT2_NRM 0x00000000U
1589 #define GPTIMER_IOCTL_COUT2_LOW 0x00000400U
1590 #define GPTIMER_IOCTL_COUT2_HIGH 0x00000800U
1591 #define GPTIMER_IOCTL_COUT2_INV 0x00000C00U
1592 /*
1593 
1594  Field: OUT3
1595  From..to bits: 12...13
1596  DefaultValue: 0x0
1597  Access type: read-write
1598  Description: IO output 3 control
1599 
1600  This bit field controls IO output 3.
1601 
1602  ENUMs:
1603  NRM: Normal output. The IO output is not changed.
1604  LOW: Driven low. The IO output is driven low.
1605  HIGH: Driven high. The IO output is driven high.
1606  INV: Inverted value. The IO output is inverted.
1607 */
1608 #define GPTIMER_IOCTL_OUT3_W 2U
1609 #define GPTIMER_IOCTL_OUT3_M 0x00003000U
1610 #define GPTIMER_IOCTL_OUT3_S 12U
1611 #define GPTIMER_IOCTL_OUT3_NRM 0x00000000U
1612 #define GPTIMER_IOCTL_OUT3_LOW 0x00001000U
1613 #define GPTIMER_IOCTL_OUT3_HIGH 0x00002000U
1614 #define GPTIMER_IOCTL_OUT3_INV 0x00003000U
1615 /*
1616 
1617  Field: COUT3
1618  From..to bits: 14...15
1619  DefaultValue: 0x0
1620  Access type: read-write
1621  Description: IO complementary output 3 control
1622 
1623  This bit field controls IO complementary output 3.
1624 
1625  ENUMs:
1626  NRM: Normal output. The IO complementary output is not changed.
1627  LOW: Driven low. The IO complementary output is driven low.
1628  HIGH: Driven high. The IO complementary output is driven high.
1629  INV: Inverted value. The IO complementary output is inverted.
1630 */
1631 #define GPTIMER_IOCTL_COUT3_W 2U
1632 #define GPTIMER_IOCTL_COUT3_M 0x0000C000U
1633 #define GPTIMER_IOCTL_COUT3_S 14U
1634 #define GPTIMER_IOCTL_COUT3_NRM 0x00000000U
1635 #define GPTIMER_IOCTL_COUT3_LOW 0x00004000U
1636 #define GPTIMER_IOCTL_COUT3_HIGH 0x00008000U
1637 #define GPTIMER_IOCTL_COUT3_INV 0x0000C000U
1638 
1639 
1640 /*-----------------------------------REGISTER------------------------------------
1641  Register name: IMASK
1642  Offset name: GPTIMER_O_IMASK
1643  Relative address: 0x68
1644  Description: Interrupt mask. This register selects interrupt sources which are allowed to pass from [RIS.*] to [MIS.*] when the corresponding bit-fields are set to 1.
1645  Default Value: 0x00000000
1646 
1647  Field: TGT
1648  From..to bits: 0...0
1649  DefaultValue: 0x0
1650  Access type: read-write
1651  Description: Enable [RIS.TGT] interrupt.
1652 
1653  ENUMs:
1654  DIS: Disable
1655  EN: Enable
1656 */
1657 #define GPTIMER_IMASK_TGT 0x00000001U
1658 #define GPTIMER_IMASK_TGT_M 0x00000001U
1659 #define GPTIMER_IMASK_TGT_S 0U
1660 #define GPTIMER_IMASK_TGT_DIS 0x00000000U
1661 #define GPTIMER_IMASK_TGT_EN 0x00000001U
1662 /*
1663 
1664  Field: ZERO
1665  From..to bits: 1...1
1666  DefaultValue: 0x0
1667  Access type: read-write
1668  Description: Enable [RIS.ZERO] interrupt.
1669 
1670  ENUMs:
1671  DIS: Disable
1672  EN: Enable
1673 */
1674 #define GPTIMER_IMASK_ZERO 0x00000002U
1675 #define GPTIMER_IMASK_ZERO_M 0x00000002U
1676 #define GPTIMER_IMASK_ZERO_S 1U
1677 #define GPTIMER_IMASK_ZERO_DIS 0x00000000U
1678 #define GPTIMER_IMASK_ZERO_EN 0x00000002U
1679 /*
1680 
1681  Field: DBLTRANS
1682  From..to bits: 2...2
1683  DefaultValue: 0x0
1684  Access type: read-write
1685  Description: Enable [RIS.DBLTRANS] interrupt.
1686 
1687  ENUMs:
1688  DIS: Disable
1689  EN: Enable
1690 */
1691 #define GPTIMER_IMASK_DBLTRANS 0x00000004U
1692 #define GPTIMER_IMASK_DBLTRANS_M 0x00000004U
1693 #define GPTIMER_IMASK_DBLTRANS_S 2U
1694 #define GPTIMER_IMASK_DBLTRANS_DIS 0x00000000U
1695 #define GPTIMER_IMASK_DBLTRANS_EN 0x00000004U
1696 /*
1697 
1698  Field: CNTRCHNG
1699  From..to bits: 3...3
1700  DefaultValue: 0x0
1701  Access type: read-write
1702  Description: Enable [RIS.CNTRCHNG] interrupt.
1703 
1704  ENUMs:
1705  DIS: Disable
1706  EN: Enable
1707 */
1708 #define GPTIMER_IMASK_CNTRCHNG 0x00000008U
1709 #define GPTIMER_IMASK_CNTRCHNG_M 0x00000008U
1710 #define GPTIMER_IMASK_CNTRCHNG_S 3U
1711 #define GPTIMER_IMASK_CNTRCHNG_DIS 0x00000000U
1712 #define GPTIMER_IMASK_CNTRCHNG_EN 0x00000008U
1713 /*
1714 
1715  Field: DIRCHNG
1716  From..to bits: 4...4
1717  DefaultValue: 0x0
1718  Access type: read-write
1719  Description: Enable [RIS.DIRCHNG] interrupt.
1720 
1721  ENUMs:
1722  DIS: Disable
1723  EN: Enable
1724 */
1725 #define GPTIMER_IMASK_DIRCHNG 0x00000010U
1726 #define GPTIMER_IMASK_DIRCHNG_M 0x00000010U
1727 #define GPTIMER_IMASK_DIRCHNG_S 4U
1728 #define GPTIMER_IMASK_DIRCHNG_DIS 0x00000000U
1729 #define GPTIMER_IMASK_DIRCHNG_EN 0x00000010U
1730 /*
1731 
1732  Field: IDX
1733  From..to bits: 5...5
1734  DefaultValue: 0x0
1735  Access type: read-write
1736  Description: Enable [RIS.IDX] interrupt.
1737 
1738  ENUMs:
1739  DIS: Disable
1740  EN: Enable
1741 */
1742 #define GPTIMER_IMASK_IDX 0x00000020U
1743 #define GPTIMER_IMASK_IDX_M 0x00000020U
1744 #define GPTIMER_IMASK_IDX_S 5U
1745 #define GPTIMER_IMASK_IDX_DIS 0x00000000U
1746 #define GPTIMER_IMASK_IDX_EN 0x00000020U
1747 /*
1748 
1749  Field: FAULT
1750  From..to bits: 6...6
1751  DefaultValue: 0x0
1752  Access type: read-write
1753  Description: Enable [RIS.FAULT] interrupt.
1754 
1755  ENUMs:
1756  DIS: Disable
1757  EN: Enable
1758 */
1759 #define GPTIMER_IMASK_FAULT 0x00000040U
1760 #define GPTIMER_IMASK_FAULT_M 0x00000040U
1761 #define GPTIMER_IMASK_FAULT_S 6U
1762 #define GPTIMER_IMASK_FAULT_DIS 0x00000000U
1763 #define GPTIMER_IMASK_FAULT_EN 0x00000040U
1764 /*
1765 
1766  Field: C0CC
1767  From..to bits: 8...8
1768  DefaultValue: 0x0
1769  Access type: read-write
1770  Description: Enable [RIS.C0CC] interrupt.
1771 
1772  ENUMs:
1773  DIS: Disable
1774  EN: Enable
1775 */
1776 #define GPTIMER_IMASK_C0CC 0x00000100U
1777 #define GPTIMER_IMASK_C0CC_M 0x00000100U
1778 #define GPTIMER_IMASK_C0CC_S 8U
1779 #define GPTIMER_IMASK_C0CC_DIS 0x00000000U
1780 #define GPTIMER_IMASK_C0CC_EN 0x00000100U
1781 /*
1782 
1783  Field: C1CC
1784  From..to bits: 9...9
1785  DefaultValue: 0x0
1786  Access type: read-write
1787  Description: Enable [RIS.C1CC] interrupt.
1788 
1789  ENUMs:
1790  DIS: Disable
1791  EN: Enable
1792 */
1793 #define GPTIMER_IMASK_C1CC 0x00000200U
1794 #define GPTIMER_IMASK_C1CC_M 0x00000200U
1795 #define GPTIMER_IMASK_C1CC_S 9U
1796 #define GPTIMER_IMASK_C1CC_DIS 0x00000000U
1797 #define GPTIMER_IMASK_C1CC_EN 0x00000200U
1798 /*
1799 
1800  Field: C2CC
1801  From..to bits: 10...10
1802  DefaultValue: 0x0
1803  Access type: read-write
1804  Description: Enable [RIS.C2CC] interrupt.
1805 
1806  ENUMs:
1807  DIS: Disable
1808  EN: Enable
1809 */
1810 #define GPTIMER_IMASK_C2CC 0x00000400U
1811 #define GPTIMER_IMASK_C2CC_M 0x00000400U
1812 #define GPTIMER_IMASK_C2CC_S 10U
1813 #define GPTIMER_IMASK_C2CC_DIS 0x00000000U
1814 #define GPTIMER_IMASK_C2CC_EN 0x00000400U
1815 /*
1816 
1817  Field: C3CC
1818  From..to bits: 11...11
1819  DefaultValue: 0x0
1820  Access type: read-write
1821  Description: Enable [RIS.C3CC] interrupt.
1822 
1823  ENUMs:
1824  DIS: Disable
1825  EN: Enable
1826 */
1827 #define GPTIMER_IMASK_C3CC 0x00000800U
1828 #define GPTIMER_IMASK_C3CC_M 0x00000800U
1829 #define GPTIMER_IMASK_C3CC_S 11U
1830 #define GPTIMER_IMASK_C3CC_DIS 0x00000000U
1831 #define GPTIMER_IMASK_C3CC_EN 0x00000800U
1832 
1833 
1834 /*-----------------------------------REGISTER------------------------------------
1835  Register name: RIS
1836  Offset name: GPTIMER_O_RIS
1837  Relative address: 0x6C
1838  Description: Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
1839  Default Value: 0x00000000
1840 
1841  Field: TGT
1842  From..to bits: 0...0
1843  DefaultValue: 0x0
1844  Access type: read-only
1845  Description: Status of the [TGT] interrupt. The interrupt is set when [CNTR.*] = [TGT.*].
1846 
1847  ENUMs:
1848  CLR: Cleared
1849  SET: Set
1850 */
1851 #define GPTIMER_RIS_TGT 0x00000001U
1852 #define GPTIMER_RIS_TGT_M 0x00000001U
1853 #define GPTIMER_RIS_TGT_S 0U
1854 #define GPTIMER_RIS_TGT_CLR 0x00000000U
1855 #define GPTIMER_RIS_TGT_SET 0x00000001U
1856 /*
1857 
1858  Field: ZERO
1859  From..to bits: 1...1
1860  DefaultValue: 0x0
1861  Access type: read-only
1862  Description: Status of the [ZERO] interrupt. The interrupt is set when [CNTR.*] = 0.
1863 
1864  ENUMs:
1865  CLR: Cleared
1866  SET: Set
1867 */
1868 #define GPTIMER_RIS_ZERO 0x00000002U
1869 #define GPTIMER_RIS_ZERO_M 0x00000002U
1870 #define GPTIMER_RIS_ZERO_S 1U
1871 #define GPTIMER_RIS_ZERO_CLR 0x00000000U
1872 #define GPTIMER_RIS_ZERO_SET 0x00000002U
1873 /*
1874 
1875  Field: DBLTRANS
1876  From..to bits: 2...2
1877  DefaultValue: 0x0
1878  Access type: read-only
1879  Description: Status of the [DBLTRANS] interrupt. The interrupt is set when a double transition has happened during QDEC mode.
1880 
1881  ENUMs:
1882  CLR: Cleared
1883  SET: Set
1884 */
1885 #define GPTIMER_RIS_DBLTRANS 0x00000004U
1886 #define GPTIMER_RIS_DBLTRANS_M 0x00000004U
1887 #define GPTIMER_RIS_DBLTRANS_S 2U
1888 #define GPTIMER_RIS_DBLTRANS_CLR 0x00000000U
1889 #define GPTIMER_RIS_DBLTRANS_SET 0x00000004U
1890 /*
1891 
1892  Field: CNTRCHNG
1893  From..to bits: 3...3
1894  DefaultValue: 0x0
1895  Access type: read-only
1896  Description: Status of the [CNTRCHNG] interrupt. The interrupt is set when the counter increments or decrements.
1897 
1898  ENUMs:
1899  CLR: Cleared
1900  SET: Set
1901 */
1902 #define GPTIMER_RIS_CNTRCHNG 0x00000008U
1903 #define GPTIMER_RIS_CNTRCHNG_M 0x00000008U
1904 #define GPTIMER_RIS_CNTRCHNG_S 3U
1905 #define GPTIMER_RIS_CNTRCHNG_CLR 0x00000000U
1906 #define GPTIMER_RIS_CNTRCHNG_SET 0x00000008U
1907 /*
1908 
1909  Field: DIRCHNG
1910  From..to bits: 4...4
1911  DefaultValue: 0x0
1912  Access type: read-only
1913  Description: Status of the [DIRCHNG] interrupt. The interrupt is set when the direction of the counter changes.
1914 
1915  ENUMs:
1916  CLR: Cleared
1917  SET: Set
1918 */
1919 #define GPTIMER_RIS_DIRCHNG 0x00000010U
1920 #define GPTIMER_RIS_DIRCHNG_M 0x00000010U
1921 #define GPTIMER_RIS_DIRCHNG_S 4U
1922 #define GPTIMER_RIS_DIRCHNG_CLR 0x00000000U
1923 #define GPTIMER_RIS_DIRCHNG_SET 0x00000010U
1924 /*
1925 
1926  Field: IDX
1927  From..to bits: 5...5
1928  DefaultValue: 0x0
1929  Access type: read-only
1930  Description: Status of the [IDX] interrupt. The interrupt is set when [IDX] is active.
1931 
1932  ENUMs:
1933  CLR: Cleared
1934  SET: Set
1935 */
1936 #define GPTIMER_RIS_IDX 0x00000020U
1937 #define GPTIMER_RIS_IDX_M 0x00000020U
1938 #define GPTIMER_RIS_IDX_S 5U
1939 #define GPTIMER_RIS_IDX_CLR 0x00000000U
1940 #define GPTIMER_RIS_IDX_SET 0x00000020U
1941 /*
1942 
1943  Field: FAULT
1944  From..to bits: 6...6
1945  DefaultValue: 0x0
1946  Access type: read-only
1947  Description: Status of the [FAULT] interrupt. The interrupt is set immediately on active fault input.
1948 
1949  ENUMs:
1950  CLR: Cleared
1951  SET: Set
1952 */
1953 #define GPTIMER_RIS_FAULT 0x00000040U
1954 #define GPTIMER_RIS_FAULT_M 0x00000040U
1955 #define GPTIMER_RIS_FAULT_S 6U
1956 #define GPTIMER_RIS_FAULT_CLR 0x00000000U
1957 #define GPTIMER_RIS_FAULT_SET 0x00000040U
1958 /*
1959 
1960  Field: C0CC
1961  From..to bits: 8...8
1962  DefaultValue: 0x0
1963  Access type: read-only
1964  Description: Status of the [C0CC] interrupt. The interrupt is set when [C0CC] has capture or compare event.
1965 
1966  ENUMs:
1967  CLR: Cleared
1968  SET: Set
1969 */
1970 #define GPTIMER_RIS_C0CC 0x00000100U
1971 #define GPTIMER_RIS_C0CC_M 0x00000100U
1972 #define GPTIMER_RIS_C0CC_S 8U
1973 #define GPTIMER_RIS_C0CC_CLR 0x00000000U
1974 #define GPTIMER_RIS_C0CC_SET 0x00000100U
1975 /*
1976 
1977  Field: C1CC
1978  From..to bits: 9...9
1979  DefaultValue: 0x0
1980  Access type: read-only
1981  Description: Status of the [C1CC] interrupt. The interrupt is set when [C1CC] has capture or compare event.
1982 
1983  ENUMs:
1984  CLR: Cleared
1985  SET: Set
1986 */
1987 #define GPTIMER_RIS_C1CC 0x00000200U
1988 #define GPTIMER_RIS_C1CC_M 0x00000200U
1989 #define GPTIMER_RIS_C1CC_S 9U
1990 #define GPTIMER_RIS_C1CC_CLR 0x00000000U
1991 #define GPTIMER_RIS_C1CC_SET 0x00000200U
1992 /*
1993 
1994  Field: C2CC
1995  From..to bits: 10...10
1996  DefaultValue: 0x0
1997  Access type: read-only
1998  Description: Status of the [C2CC] interrupt. The interrupt is set when [C2CC] has capture or compare event.
1999 
2000  ENUMs:
2001  CLR: Cleared
2002  SET: Set
2003 */
2004 #define GPTIMER_RIS_C2CC 0x00000400U
2005 #define GPTIMER_RIS_C2CC_M 0x00000400U
2006 #define GPTIMER_RIS_C2CC_S 10U
2007 #define GPTIMER_RIS_C2CC_CLR 0x00000000U
2008 #define GPTIMER_RIS_C2CC_SET 0x00000400U
2009 /*
2010 
2011  Field: C3CC
2012  From..to bits: 11...11
2013  DefaultValue: 0x0
2014  Access type: read-only
2015  Description: Status of the [C3CC] interrupt. The interrupt is set when [C3CC] has capture or compare event.
2016 
2017  ENUMs:
2018  DIS: Disable
2019  EN: Enable
2020 */
2021 #define GPTIMER_RIS_C3CC 0x00000800U
2022 #define GPTIMER_RIS_C3CC_M 0x00000800U
2023 #define GPTIMER_RIS_C3CC_S 11U
2024 #define GPTIMER_RIS_C3CC_DIS 0x00000000U
2025 #define GPTIMER_RIS_C3CC_EN 0x00000800U
2026 
2027 
2028 /*-----------------------------------REGISTER------------------------------------
2029  Register name: MIS
2030  Offset name: GPTIMER_O_MIS
2031  Relative address: 0x70
2032  Description: Masked interrupt status. This register is simply a bit-wise AND of the contents of [IMASK.*] and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding [ICLR.*] register bit.
2033  Default Value: 0x00000000
2034 
2035  Field: TGT
2036  From..to bits: 0...0
2037  DefaultValue: 0x0
2038  Access type: read-only
2039  Description: Masked status of the [RIS.TGT] interrupt.
2040 
2041  ENUMs:
2042  CLR: Cleared
2043  SET: Set
2044 */
2045 #define GPTIMER_MIS_TGT 0x00000001U
2046 #define GPTIMER_MIS_TGT_M 0x00000001U
2047 #define GPTIMER_MIS_TGT_S 0U
2048 #define GPTIMER_MIS_TGT_CLR 0x00000000U
2049 #define GPTIMER_MIS_TGT_SET 0x00000001U
2050 /*
2051 
2052  Field: ZERO
2053  From..to bits: 1...1
2054  DefaultValue: 0x0
2055  Access type: read-only
2056  Description: Masked status of the [RIS.ZERO] interrupt.
2057 
2058  ENUMs:
2059  CLR: Cleared
2060  SET: Set
2061 */
2062 #define GPTIMER_MIS_ZERO 0x00000002U
2063 #define GPTIMER_MIS_ZERO_M 0x00000002U
2064 #define GPTIMER_MIS_ZERO_S 1U
2065 #define GPTIMER_MIS_ZERO_CLR 0x00000000U
2066 #define GPTIMER_MIS_ZERO_SET 0x00000002U
2067 /*
2068 
2069  Field: DBLTRANS
2070  From..to bits: 2...2
2071  DefaultValue: 0x0
2072  Access type: read-only
2073  Description: Masked status of the [RIS.DBLTRANS] interrupt.
2074 
2075  ENUMs:
2076  CLR: Cleared
2077  SET: Set
2078 */
2079 #define GPTIMER_MIS_DBLTRANS 0x00000004U
2080 #define GPTIMER_MIS_DBLTRANS_M 0x00000004U
2081 #define GPTIMER_MIS_DBLTRANS_S 2U
2082 #define GPTIMER_MIS_DBLTRANS_CLR 0x00000000U
2083 #define GPTIMER_MIS_DBLTRANS_SET 0x00000004U
2084 /*
2085 
2086  Field: CNTRCHNG
2087  From..to bits: 3...3
2088  DefaultValue: 0x0
2089  Access type: read-only
2090  Description: Masked status of the [RIS.CNTRCHNG] interrupt.
2091 
2092  ENUMs:
2093  CLR: Cleared
2094  SET: Set
2095 */
2096 #define GPTIMER_MIS_CNTRCHNG 0x00000008U
2097 #define GPTIMER_MIS_CNTRCHNG_M 0x00000008U
2098 #define GPTIMER_MIS_CNTRCHNG_S 3U
2099 #define GPTIMER_MIS_CNTRCHNG_CLR 0x00000000U
2100 #define GPTIMER_MIS_CNTRCHNG_SET 0x00000008U
2101 /*
2102 
2103  Field: DIRCHNG
2104  From..to bits: 4...4
2105  DefaultValue: 0x0
2106  Access type: read-only
2107  Description: Masked status of the [RIS.DIRCHNG] interrupt.
2108 
2109  ENUMs:
2110  CLR: Cleared
2111  SET: Set
2112 */
2113 #define GPTIMER_MIS_DIRCHNG 0x00000010U
2114 #define GPTIMER_MIS_DIRCHNG_M 0x00000010U
2115 #define GPTIMER_MIS_DIRCHNG_S 4U
2116 #define GPTIMER_MIS_DIRCHNG_CLR 0x00000000U
2117 #define GPTIMER_MIS_DIRCHNG_SET 0x00000010U
2118 /*
2119 
2120  Field: IDX
2121  From..to bits: 5...5
2122  DefaultValue: 0x0
2123  Access type: read-only
2124  Description: Masked status of the [RIS.IDX] interrupt.
2125 
2126  ENUMs:
2127  CLR: Cleared
2128  SET: Set
2129 */
2130 #define GPTIMER_MIS_IDX 0x00000020U
2131 #define GPTIMER_MIS_IDX_M 0x00000020U
2132 #define GPTIMER_MIS_IDX_S 5U
2133 #define GPTIMER_MIS_IDX_CLR 0x00000000U
2134 #define GPTIMER_MIS_IDX_SET 0x00000020U
2135 /*
2136 
2137  Field: FAULT
2138  From..to bits: 6...6
2139  DefaultValue: 0x0
2140  Access type: read-only
2141  Description: Masked status of the [RIS.FAULT] interrupt.
2142 
2143  ENUMs:
2144  CLR: Cleared
2145  SET: Set
2146 */
2147 #define GPTIMER_MIS_FAULT 0x00000040U
2148 #define GPTIMER_MIS_FAULT_M 0x00000040U
2149 #define GPTIMER_MIS_FAULT_S 6U
2150 #define GPTIMER_MIS_FAULT_CLR 0x00000000U
2151 #define GPTIMER_MIS_FAULT_SET 0x00000040U
2152 /*
2153 
2154  Field: C0CC
2155  From..to bits: 8...8
2156  DefaultValue: 0x0
2157  Access type: read-only
2158  Description: Masked status of the [RIS.C0CC] interrupt.
2159 
2160  ENUMs:
2161  CLR: Cleared
2162  SET: Set
2163 */
2164 #define GPTIMER_MIS_C0CC 0x00000100U
2165 #define GPTIMER_MIS_C0CC_M 0x00000100U
2166 #define GPTIMER_MIS_C0CC_S 8U
2167 #define GPTIMER_MIS_C0CC_CLR 0x00000000U
2168 #define GPTIMER_MIS_C0CC_SET 0x00000100U
2169 /*
2170 
2171  Field: C1CC
2172  From..to bits: 9...9
2173  DefaultValue: 0x0
2174  Access type: read-only
2175  Description: Masked status of the [RIS.C1CC] interrupt.
2176 
2177  ENUMs:
2178  CLR: Cleared
2179  SET: Set
2180 */
2181 #define GPTIMER_MIS_C1CC 0x00000200U
2182 #define GPTIMER_MIS_C1CC_M 0x00000200U
2183 #define GPTIMER_MIS_C1CC_S 9U
2184 #define GPTIMER_MIS_C1CC_CLR 0x00000000U
2185 #define GPTIMER_MIS_C1CC_SET 0x00000200U
2186 /*
2187 
2188  Field: C2CC
2189  From..to bits: 10...10
2190  DefaultValue: 0x0
2191  Access type: read-only
2192  Description: Masked status of the [RIS.C2CC] interrupt.
2193 
2194  ENUMs:
2195  CLR: Cleared
2196  SET: Set
2197 */
2198 #define GPTIMER_MIS_C2CC 0x00000400U
2199 #define GPTIMER_MIS_C2CC_M 0x00000400U
2200 #define GPTIMER_MIS_C2CC_S 10U
2201 #define GPTIMER_MIS_C2CC_CLR 0x00000000U
2202 #define GPTIMER_MIS_C2CC_SET 0x00000400U
2203 /*
2204 
2205  Field: C3CC
2206  From..to bits: 11...11
2207  DefaultValue: 0x0
2208  Access type: read-only
2209  Description: Masked status of the [RIS.C3CC] interrupt.
2210 
2211  ENUMs:
2212  CLR: Cleared
2213  SET: Set
2214 */
2215 #define GPTIMER_MIS_C3CC 0x00000800U
2216 #define GPTIMER_MIS_C3CC_M 0x00000800U
2217 #define GPTIMER_MIS_C3CC_S 11U
2218 #define GPTIMER_MIS_C3CC_CLR 0x00000000U
2219 #define GPTIMER_MIS_C3CC_SET 0x00000800U
2220 
2221 
2222 /*-----------------------------------REGISTER------------------------------------
2223  Register name: ISET
2224  Offset name: GPTIMER_O_ISET
2225  Relative address: 0x74
2226  Description: Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding [RIS.*] bit also gets set. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets set.
2227  Default Value: 0x00000000
2228 
2229  Field: TGT
2230  From..to bits: 0...0
2231  DefaultValue: 0x0
2232  Access type: write-only
2233  Description: Set the [RIS.TGT] interrupt.
2234 
2235  ENUMs:
2236  NO_EFFECT: No effect
2237  SET: Set
2238 */
2239 #define GPTIMER_ISET_TGT 0x00000001U
2240 #define GPTIMER_ISET_TGT_M 0x00000001U
2241 #define GPTIMER_ISET_TGT_S 0U
2242 #define GPTIMER_ISET_TGT_NO_EFFECT 0x00000000U
2243 #define GPTIMER_ISET_TGT_SET 0x00000001U
2244 /*
2245 
2246  Field: ZERO
2247  From..to bits: 1...1
2248  DefaultValue: 0x0
2249  Access type: write-only
2250  Description: Set the [RIS.ZERO] interrupt.
2251 
2252  ENUMs:
2253  NO_EFFECT: No effect
2254  SET: Set
2255 */
2256 #define GPTIMER_ISET_ZERO 0x00000002U
2257 #define GPTIMER_ISET_ZERO_M 0x00000002U
2258 #define GPTIMER_ISET_ZERO_S 1U
2259 #define GPTIMER_ISET_ZERO_NO_EFFECT 0x00000000U
2260 #define GPTIMER_ISET_ZERO_SET 0x00000002U
2261 /*
2262 
2263  Field: DBLTRANS
2264  From..to bits: 2...2
2265  DefaultValue: 0x0
2266  Access type: write-only
2267  Description: Set the [RIS.DBLTRANS] interrupt.
2268 
2269  ENUMs:
2270  NO_EFFECT: No effect
2271  SET: Set
2272 */
2273 #define GPTIMER_ISET_DBLTRANS 0x00000004U
2274 #define GPTIMER_ISET_DBLTRANS_M 0x00000004U
2275 #define GPTIMER_ISET_DBLTRANS_S 2U
2276 #define GPTIMER_ISET_DBLTRANS_NO_EFFECT 0x00000000U
2277 #define GPTIMER_ISET_DBLTRANS_SET 0x00000004U
2278 /*
2279 
2280  Field: CNTRCHNG
2281  From..to bits: 3...3
2282  DefaultValue: 0x0
2283  Access type: write-only
2284  Description: Set the [RIS.CNTRCHNG] interrupt.
2285 
2286  ENUMs:
2287  NO_EFFECT: No effect
2288  SET: Set
2289 */
2290 #define GPTIMER_ISET_CNTRCHNG 0x00000008U
2291 #define GPTIMER_ISET_CNTRCHNG_M 0x00000008U
2292 #define GPTIMER_ISET_CNTRCHNG_S 3U
2293 #define GPTIMER_ISET_CNTRCHNG_NO_EFFECT 0x00000000U
2294 #define GPTIMER_ISET_CNTRCHNG_SET 0x00000008U
2295 /*
2296 
2297  Field: DIRCHNG
2298  From..to bits: 4...4
2299  DefaultValue: 0x0
2300  Access type: write-only
2301  Description: Set the [RIS.DIRCHNG] interrupt.
2302 
2303  ENUMs:
2304  NO_EFFECT: No effect
2305  SET: Set
2306 */
2307 #define GPTIMER_ISET_DIRCHNG 0x00000010U
2308 #define GPTIMER_ISET_DIRCHNG_M 0x00000010U
2309 #define GPTIMER_ISET_DIRCHNG_S 4U
2310 #define GPTIMER_ISET_DIRCHNG_NO_EFFECT 0x00000000U
2311 #define GPTIMER_ISET_DIRCHNG_SET 0x00000010U
2312 /*
2313 
2314  Field: IDX
2315  From..to bits: 5...5
2316  DefaultValue: 0x0
2317  Access type: write-only
2318  Description: Set the [RIS.IDX] interrupt.
2319 
2320  ENUMs:
2321  NO_EFFECT: No effect
2322  SET: Set
2323 */
2324 #define GPTIMER_ISET_IDX 0x00000020U
2325 #define GPTIMER_ISET_IDX_M 0x00000020U
2326 #define GPTIMER_ISET_IDX_S 5U
2327 #define GPTIMER_ISET_IDX_NO_EFFECT 0x00000000U
2328 #define GPTIMER_ISET_IDX_SET 0x00000020U
2329 /*
2330 
2331  Field: FAULT
2332  From..to bits: 6...6
2333  DefaultValue: 0x0
2334  Access type: write-only
2335  Description: Set the [RIS.FAULT] interrupt.
2336 
2337  ENUMs:
2338  NO_EFFECT: No effect
2339  SET: Set
2340 */
2341 #define GPTIMER_ISET_FAULT 0x00000040U
2342 #define GPTIMER_ISET_FAULT_M 0x00000040U
2343 #define GPTIMER_ISET_FAULT_S 6U
2344 #define GPTIMER_ISET_FAULT_NO_EFFECT 0x00000000U
2345 #define GPTIMER_ISET_FAULT_SET 0x00000040U
2346 /*
2347 
2348  Field: C0CC
2349  From..to bits: 8...8
2350  DefaultValue: 0x0
2351  Access type: write-only
2352  Description: Set the [RIS.C0CC] interrupt.
2353 
2354  ENUMs:
2355  NO_EFFECT: No effect
2356  SET: Set
2357 */
2358 #define GPTIMER_ISET_C0CC 0x00000100U
2359 #define GPTIMER_ISET_C0CC_M 0x00000100U
2360 #define GPTIMER_ISET_C0CC_S 8U
2361 #define GPTIMER_ISET_C0CC_NO_EFFECT 0x00000000U
2362 #define GPTIMER_ISET_C0CC_SET 0x00000100U
2363 /*
2364 
2365  Field: C1CC
2366  From..to bits: 9...9
2367  DefaultValue: 0x0
2368  Access type: write-only
2369  Description: Set the [RIS.C1CC] interrupt.
2370 
2371  ENUMs:
2372  NO_EFFECT: No effect
2373  SET: Set
2374 */
2375 #define GPTIMER_ISET_C1CC 0x00000200U
2376 #define GPTIMER_ISET_C1CC_M 0x00000200U
2377 #define GPTIMER_ISET_C1CC_S 9U
2378 #define GPTIMER_ISET_C1CC_NO_EFFECT 0x00000000U
2379 #define GPTIMER_ISET_C1CC_SET 0x00000200U
2380 /*
2381 
2382  Field: C2CC
2383  From..to bits: 10...10
2384  DefaultValue: 0x0
2385  Access type: write-only
2386  Description: Set the [RIS.C2CC] interrupt.
2387 
2388  ENUMs:
2389  NO_EFFECT: No effect
2390  SET: Set
2391 */
2392 #define GPTIMER_ISET_C2CC 0x00000400U
2393 #define GPTIMER_ISET_C2CC_M 0x00000400U
2394 #define GPTIMER_ISET_C2CC_S 10U
2395 #define GPTIMER_ISET_C2CC_NO_EFFECT 0x00000000U
2396 #define GPTIMER_ISET_C2CC_SET 0x00000400U
2397 /*
2398 
2399  Field: C3CC
2400  From..to bits: 11...11
2401  DefaultValue: 0x0
2402  Access type: write-only
2403  Description: Set the [RIS.C3CC] interrupt.
2404 
2405  ENUMs:
2406  NO_EFFECT: No effect
2407  SET: Set
2408 */
2409 #define GPTIMER_ISET_C3CC 0x00000800U
2410 #define GPTIMER_ISET_C3CC_M 0x00000800U
2411 #define GPTIMER_ISET_C3CC_S 11U
2412 #define GPTIMER_ISET_C3CC_NO_EFFECT 0x00000000U
2413 #define GPTIMER_ISET_C3CC_SET 0x00000800U
2414 
2415 
2416 /*-----------------------------------REGISTER------------------------------------
2417  Register name: ICLR
2418  Offset name: GPTIMER_O_ICLR
2419  Relative address: 0x78
2420  Description: Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding [RIS.*] bit also gets cleared. If the corresponding [IMASK.*] bit is set, then the corresponding [MIS.*] register bit also gets cleared.
2421  Default Value: 0x00000000
2422 
2423  Field: TGT
2424  From..to bits: 0...0
2425  DefaultValue: 0x0
2426  Access type: write-only
2427  Description: Clear the [RIS.TGT] interrupt.
2428 
2429  ENUMs:
2430  NO_EFFECT: No effect
2431  CLR: Clear
2432 */
2433 #define GPTIMER_ICLR_TGT 0x00000001U
2434 #define GPTIMER_ICLR_TGT_M 0x00000001U
2435 #define GPTIMER_ICLR_TGT_S 0U
2436 #define GPTIMER_ICLR_TGT_NO_EFFECT 0x00000000U
2437 #define GPTIMER_ICLR_TGT_CLR 0x00000001U
2438 /*
2439 
2440  Field: ZERO
2441  From..to bits: 1...1
2442  DefaultValue: 0x0
2443  Access type: write-only
2444  Description: Clear the [RIS.ZERO] interrupt.
2445 
2446  ENUMs:
2447  NO_EFFECT: No effect
2448  CLR: Clear
2449 */
2450 #define GPTIMER_ICLR_ZERO 0x00000002U
2451 #define GPTIMER_ICLR_ZERO_M 0x00000002U
2452 #define GPTIMER_ICLR_ZERO_S 1U
2453 #define GPTIMER_ICLR_ZERO_NO_EFFECT 0x00000000U
2454 #define GPTIMER_ICLR_ZERO_CLR 0x00000002U
2455 /*
2456 
2457  Field: DBLTRANS
2458  From..to bits: 2...2
2459  DefaultValue: 0x0
2460  Access type: write-only
2461  Description: Clear the [RIS.DBLTRANS] interrupt.
2462 
2463  ENUMs:
2464  NO_EFFECT: No effect
2465  CLR: Clear
2466 */
2467 #define GPTIMER_ICLR_DBLTRANS 0x00000004U
2468 #define GPTIMER_ICLR_DBLTRANS_M 0x00000004U
2469 #define GPTIMER_ICLR_DBLTRANS_S 2U
2470 #define GPTIMER_ICLR_DBLTRANS_NO_EFFECT 0x00000000U
2471 #define GPTIMER_ICLR_DBLTRANS_CLR 0x00000004U
2472 /*
2473 
2474  Field: CNTRCHNG
2475  From..to bits: 3...3
2476  DefaultValue: 0x0
2477  Access type: write-only
2478  Description: Clear the [RIS.CNTRCHNG] interrupt.
2479 
2480  ENUMs:
2481  NO_EFFECT: No effect
2482  CLR: Clear
2483 */
2484 #define GPTIMER_ICLR_CNTRCHNG 0x00000008U
2485 #define GPTIMER_ICLR_CNTRCHNG_M 0x00000008U
2486 #define GPTIMER_ICLR_CNTRCHNG_S 3U
2487 #define GPTIMER_ICLR_CNTRCHNG_NO_EFFECT 0x00000000U
2488 #define GPTIMER_ICLR_CNTRCHNG_CLR 0x00000008U
2489 /*
2490 
2491  Field: DIRCHNG
2492  From..to bits: 4...4
2493  DefaultValue: 0x0
2494  Access type: write-only
2495  Description: Clear the [RIS.DIRCHNG] interrupt.
2496 
2497  ENUMs:
2498  NO_EFFECT: No effect
2499  CLR: Clear
2500 */
2501 #define GPTIMER_ICLR_DIRCHNG 0x00000010U
2502 #define GPTIMER_ICLR_DIRCHNG_M 0x00000010U
2503 #define GPTIMER_ICLR_DIRCHNG_S 4U
2504 #define GPTIMER_ICLR_DIRCHNG_NO_EFFECT 0x00000000U
2505 #define GPTIMER_ICLR_DIRCHNG_CLR 0x00000010U
2506 /*
2507 
2508  Field: IDX
2509  From..to bits: 5...5
2510  DefaultValue: 0x0
2511  Access type: write-only
2512  Description: Clear the [RIS.IDX] interrupt.
2513 
2514  ENUMs:
2515  NO_EFFECT: No effect
2516  CLR: Clear
2517 */
2518 #define GPTIMER_ICLR_IDX 0x00000020U
2519 #define GPTIMER_ICLR_IDX_M 0x00000020U
2520 #define GPTIMER_ICLR_IDX_S 5U
2521 #define GPTIMER_ICLR_IDX_NO_EFFECT 0x00000000U
2522 #define GPTIMER_ICLR_IDX_CLR 0x00000020U
2523 /*
2524 
2525  Field: FAULT
2526  From..to bits: 6...6
2527  DefaultValue: 0x0
2528  Access type: write-only
2529  Description: Clear the [RIS.FAULT] interrupt.
2530 
2531  ENUMs:
2532  NO_EFFECT: No effect
2533  CLR: Clear
2534 */
2535 #define GPTIMER_ICLR_FAULT 0x00000040U
2536 #define GPTIMER_ICLR_FAULT_M 0x00000040U
2537 #define GPTIMER_ICLR_FAULT_S 6U
2538 #define GPTIMER_ICLR_FAULT_NO_EFFECT 0x00000000U
2539 #define GPTIMER_ICLR_FAULT_CLR 0x00000040U
2540 /*
2541 
2542  Field: C0CC
2543  From..to bits: 8...8
2544  DefaultValue: 0x0
2545  Access type: write-only
2546  Description: Clear the [RIS.C0CC] interrupt.
2547 
2548  ENUMs:
2549  NO_EFFECT: No effect
2550  CLR: Clear
2551 */
2552 #define GPTIMER_ICLR_C0CC 0x00000100U
2553 #define GPTIMER_ICLR_C0CC_M 0x00000100U
2554 #define GPTIMER_ICLR_C0CC_S 8U
2555 #define GPTIMER_ICLR_C0CC_NO_EFFECT 0x00000000U
2556 #define GPTIMER_ICLR_C0CC_CLR 0x00000100U
2557 /*
2558 
2559  Field: C1CC
2560  From..to bits: 9...9
2561  DefaultValue: 0x0
2562  Access type: write-only
2563  Description: Clear the [RIS.C1CC] interrupt.
2564 
2565  ENUMs:
2566  NO_EFFECT: No effect
2567  CLR: Clear
2568 */
2569 #define GPTIMER_ICLR_C1CC 0x00000200U
2570 #define GPTIMER_ICLR_C1CC_M 0x00000200U
2571 #define GPTIMER_ICLR_C1CC_S 9U
2572 #define GPTIMER_ICLR_C1CC_NO_EFFECT 0x00000000U
2573 #define GPTIMER_ICLR_C1CC_CLR 0x00000200U
2574 /*
2575 
2576  Field: C2CC
2577  From..to bits: 10...10
2578  DefaultValue: 0x0
2579  Access type: write-only
2580  Description: Clear the [RIS.C2CC] interrupt.
2581 
2582  ENUMs:
2583  NO_EFFECT: No effect
2584  CLR: Clear
2585 */
2586 #define GPTIMER_ICLR_C2CC 0x00000400U
2587 #define GPTIMER_ICLR_C2CC_M 0x00000400U
2588 #define GPTIMER_ICLR_C2CC_S 10U
2589 #define GPTIMER_ICLR_C2CC_NO_EFFECT 0x00000000U
2590 #define GPTIMER_ICLR_C2CC_CLR 0x00000400U
2591 /*
2592 
2593  Field: C3CC
2594  From..to bits: 11...11
2595  DefaultValue: 0x0
2596  Access type: write-only
2597  Description: Clear the [RIS.C3CC] interrupt.
2598 
2599  ENUMs:
2600  NO_EFFECT: No effect
2601  CLR: Clear
2602 */
2603 #define GPTIMER_ICLR_C3CC 0x00000800U
2604 #define GPTIMER_ICLR_C3CC_M 0x00000800U
2605 #define GPTIMER_ICLR_C3CC_S 11U
2606 #define GPTIMER_ICLR_C3CC_NO_EFFECT 0x00000000U
2607 #define GPTIMER_ICLR_C3CC_CLR 0x00000800U
2608 
2609 
2610 /*-----------------------------------REGISTER------------------------------------
2611  Register name: IMSET
2612  Offset name: GPTIMER_O_IMSET
2613  Relative address: 0x7C
2614  Description: Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding [IMASK.*] bit.
2615  Default Value: 0x00000000
2616 
2617  Field: TGT
2618  From..to bits: 0...0
2619  DefaultValue: 0x0
2620  Access type: write-only
2621  Description: Set the [MIS.TGT] mask.
2622 
2623  ENUMs:
2624  NO_EFFECT: No effect
2625  SET: Set
2626 */
2627 #define GPTIMER_IMSET_TGT 0x00000001U
2628 #define GPTIMER_IMSET_TGT_M 0x00000001U
2629 #define GPTIMER_IMSET_TGT_S 0U
2630 #define GPTIMER_IMSET_TGT_NO_EFFECT 0x00000000U
2631 #define GPTIMER_IMSET_TGT_SET 0x00000001U
2632 /*
2633 
2634  Field: ZERO
2635  From..to bits: 1...1
2636  DefaultValue: 0x0
2637  Access type: write-only
2638  Description: Set the [MIS.ZERO] mask.
2639 
2640  ENUMs:
2641  NO_EFFECT: No effect
2642  SET: Set
2643 */
2644 #define GPTIMER_IMSET_ZERO 0x00000002U
2645 #define GPTIMER_IMSET_ZERO_M 0x00000002U
2646 #define GPTIMER_IMSET_ZERO_S 1U
2647 #define GPTIMER_IMSET_ZERO_NO_EFFECT 0x00000000U
2648 #define GPTIMER_IMSET_ZERO_SET 0x00000002U
2649 /*
2650 
2651  Field: DBLTRANS
2652  From..to bits: 2...2
2653  DefaultValue: 0x0
2654  Access type: write-only
2655  Description: Set the [MIS.DBLTRANS] mask.
2656 
2657  ENUMs:
2658  NO_EFFECT: No effect
2659  SET: Set
2660 */
2661 #define GPTIMER_IMSET_DBLTRANS 0x00000004U
2662 #define GPTIMER_IMSET_DBLTRANS_M 0x00000004U
2663 #define GPTIMER_IMSET_DBLTRANS_S 2U
2664 #define GPTIMER_IMSET_DBLTRANS_NO_EFFECT 0x00000000U
2665 #define GPTIMER_IMSET_DBLTRANS_SET 0x00000004U
2666 /*
2667 
2668  Field: CNTRCHNG
2669  From..to bits: 3...3
2670  DefaultValue: 0x0
2671  Access type: write-only
2672  Description: Set the [MIS.CNTRCHNG] mask.
2673 
2674  ENUMs:
2675  NO_EFFECT: No effect
2676  SET: Set
2677 */
2678 #define GPTIMER_IMSET_CNTRCHNG 0x00000008U
2679 #define GPTIMER_IMSET_CNTRCHNG_M 0x00000008U
2680 #define GPTIMER_IMSET_CNTRCHNG_S 3U
2681 #define GPTIMER_IMSET_CNTRCHNG_NO_EFFECT 0x00000000U
2682 #define GPTIMER_IMSET_CNTRCHNG_SET 0x00000008U
2683 /*
2684 
2685  Field: DIRCHNG
2686  From..to bits: 4...4
2687  DefaultValue: 0x0
2688  Access type: write-only
2689  Description: Set the [MIS.DIRCHNG] mask.
2690 
2691  ENUMs:
2692  NO_EFFECT: No effect
2693  SET: Set
2694 */
2695 #define GPTIMER_IMSET_DIRCHNG 0x00000010U
2696 #define GPTIMER_IMSET_DIRCHNG_M 0x00000010U
2697 #define GPTIMER_IMSET_DIRCHNG_S 4U
2698 #define GPTIMER_IMSET_DIRCHNG_NO_EFFECT 0x00000000U
2699 #define GPTIMER_IMSET_DIRCHNG_SET 0x00000010U
2700 /*
2701 
2702  Field: IDX
2703  From..to bits: 5...5
2704  DefaultValue: 0x0
2705  Access type: write-only
2706  Description: Set the [MIS.IDX] mask.
2707 
2708  ENUMs:
2709  NO_EFFECT: No effect
2710  SET: Set
2711 */
2712 #define GPTIMER_IMSET_IDX 0x00000020U
2713 #define GPTIMER_IMSET_IDX_M 0x00000020U
2714 #define GPTIMER_IMSET_IDX_S 5U
2715 #define GPTIMER_IMSET_IDX_NO_EFFECT 0x00000000U
2716 #define GPTIMER_IMSET_IDX_SET 0x00000020U
2717 /*
2718 
2719  Field: FAULT
2720  From..to bits: 6...6
2721  DefaultValue: 0x0
2722  Access type: write-only
2723  Description: Set the [MIS.FAULT] mask.
2724 
2725  ENUMs:
2726  NO_EFFECT: No effect
2727  SET: Set
2728 */
2729 #define GPTIMER_IMSET_FAULT 0x00000040U
2730 #define GPTIMER_IMSET_FAULT_M 0x00000040U
2731 #define GPTIMER_IMSET_FAULT_S 6U
2732 #define GPTIMER_IMSET_FAULT_NO_EFFECT 0x00000000U
2733 #define GPTIMER_IMSET_FAULT_SET 0x00000040U
2734 /*
2735 
2736  Field: C0CC
2737  From..to bits: 8...8
2738  DefaultValue: 0x0
2739  Access type: write-only
2740  Description: Set the [MIS.C0CC] mask.
2741 
2742  ENUMs:
2743  NO_EFFECT: No effect
2744  SET: Set
2745 */
2746 #define GPTIMER_IMSET_C0CC 0x00000100U
2747 #define GPTIMER_IMSET_C0CC_M 0x00000100U
2748 #define GPTIMER_IMSET_C0CC_S 8U
2749 #define GPTIMER_IMSET_C0CC_NO_EFFECT 0x00000000U
2750 #define GPTIMER_IMSET_C0CC_SET 0x00000100U
2751 /*
2752 
2753  Field: C1CC
2754  From..to bits: 9...9
2755  DefaultValue: 0x0
2756  Access type: write-only
2757  Description: Set the [MIS.C1CC] mask.
2758 
2759  ENUMs:
2760  NO_EFFECT: No effect
2761  SET: Set
2762 */
2763 #define GPTIMER_IMSET_C1CC 0x00000200U
2764 #define GPTIMER_IMSET_C1CC_M 0x00000200U
2765 #define GPTIMER_IMSET_C1CC_S 9U
2766 #define GPTIMER_IMSET_C1CC_NO_EFFECT 0x00000000U
2767 #define GPTIMER_IMSET_C1CC_SET 0x00000200U
2768 /*
2769 
2770  Field: C2CC
2771  From..to bits: 10...10
2772  DefaultValue: 0x0
2773  Access type: write-only
2774  Description: Set the [MIS.C2CC] mask.
2775 
2776  ENUMs:
2777  NO_EFFECT: No effect
2778  SET: Set
2779 */
2780 #define GPTIMER_IMSET_C2CC 0x00000400U
2781 #define GPTIMER_IMSET_C2CC_M 0x00000400U
2782 #define GPTIMER_IMSET_C2CC_S 10U
2783 #define GPTIMER_IMSET_C2CC_NO_EFFECT 0x00000000U
2784 #define GPTIMER_IMSET_C2CC_SET 0x00000400U
2785 /*
2786 
2787  Field: C3CC
2788  From..to bits: 11...11
2789  DefaultValue: 0x0
2790  Access type: write-only
2791  Description: Set the [MIS.C3CC] mask.
2792 
2793  ENUMs:
2794  NO_EFFECT: No effect
2795  SET: Set
2796 */
2797 #define GPTIMER_IMSET_C3CC 0x00000800U
2798 #define GPTIMER_IMSET_C3CC_M 0x00000800U
2799 #define GPTIMER_IMSET_C3CC_S 11U
2800 #define GPTIMER_IMSET_C3CC_NO_EFFECT 0x00000000U
2801 #define GPTIMER_IMSET_C3CC_SET 0x00000800U
2802 
2803 
2804 /*-----------------------------------REGISTER------------------------------------
2805  Register name: IMCLR
2806  Offset name: GPTIMER_O_IMCLR
2807  Relative address: 0x80
2808  Description: Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding [IMASK.*] bit.
2809  Default Value: 0x00000000
2810 
2811  Field: TGT
2812  From..to bits: 0...0
2813  DefaultValue: 0x0
2814  Access type: write-only
2815  Description: Clear the [MIS.TGT] mask.
2816 
2817  ENUMs:
2818  NO_EFFECT: No effect
2819  CLR: Clear
2820 */
2821 #define GPTIMER_IMCLR_TGT 0x00000001U
2822 #define GPTIMER_IMCLR_TGT_M 0x00000001U
2823 #define GPTIMER_IMCLR_TGT_S 0U
2824 #define GPTIMER_IMCLR_TGT_NO_EFFECT 0x00000000U
2825 #define GPTIMER_IMCLR_TGT_CLR 0x00000001U
2826 /*
2827 
2828  Field: ZERO
2829  From..to bits: 1...1
2830  DefaultValue: 0x0
2831  Access type: write-only
2832  Description: Clear the [MIS.ZERO] mask.
2833 
2834  ENUMs:
2835  NO_EFFECT: No effect
2836  CLR: Clear
2837 */
2838 #define GPTIMER_IMCLR_ZERO 0x00000002U
2839 #define GPTIMER_IMCLR_ZERO_M 0x00000002U
2840 #define GPTIMER_IMCLR_ZERO_S 1U
2841 #define GPTIMER_IMCLR_ZERO_NO_EFFECT 0x00000000U
2842 #define GPTIMER_IMCLR_ZERO_CLR 0x00000002U
2843 /*
2844 
2845  Field: DBLTRANS
2846  From..to bits: 2...2
2847  DefaultValue: 0x0
2848  Access type: write-only
2849  Description: Clear the [MIS.DBLTRANS] mask.
2850 
2851  ENUMs:
2852  NO_EFFECT: No effect
2853  CLR: Clear
2854 */
2855 #define GPTIMER_IMCLR_DBLTRANS 0x00000004U
2856 #define GPTIMER_IMCLR_DBLTRANS_M 0x00000004U
2857 #define GPTIMER_IMCLR_DBLTRANS_S 2U
2858 #define GPTIMER_IMCLR_DBLTRANS_NO_EFFECT 0x00000000U
2859 #define GPTIMER_IMCLR_DBLTRANS_CLR 0x00000004U
2860 /*
2861 
2862  Field: CNTRCHNG
2863  From..to bits: 3...3
2864  DefaultValue: 0x0
2865  Access type: write-only
2866  Description: Clear the [MIS.CNTRCHNG] mask.
2867 
2868  ENUMs:
2869  NO_EFFECT: No effect
2870  CLR: Clear
2871 */
2872 #define GPTIMER_IMCLR_CNTRCHNG 0x00000008U
2873 #define GPTIMER_IMCLR_CNTRCHNG_M 0x00000008U
2874 #define GPTIMER_IMCLR_CNTRCHNG_S 3U
2875 #define GPTIMER_IMCLR_CNTRCHNG_NO_EFFECT 0x00000000U
2876 #define GPTIMER_IMCLR_CNTRCHNG_CLR 0x00000008U
2877 /*
2878 
2879  Field: DIRCHNG
2880  From..to bits: 4...4
2881  DefaultValue: 0x0
2882  Access type: write-only
2883  Description: Clear the [MIS.DIRCHNG] mask.
2884 
2885  ENUMs:
2886  NO_EFFECT: No effect
2887  CLR: Clear
2888 */
2889 #define GPTIMER_IMCLR_DIRCHNG 0x00000010U
2890 #define GPTIMER_IMCLR_DIRCHNG_M 0x00000010U
2891 #define GPTIMER_IMCLR_DIRCHNG_S 4U
2892 #define GPTIMER_IMCLR_DIRCHNG_NO_EFFECT 0x00000000U
2893 #define GPTIMER_IMCLR_DIRCHNG_CLR 0x00000010U
2894 /*
2895 
2896  Field: IDX
2897  From..to bits: 5...5
2898  DefaultValue: 0x0
2899  Access type: write-only
2900  Description: Clear the [MIS.IDX] mask.
2901 
2902  ENUMs:
2903  NO_EFFECT: No effect
2904  CLR: Clear
2905 */
2906 #define GPTIMER_IMCLR_IDX 0x00000020U
2907 #define GPTIMER_IMCLR_IDX_M 0x00000020U
2908 #define GPTIMER_IMCLR_IDX_S 5U
2909 #define GPTIMER_IMCLR_IDX_NO_EFFECT 0x00000000U
2910 #define GPTIMER_IMCLR_IDX_CLR 0x00000020U
2911 /*
2912 
2913  Field: FAULT
2914  From..to bits: 6...6
2915  DefaultValue: 0x0
2916  Access type: write-only
2917  Description: Clear the [MIS.FAULT] mask.
2918 
2919  ENUMs:
2920  NO_EFFECT: No effect
2921  CLR: Clear
2922 */
2923 #define GPTIMER_IMCLR_FAULT 0x00000040U
2924 #define GPTIMER_IMCLR_FAULT_M 0x00000040U
2925 #define GPTIMER_IMCLR_FAULT_S 6U
2926 #define GPTIMER_IMCLR_FAULT_NO_EFFECT 0x00000000U
2927 #define GPTIMER_IMCLR_FAULT_CLR 0x00000040U
2928 /*
2929 
2930  Field: C0CC
2931  From..to bits: 8...8
2932  DefaultValue: 0x0
2933  Access type: write-only
2934  Description: Clear the [MIS.C0CC] mask.
2935 
2936  ENUMs:
2937  NO_EFFECT: No effect
2938  CLR: Clear
2939 */
2940 #define GPTIMER_IMCLR_C0CC 0x00000100U
2941 #define GPTIMER_IMCLR_C0CC_M 0x00000100U
2942 #define GPTIMER_IMCLR_C0CC_S 8U
2943 #define GPTIMER_IMCLR_C0CC_NO_EFFECT 0x00000000U
2944 #define GPTIMER_IMCLR_C0CC_CLR 0x00000100U
2945 /*
2946 
2947  Field: C1CC
2948  From..to bits: 9...9
2949  DefaultValue: 0x0
2950  Access type: write-only
2951  Description: Clear the [MIS.C1CC] mask.
2952 
2953  ENUMs:
2954  NO_EFFECT: No effect
2955  CLR: Clear
2956 */
2957 #define GPTIMER_IMCLR_C1CC 0x00000200U
2958 #define GPTIMER_IMCLR_C1CC_M 0x00000200U
2959 #define GPTIMER_IMCLR_C1CC_S 9U
2960 #define GPTIMER_IMCLR_C1CC_NO_EFFECT 0x00000000U
2961 #define GPTIMER_IMCLR_C1CC_CLR 0x00000200U
2962 /*
2963 
2964  Field: C2CC
2965  From..to bits: 10...10
2966  DefaultValue: 0x0
2967  Access type: write-only
2968  Description: Clear the [MIS.C2CC] mask.
2969 
2970  ENUMs:
2971  NO_EFFECT: No effect
2972  CLR: Clear
2973 */
2974 #define GPTIMER_IMCLR_C2CC 0x00000400U
2975 #define GPTIMER_IMCLR_C2CC_M 0x00000400U
2976 #define GPTIMER_IMCLR_C2CC_S 10U
2977 #define GPTIMER_IMCLR_C2CC_NO_EFFECT 0x00000000U
2978 #define GPTIMER_IMCLR_C2CC_CLR 0x00000400U
2979 /*
2980 
2981  Field: C3CC
2982  From..to bits: 11...11
2983  DefaultValue: 0x0
2984  Access type: write-only
2985  Description: Clear the [MIS.C3CC] mask.
2986 
2987  ENUMs:
2988  NO_EFFECT: No effect
2989  CLR: Clear
2990 */
2991 #define GPTIMER_IMCLR_C3CC 0x00000800U
2992 #define GPTIMER_IMCLR_C3CC_M 0x00000800U
2993 #define GPTIMER_IMCLR_C3CC_S 11U
2994 #define GPTIMER_IMCLR_C3CC_NO_EFFECT 0x00000000U
2995 #define GPTIMER_IMCLR_C3CC_CLR 0x00000800U
2996 
2997 
2998 /*-----------------------------------REGISTER------------------------------------
2999  Register name: EMU
3000  Offset name: GPTIMER_O_EMU
3001  Relative address: 0x84
3002  Description: Debug control
3003 
3004  This register can be used to freeze the timer when CPU halts when [HALT] is set to 1. When [HALT] is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, [PARK.*], if the timer has this register, should be configured additionally. If this timer does not have the [PARK.*] register a predefined output value during CPU halt is not possible.
3005  Default Value: 0x00000000
3006 
3007  Field: HALT
3008  From..to bits: 0...0
3009  DefaultValue: 0x0
3010  Access type: read-write
3011  Description: Halt LGPT when CPU is halted in debug.
3012 
3013  ENUMs:
3014  DIS: Disable.
3015  EN: Enable.
3016 */
3017 #define GPTIMER_EMU_HALT 0x00000001U
3018 #define GPTIMER_EMU_HALT_M 0x00000001U
3019 #define GPTIMER_EMU_HALT_S 0U
3020 #define GPTIMER_EMU_HALT_DIS 0x00000000U
3021 #define GPTIMER_EMU_HALT_EN 0x00000001U
3022 /*
3023 
3024  Field: CTL
3025  From..to bits: 1...1
3026  DefaultValue: 0x0
3027  Access type: read-write
3028  Description: Halt control.
3029 
3030  Configure when the counter shall stop upon CPU halt. This bitfield only applies if [HALT] = 1.
3031 
3032  ENUMs:
3033  IMMEDIATE: Immediate reaction. The counter stops immediately on debug halt.
3034  ZERCOND: Zero condition. The counter stops when [CNTR.*] = 0.
3035 */
3036 #define GPTIMER_EMU_CTL 0x00000002U
3037 #define GPTIMER_EMU_CTL_M 0x00000002U
3038 #define GPTIMER_EMU_CTL_S 1U
3039 #define GPTIMER_EMU_CTL_IMMEDIATE 0x00000000U
3040 #define GPTIMER_EMU_CTL_ZERCOND 0x00000002U
3041 
3042 
3043 /*-----------------------------------REGISTER------------------------------------
3044  Register name: C0CFG
3045  Offset name: GPTIMER_O_C0CFG
3046  Relative address: 0xC0
3047  Description: Channel 0 Configuration
3048 
3049  This register configures channel function and enables outputs.
3050 
3051  Each channel has an edge-detection circuit. The the edge-detection circuit is:
3052  - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS.
3053  - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode.
3054 
3055  The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
3056 
3057  The channel input signal enters the edge-detection circuit. False capture events can occur when:
3058  - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
3059  - the [CCACT] field is reconfigured while CTL.MODE is different from DIS.
3060 
3061  Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS:
3062  - Set [EDGE] to NONE.
3063  - Configure [CCACT].
3064  - Wait for three system clock periods before setting [EDGE] different from NONE.
3065  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3066  Default Value: 0x00000000
3067 
3068  Field: CCACT
3069  From..to bits: 0...3
3070  DefaultValue: 0x0
3071  Access type: read-write
3072  Description: Capture-Compare action.
3073 
3074  Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.*]. The corresponding output event will be set 1 timer period after [CNTR.*] = [C0CC.*].
3075 
3076  ENUMs:
3077  DIS: Disable channel.
3078  SET_ON_CAPT_DIS: Set on capture, and then disable channel.
3079 
3080  Channel function sequence:
3081  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C0CC.VAL].
3082  - Disable channel.
3083 
3084  Primary use scenario is to select this function before starting the timer.
3085  Follow these steps to select this function while [CTL.MODE] is different from DIS:
3086  - Set CCACT to SET_ON_CAPT with no output enable.
3087  - Configure [INPUT] (optional).
3088  - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
3089 
3090  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3091  CLR_ON_0_TGL_ON_CMP: Clear on zero, toggle on compare repeatedly.
3092 
3093  Channel function sequence:
3094  - Clear enabled outputs when [CNTR.VAL] = 0.
3095  - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3096 
3097  Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
3098 
3099  When [C0CC.VAL] <= [TGT.VAL]:
3100  Duty cycle = 1 - ( [C0CC.VAL] / [TGT.VAL] ).
3101 
3102  When [C0CC.VAL] > [TGT.VAL]:
3103  Duty cycle = 0.
3104 
3105  Enabled outputs are set when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
3106  SET_ON_0_TGL_ON_CMP: Set on zero, toggle on compare repeatedly.
3107 
3108  Channel function sequence:
3109  - Set enabled outputs when [CNTR.VAL] = 0.
3110  - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3111 
3112  Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
3113 
3114  When [C0CC.VAL] <= [TGT.VAL]:
3115  Duty cycle = [C0CC.VAL] / ( [TGT.VAL] + 1 ).
3116 
3117  When [C0CC.VAL] > [TGT.VAL]:
3118  Duty cycle = 1.
3119 
3120  Enabled outputs are cleared when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
3121  CLR_ON_CMP: Clear on compare repeatedly.
3122 
3123  Channel function sequence:
3124  - Clear enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3125  SET_ON_CMP: Set on compare repeatedly.
3126 
3127  Channel function sequence:
3128  - Set enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3129  TGL_ON_CMP: Toggle on compare repeatedly.
3130 
3131  Channel function sequence:
3132  - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3133  PULSE_ON_CMP: Pulse on compare repeatedly.
3134 
3135  Channel function sequence:
3136  - Pulse enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3137 
3138  The output is high for two timer clock periods.
3139  CLR_ON_0_TGL_ON_CMP_DIS: Clear on zero, toggle on compare, and then disable channel.
3140 
3141  Channel function sequence:
3142  - Clear enabled outputs when [CNTR.VAL] = 0.
3143  - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3144  - Disable channel.
3145 
3146  Enabled outputs are set when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
3147  SET_ON_0_TGL_ON_CMP_DIS: Set on zero, toggle on compare, and then disable channel.
3148 
3149  Channel function sequence:
3150  - Set enabled outputs when [CNTR.VAL] = 0.
3151  - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3152  - Disable channel.
3153 
3154  Enabled outputs are cleared when [C0CC.VAL] = 0 and [CNTR.VAL] = 0.
3155  CLR_ON_CMP_DIS: Clear on compare, and then disable channel.
3156 
3157  Channel function sequence:
3158  - Clear enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3159  - Disable channel.
3160  SET_ON_CMP_DIS: Set on compare, and then disable channel.
3161 
3162  Channel function sequence:
3163  - Set enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3164  - Disable channel.
3165  TGL_ON_CMP_DIS: Toggle on compare, and then disable channel.
3166 
3167  Channel function sequence:
3168  - Toggle enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3169  - Disable channel.
3170  PULSE_ON_CMP_DIS: Pulse on compare, and then disable channel.
3171 
3172  Channel function sequence:
3173  - Pulse enabled outputs when [C0CC.VAL] = [CNTR.VAL].
3174  - Disable channel.
3175 
3176  The output is high for two timer clock periods.
3177  PER_PULSE_WIDTH_MEAS: Period and pulse width measurement.
3178 
3179  Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE].
3180 
3181  Set enabled outputs and [RIS.C0CC] when [C0CC.VAL] contains signal period and [PC0CC.VAL] contains signal pulse width.
3182 
3183  Notes:
3184  - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER.
3185  - The counter restarts in the selected timer mode when [C0CC.VAL] contains the signal period.
3186  - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
3187  - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT].
3188 
3189  Signal property requirements:
3190  - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period.
3191  - Signal Period <= MAX([CNTR.*]) * (1 + [PRECFG.TICKDIV] ) * timer clock period.
3192  - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
3193  SET_ON_CAPT: Set on capture repeatedly.
3194 
3195  Channel function sequence:
3196  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C0CC.VAL].
3197 */
3198 #define GPTIMER_C0CFG_CCACT_W 4U
3199 #define GPTIMER_C0CFG_CCACT_M 0x0000000FU
3200 #define GPTIMER_C0CFG_CCACT_S 0U
3201 #define GPTIMER_C0CFG_CCACT_DIS 0x00000000U
3202 #define GPTIMER_C0CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U
3203 #define GPTIMER_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU
3204 #define GPTIMER_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU
3205 #define GPTIMER_C0CFG_CCACT_CLR_ON_CMP 0x0000000CU
3206 #define GPTIMER_C0CFG_CCACT_SET_ON_CMP 0x0000000DU
3207 #define GPTIMER_C0CFG_CCACT_TGL_ON_CMP 0x0000000EU
3208 #define GPTIMER_C0CFG_CCACT_PULSE_ON_CMP 0x0000000FU
3209 #define GPTIMER_C0CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U
3210 #define GPTIMER_C0CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U
3211 #define GPTIMER_C0CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U
3212 #define GPTIMER_C0CFG_CCACT_SET_ON_CMP_DIS 0x00000005U
3213 #define GPTIMER_C0CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U
3214 #define GPTIMER_C0CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U
3215 #define GPTIMER_C0CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U
3216 #define GPTIMER_C0CFG_CCACT_SET_ON_CAPT 0x00000009U
3217 /*
3218 
3219  Field: EDGE
3220  From..to bits: 4...5
3221  DefaultValue: 0x0
3222  Access type: read-write
3223  Description: Determines the edge that triggers the channel input event. This happens post filter.
3224 
3225  ENUMs:
3226  NONE: Input is turned off.
3227  RISE: Input event is triggered at rising edge.
3228  FALL: Input event is triggered at falling edge.
3229  BOTH: Input event is triggered at both edges.
3230 */
3231 #define GPTIMER_C0CFG_EDGE_W 2U
3232 #define GPTIMER_C0CFG_EDGE_M 0x00000030U
3233 #define GPTIMER_C0CFG_EDGE_S 4U
3234 #define GPTIMER_C0CFG_EDGE_NONE 0x00000000U
3235 #define GPTIMER_C0CFG_EDGE_RISE 0x00000010U
3236 #define GPTIMER_C0CFG_EDGE_FALL 0x00000020U
3237 #define GPTIMER_C0CFG_EDGE_BOTH 0x00000030U
3238 /*
3239 
3240  Field: INPUT
3241  From..to bits: 6...6
3242  DefaultValue: 0x0
3243  Access type: read-write
3244  Description: Select channel input.
3245 
3246  ENUMs:
3247  EV: Event fabric
3248  IO: IO controller
3249 */
3250 #define GPTIMER_C0CFG_INPUT 0x00000040U
3251 #define GPTIMER_C0CFG_INPUT_M 0x00000040U
3252 #define GPTIMER_C0CFG_INPUT_S 6U
3253 #define GPTIMER_C0CFG_INPUT_EV 0x00000000U
3254 #define GPTIMER_C0CFG_INPUT_IO 0x00000040U
3255 /*
3256 
3257  Field: OUT0
3258  From..to bits: 8...8
3259  DefaultValue: 0x0
3260  Access type: read-write
3261  Description: Output 0 enable.
3262 
3263  When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.
3264 
3265  ENUMs:
3266  DIS: Channel 0 does not control output 0.
3267  EN: Channel 0 controls output 0.
3268 */
3269 #define GPTIMER_C0CFG_OUT0 0x00000100U
3270 #define GPTIMER_C0CFG_OUT0_M 0x00000100U
3271 #define GPTIMER_C0CFG_OUT0_S 8U
3272 #define GPTIMER_C0CFG_OUT0_DIS 0x00000000U
3273 #define GPTIMER_C0CFG_OUT0_EN 0x00000100U
3274 /*
3275 
3276  Field: OUT1
3277  From..to bits: 9...9
3278  DefaultValue: 0x0
3279  Access type: read-write
3280  Description: Output 1 enable.
3281 
3282  When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.
3283 
3284  ENUMs:
3285  DIS: Channel 0 does not control output 1.
3286  EN: Channel 0 controls output 1.
3287 */
3288 #define GPTIMER_C0CFG_OUT1 0x00000200U
3289 #define GPTIMER_C0CFG_OUT1_M 0x00000200U
3290 #define GPTIMER_C0CFG_OUT1_S 9U
3291 #define GPTIMER_C0CFG_OUT1_DIS 0x00000000U
3292 #define GPTIMER_C0CFG_OUT1_EN 0x00000200U
3293 /*
3294 
3295  Field: OUT2
3296  From..to bits: 10...10
3297  DefaultValue: 0x0
3298  Access type: read-write
3299  Description: Output 2 enable.
3300 
3301  When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.
3302 
3303  ENUMs:
3304  DIS: Channel 0 does not control output 2.
3305  EN: Channel 0 controls output 2.
3306 */
3307 #define GPTIMER_C0CFG_OUT2 0x00000400U
3308 #define GPTIMER_C0CFG_OUT2_M 0x00000400U
3309 #define GPTIMER_C0CFG_OUT2_S 10U
3310 #define GPTIMER_C0CFG_OUT2_DIS 0x00000000U
3311 #define GPTIMER_C0CFG_OUT2_EN 0x00000400U
3312 /*
3313 
3314  Field: OUT3
3315  From..to bits: 11...11
3316  DefaultValue: 0x0
3317  Access type: read-write
3318  Description: Output 3 enable.
3319 
3320  When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.
3321 
3322  ENUMs:
3323  DIS: Channel 0 does not control output 3.
3324  EN: Channel 0 controls output 3.
3325 */
3326 #define GPTIMER_C0CFG_OUT3 0x00000800U
3327 #define GPTIMER_C0CFG_OUT3_M 0x00000800U
3328 #define GPTIMER_C0CFG_OUT3_S 11U
3329 #define GPTIMER_C0CFG_OUT3_DIS 0x00000000U
3330 #define GPTIMER_C0CFG_OUT3_EN 0x00000800U
3331 
3332 
3333 /*-----------------------------------REGISTER------------------------------------
3334  Register name: C1CFG
3335  Offset name: GPTIMER_O_C1CFG
3336  Relative address: 0xC4
3337  Description: Channel 1 Configuration
3338 
3339  This register configures channel function and enables outputs.
3340 
3341  Each channel has an edge-detection circuit. The the edge-detection circuit is:
3342  - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS.
3343  - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode.
3344 
3345  The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
3346 
3347  The channel input signal enters the edge-detection circuit. False capture events can occur when:
3348  - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
3349  - the [CCACT] field is reconfigured while CTL.MODE is different from DIS.
3350 
3351  Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS:
3352  - Set [EDGE] to NONE.
3353  - Configure [CCACT].
3354  - Wait for three system clock periods before setting [EDGE] different from NONE.
3355  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3356  Default Value: 0x00000000
3357 
3358  Field: CCACT
3359  From..to bits: 0...3
3360  DefaultValue: 0x0
3361  Access type: read-write
3362  Description: Capture-Compare action.
3363 
3364  Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.*]. The corresponding output event will be set 1 timer period after [CNTR.*] = [C1CC.*].
3365 
3366  ENUMs:
3367  DIS: Disable channel.
3368  SET_ON_CAPT_DIS: Set on capture, and then disable channel.
3369 
3370  Channel function sequence:
3371  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C1CC.VAL].
3372  - Disable channel.
3373 
3374  Primary use scenario is to select this function before starting the timer.
3375  Follow these steps to select this function while [CTL.MODE] is different from DIS:
3376  - Set CCACT to SET_ON_CAPT with no output enable.
3377  - Configure [INPUT] (optional).
3378  - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
3379 
3380  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3381  CLR_ON_0_TGL_ON_CMP: Clear on zero, toggle on compare repeatedly.
3382 
3383  Channel function sequence:
3384  - Clear enabled outputs when [CNTR.VAL] = 0.
3385  - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3386 
3387  Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
3388 
3389  When [C1CC.VAL] <= [TGT.VAL]:
3390  Duty cycle = 1 - ( [C1CC.VAL] / [TGT.VAL] ).
3391 
3392  When [C1CC.VAL] > [TGT.VAL]:
3393  Duty cycle = 0.
3394 
3395  Enabled outputs are set when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
3396  SET_ON_0_TGL_ON_CMP: Set on zero, toggle on compare repeatedly.
3397 
3398  Channel function sequence:
3399  - Set enabled outputs when [CNTR.VAL] = 0.
3400  - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3401 
3402  Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
3403 
3404  When [C1CC.VAL] <= [TGT.VAL]:
3405  Duty cycle = [C1CC.VAL] / ( [TGT.VAL] + 1 ).
3406 
3407  When [C1CC.VAL] > [TGT.VAL]:
3408  Duty cycle = 1.
3409 
3410  Enabled outputs are cleared when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
3411  CLR_ON_CMP: Clear on compare repeatedly.
3412 
3413  Channel function sequence:
3414  - Clear enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3415  SET_ON_CMP: Set on compare repeatedly.
3416 
3417  Channel function sequence:
3418  - Set enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3419  TGL_ON_CMP: Toggle on compare repeatedly.
3420 
3421  Channel function sequence:
3422  - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3423  PULSE_ON_CMP: Pulse on compare repeatedly.
3424 
3425  Channel function sequence:
3426  - Pulse enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3427 
3428  The output is high for two timer clock periods.
3429  CLR_ON_0_TGL_ON_CMP_DIS: Clear on zero, toggle on compare, and then disable channel.
3430 
3431  Channel function sequence:
3432  - Clear enabled outputs when [CNTR.VAL] = 0.
3433  - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3434  - Disable channel.
3435 
3436  Enabled outputs are set when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
3437  SET_ON_0_TGL_ON_CMP_DIS: Set on zero, toggle on compare, and then disable channel.
3438 
3439  Channel function sequence:
3440  - Set enabled outputs when [CNTR.VAL] = 0.
3441  - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3442  - Disable channel.
3443 
3444  Enabled outputs are cleared when [C1CC.VAL] = 0 and [CNTR.VAL] = 0.
3445  CLR_ON_CMP_DIS: Clear on compare, and then disable channel.
3446 
3447  Channel function sequence:
3448  - Clear enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3449  - Disable channel.
3450  SET_ON_CMP_DIS: Set on compare, and then disable channel.
3451 
3452  Channel function sequence:
3453  - Set enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3454  - Disable channel.
3455  TGL_ON_CMP_DIS: Toggle on compare, and then disable channel.
3456 
3457  Channel function sequence:
3458  - Toggle enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3459  - Disable channel.
3460  PULSE_ON_CMP_DIS: Pulse on compare, and then disable channel.
3461 
3462  Channel function sequence:
3463  - Pulse enabled outputs when [C1CC.VAL] = [CNTR.VAL].
3464  - Disable channel.
3465 
3466  The output is high for two timer clock periods.
3467  PER_PULSE_WIDTH_MEAS: Period and pulse width measurement.
3468 
3469  Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE].
3470 
3471  Set enabled outputs and [RIS.C1CC] when [C1CC.VAL] contains signal period and [PC1CC.VAL] contains signal pulse width.
3472 
3473  Notes:
3474  - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER.
3475  - The counter restarts in the selected timer mode when [C1CC.VAL] contains the signal period.
3476  - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
3477  - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT].
3478 
3479  Signal property requirements:
3480  - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period.
3481  - Signal Period <= MAX([CNTR.*]) * (1 + [PRECFG.TICKDIV] ) * timer clock period.
3482  - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
3483  SET_ON_CAPT: Set on capture repeatedly.
3484 
3485  Channel function sequence:
3486  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C1CC.VAL].
3487 
3488 
3489 */
3490 #define GPTIMER_C1CFG_CCACT_W 4U
3491 #define GPTIMER_C1CFG_CCACT_M 0x0000000FU
3492 #define GPTIMER_C1CFG_CCACT_S 0U
3493 #define GPTIMER_C1CFG_CCACT_DIS 0x00000000U
3494 #define GPTIMER_C1CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U
3495 #define GPTIMER_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU
3496 #define GPTIMER_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU
3497 #define GPTIMER_C1CFG_CCACT_CLR_ON_CMP 0x0000000CU
3498 #define GPTIMER_C1CFG_CCACT_SET_ON_CMP 0x0000000DU
3499 #define GPTIMER_C1CFG_CCACT_TGL_ON_CMP 0x0000000EU
3500 #define GPTIMER_C1CFG_CCACT_PULSE_ON_CMP 0x0000000FU
3501 #define GPTIMER_C1CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U
3502 #define GPTIMER_C1CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U
3503 #define GPTIMER_C1CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U
3504 #define GPTIMER_C1CFG_CCACT_SET_ON_CMP_DIS 0x00000005U
3505 #define GPTIMER_C1CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U
3506 #define GPTIMER_C1CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U
3507 #define GPTIMER_C1CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U
3508 #define GPTIMER_C1CFG_CCACT_SET_ON_CAPT 0x00000009U
3509 /*
3510 
3511  Field: EDGE
3512  From..to bits: 4...5
3513  DefaultValue: 0x0
3514  Access type: read-write
3515  Description: Determines the edge that triggers the channel input event. This happens post filter.
3516 
3517  ENUMs:
3518  NONE: Input is turned off.
3519  RISE: Input event is triggered at rising edge.
3520  FALL: Input event is triggered at falling edge.
3521  BOTH: Input event is triggered at both edges.
3522 */
3523 #define GPTIMER_C1CFG_EDGE_W 2U
3524 #define GPTIMER_C1CFG_EDGE_M 0x00000030U
3525 #define GPTIMER_C1CFG_EDGE_S 4U
3526 #define GPTIMER_C1CFG_EDGE_NONE 0x00000000U
3527 #define GPTIMER_C1CFG_EDGE_RISE 0x00000010U
3528 #define GPTIMER_C1CFG_EDGE_FALL 0x00000020U
3529 #define GPTIMER_C1CFG_EDGE_BOTH 0x00000030U
3530 /*
3531 
3532  Field: INPUT
3533  From..to bits: 6...6
3534  DefaultValue: 0x0
3535  Access type: read-write
3536  Description: Select channel input.
3537 
3538  ENUMs:
3539  EV: Event fabric
3540  IO: IO controller
3541 */
3542 #define GPTIMER_C1CFG_INPUT 0x00000040U
3543 #define GPTIMER_C1CFG_INPUT_M 0x00000040U
3544 #define GPTIMER_C1CFG_INPUT_S 6U
3545 #define GPTIMER_C1CFG_INPUT_EV 0x00000000U
3546 #define GPTIMER_C1CFG_INPUT_IO 0x00000040U
3547 /*
3548 
3549  Field: OUT0
3550  From..to bits: 8...8
3551  DefaultValue: 0x0
3552  Access type: read-write
3553  Description: Output 0 enable.
3554  When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.
3555 
3556 
3557  ENUMs:
3558  DIS: Channel 1 does not control output 0.
3559  EN: Channel 1 controls output 0.
3560 */
3561 #define GPTIMER_C1CFG_OUT0 0x00000100U
3562 #define GPTIMER_C1CFG_OUT0_M 0x00000100U
3563 #define GPTIMER_C1CFG_OUT0_S 8U
3564 #define GPTIMER_C1CFG_OUT0_DIS 0x00000000U
3565 #define GPTIMER_C1CFG_OUT0_EN 0x00000100U
3566 /*
3567 
3568  Field: OUT1
3569  From..to bits: 9...9
3570  DefaultValue: 0x0
3571  Access type: read-write
3572  Description: Output 1 enable.
3573 
3574  When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.
3575 
3576  ENUMs:
3577  DIS: Channel 1 does not control output 1.
3578  EN: Channel 1 controls output 1.
3579 */
3580 #define GPTIMER_C1CFG_OUT1 0x00000200U
3581 #define GPTIMER_C1CFG_OUT1_M 0x00000200U
3582 #define GPTIMER_C1CFG_OUT1_S 9U
3583 #define GPTIMER_C1CFG_OUT1_DIS 0x00000000U
3584 #define GPTIMER_C1CFG_OUT1_EN 0x00000200U
3585 /*
3586 
3587  Field: OUT2
3588  From..to bits: 10...10
3589  DefaultValue: 0x0
3590  Access type: read-write
3591  Description: Output 2 enable.
3592 
3593  When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.
3594 
3595  ENUMs:
3596  DIS: Channel 1 does not control output 2.
3597  EN: Channel 1 controls output 2.
3598 */
3599 #define GPTIMER_C1CFG_OUT2 0x00000400U
3600 #define GPTIMER_C1CFG_OUT2_M 0x00000400U
3601 #define GPTIMER_C1CFG_OUT2_S 10U
3602 #define GPTIMER_C1CFG_OUT2_DIS 0x00000000U
3603 #define GPTIMER_C1CFG_OUT2_EN 0x00000400U
3604 /*
3605 
3606  Field: OUT3
3607  From..to bits: 11...11
3608  DefaultValue: 0x0
3609  Access type: read-write
3610  Description: Output 3 enable.
3611 
3612  When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.
3613 
3614  ENUMs:
3615  DIS: Channel 1 does not control output 3.
3616  EN: Channel 1 controls output 3.
3617 */
3618 #define GPTIMER_C1CFG_OUT3 0x00000800U
3619 #define GPTIMER_C1CFG_OUT3_M 0x00000800U
3620 #define GPTIMER_C1CFG_OUT3_S 11U
3621 #define GPTIMER_C1CFG_OUT3_DIS 0x00000000U
3622 #define GPTIMER_C1CFG_OUT3_EN 0x00000800U
3623 
3624 
3625 /*-----------------------------------REGISTER------------------------------------
3626  Register name: C2CFG
3627  Offset name: GPTIMER_O_C2CFG
3628  Relative address: 0xC8
3629  Description: Channel 2 Configuration
3630 
3631  This register configures channel function and enables outputs.
3632 
3633  Each channel has an edge-detection circuit. The the edge-detection circuit is:
3634  - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS.
3635  - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode.
3636 
3637  The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
3638 
3639  The channel input signal enters the edge-detection circuit. False capture events can occur when:
3640  - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
3641  - the [CCACT] field is reconfigured while CTL.MODE is different from DIS.
3642 
3643  Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS:
3644  - Set [EDGE] to NONE.
3645  - Configure [CCACT].
3646  - Wait for three system clock periods before setting [EDGE] different from NONE.
3647  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3648  Default Value: 0x00000000
3649 
3650  Field: CCACT
3651  From..to bits: 0...3
3652  DefaultValue: 0x0
3653  Access type: read-write
3654  Description: Capture-Compare action.
3655 
3656  Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.*]. The corresponding output event will be set 1 timer period after [CNTR.*] = [C2CC.*].
3657 
3658  ENUMs:
3659  DIS: Disable channel.
3660  SET_ON_CAPT_DIS: Set on capture, and then disable channel.
3661 
3662  Channel function sequence:
3663  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C2CC.VAL].
3664  - Disable channel.
3665 
3666  Primary use scenario is to select this function before starting the timer.
3667  Follow these steps to select this function while [CTL.MODE] is different from DIS:
3668  - Set CCACT to SET_ON_CAPT with no output enable.
3669  - Configure [INPUT] (optional).
3670  - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
3671 
3672  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3673  CLR_ON_0_TGL_ON_CMP: Clear on zero, toggle on compare repeatedly.
3674 
3675  Channel function sequence:
3676  - Clear enabled outputs when [CNTR.VAL] = 0.
3677  - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3678 
3679  Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
3680 
3681  When [C2CC.VAL] <= [TGT.VAL]:
3682  Duty cycle = 1 - ( [C2CC.VAL] / [TGT.VAL] ).
3683 
3684  When [C2CC.VAL] > [TGT.VAL]:
3685  Duty cycle = 0.
3686 
3687  Enabled outputs are set when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
3688  SET_ON_0_TGL_ON_CMP: Set on zero, toggle on compare repeatedly.
3689 
3690  Channel function sequence:
3691  - Set enabled outputs when [CNTR.VAL] = 0.
3692  - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3693 
3694  Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
3695 
3696  When [C2CC.VAL] <= [TGT.VAL]:
3697  Duty cycle = [C2CC.VAL] / ( [TGT.VAL] + 1 ).
3698 
3699  When [C2CC.VAL] > [TGT.VAL]:
3700  Duty cycle = 1.
3701 
3702  Enabled outputs are cleared when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
3703  CLR_ON_CMP: Clear on compare repeatedly.
3704 
3705  Channel function sequence:
3706  - Clear enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3707  SET_ON_CMP: Set on compare repeatedly.
3708 
3709  Channel function sequence:
3710  - Set enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3711  TGL_ON_CMP: Toggle on compare repeatedly.
3712 
3713  Channel function sequence:
3714  - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3715  PULSE_ON_CMP: Pulse on compare repeatedly.
3716 
3717  Channel function sequence:
3718  - Pulse enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3719 
3720  The output is high for two timer clock periods.
3721  CLR_ON_0_TGL_ON_CMP_DIS: Clear on zero, toggle on compare, and then disable channel.
3722 
3723  Channel function sequence:
3724  - Clear enabled outputs when [CNTR.VAL] = 0.
3725  - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3726  - Disable channel.
3727 
3728  Enabled outputs are set when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
3729  SET_ON_0_TGL_ON_CMP_DIS: Set on zero, toggle on compare, and then disable channel.
3730 
3731  Channel function sequence:
3732  - Set enabled outputs when [CNTR.VAL] = 0.
3733  - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3734  - Disable channel.
3735 
3736  Enabled outputs are cleared when [C2CC.VAL] = 0 and [CNTR.VAL] = 0.
3737  CLR_ON_CMP_DIS: Clear on compare, and then disable channel.
3738 
3739  Channel function sequence:
3740  - Clear enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3741  - Disable channel.
3742  SET_ON_CMP_DIS: Set on compare, and then disable channel.
3743 
3744  Channel function sequence:
3745  - Set enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3746  - Disable channel.
3747  TGL_ON_CMP_DIS: Toggle on compare, and then disable channel.
3748 
3749  Channel function sequence:
3750  - Toggle enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3751  - Disable channel.
3752  PULSE_ON_CMP_DIS: Pulse on compare, and then disable channel.
3753 
3754  Channel function sequence:
3755  - Pulse enabled outputs when [C2CC.VAL] = [CNTR.VAL].
3756  - Disable channel.
3757 
3758  The output is high for two timer clock periods.
3759  PER_PULSE_WIDTH_MEAS: Period and pulse width measurement.
3760 
3761  Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE].
3762 
3763  Set enabled outputs and [RIS.C2CC] when [C2CC.VAL] contains signal period and [PC2CC.VAL] contains signal pulse width.
3764 
3765  Notes:
3766  - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER.
3767  - The counter restarts in the selected timer mode when [C2CC.VAL] contains the signal period.
3768  - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
3769  - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT].
3770 
3771  Signal property requirements:
3772  - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period.
3773  - Signal Period <= MAX([CNTR.*]) * (1 + [PRECFG.TICKDIV] ) * timer clock period.
3774  - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
3775  SET_ON_CAPT: Set on capture repeatedly.
3776 
3777  Channel function sequence:
3778  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C2CC.VAL].
3779 
3780 
3781 */
3782 #define GPTIMER_C2CFG_CCACT_W 4U
3783 #define GPTIMER_C2CFG_CCACT_M 0x0000000FU
3784 #define GPTIMER_C2CFG_CCACT_S 0U
3785 #define GPTIMER_C2CFG_CCACT_DIS 0x00000000U
3786 #define GPTIMER_C2CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U
3787 #define GPTIMER_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU
3788 #define GPTIMER_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU
3789 #define GPTIMER_C2CFG_CCACT_CLR_ON_CMP 0x0000000CU
3790 #define GPTIMER_C2CFG_CCACT_SET_ON_CMP 0x0000000DU
3791 #define GPTIMER_C2CFG_CCACT_TGL_ON_CMP 0x0000000EU
3792 #define GPTIMER_C2CFG_CCACT_PULSE_ON_CMP 0x0000000FU
3793 #define GPTIMER_C2CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U
3794 #define GPTIMER_C2CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U
3795 #define GPTIMER_C2CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U
3796 #define GPTIMER_C2CFG_CCACT_SET_ON_CMP_DIS 0x00000005U
3797 #define GPTIMER_C2CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U
3798 #define GPTIMER_C2CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U
3799 #define GPTIMER_C2CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U
3800 #define GPTIMER_C2CFG_CCACT_SET_ON_CAPT 0x00000009U
3801 /*
3802 
3803  Field: EDGE
3804  From..to bits: 4...5
3805  DefaultValue: 0x0
3806  Access type: read-write
3807  Description: Determines the edge that triggers the channel input event. This happens post filter.
3808 
3809  ENUMs:
3810  NONE: Input is turned off.
3811  RISE: Input event is triggered at rising edge.
3812  FALL: Input event is triggered at falling edge.
3813  BOTH: Input event is triggered at both edges.
3814 */
3815 #define GPTIMER_C2CFG_EDGE_W 2U
3816 #define GPTIMER_C2CFG_EDGE_M 0x00000030U
3817 #define GPTIMER_C2CFG_EDGE_S 4U
3818 #define GPTIMER_C2CFG_EDGE_NONE 0x00000000U
3819 #define GPTIMER_C2CFG_EDGE_RISE 0x00000010U
3820 #define GPTIMER_C2CFG_EDGE_FALL 0x00000020U
3821 #define GPTIMER_C2CFG_EDGE_BOTH 0x00000030U
3822 /*
3823 
3824  Field: INPUT
3825  From..to bits: 6...6
3826  DefaultValue: 0x0
3827  Access type: read-write
3828  Description: Select channel input.
3829 
3830  ENUMs:
3831  EV: Event fabric
3832  IO: IO controller
3833 */
3834 #define GPTIMER_C2CFG_INPUT 0x00000040U
3835 #define GPTIMER_C2CFG_INPUT_M 0x00000040U
3836 #define GPTIMER_C2CFG_INPUT_S 6U
3837 #define GPTIMER_C2CFG_INPUT_EV 0x00000000U
3838 #define GPTIMER_C2CFG_INPUT_IO 0x00000040U
3839 /*
3840 
3841  Field: OUT0
3842  From..to bits: 8...8
3843  DefaultValue: 0x0
3844  Access type: read-write
3845  Description: Output 0 enable.
3846 
3847  When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.
3848 
3849  ENUMs:
3850  DIS: Channel 2 does not control output 0.
3851  EN: Channel 2 controls output 0.
3852 */
3853 #define GPTIMER_C2CFG_OUT0 0x00000100U
3854 #define GPTIMER_C2CFG_OUT0_M 0x00000100U
3855 #define GPTIMER_C2CFG_OUT0_S 8U
3856 #define GPTIMER_C2CFG_OUT0_DIS 0x00000000U
3857 #define GPTIMER_C2CFG_OUT0_EN 0x00000100U
3858 /*
3859 
3860  Field: OUT1
3861  From..to bits: 9...9
3862  DefaultValue: 0x0
3863  Access type: read-write
3864  Description: Output 1 enable.
3865 
3866  When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.
3867 
3868  ENUMs:
3869  DIS: Channel 2 does not control output 1.
3870  EN: Channel 2 controls output 1.
3871 */
3872 #define GPTIMER_C2CFG_OUT1 0x00000200U
3873 #define GPTIMER_C2CFG_OUT1_M 0x00000200U
3874 #define GPTIMER_C2CFG_OUT1_S 9U
3875 #define GPTIMER_C2CFG_OUT1_DIS 0x00000000U
3876 #define GPTIMER_C2CFG_OUT1_EN 0x00000200U
3877 /*
3878 
3879  Field: OUT2
3880  From..to bits: 10...10
3881  DefaultValue: 0x0
3882  Access type: read-write
3883  Description: Output 2 enable.
3884 
3885  When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.
3886 
3887  ENUMs:
3888  DIS: Channel 2 does not control output 2.
3889  EN: Channel 2 controls output 2.
3890 */
3891 #define GPTIMER_C2CFG_OUT2 0x00000400U
3892 #define GPTIMER_C2CFG_OUT2_M 0x00000400U
3893 #define GPTIMER_C2CFG_OUT2_S 10U
3894 #define GPTIMER_C2CFG_OUT2_DIS 0x00000000U
3895 #define GPTIMER_C2CFG_OUT2_EN 0x00000400U
3896 /*
3897 
3898  Field: OUT3
3899  From..to bits: 11...11
3900  DefaultValue: 0x0
3901  Access type: read-write
3902  Description: Output 3 enable.
3903 
3904  When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.
3905 
3906  ENUMs:
3907  DIS: Channel 2 does not control output 3.
3908  EN: Channel 2 controls output 3.
3909 */
3910 #define GPTIMER_C2CFG_OUT3 0x00000800U
3911 #define GPTIMER_C2CFG_OUT3_M 0x00000800U
3912 #define GPTIMER_C2CFG_OUT3_S 11U
3913 #define GPTIMER_C2CFG_OUT3_DIS 0x00000000U
3914 #define GPTIMER_C2CFG_OUT3_EN 0x00000800U
3915 
3916 
3917 /*-----------------------------------REGISTER------------------------------------
3918  Register name: C3CFG
3919  Offset name: GPTIMER_O_C3CFG
3920  Relative address: 0xCC
3921  Description: Channel 3 Configuration
3922 
3923  This register configures channel function and enables outputs.
3924 
3925  Each channel has an edge-detection circuit. The the edge-detection circuit is:
3926  - enabled while [CCACT] selects a capture function and [CTL.MODE] is different from DIS.
3927  - flushed while [CCACT] selects a capture function and [CTL.MODE] is changed from DIS to another mode.
3928 
3929  The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
3930 
3931  The channel input signal enters the edge-detection circuit. False capture events can occur when:
3932  - the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
3933  - the [CCACT] field is reconfigured while CTL.MODE is different from DIS.
3934 
3935  Primary use scenario is to select [CCACT] before starting the timer. Follow these steps to configure [CCACT] to a capture action while [CTL.MODE] is different from DIS:
3936  - Set [EDGE] to NONE.
3937  - Configure [CCACT].
3938  - Wait for three system clock periods before setting [EDGE] different from NONE.
3939  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3940  Default Value: 0x00000000
3941 
3942  Field: CCACT
3943  From..to bits: 0...3
3944  DefaultValue: 0x0
3945  Access type: read-write
3946  Description: Capture-Compare action.
3947 
3948  Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of [CNTR.*]. The corresponding output event will be set 1 timer period after [CNTR.*] = [C3CC.*].
3949 
3950  ENUMs:
3951  DIS: Disable channel.
3952  SET_ON_CAPT_DIS: Set on capture, and then disable channel.
3953 
3954  Channel function sequence:
3955  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C3CC.VAL].
3956  - Disable channel.
3957 
3958  Primary use scenario is to select this function before starting the timer.
3959  Follow these steps to select this function while [CTL.MODE] is different from DIS:
3960  - Set CCACT to SET_ON_CAPT with no output enable.
3961  - Configure [INPUT] (optional).
3962  - Wait for three timer clock periods as defined in [PRECFG.*] before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional.
3963 
3964  These steps prevent capture events caused by expired signal values in edge-detection circuit.
3965  CLR_ON_0_TGL_ON_CMP: Clear on zero, toggle on compare repeatedly.
3966 
3967  Channel function sequence:
3968  - Clear enabled outputs when [CNTR.VAL] = 0.
3969  - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
3970 
3971  Set [CTL.MODE] to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:
3972 
3973  When [C3CC.VAL] <= [TGT.VAL]:
3974  Duty cycle = 1 - ( [C3CC.VAL] / [TGT.VAL] ).
3975 
3976  When [C3CC.VAL] > [TGT.VAL]:
3977  Duty cycle = 0.
3978 
3979  Enabled outputs are set when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
3980  SET_ON_0_TGL_ON_CMP: Set on zero, toggle on compare repeatedly.
3981 
3982  Channel function sequence:
3983  - Set enabled outputs when [CNTR.VAL] = 0.
3984  - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
3985 
3986  Set [CTL.MODE] to UP_PER for edge-aligned PWM generation. Duty cycle is given by:
3987 
3988  When [C3CC.VAL] <= [TGT.VAL]:
3989  Duty cycle = [C3CC.VAL] / ( [TGT.VAL] + 1 ).
3990 
3991  When [C3CC.VAL] > [TGT.VAL]:
3992  Duty cycle = 1.
3993 
3994  Enabled outputs are cleared when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
3995  CLR_ON_CMP: Clear on compare repeatedly.
3996 
3997  Channel function sequence:
3998  - Clear enabled outputs when [C3CC.VAL] = [CNTR.VAL].
3999  SET_ON_CMP: Set on compare repeatedly.
4000 
4001  Channel function sequence:
4002  - Set enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4003  TGL_ON_CMP: Toggle on compare repeatedly.
4004 
4005  Channel function sequence:
4006  - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4007  PULSE_ON_CMP: Pulse on compare repeatedly.
4008 
4009  Channel function sequence:
4010  - Pulse enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4011 
4012  The output is high for two timer clock periods.
4013  CLR_ON_0_TGL_ON_CMP_DIS: Clear on zero, toggle on compare, and then disable channel.
4014 
4015  Channel function sequence:
4016  - Clear enabled outputs when [CNTR.VAL] = 0.
4017  - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4018  - Disable channel.
4019 
4020  Enabled outputs are set when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
4021  SET_ON_0_TGL_ON_CMP_DIS: Set on zero, toggle on compare, and then disable channel.
4022 
4023  Channel function sequence:
4024  - Set enabled outputs when [CNTR.VAL] = 0.
4025  - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4026  - Disable channel.
4027 
4028  Enabled outputs are cleared when [C3CC.VAL] = 0 and [CNTR.VAL] = 0.
4029  CLR_ON_CMP_DIS: Clear on compare, and then disable channel.
4030 
4031  Channel function sequence:
4032  - Clear enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4033  - Disable channel.
4034  SET_ON_CMP_DIS: Set on compare, and then disable channel.
4035 
4036  Channel function sequence:
4037  - Set enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4038  - Disable channel.
4039  TGL_ON_CMP_DIS: Toggle on compare, and then disable channel.
4040 
4041  Channel function sequence:
4042  - Toggle enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4043  - Disable channel.
4044  PULSE_ON_CMP_DIS: Pulse on compare, and then disable channel.
4045 
4046  Channel function sequence:
4047  - Pulse enabled outputs when [C3CC.VAL] = [CNTR.VAL].
4048  - Disable channel.
4049 
4050  The output is high for two timer clock periods.
4051  PER_PULSE_WIDTH_MEAS: Period and pulse width measurement.
4052 
4053  Continuously capture period and pulse width of the signal selected by [INPUT] relative to the signal edge given by [EDGE].
4054 
4055  Set enabled outputs and [RIS.C3CC] when [C3CC.VAL] contains signal period and [PC3CC.VAL] contains signal pulse width.
4056 
4057  Notes:
4058  - Make sure to configure [INPUT] and CCACT when [CTL.MODE] equals DIS, then set [CTL.MODE] to UP_ONCE or UP_PER.
4059  - The counter restarts in the selected timer mode when [C3CC.VAL] contains the signal period.
4060  - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
4061  - To observe a timeout event the [RIS.TGT] interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal [TGT].
4062 
4063  Signal property requirements:
4064  - Signal Period >= 2 * ( 1 + [PRECFG.TICKDIV] ) * timer clock period.
4065  - Signal Period <= MAX([CNTR.*]) * (1 + [PRECFG.TICKDIV] ) * timer clock period.
4066  - Signal low and high phase >= (1 + [PRECFG.TICKDIV] ) * timer clock period.
4067  SET_ON_CAPT: Set on capture repeatedly.
4068 
4069  Channel function sequence:
4070  - Set enabled outputs on capture event and copy [CNTR.VAL] to [C3CC.VAL].
4071 
4072 
4073 */
4074 #define GPTIMER_C3CFG_CCACT_W 4U
4075 #define GPTIMER_C3CFG_CCACT_M 0x0000000FU
4076 #define GPTIMER_C3CFG_CCACT_S 0U
4077 #define GPTIMER_C3CFG_CCACT_DIS 0x00000000U
4078 #define GPTIMER_C3CFG_CCACT_SET_ON_CAPT_DIS 0x00000001U
4079 #define GPTIMER_C3CFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000AU
4080 #define GPTIMER_C3CFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000BU
4081 #define GPTIMER_C3CFG_CCACT_CLR_ON_CMP 0x0000000CU
4082 #define GPTIMER_C3CFG_CCACT_SET_ON_CMP 0x0000000DU
4083 #define GPTIMER_C3CFG_CCACT_TGL_ON_CMP 0x0000000EU
4084 #define GPTIMER_C3CFG_CCACT_PULSE_ON_CMP 0x0000000FU
4085 #define GPTIMER_C3CFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002U
4086 #define GPTIMER_C3CFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003U
4087 #define GPTIMER_C3CFG_CCACT_CLR_ON_CMP_DIS 0x00000004U
4088 #define GPTIMER_C3CFG_CCACT_SET_ON_CMP_DIS 0x00000005U
4089 #define GPTIMER_C3CFG_CCACT_TGL_ON_CMP_DIS 0x00000006U
4090 #define GPTIMER_C3CFG_CCACT_PULSE_ON_CMP_DIS 0x00000007U
4091 #define GPTIMER_C3CFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008U
4092 #define GPTIMER_C3CFG_CCACT_SET_ON_CAPT 0x00000009U
4093 /*
4094 
4095  Field: EDGE
4096  From..to bits: 4...5
4097  DefaultValue: 0x0
4098  Access type: read-write
4099  Description: Determines the edge that triggers the channel input event. This happens post filter.
4100 
4101  ENUMs:
4102  NONE: Input is turned off.
4103  RISE: Input event is triggered at rising edge.
4104  FALL: Input event is triggered at falling edge.
4105  BOTH: Input event is triggered at both edges.
4106 */
4107 #define GPTIMER_C3CFG_EDGE_W 2U
4108 #define GPTIMER_C3CFG_EDGE_M 0x00000030U
4109 #define GPTIMER_C3CFG_EDGE_S 4U
4110 #define GPTIMER_C3CFG_EDGE_NONE 0x00000000U
4111 #define GPTIMER_C3CFG_EDGE_RISE 0x00000010U
4112 #define GPTIMER_C3CFG_EDGE_FALL 0x00000020U
4113 #define GPTIMER_C3CFG_EDGE_BOTH 0x00000030U
4114 /*
4115 
4116  Field: INPUT
4117  From..to bits: 6...6
4118  DefaultValue: 0x0
4119  Access type: read-write
4120  Description: Select channel input.
4121 
4122  ENUMs:
4123  EV: Event fabric
4124  IO: IO controller
4125 */
4126 #define GPTIMER_C3CFG_INPUT 0x00000040U
4127 #define GPTIMER_C3CFG_INPUT_M 0x00000040U
4128 #define GPTIMER_C3CFG_INPUT_S 6U
4129 #define GPTIMER_C3CFG_INPUT_EV 0x00000000U
4130 #define GPTIMER_C3CFG_INPUT_IO 0x00000040U
4131 /*
4132 
4133  Field: OUT0
4134  From..to bits: 8...8
4135  DefaultValue: 0x0
4136  Access type: read-write
4137  Description: Output 0 enable.
4138 
4139  When 0 < [CCACT] < 8, OUT0 becomes zero after a capture or compare event.
4140 
4141  ENUMs:
4142  DIS: Channel 3 does not control output 0.
4143  EN: Channel 3 controls output 0.
4144 */
4145 #define GPTIMER_C3CFG_OUT0 0x00000100U
4146 #define GPTIMER_C3CFG_OUT0_M 0x00000100U
4147 #define GPTIMER_C3CFG_OUT0_S 8U
4148 #define GPTIMER_C3CFG_OUT0_DIS 0x00000000U
4149 #define GPTIMER_C3CFG_OUT0_EN 0x00000100U
4150 /*
4151 
4152  Field: OUT1
4153  From..to bits: 9...9
4154  DefaultValue: 0x0
4155  Access type: read-write
4156  Description: Output 1 enable.
4157 
4158  When 0 < [CCACT] < 8, OUT1 becomes zero after a capture or compare event.
4159 
4160  ENUMs:
4161  DIS: Channel 3 does not control output 1.
4162  EN: Channel 3 controls output 1.
4163 */
4164 #define GPTIMER_C3CFG_OUT1 0x00000200U
4165 #define GPTIMER_C3CFG_OUT1_M 0x00000200U
4166 #define GPTIMER_C3CFG_OUT1_S 9U
4167 #define GPTIMER_C3CFG_OUT1_DIS 0x00000000U
4168 #define GPTIMER_C3CFG_OUT1_EN 0x00000200U
4169 /*
4170 
4171  Field: OUT2
4172  From..to bits: 10...10
4173  DefaultValue: 0x0
4174  Access type: read-write
4175  Description: Output 2 enable.
4176 
4177  When 0 < [CCACT] < 8, OUT2 becomes zero after a capture or compare event.
4178 
4179  ENUMs:
4180  DIS: Channel 3 does not control output 2.
4181  EN: Channel 3 controls output 2.
4182 */
4183 #define GPTIMER_C3CFG_OUT2 0x00000400U
4184 #define GPTIMER_C3CFG_OUT2_M 0x00000400U
4185 #define GPTIMER_C3CFG_OUT2_S 10U
4186 #define GPTIMER_C3CFG_OUT2_DIS 0x00000000U
4187 #define GPTIMER_C3CFG_OUT2_EN 0x00000400U
4188 /*
4189 
4190  Field: OUT3
4191  From..to bits: 11...11
4192  DefaultValue: 0x0
4193  Access type: read-write
4194  Description: Output 3 enable.
4195 
4196  When 0 < [CCACT] < 8, OUT3 becomes zero after a capture or compare event.
4197 
4198  ENUMs:
4199  DIS: Channel 3 does not control output 3.
4200  EN: Channel 3 controls output 3.
4201 */
4202 #define GPTIMER_C3CFG_OUT3 0x00000800U
4203 #define GPTIMER_C3CFG_OUT3_M 0x00000800U
4204 #define GPTIMER_C3CFG_OUT3_S 11U
4205 #define GPTIMER_C3CFG_OUT3_DIS 0x00000000U
4206 #define GPTIMER_C3CFG_OUT3_EN 0x00000800U
4207 
4208 
4209 /*-----------------------------------REGISTER------------------------------------
4210  Register name: PTGT
4211  Offset name: GPTIMER_O_PTGT
4212  Relative address: 0xFC
4213  Description: Pipeline Target
4214  A read or write to this register will clear the [RIS.ZERO] and [RIS.TGT] interrupt.
4215 
4216 
4217  If [CTL.MODE] != QDEC.
4218  Target value for next counter period.
4219  The timer will copy [PTGT.VAL] to [TGT.VAL] on the upcoming [CNTR.*] zero crossing only if [PTGT.VAL] has been written. The copy does not happen when restarting the timer.
4220  This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.
4221 
4222  If [CTL.MODE] = QDEC
4223  The [CNTR.*] value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, [CNTR.*] is loaded with zero on IDX.
4224  In this mode the VALUE is not loaded into [TGT] on zero crossing.
4225  Default Value: 0x00000000
4226 
4227  Field: VAL
4228  From..to bits: 0...31
4229  DefaultValue: 0x0
4230  Access type: read-write
4231  Description: The pipleline target value.
4232 
4233 */
4234 #define GPTIMER_PTGT_VAL_W 32U
4235 #define GPTIMER_PTGT_VAL_M 0xFFFFFFFFU
4236 #define GPTIMER_PTGT_VAL_S 0U
4237 
4238 
4239 /*-----------------------------------REGISTER------------------------------------
4240  Register name: PC0CC
4241  Offset name: GPTIMER_O_PC0CC
4242  Relative address: 0x100
4243  Description: Pipeline Channel 0 Capture Compare
4244  Default Value: 0x00000000
4245 
4246  Field: VAL
4247  From..to bits: 0...31
4248  DefaultValue: 0x0
4249  Access type: read-write
4250  Description: Pipeline Capture Compare value.
4251 
4252  User defined pipeline compare value or channel-updated capture value.
4253 
4254  A read or write to this register will clear the [RIS.C0CC] interrupt.
4255 
4256  Compare mode:
4257  An update of VAL will be transferred to [C0CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
4258 
4259  Capture mode:
4260  When [C0CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C0CFG.EDGE].
4261 
4262 */
4263 #define GPTIMER_PC0CC_VAL_W 32U
4264 #define GPTIMER_PC0CC_VAL_M 0xFFFFFFFFU
4265 #define GPTIMER_PC0CC_VAL_S 0U
4266 
4267 
4268 /*-----------------------------------REGISTER------------------------------------
4269  Register name: PC1CC
4270  Offset name: GPTIMER_O_PC1CC
4271  Relative address: 0x104
4272  Description: Pipeline Channel 1 Capture Compare
4273  Default Value: 0x00000000
4274 
4275  Field: VAL
4276  From..to bits: 0...31
4277  DefaultValue: 0x0
4278  Access type: read-write
4279  Description: Pipeline Capture Compare value.
4280 
4281  User defined pipeline compare value or channel-updated capture value.
4282 
4283  A read or write to this register will clear the [RIS.C1CC] interrupt.
4284 
4285  Compare mode:
4286  An update of VAL will be transferred to [C1CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
4287 
4288  Capture mode:
4289  When [C1CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C1CFG.EDGE].
4290 
4291 */
4292 #define GPTIMER_PC1CC_VAL_W 32U
4293 #define GPTIMER_PC1CC_VAL_M 0xFFFFFFFFU
4294 #define GPTIMER_PC1CC_VAL_S 0U
4295 
4296 
4297 /*-----------------------------------REGISTER------------------------------------
4298  Register name: PC2CC
4299  Offset name: GPTIMER_O_PC2CC
4300  Relative address: 0x108
4301  Description: Pipeline Channel 2 Capture Compare
4302  Default Value: 0x00000000
4303 
4304  Field: VAL
4305  From..to bits: 0...31
4306  DefaultValue: 0x0
4307  Access type: read-write
4308  Description: Pipeline Capture Compare value.
4309 
4310  User defined pipeline compare value or channel-updated capture value.
4311 
4312  A read or write to this register will clear the [RIS.C2CC] interrupt.
4313 
4314  Compare mode:
4315  An update of VAL will be transferred to [C2CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
4316 
4317  Capture mode:
4318  When [C2CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C2CFG.EDGE].
4319 
4320 */
4321 #define GPTIMER_PC2CC_VAL_W 32U
4322 #define GPTIMER_PC2CC_VAL_M 0xFFFFFFFFU
4323 #define GPTIMER_PC2CC_VAL_S 0U
4324 
4325 
4326 /*-----------------------------------REGISTER------------------------------------
4327  Register name: PC3CC
4328  Offset name: GPTIMER_O_PC3CC
4329  Relative address: 0x10C
4330  Description: Pipeline Channel 3 Capture Compare
4331  Default Value: 0x00000000
4332 
4333  Field: VAL
4334  From..to bits: 0...31
4335  DefaultValue: 0x0
4336  Access type: read-write
4337  Description: Pipeline Capture Compare value.
4338 
4339  User defined pipeline compare value or channel-updated capture value.
4340 
4341  A read or write to this register will clear the [RIS.C3CC] interrupt.
4342 
4343  Compare mode:
4344  An update of VAL will be transferred to [C3CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal.
4345 
4346  Capture mode:
4347  When [C3CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C3CFG.EDGE].
4348 
4349 */
4350 #define GPTIMER_PC3CC_VAL_W 32U
4351 #define GPTIMER_PC3CC_VAL_M 0xFFFFFFFFU
4352 #define GPTIMER_PC3CC_VAL_S 0U
4353 
4354 
4355 /*-----------------------------------REGISTER------------------------------------
4356  Register name: TGT
4357  Offset name: GPTIMER_O_TGT
4358  Relative address: 0x13C
4359  Description: Target
4360 
4361  User defined counter target.
4362  A read or write to this register will clear the [RIS.ZERO] and [RIS.TGT] interrupt.
4363  Default Value: 0x00000000
4364 
4365  Field: VAL
4366  From..to bits: 0...31
4367  DefaultValue: 0x0
4368  Access type: read-write
4369  Description: User defined counter target value.
4370 
4371 */
4372 #define GPTIMER_TGT_VAL_W 32U
4373 #define GPTIMER_TGT_VAL_M 0xFFFFFFFFU
4374 #define GPTIMER_TGT_VAL_S 0U
4375 
4376 
4377 /*-----------------------------------REGISTER------------------------------------
4378  Register name: C0CC
4379  Offset name: GPTIMER_O_C0CC
4380  Relative address: 0x140
4381  Description: Channel 0 Capture Compare
4382  Default Value: 0x00000000
4383 
4384  Field: VAL
4385  From..to bits: 0...31
4386  DefaultValue: 0x0
4387  Access type: read-write
4388  Description: Capture Compare value.
4389 
4390  User defined compare value or channel-updated capture value.
4391 
4392  A read or write to this register will clear the [RIS.C0CC] interrupt.
4393 
4394  Compare mode:
4395  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C0CFG.CCACT] when these are equal.
4396 
4397  Capture mode:
4398  The current counter value is stored in VAL when a capture event occurs. [C0CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4399 
4400 */
4401 #define GPTIMER_C0CC_VAL_W 32U
4402 #define GPTIMER_C0CC_VAL_M 0xFFFFFFFFU
4403 #define GPTIMER_C0CC_VAL_S 0U
4404 
4405 
4406 /*-----------------------------------REGISTER------------------------------------
4407  Register name: C1CC
4408  Offset name: GPTIMER_O_C1CC
4409  Relative address: 0x144
4410  Description: Channel 1 Capture Compare
4411  Default Value: 0x00000000
4412 
4413  Field: VAL
4414  From..to bits: 0...31
4415  DefaultValue: 0x0
4416  Access type: read-write
4417  Description: Capture Compare value.
4418 
4419  User defined compare value or channel-updated capture value.
4420 
4421  A read or write to this register will clear the [RIS.C1CC] interrupt.
4422 
4423  Compare mode:
4424  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C1CFG.CCACT] when these are equal.
4425 
4426  Capture mode:
4427  The current counter value is stored in VAL when a capture event occurs. [C1CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4428 
4429 */
4430 #define GPTIMER_C1CC_VAL_W 32U
4431 #define GPTIMER_C1CC_VAL_M 0xFFFFFFFFU
4432 #define GPTIMER_C1CC_VAL_S 0U
4433 
4434 
4435 /*-----------------------------------REGISTER------------------------------------
4436  Register name: C2CC
4437  Offset name: GPTIMER_O_C2CC
4438  Relative address: 0x148
4439  Description: Channel 2 Capture Compare
4440  Default Value: 0x00000000
4441 
4442  Field: VAL
4443  From..to bits: 0...31
4444  DefaultValue: 0x0
4445  Access type: read-write
4446  Description: Capture Compare value.
4447 
4448  User defined compare value or channel-updated capture value.
4449 
4450  A read or write to this register will clear the [RIS.C2CC] interrupt.
4451 
4452  Compare mode:
4453  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C2CFG.CCACT] when these are equal.
4454 
4455  Capture mode:
4456  The current counter value is stored in VAL when a capture event occurs. [C2CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4457 
4458 */
4459 #define GPTIMER_C2CC_VAL_W 32U
4460 #define GPTIMER_C2CC_VAL_M 0xFFFFFFFFU
4461 #define GPTIMER_C2CC_VAL_S 0U
4462 
4463 
4464 /*-----------------------------------REGISTER------------------------------------
4465  Register name: C3CC
4466  Offset name: GPTIMER_O_C3CC
4467  Relative address: 0x14C
4468  Description: Channel 3 Capture Compare
4469  Default Value: 0x00000000
4470 
4471  Field: VAL
4472  From..to bits: 0...31
4473  DefaultValue: 0x0
4474  Access type: read-write
4475  Description: Capture Compare value.
4476 
4477  User defined compare value or channel-updated capture value.
4478 
4479  A read or write to this register will clear the [RIS.C3CC] interrupt.
4480 
4481  Compare mode:
4482  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C3CFG.CCACT] when these are equal.
4483 
4484  Capture mode:
4485  The current counter value is stored in VAL when a capture event occurs. [C3CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4486 
4487 */
4488 #define GPTIMER_C3CC_VAL_W 32U
4489 #define GPTIMER_C3CC_VAL_M 0xFFFFFFFFU
4490 #define GPTIMER_C3CC_VAL_S 0U
4491 
4492 
4493 /*-----------------------------------REGISTER------------------------------------
4494  Register name: PTGTNC
4495  Offset name: GPTIMER_O_PTGTNC
4496  Relative address: 0x17C
4497  Description: Pipeline Target No Clear
4498 
4499  Use this register to read or write to [PTGT.*] without clearing the [RIS.ZERO] and [RIS.TGT] interrupt.
4500  Default Value: 0x00000000
4501 
4502  Field: VAL
4503  From..to bits: 0...31
4504  DefaultValue: 0x0
4505  Access type: read-write
4506  Description: A read or write to this register will not clear the [RIS.TGT] interrupt.
4507 
4508  If [CTL.MODE] != QDEC.
4509  Target value for next counter period.
4510  The timer copies VAL to [TGT.VAL] when [CNTR.VAL] becomes 0. The copy does not happen when restarting the timer.
4511  This is useful to avoid period jitter in **PWM** applications with time-varying period, sometimes referenced as phase corrected PWM.
4512 
4513  If [CTL.MODE] = QDEC.
4514  The [CNTR.VAL] is updated with VAL on IDX. VAL is not loaded into [TGT.VAL] when [CNTR.VAL] becomes 0.
4515 
4516 */
4517 #define GPTIMER_PTGTNC_VAL_W 32U
4518 #define GPTIMER_PTGTNC_VAL_M 0xFFFFFFFFU
4519 #define GPTIMER_PTGTNC_VAL_S 0U
4520 
4521 
4522 /*-----------------------------------REGISTER------------------------------------
4523  Register name: PC0CCNC
4524  Offset name: GPTIMER_O_PC0CCNC
4525  Relative address: 0x180
4526  Description: Pipeline Channel 0 Capture Compare No Clear
4527  Default Value: 0x00000000
4528 
4529  Field: VAL
4530  From..to bits: 0...31
4531  DefaultValue: 0x0
4532  Access type: read-write
4533  Description: Pipeline Capture Compare value.
4534 
4535  User defined pipeline compare value or channel-updated capture value.
4536 
4537  A read or write to this register will not clear the [RIS.C0CC] interrupt.
4538 
4539  Compare mode:
4540  An update of VAL will be transferred to [C0CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for **PWM** generation and prevents jitter on the edges of the generated signal.
4541 
4542  Capture mode:
4543  When [C0CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C0CFG.EDGE].
4544 
4545 */
4546 #define GPTIMER_PC0CCNC_VAL_W 32U
4547 #define GPTIMER_PC0CCNC_VAL_M 0xFFFFFFFFU
4548 #define GPTIMER_PC0CCNC_VAL_S 0U
4549 
4550 
4551 /*-----------------------------------REGISTER------------------------------------
4552  Register name: PC1CCNC
4553  Offset name: GPTIMER_O_PC1CCNC
4554  Relative address: 0x184
4555  Description: Pipeline Channel 1 Capture Compare No Clear
4556  Default Value: 0x00000000
4557 
4558  Field: VAL
4559  From..to bits: 0...31
4560  DefaultValue: 0x0
4561  Access type: read-write
4562  Description: Pipeline Capture Compare value.
4563 
4564  User defined pipeline compare value or channel-updated capture value.
4565 
4566  A read or write to this register will not clear the [RIS.C1CC] interrupt.
4567 
4568  Compare mode:
4569  An update of VAL will be transferred to [C1CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for **PWM** generation and prevents jitter on the edges of the generated signal.
4570 
4571  Capture mode:
4572  When [C1CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C1CFG.EDGE].
4573 
4574 */
4575 #define GPTIMER_PC1CCNC_VAL_W 32U
4576 #define GPTIMER_PC1CCNC_VAL_M 0xFFFFFFFFU
4577 #define GPTIMER_PC1CCNC_VAL_S 0U
4578 
4579 
4580 /*-----------------------------------REGISTER------------------------------------
4581  Register name: PC2CCNC
4582  Offset name: GPTIMER_O_PC2CCNC
4583  Relative address: 0x188
4584  Description: Pipeline Channel 2 Capture Compare No Clear
4585  Default Value: 0x00000000
4586 
4587  Field: VAL
4588  From..to bits: 0...31
4589  DefaultValue: 0x0
4590  Access type: read-write
4591  Description: Pipeline Capture Compare value.
4592 
4593  User defined pipeline compare value or channel-updated capture value.
4594 
4595  A read or write to this register will not clear the [RIS.C2CC] interrupt.
4596 
4597  Compare mode:
4598  An update of VAL will be transferred to [C2CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for **PWM** generation and prevents jitter on the edges of the generated signal.
4599 
4600  Capture mode:
4601  When [C2CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C2CFG.EDGE].
4602 
4603 */
4604 #define GPTIMER_PC2CCNC_VAL_W 32U
4605 #define GPTIMER_PC2CCNC_VAL_M 0xFFFFFFFFU
4606 #define GPTIMER_PC2CCNC_VAL_S 0U
4607 
4608 
4609 /*-----------------------------------REGISTER------------------------------------
4610  Register name: PC3CCNC
4611  Offset name: GPTIMER_O_PC3CCNC
4612  Relative address: 0x18C
4613  Description: Pipeline Channel 3 Capture Compare No Clear
4614  Default Value: 0x00000000
4615 
4616  Field: VAL
4617  From..to bits: 0...31
4618  DefaultValue: 0x0
4619  Access type: read-write
4620  Description: Pipeline Capture Compare value.
4621 
4622  User defined pipeline compare value or channel-updated capture value.
4623 
4624  A read or write to this register will not clear the [RIS.C3CC] interrupt.
4625 
4626  Compare mode:
4627  An update of VAL will be transferred to [C3CC.VAL] when the next [CNTR.VAL] is zero and [CTL.MODE] is different from DIS. This is useful for **PWM** generation and prevents jitter on the edges of the generated signal.
4628 
4629  Capture mode:
4630  When [C3CFG.CCACT] equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by [C3CFG.EDGE].
4631 
4632 */
4633 #define GPTIMER_PC3CCNC_VAL_W 32U
4634 #define GPTIMER_PC3CCNC_VAL_M 0xFFFFFFFFU
4635 #define GPTIMER_PC3CCNC_VAL_S 0U
4636 
4637 
4638 /*-----------------------------------REGISTER------------------------------------
4639  Register name: TGTNC
4640  Offset name: GPTIMER_O_TGTNC
4641  Relative address: 0x1BC
4642  Description: Target No Clear
4643 
4644  Use this register to read or write to [TGT.*] without clearing the [RIS.ZERO] and [RIS.TGT] interrupt.
4645  Default Value: 0x00000000
4646 
4647  Field: VAL
4648  From..to bits: 0...31
4649  DefaultValue: 0x0
4650  Access type: read-write
4651  Description: User defined counter target value.
4652 
4653 */
4654 #define GPTIMER_TGTNC_VAL_W 32U
4655 #define GPTIMER_TGTNC_VAL_M 0xFFFFFFFFU
4656 #define GPTIMER_TGTNC_VAL_S 0U
4657 
4658 
4659 /*-----------------------------------REGISTER------------------------------------
4660  Register name: C0CCNC
4661  Offset name: GPTIMER_O_C0CCNC
4662  Relative address: 0x1C0
4663  Description: Channel 0 Capture Compare No Clear
4664  Default Value: 0x00000000
4665 
4666  Field: VAL
4667  From..to bits: 0...31
4668  DefaultValue: 0x0
4669  Access type: read-write
4670  Description: Capture Compare value.
4671 
4672  User defined compare value or channel-updated capture value.
4673 
4674  A read or write to this register will not clear the [RIS.C0CC] interrupt.
4675 
4676  Compare mode:
4677  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C0CFG.CCACT] when these are equal.
4678 
4679  Capture mode:
4680  The current counter value is stored in VAL when a capture event occurs. [C0CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4681 
4682 */
4683 #define GPTIMER_C0CCNC_VAL_W 32U
4684 #define GPTIMER_C0CCNC_VAL_M 0xFFFFFFFFU
4685 #define GPTIMER_C0CCNC_VAL_S 0U
4686 
4687 
4688 /*-----------------------------------REGISTER------------------------------------
4689  Register name: C1CCNC
4690  Offset name: GPTIMER_O_C1CCNC
4691  Relative address: 0x1C4
4692  Description: Channel 1 Capture Compare No Clear
4693  Default Value: 0x00000000
4694 
4695  Field: VAL
4696  From..to bits: 0...31
4697  DefaultValue: 0x0
4698  Access type: read-write
4699  Description: Capture Compare value.
4700 
4701  User defined compare value or channel-updated capture value.
4702 
4703  A read or write to this register will not clear the [RIS.C1CC] interrupt.
4704 
4705  Compare mode:
4706  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C1CFG.CCACT] when these are equal.
4707 
4708  Capture mode:
4709  The current counter value is stored in VAL when a capture event occurs. [C1CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4710 
4711 */
4712 #define GPTIMER_C1CCNC_VAL_W 32U
4713 #define GPTIMER_C1CCNC_VAL_M 0xFFFFFFFFU
4714 #define GPTIMER_C1CCNC_VAL_S 0U
4715 
4716 
4717 /*-----------------------------------REGISTER------------------------------------
4718  Register name: C2CCNC
4719  Offset name: GPTIMER_O_C2CCNC
4720  Relative address: 0x1C8
4721  Description: Channel 2 Capture Compare No Clear
4722  Default Value: 0x00000000
4723 
4724  Field: VAL
4725  From..to bits: 0...31
4726  DefaultValue: 0x0
4727  Access type: read-write
4728  Description: Capture Compare value.
4729 
4730  User defined compare value or channel-updated capture value.
4731 
4732  A read or write to this register will not clear the [RIS.C2CC] interrupt.
4733 
4734  Compare mode:
4735  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C2CFG.CCACT] when these are equal.
4736 
4737  Capture mode:
4738  The current counter value is stored in VAL when a capture event occurs. [C2CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4739 
4740 */
4741 #define GPTIMER_C2CCNC_VAL_W 32U
4742 #define GPTIMER_C2CCNC_VAL_M 0xFFFFFFFFU
4743 #define GPTIMER_C2CCNC_VAL_S 0U
4744 
4745 
4746 /*-----------------------------------REGISTER------------------------------------
4747  Register name: C3CCNC
4748  Offset name: GPTIMER_O_C3CCNC
4749  Relative address: 0x1CC
4750  Description: Channel 3 Capture Compare No Clear
4751  Default Value: 0x00000000
4752 
4753  Field: VAL
4754  From..to bits: 0...31
4755  DefaultValue: 0x0
4756  Access type: read-write
4757  Description: Capture Compare value.
4758 
4759  User defined compare value or channel-updated capture value.
4760 
4761  A read or write to this register will not clear the [RIS.C3CC] interrupt.
4762 
4763  Compare mode:
4764  VAL is compared against [CNTR.VAL] and an event is generated as specified by [C3CFG.CCACT] when these are equal.
4765 
4766  Capture mode:
4767  The current counter value is stored in VAL when a capture event occurs. [C3CFG.CCACT] determines if VAL is a signal period or a regular capture value.
4768 
4769 */
4770 #define GPTIMER_C3CCNC_VAL_W 32U
4771 #define GPTIMER_C3CCNC_VAL_M 0xFFFFFFFFU
4772 #define GPTIMER_C3CCNC_VAL_S 0U
4773 
4774 
4775 /*-----------------------------------REGISTER------------------------------------
4776  Register name: CLKCFG
4777  Offset name: GPTIMER_O_CLKCFG
4778  Relative address: 0x1000
4779  Description: Clock Enable Register
4780  Default Value: 0x00000000
4781 
4782  Field: ENABLE
4783  From..to bits: 0...0
4784  DefaultValue: 0x0
4785  Access type: read-write
4786  Description: GPTimer main clock Enable
4787 
4788 */
4789 #define GPTIMER_CLKCFG_ENABLE 0x00000001U
4790 #define GPTIMER_CLKCFG_ENABLE_M 0x00000001U
4791 #define GPTIMER_CLKCFG_ENABLE_S 0U
4792 
4793 #endif /* __HW_GPTIMER_H__*/