CC35xxDriverLibrary
hw_dcache.h
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1 /******************************************************************************
2 * Filename: hw_dcache.h
3 *
4 * Description: Defines and prototypes for the DCACHE peripheral.
5 *
6 * Copyright (c) 2023-2025, Texas Instruments Incorporated
7 * All rights reserved.
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35 ******************************************************************************/
36 #ifndef __HW_DCACHE_H__
37 #define __HW_DCACHE_H__
38 /*-------------------------------------------------------------------------------
39 
40 This section defines the register offsets of the DCACHE component
41 
42 --------------------------------------------------------------------------------- */
43 
44 //
45 #define DCACHE_O_MOD_VER 0x00000000U
46 
47 //
48 #define DCACHE_O_CTRL 0x00000004U
49 
50 //
51 #define DCACHE_O_STS 0x00000008U
52 
53 //
54 #define DCACHE_O_CAL 0x00000010U
55 
56 //
57 #define DCACHE_O_CAH 0x00000018U
58 
59 //
60 #define DCACHE_O_READ_COUNTER 0x00000040U
61 
62 //
63 #define DCACHE_O_WRITE_COUNTER 0x00000044U
64 
65 //When having OTFDE AHB error, Latch the address accessed by D-cache
66 #define DCACHE_O_ADDRESS_LATCH 0x00000048U
67 
68 //CACHE_FSM_STATE
69 #define DCACHE_O_CACHE_FSM_STATE 0x0000004CU
70 
71 //
72 #define DCACHE_O_IRQSTATUS_RAW 0x00000080U
73 
74 //
75 #define DCACHE_O_IRQSTATUS_MSK 0x00000084U
76 
77 //
78 #define DCACHE_O_IRQENABLE_SET 0x00000088U
79 
80 //
81 #define DCACHE_O_IRQENABLE_CLR 0x0000008CU
82 
83 //Flush and invalidates requests
84 #define DCACHE_O_CTRL1 0x000000C0U
85 
86 //Flush and invalidates status
87 #define DCACHE_O_STATUS1 0x000000C4U
88 
89 
90 
91 /*-----------------------------------REGISTER------------------------------------
92  Register name: MOD_VER
93  Offset name: DCACHE_O_MOD_VER
94  Relative address: 0x0
95  Description:
96  The Module and Version Register identifies the module identifier and revision of the L1 module.
97 
98  Default Value: 0x68800800
99 
100  Field: MINOR_REVISION
101  From..to bits: 0...5
102  DefaultValue: 0x0
103  Access type: read-only
104  Description: Minor Revision.
105 
106 */
107 #define DCACHE_MOD_VER_MINOR_REVISION_W 6U
108 #define DCACHE_MOD_VER_MINOR_REVISION_M 0x0000003FU
109 #define DCACHE_MOD_VER_MINOR_REVISION_S 0U
110 /*
111 
112  Field: CUSTOM_REVISION
113  From..to bits: 6...7
114  DefaultValue: 0x0
115  Access type: read-only
116  Description: Custom Revision.
117 
118 */
119 #define DCACHE_MOD_VER_CUSTOM_REVISION_W 2U
120 #define DCACHE_MOD_VER_CUSTOM_REVISION_M 0x000000C0U
121 #define DCACHE_MOD_VER_CUSTOM_REVISION_S 6U
122 /*
123 
124  Field: MAJOR_REVISION
125  From..to bits: 8...10
126  DefaultValue: 0x0
127  Access type: read-only
128  Description: Major Revision.
129 
130 */
131 #define DCACHE_MOD_VER_MAJOR_REVISION_W 3U
132 #define DCACHE_MOD_VER_MAJOR_REVISION_M 0x00000700U
133 #define DCACHE_MOD_VER_MAJOR_REVISION_S 8U
134 /*
135 
136  Field: RTL_VERSION
137  From..to bits: 11...15
138  DefaultValue: 0x1
139  Access type: read-only
140  Description: RTL Version.
141 
142 */
143 #define DCACHE_MOD_VER_RTL_VERSION_W 5U
144 #define DCACHE_MOD_VER_RTL_VERSION_M 0x0000F800U
145 #define DCACHE_MOD_VER_RTL_VERSION_S 11U
146 /*
147 
148  Field: MODULE_ID
149  From..to bits: 16...27
150  DefaultValue: 0x880
151  Access type: read-only
152  Description: L1 module ID.
153 
154 */
155 #define DCACHE_MOD_VER_MODULE_ID_W 12U
156 #define DCACHE_MOD_VER_MODULE_ID_M 0x0FFF0000U
157 #define DCACHE_MOD_VER_MODULE_ID_S 16U
158 /*
159 
160  Field: BU
161  From..to bits: 28...29
162  DefaultValue: 0x2
163  Access type: read-only
164  Description: Module Business Unit
165 
166 */
167 #define DCACHE_MOD_VER_BU_W 2U
168 #define DCACHE_MOD_VER_BU_M 0x30000000U
169 #define DCACHE_MOD_VER_BU_S 28U
170 /*
171 
172  Field: SCHEME
173  From..to bits: 30...31
174  DefaultValue: 0x1
175  Access type: read-only
176  Description: Module Scheme
177 
178 */
179 #define DCACHE_MOD_VER_SCHEME_W 2U
180 #define DCACHE_MOD_VER_SCHEME_M 0xC0000000U
181 #define DCACHE_MOD_VER_SCHEME_S 30U
182 
183 
184 /*-----------------------------------REGISTER------------------------------------
185  Register name: CTRL
186  Offset name: DCACHE_O_CTRL
187  Relative address: 0x4
188  Description:
189  The control register defines the size of the remote cache data storage memory to use and whether the L1 is enabled.
190 
191  Default Value: 0x40000000
192 
193  Field: RENABLE
194  From..to bits: 30...30
195  DefaultValue: 0x1
196  Access type: read-write
197  Description: The ~irenable field determines if half the cache space is RAM or cache. #br# 0: No RAM 64K of cache#br# 1: RAM 32K of cache, 32K of RAM. This field is write protected when ~icenable is set or the t_cfg_lock_ipcfg input is high.
198 
199 */
200 #define DCACHE_CTRL_RENABLE 0x40000000U
201 #define DCACHE_CTRL_RENABLE_M 0x40000000U
202 #define DCACHE_CTRL_RENABLE_S 30U
203 /*
204 
205  Field: CENABLE
206  From..to bits: 31...31
207  DefaultValue: 0x0
208  Access type: read-write
209  Description: The ~icenable field determines whether the L1 configuration is enabled or not.#br# 0: Disabled#br# 1: Enabled #br# This field is write protected when the t_cfg_lock_ipcfg input is high.
210 
211 */
212 #define DCACHE_CTRL_CENABLE 0x80000000U
213 #define DCACHE_CTRL_CENABLE_M 0x80000000U
214 #define DCACHE_CTRL_CENABLE_S 31U
215 
216 
217 /*-----------------------------------REGISTER------------------------------------
218  Register name: STS
219  Offset name: DCACHE_O_STS
220  Relative address: 0x8
221  Description:
222  The Status register displays the state of the L1 module
223 
224  Default Value: 0x00000000
225 
226  Field: OK_TO_GO
227  From..to bits: 31...31
228  DefaultValue: 0x0
229  Access type: read-only
230  Description: The ~iok_to_go status bit indicates the Tag/LRU Ram has been initialized and the cache is in an operable state.
231 
232 */
233 #define DCACHE_STS_OK_TO_GO 0x80000000U
234 #define DCACHE_STS_OK_TO_GO_M 0x80000000U
235 #define DCACHE_STS_OK_TO_GO_S 31U
236 
237 
238 /*-----------------------------------REGISTER------------------------------------
239  Register name: CAL
240  Offset name: DCACHE_O_CAL
241  Relative address: 0x10
242  Description:
243  The L1 Cache Address Low Register defines start of the L1 cacheable space. The L1 cache can cache up to a range of 8MB of of the target Flash as defined by CAL>=CachedRange<=CAH. This register is write protected when ~icenable is set or the t_cfg_lock_ipcfg input is high.
244 
245  Default Value: 0x00000000
246 
247  Field: ADDR_LO
248  From..to bits: 12...31
249  DefaultValue: 0x0
250  Access type: read-write
251  Description: The ~iaddr_lo defines the L1 low address[31:12] for the L1 to cache. The remaining bits 10:0 are assumed to be zero.
252 
253 */
254 #define DCACHE_CAL_ADDR_LO_W 20U
255 #define DCACHE_CAL_ADDR_LO_M 0xFFFFF000U
256 #define DCACHE_CAL_ADDR_LO_S 12U
257 
258 
259 /*-----------------------------------REGISTER------------------------------------
260  Register name: CAH
261  Offset name: DCACHE_O_CAH
262  Relative address: 0x18
263  Description:
264  The L1 Cache Address High Register defines end of the L1 cacheable space. The L1 cache can cache up to a range of 8MB of of the target Flash as defined by CAL>=CachedRange<=CAH. This register is write protected when ~icenable is set or the t_cfg_lock_ipcfg input is high.
265 
266  Default Value: 0x00000000
267 
268  Field: ADDR_HI
269  From..to bits: 12...31
270  DefaultValue: 0x0
271  Access type: read-write
272  Description: The ~iaddr_hi defines the L1 high address[31:12] for the L1 to cache. The remaining bits 10:0 are assumed to be ones.
273 
274 */
275 #define DCACHE_CAH_ADDR_HI_W 20U
276 #define DCACHE_CAH_ADDR_HI_M 0xFFFFF000U
277 #define DCACHE_CAH_ADDR_HI_S 12U
278 
279 
280 /*-----------------------------------REGISTER------------------------------------
281  Register name: READ_COUNTER
282  Offset name: DCACHE_O_READ_COUNTER
283  Relative address: 0x40
284  Description:
285  The L1 HIT Counter register holds the number of L1 Hits to the internal cache.
286 
287  Default Value: 0x00000000
288 
289  Field: READ_MISS_COUNTER
290  From..to bits: 0...11
291  DefaultValue: 0x0
292  Access type: read-write
293  Description: The miss Counts the number of misses to the L1 cache.
294  Writing zero to this register will clear its contents.
295 
296  When one reach the max, the rest of the counters are halted too.
297 
298 */
299 #define DCACHE_READ_COUNTER_READ_MISS_COUNTER_W 12U
300 #define DCACHE_READ_COUNTER_READ_MISS_COUNTER_M 0x00000FFFU
301 #define DCACHE_READ_COUNTER_READ_MISS_COUNTER_S 0U
302 /*
303 
304  Field: READ_HIT_COUNTER
305  From..to bits: 12...31
306  DefaultValue: 0x0
307  Access type: read-write
308  Description: The hit Counts the number of hits to the L1 cache.
309  Writing zero to this register will clear its contents
310 
311  When one reach the max, the rest of the counters are halted too.
312 
313 */
314 #define DCACHE_READ_COUNTER_READ_HIT_COUNTER_W 20U
315 #define DCACHE_READ_COUNTER_READ_HIT_COUNTER_M 0xFFFFF000U
316 #define DCACHE_READ_COUNTER_READ_HIT_COUNTER_S 12U
317 
318 
319 /*-----------------------------------REGISTER------------------------------------
320  Register name: WRITE_COUNTER
321  Offset name: DCACHE_O_WRITE_COUNTER
322  Relative address: 0x44
323  Description:
324  The L1 MISS Counter register holds the number of L1 Misses to the internal cache.
325 
326  Default Value: 0x00000000
327 
328  Field: WRITE_MISS_COUNTER
329  From..to bits: 0...11
330  DefaultValue: 0x0
331  Access type: read-write
332  Description: The miss Counts the number of misses to the L1 cache.
333  Writing zero to this register will clear its contents.
334 
335  When one reach the max, the rest of the counters are halted too
336 
337 */
338 #define DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_W 12U
339 #define DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_M 0x00000FFFU
340 #define DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_S 0U
341 /*
342 
343  Field: WRITE_HIT_COUNTER
344  From..to bits: 12...31
345  DefaultValue: 0x0
346  Access type: read-write
347  Description: The hit Counts the number of hits to the L1 cache.
348  Writing zero to this register will clear its contents.
349 
350  When one reach the max, the rest of the counters are halted too.
351 
352 */
353 #define DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_W 20U
354 #define DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_M 0xFFFFF000U
355 #define DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_S 12U
356 
357 
358 /*-----------------------------------REGISTER------------------------------------
359  Register name: ADDRESS_LATCH
360  Offset name: DCACHE_O_ADDRESS_LATCH
361  Relative address: 0x48
362  Description: When having OTFDE AHB error, Latch the address accessed by D-cache
363  Default Value: 0x00000000
364 
365  Field: ADDRESS_LATCH
366  From..to bits: 0...31
367  DefaultValue: 0x0
368  Access type: read-write
369  Description: When D-cache receive AHB error from the OTFDE it should latch the address accessed by D-cache.
370  (OTFDE generates an error for write only)
371 
372  Writing zero to this register will clear its contents.
373 
374 */
375 #define DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_W 32U
376 #define DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_M 0xFFFFFFFFU
377 #define DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_S 0U
378 
379 
380 /*-----------------------------------REGISTER------------------------------------
381  Register name: CACHE_FSM_STATE
382  Offset name: DCACHE_O_CACHE_FSM_STATE
383  Relative address: 0x4C
384  Description:
385  Default Value: NA
386 
387  Field: FSM_STATE
388  From..to bits: 0...4
389  DefaultValue: NA
390  Access type: read-only
391  Description: Dcache current FSM state
392 
393  WIDLE = 5'd0; - No access to D-cache
394  WRAMWR = 5'd1; - Data RAM Write
395  WRAMRD = 5'd2; - Data RAM Read
396  WCREADT = 5'd4; - Read Hit
397  WCREADC = 5'd5; - Read Miss
398  WCWRITET = 5'd6; - Write Hit
399  EVICT = 5'd7; -Write back to PSRAM
400  WR_ALLOC = 5'd8; - Write Allocate in write miss
401  RD_WA = 5'd9; - Word aligned read for a byte aligned read
402  WD = 5'd10; - Writing data to PSRAM
403  RDATA_CACHE = 5'd3; Reading data RAM for eviction
404  DEC_DIR = 5'd11; - Deciding direction
405  RDATA_CACHE_FLUSH = 5'd12; Reading data from data RAM for flush
406  RD_SET = 5'd13; Reading TAG & MRU
407  DET_GRANT = 5'd14; Detecting the granted way to evict
408  EVICT_FLUSH = 5'd15; Eviction during Flush
409  WD_DEBUG = 5'd16; Writing data to PSRAM during a debugger access
410 
411 */
412 #define DCACHE_CACHE_FSM_STATE_FSM_STATE_W 5U
413 #define DCACHE_CACHE_FSM_STATE_FSM_STATE_M 0x0000001FU
414 #define DCACHE_CACHE_FSM_STATE_FSM_STATE_S 0U
415 
416 
417 /*-----------------------------------REGISTER------------------------------------
418  Register name: IRQSTATUS_RAW
419  Offset name: DCACHE_O_IRQSTATUS_RAW
420  Relative address: 0x80
421  Description:
422  The Interrupt Raw Status Register holds the raw status of the L1 error interrupts.
423  Note: Read to the field of this register gives raw status of corresponding interrupt. S/W can set corresponding interrupt field for diagnostic purposes.
424 
425  Default Value: 0x00000000
426 
427  Field: LOCK_CFG_WR
428  From..to bits: 1...1
429  DefaultValue: 0x0
430  Access type: read-write
431  Description: The ~ilock_cfg_wr bit indicates a write to a locked configuration register has occured. Write 1 to set the ~ilock_cfg_wr status for diagnostic purposes. Writing a 0 has no effect.
432 
433 */
434 #define DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR 0x00000002U
435 #define DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_M 0x00000002U
436 #define DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_S 1U
437 
438 
439 /*-----------------------------------REGISTER------------------------------------
440  Register name: IRQSTATUS_MSK
441  Offset name: DCACHE_O_IRQSTATUS_MSK
442  Relative address: 0x84
443  Description:
444  The Interrupt Masked Status Register holds the masked status for the L1 error interrupts. Writing to this register will EOI the interrupt, that is if another interrupt is pending, a new pulse interrupt will be generated.
445  Note: Read to the field of this register gives masked status of corresponding interrupt. Writing 1 to the field of this register clears corresponding interrupt.
446 
447  Default Value: 0x00000000
448 
449  Field: LOCK_CFG_WR
450  From..to bits: 1...1
451  DefaultValue: 0x0
452  Access type: read-write
453  Description: The ~ilock_cfg_wr bit indicates a write to a locked configuration register has occured. Write 1 to clear the ~ilock_cfg_wr status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect to this field.
454 
455 */
456 #define DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR 0x00000002U
457 #define DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_M 0x00000002U
458 #define DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_S 1U
459 
460 
461 /*-----------------------------------REGISTER------------------------------------
462  Register name: IRQENABLE_SET
463  Offset name: DCACHE_O_IRQENABLE_SET
464  Relative address: 0x88
465  Description:
466  The Interrupt Enable Set Register holds the interrupt enable status of the L1 error interrupts.
467  Note:Writing 1 to field of this register will not mask the corresponding interrupt. IRQSTATUS_RAW and IRQSTATUS_MSK status field gives the same status.
468 
469  Default Value: 0x00000000
470 
471  Field: EN_LOCK_CFG_WR
472  From..to bits: 1...1
473  DefaultValue: 0x0
474  Access type: read-write
475  Description: Interrupt Enable Set for ~ilock_cfg_wr error bit. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.
476 
477 */
478 #define DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR 0x00000002U
479 #define DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_M 0x00000002U
480 #define DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_S 1U
481 
482 
483 /*-----------------------------------REGISTER------------------------------------
484  Register name: IRQENABLE_CLR
485  Offset name: DCACHE_O_IRQENABLE_CLR
486  Relative address: 0x8C
487  Description:
488  The Interrupt Enable Clear Register holds the interrupt enable status of the L1 error interrupts.
489  Note:Writing 1 to field of this register masks the corresponding interrupt. IRQSTATUS_RAW and IRQSTATUS_MSK status field gives the raw status and masked status respectively
490 
491  Default Value: 0x00000000
492 
493  Field: EN_LOCK_CFG_WR
494  From..to bits: 1...1
495  DefaultValue: 0x0
496  Access type: read-write
497  Description: Interrupt Enable Clear for ~ilock_cfg_wr error bit. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.
498 
499 */
500 #define DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR 0x00000002U
501 #define DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_M 0x00000002U
502 #define DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_S 1U
503 
504 
505 /*-----------------------------------REGISTER------------------------------------
506  Register name: CTRL1
507  Offset name: DCACHE_O_CTRL1
508  Relative address: 0xC0
509  Description: Flush and invalidates requests
510  Default Value: 0x00000000
511 
512  Field: INVALIDATE
513  From..to bits: 30...30
514  DefaultValue: 0x0
515  Access type: read-write
516  Description: 0x0 - Do nothing
517  0x1 - Invalidate
518  This bit is self cleared when invalidate completed
519 
520 
521 */
522 #define DCACHE_CTRL1_INVALIDATE 0x40000000U
523 #define DCACHE_CTRL1_INVALIDATE_M 0x40000000U
524 #define DCACHE_CTRL1_INVALIDATE_S 30U
525 /*
526 
527  Field: FLUSH
528  From..to bits: 31...31
529  DefaultValue: 0x0
530  Access type: read-write
531  Description: 0x0 - Do nothing
532  0x1 - Flush
533  The bit is self cleared when flush completed
534 
535 */
536 #define DCACHE_CTRL1_FLUSH 0x80000000U
537 #define DCACHE_CTRL1_FLUSH_M 0x80000000U
538 #define DCACHE_CTRL1_FLUSH_S 31U
539 
540 
541 /*-----------------------------------REGISTER------------------------------------
542  Register name: STATUS1
543  Offset name: DCACHE_O_STATUS1
544  Relative address: 0xC4
545  Description: Flush and invalidates status
546 
547  Default Value: 0x00000000
548 
549  Field: FLUSH_FAIL
550  From..to bits: 29...29
551  DefaultValue: 0x0
552  Access type: read-only
553  Description: This bit indicates that Flush has failed
554  ( Bit is cleared when Flush request bit is asserted )
555 
556 
557 */
558 #define DCACHE_STATUS1_FLUSH_FAIL 0x20000000U
559 #define DCACHE_STATUS1_FLUSH_FAIL_M 0x20000000U
560 #define DCACHE_STATUS1_FLUSH_FAIL_S 29U
561 /*
562 
563  Field: INVALIDATE_STATUS
564  From..to bits: 30...30
565  DefaultValue: 0x0
566  Access type: read-only
567  Description: This bit indicates that invalidate has been completed
568  ( Bit is cleared when flush request bit is asserted )
569 
570 */
571 #define DCACHE_STATUS1_INVALIDATE_STATUS 0x40000000U
572 #define DCACHE_STATUS1_INVALIDATE_STATUS_M 0x40000000U
573 #define DCACHE_STATUS1_INVALIDATE_STATUS_S 30U
574 /*
575 
576  Field: FLUSH_STATUS
577  From..to bits: 31...31
578  DefaultValue: 0x0
579  Access type: read-only
580  Description: This bit indicates that Flush as been completed
581  ( Bit is cleared when Flush request bit is asserted )
582 
583 */
584 #define DCACHE_STATUS1_FLUSH_STATUS 0x80000000U
585 #define DCACHE_STATUS1_FLUSH_STATUS_M 0x80000000U
586 #define DCACHE_STATUS1_FLUSH_STATUS_S 31U
587 
588 #endif /* __HW_DCACHE_H__*/