Macros
#define	DCACHE_O_MOD_VER 0x00000000U

#define	DCACHE_O_CTRL 0x00000004U

#define	DCACHE_O_STS 0x00000008U

#define	DCACHE_O_CAL 0x00000010U

#define	DCACHE_O_CAH 0x00000018U

#define	DCACHE_O_READ_COUNTER 0x00000040U

#define	DCACHE_O_WRITE_COUNTER 0x00000044U

#define	DCACHE_O_ADDRESS_LATCH 0x00000048U

#define	DCACHE_O_CACHE_FSM_STATE 0x0000004CU

#define	DCACHE_O_IRQSTATUS_RAW 0x00000080U

#define	DCACHE_O_IRQSTATUS_MSK 0x00000084U

#define	DCACHE_O_IRQENABLE_SET 0x00000088U

#define	DCACHE_O_IRQENABLE_CLR 0x0000008CU

#define	DCACHE_O_CTRL1 0x000000C0U

#define	DCACHE_O_STATUS1 0x000000C4U

#define	DCACHE_MOD_VER_MINOR_REVISION_W 6U

#define	DCACHE_MOD_VER_MINOR_REVISION_M 0x0000003FU

#define	DCACHE_MOD_VER_MINOR_REVISION_S 0U

#define	DCACHE_MOD_VER_CUSTOM_REVISION_W 2U

#define	DCACHE_MOD_VER_CUSTOM_REVISION_M 0x000000C0U

#define	DCACHE_MOD_VER_CUSTOM_REVISION_S 6U

#define	DCACHE_MOD_VER_MAJOR_REVISION_W 3U

#define	DCACHE_MOD_VER_MAJOR_REVISION_M 0x00000700U

#define	DCACHE_MOD_VER_MAJOR_REVISION_S 8U

#define	DCACHE_MOD_VER_RTL_VERSION_W 5U

#define	DCACHE_MOD_VER_RTL_VERSION_M 0x0000F800U

#define	DCACHE_MOD_VER_RTL_VERSION_S 11U

#define	DCACHE_MOD_VER_MODULE_ID_W 12U

#define	DCACHE_MOD_VER_MODULE_ID_M 0x0FFF0000U

#define	DCACHE_MOD_VER_MODULE_ID_S 16U

#define	DCACHE_MOD_VER_BU_W 2U

#define	DCACHE_MOD_VER_BU_M 0x30000000U

#define	DCACHE_MOD_VER_BU_S 28U

#define	DCACHE_MOD_VER_SCHEME_W 2U

#define	DCACHE_MOD_VER_SCHEME_M 0xC0000000U

#define	DCACHE_MOD_VER_SCHEME_S 30U

#define	DCACHE_CTRL_RENABLE 0x40000000U

#define	DCACHE_CTRL_RENABLE_M 0x40000000U

#define	DCACHE_CTRL_RENABLE_S 30U

#define	DCACHE_CTRL_CENABLE 0x80000000U

#define	DCACHE_CTRL_CENABLE_M 0x80000000U

#define	DCACHE_CTRL_CENABLE_S 31U

#define	DCACHE_STS_OK_TO_GO 0x80000000U

#define	DCACHE_STS_OK_TO_GO_M 0x80000000U

#define	DCACHE_STS_OK_TO_GO_S 31U

#define	DCACHE_CAL_ADDR_LO_W 20U

#define	DCACHE_CAL_ADDR_LO_M 0xFFFFF000U

#define	DCACHE_CAL_ADDR_LO_S 12U

#define	DCACHE_CAH_ADDR_HI_W 20U

#define	DCACHE_CAH_ADDR_HI_M 0xFFFFF000U

#define	DCACHE_CAH_ADDR_HI_S 12U

#define	DCACHE_READ_COUNTER_READ_MISS_COUNTER_W 12U

#define	DCACHE_READ_COUNTER_READ_MISS_COUNTER_M 0x00000FFFU

#define	DCACHE_READ_COUNTER_READ_MISS_COUNTER_S 0U

#define	DCACHE_READ_COUNTER_READ_HIT_COUNTER_W 20U

#define	DCACHE_READ_COUNTER_READ_HIT_COUNTER_M 0xFFFFF000U

#define	DCACHE_READ_COUNTER_READ_HIT_COUNTER_S 12U

#define	DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_W 12U

#define	DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_M 0x00000FFFU

#define	DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_S 0U

#define	DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_W 20U

#define	DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_M 0xFFFFF000U

#define	DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_S 12U

#define	DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_W 32U

#define	DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_M 0xFFFFFFFFU

#define	DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_S 0U

#define	DCACHE_CACHE_FSM_STATE_FSM_STATE_W 5U

#define	DCACHE_CACHE_FSM_STATE_FSM_STATE_M 0x0000001FU

#define	DCACHE_CACHE_FSM_STATE_FSM_STATE_S 0U

#define	DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR 0x00000002U

#define	DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_M 0x00000002U

#define	DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_S 1U

#define	DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR 0x00000002U

#define	DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_M 0x00000002U

#define	DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_S 1U

#define	DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR 0x00000002U

#define	DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_M 0x00000002U

#define	DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_S 1U

#define	DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR 0x00000002U

#define	DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_M 0x00000002U

#define	DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_S 1U

#define	DCACHE_CTRL1_INVALIDATE 0x40000000U

#define	DCACHE_CTRL1_INVALIDATE_M 0x40000000U

#define	DCACHE_CTRL1_INVALIDATE_S 30U

#define	DCACHE_CTRL1_FLUSH 0x80000000U

#define	DCACHE_CTRL1_FLUSH_M 0x80000000U

#define	DCACHE_CTRL1_FLUSH_S 31U

#define	DCACHE_STATUS1_FLUSH_FAIL 0x20000000U

#define	DCACHE_STATUS1_FLUSH_FAIL_M 0x20000000U

#define	DCACHE_STATUS1_FLUSH_FAIL_S 29U

#define	DCACHE_STATUS1_INVALIDATE_STATUS 0x40000000U

#define	DCACHE_STATUS1_INVALIDATE_STATUS_M 0x40000000U

#define	DCACHE_STATUS1_INVALIDATE_STATUS_S 30U

#define	DCACHE_STATUS1_FLUSH_STATUS 0x80000000U

#define	DCACHE_STATUS1_FLUSH_STATUS_M 0x80000000U

#define	DCACHE_STATUS1_FLUSH_STATUS_S 31U

Macro Definition Documentation

§ DCACHE_O_MOD_VER

#define DCACHE_O_MOD_VER 0x00000000U

§ DCACHE_O_CTRL

#define DCACHE_O_CTRL 0x00000004U

§ DCACHE_O_STS

#define DCACHE_O_STS 0x00000008U

§ DCACHE_O_CAL

#define DCACHE_O_CAL 0x00000010U

§ DCACHE_O_CAH

#define DCACHE_O_CAH 0x00000018U

§ DCACHE_O_READ_COUNTER

#define DCACHE_O_READ_COUNTER 0x00000040U

§ DCACHE_O_WRITE_COUNTER

#define DCACHE_O_WRITE_COUNTER 0x00000044U

§ DCACHE_O_ADDRESS_LATCH

#define DCACHE_O_ADDRESS_LATCH 0x00000048U

§ DCACHE_O_CACHE_FSM_STATE

#define DCACHE_O_CACHE_FSM_STATE 0x0000004CU

§ DCACHE_O_IRQSTATUS_RAW

#define DCACHE_O_IRQSTATUS_RAW 0x00000080U

§ DCACHE_O_IRQSTATUS_MSK

#define DCACHE_O_IRQSTATUS_MSK 0x00000084U

§ DCACHE_O_IRQENABLE_SET

#define DCACHE_O_IRQENABLE_SET 0x00000088U

§ DCACHE_O_IRQENABLE_CLR

#define DCACHE_O_IRQENABLE_CLR 0x0000008CU

§ DCACHE_O_CTRL1

#define DCACHE_O_CTRL1 0x000000C0U

§ DCACHE_O_STATUS1

#define DCACHE_O_STATUS1 0x000000C4U

§ DCACHE_MOD_VER_MINOR_REVISION_W

#define DCACHE_MOD_VER_MINOR_REVISION_W 6U

§ DCACHE_MOD_VER_MINOR_REVISION_M

#define DCACHE_MOD_VER_MINOR_REVISION_M 0x0000003FU

§ DCACHE_MOD_VER_MINOR_REVISION_S

#define DCACHE_MOD_VER_MINOR_REVISION_S 0U

§ DCACHE_MOD_VER_CUSTOM_REVISION_W

#define DCACHE_MOD_VER_CUSTOM_REVISION_W 2U

§ DCACHE_MOD_VER_CUSTOM_REVISION_M

#define DCACHE_MOD_VER_CUSTOM_REVISION_M 0x000000C0U

§ DCACHE_MOD_VER_CUSTOM_REVISION_S

#define DCACHE_MOD_VER_CUSTOM_REVISION_S 6U

§ DCACHE_MOD_VER_MAJOR_REVISION_W

#define DCACHE_MOD_VER_MAJOR_REVISION_W 3U

§ DCACHE_MOD_VER_MAJOR_REVISION_M

#define DCACHE_MOD_VER_MAJOR_REVISION_M 0x00000700U

§ DCACHE_MOD_VER_MAJOR_REVISION_S

#define DCACHE_MOD_VER_MAJOR_REVISION_S 8U

§ DCACHE_MOD_VER_RTL_VERSION_W

#define DCACHE_MOD_VER_RTL_VERSION_W 5U

§ DCACHE_MOD_VER_RTL_VERSION_M

#define DCACHE_MOD_VER_RTL_VERSION_M 0x0000F800U

§ DCACHE_MOD_VER_RTL_VERSION_S

#define DCACHE_MOD_VER_RTL_VERSION_S 11U

§ DCACHE_MOD_VER_MODULE_ID_W

#define DCACHE_MOD_VER_MODULE_ID_W 12U

§ DCACHE_MOD_VER_MODULE_ID_M

#define DCACHE_MOD_VER_MODULE_ID_M 0x0FFF0000U

§ DCACHE_MOD_VER_MODULE_ID_S

#define DCACHE_MOD_VER_MODULE_ID_S 16U

§ DCACHE_MOD_VER_BU_W

#define DCACHE_MOD_VER_BU_W 2U

§ DCACHE_MOD_VER_BU_M

#define DCACHE_MOD_VER_BU_M 0x30000000U

§ DCACHE_MOD_VER_BU_S

#define DCACHE_MOD_VER_BU_S 28U

§ DCACHE_MOD_VER_SCHEME_W

#define DCACHE_MOD_VER_SCHEME_W 2U

§ DCACHE_MOD_VER_SCHEME_M

#define DCACHE_MOD_VER_SCHEME_M 0xC0000000U

§ DCACHE_MOD_VER_SCHEME_S

#define DCACHE_MOD_VER_SCHEME_S 30U

§ DCACHE_CTRL_RENABLE

#define DCACHE_CTRL_RENABLE 0x40000000U

§ DCACHE_CTRL_RENABLE_M

#define DCACHE_CTRL_RENABLE_M 0x40000000U

§ DCACHE_CTRL_RENABLE_S

#define DCACHE_CTRL_RENABLE_S 30U

§ DCACHE_CTRL_CENABLE

#define DCACHE_CTRL_CENABLE 0x80000000U

§ DCACHE_CTRL_CENABLE_M

#define DCACHE_CTRL_CENABLE_M 0x80000000U

§ DCACHE_CTRL_CENABLE_S

#define DCACHE_CTRL_CENABLE_S 31U

§ DCACHE_STS_OK_TO_GO

#define DCACHE_STS_OK_TO_GO 0x80000000U

§ DCACHE_STS_OK_TO_GO_M

#define DCACHE_STS_OK_TO_GO_M 0x80000000U

§ DCACHE_STS_OK_TO_GO_S

#define DCACHE_STS_OK_TO_GO_S 31U

§ DCACHE_CAL_ADDR_LO_W

#define DCACHE_CAL_ADDR_LO_W 20U

§ DCACHE_CAL_ADDR_LO_M

#define DCACHE_CAL_ADDR_LO_M 0xFFFFF000U

§ DCACHE_CAL_ADDR_LO_S

#define DCACHE_CAL_ADDR_LO_S 12U

§ DCACHE_CAH_ADDR_HI_W

#define DCACHE_CAH_ADDR_HI_W 20U

§ DCACHE_CAH_ADDR_HI_M

#define DCACHE_CAH_ADDR_HI_M 0xFFFFF000U

§ DCACHE_CAH_ADDR_HI_S

#define DCACHE_CAH_ADDR_HI_S 12U

§ DCACHE_READ_COUNTER_READ_MISS_COUNTER_W

#define DCACHE_READ_COUNTER_READ_MISS_COUNTER_W 12U

§ DCACHE_READ_COUNTER_READ_MISS_COUNTER_M

#define DCACHE_READ_COUNTER_READ_MISS_COUNTER_M 0x00000FFFU

§ DCACHE_READ_COUNTER_READ_MISS_COUNTER_S

#define DCACHE_READ_COUNTER_READ_MISS_COUNTER_S 0U

§ DCACHE_READ_COUNTER_READ_HIT_COUNTER_W

#define DCACHE_READ_COUNTER_READ_HIT_COUNTER_W 20U

§ DCACHE_READ_COUNTER_READ_HIT_COUNTER_M

#define DCACHE_READ_COUNTER_READ_HIT_COUNTER_M 0xFFFFF000U

§ DCACHE_READ_COUNTER_READ_HIT_COUNTER_S

#define DCACHE_READ_COUNTER_READ_HIT_COUNTER_S 12U

§ DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_W

#define DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_W 12U

§ DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_M

#define DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_M 0x00000FFFU

§ DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_S

#define DCACHE_WRITE_COUNTER_WRITE_MISS_COUNTER_S 0U

§ DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_W

#define DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_W 20U

§ DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_M

#define DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_M 0xFFFFF000U

§ DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_S

#define DCACHE_WRITE_COUNTER_WRITE_HIT_COUNTER_S 12U

§ DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_W

#define DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_W 32U

§ DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_M

#define DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_M 0xFFFFFFFFU

§ DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_S

#define DCACHE_ADDRESS_LATCH_ADDRESS_LATCH_S 0U

§ DCACHE_CACHE_FSM_STATE_FSM_STATE_W

#define DCACHE_CACHE_FSM_STATE_FSM_STATE_W 5U

§ DCACHE_CACHE_FSM_STATE_FSM_STATE_M

#define DCACHE_CACHE_FSM_STATE_FSM_STATE_M 0x0000001FU

§ DCACHE_CACHE_FSM_STATE_FSM_STATE_S

#define DCACHE_CACHE_FSM_STATE_FSM_STATE_S 0U

§ DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR

#define DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR 0x00000002U

§ DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_M

#define DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_M 0x00000002U

§ DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_S

#define DCACHE_IRQSTATUS_RAW_LOCK_CFG_WR_S 1U

§ DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR

#define DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR 0x00000002U

§ DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_M

#define DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_M 0x00000002U

§ DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_S

#define DCACHE_IRQSTATUS_MSK_LOCK_CFG_WR_S 1U

§ DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR

#define DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR 0x00000002U

§ DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_M

#define DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_M 0x00000002U

§ DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_S

#define DCACHE_IRQENABLE_SET_EN_LOCK_CFG_WR_S 1U

§ DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR

#define DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR 0x00000002U

§ DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_M

#define DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_M 0x00000002U

§ DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_S

#define DCACHE_IRQENABLE_CLR_EN_LOCK_CFG_WR_S 1U

§ DCACHE_CTRL1_INVALIDATE

#define DCACHE_CTRL1_INVALIDATE 0x40000000U

§ DCACHE_CTRL1_INVALIDATE_M

#define DCACHE_CTRL1_INVALIDATE_M 0x40000000U

§ DCACHE_CTRL1_INVALIDATE_S

#define DCACHE_CTRL1_INVALIDATE_S 30U

§ DCACHE_CTRL1_FLUSH

#define DCACHE_CTRL1_FLUSH 0x80000000U

§ DCACHE_CTRL1_FLUSH_M

#define DCACHE_CTRL1_FLUSH_M 0x80000000U

§ DCACHE_CTRL1_FLUSH_S

#define DCACHE_CTRL1_FLUSH_S 31U

§ DCACHE_STATUS1_FLUSH_FAIL

#define DCACHE_STATUS1_FLUSH_FAIL 0x20000000U

§ DCACHE_STATUS1_FLUSH_FAIL_M

#define DCACHE_STATUS1_FLUSH_FAIL_M 0x20000000U

§ DCACHE_STATUS1_FLUSH_FAIL_S

#define DCACHE_STATUS1_FLUSH_FAIL_S 29U

§ DCACHE_STATUS1_INVALIDATE_STATUS

#define DCACHE_STATUS1_INVALIDATE_STATUS 0x40000000U

§ DCACHE_STATUS1_INVALIDATE_STATUS_M

#define DCACHE_STATUS1_INVALIDATE_STATUS_M 0x40000000U

§ DCACHE_STATUS1_INVALIDATE_STATUS_S

#define DCACHE_STATUS1_INVALIDATE_STATUS_S 30U

§ DCACHE_STATUS1_FLUSH_STATUS

#define DCACHE_STATUS1_FLUSH_STATUS 0x80000000U

§ DCACHE_STATUS1_FLUSH_STATUS_M

#define DCACHE_STATUS1_FLUSH_STATUS_M 0x80000000U

§ DCACHE_STATUS1_FLUSH_STATUS_S

#define DCACHE_STATUS1_FLUSH_STATUS_S 31U

Macros