Macros
#define	CORE_AON_O_INIT 0x00000004U

#define	CORE_AON_O_WUCSKP 0x00000008U

#define	CORE_AON_O_CPUWAIT 0x00000014U

#define	CORE_AON_O_CRMBCTL 0x00000018U

#define	CORE_AON_O_CFGWUTP 0x0000001CU

#define	CORE_AON_O_CFGWICSNS 0x00000024U

#define	CORE_AON_O_CFGTMRWU 0x0000002CU

#define	CORE_AON_O_CFGWDT 0x00000034U

#define	CORE_AON_O_WUREQ 0x00000038U

#define	CORE_AON_O_CFGSHSLP 0x00000040U

#define	CORE_AON_O_FCLKARMCMD 0x00000054U

#define	CORE_AON_O_SLPTIMSL 0x00000058U

#define	CORE_AON_O_TMREN 0x0000005CU

#define	CORE_AON_O_CATLSELOV 0x0000006CU

#define	CORE_AON_O_SLPTIMFAST 0x00000074U

#define	CORE_AON_O_IOWUANDIRQ 0x0000009CU

#define	CORE_AON_O_IOWUORIRQ 0x000000A0U

#define	CORE_AON_O_IOWUANDIRQ1 0x000000A4U

#define	CORE_AON_O_IOWUORIRQ1 0x000000A8U

#define	CORE_AON_O_TMRWUREQ 0x000000ACU

#define	CORE_AON_O_WDTREQ 0x000000B0U

#define	CORE_AON_O_FRCCR 0x000000D8U

#define	CORE_AON_O_CRICG 0x000000DCU

#define	CORE_AON_O_CRWUC 0x000000E0U

#define	CORE_AON_O_NABHIRQCFG 0x000000E4U

#define	CORE_AON_O_IOTP0 0x000000E8U

#define	CORE_AON_O_IOTP1 0x000000ECU

#define	CORE_AON_O_IOOENCFG0 0x000000F8U

#define	CORE_AON_O_IOOENCFG1 0x000000FCU

#define	CORE_AON_INIT_DISMMU 0x00000001U

#define	CORE_AON_INIT_DISMMU_M 0x00000001U

#define	CORE_AON_INIT_DISMMU_S 0U

#define	CORE_AON_INIT_TPDESCRF_W 3U

#define	CORE_AON_INIT_TPDESCRF_M 0x00000070U

#define	CORE_AON_INIT_TPDESCRF_S 4U

#define	CORE_AON_WUCSKP_PRCMVLD 0x00000001U

#define	CORE_AON_WUCSKP_PRCMVLD_M 0x00000001U

#define	CORE_AON_WUCSKP_PRCMVLD_S 0U

#define	CORE_AON_WUCSKP_PDVLD 0x00000002U

#define	CORE_AON_WUCSKP_PDVLD_M 0x00000002U

#define	CORE_AON_WUCSKP_PDVLD_S 1U

#define	CORE_AON_CPUWAIT_M3 0x00000001U

#define	CORE_AON_CPUWAIT_M3_M 0x00000001U

#define	CORE_AON_CPUWAIT_M3_S 0U

#define	CORE_AON_CPUWAIT_OVSEL 0x00000002U

#define	CORE_AON_CPUWAIT_OVSEL_M 0x00000002U

#define	CORE_AON_CPUWAIT_OVSEL_S 1U

#define	CORE_AON_CRMBCTL_OVEN 0x00000001U

#define	CORE_AON_CRMBCTL_OVEN_M 0x00000001U

#define	CORE_AON_CRMBCTL_OVEN_S 0U

#define	CORE_AON_CRMBCTL_OVVAL 0x00000100U

#define	CORE_AON_CRMBCTL_OVVAL_M 0x00000100U

#define	CORE_AON_CRMBCTL_OVVAL_S 8U

#define	CORE_AON_CFGWUTP_VAL_W 25U

#define	CORE_AON_CFGWUTP_VAL_M 0x01FFFFFFU

#define	CORE_AON_CFGWUTP_VAL_S 0U

#define	CORE_AON_CFGWICSNS_VAL_W 25U

#define	CORE_AON_CFGWICSNS_VAL_M 0x01FFFFFFU

#define	CORE_AON_CFGWICSNS_VAL_S 0U

#define	CORE_AON_CFGTMRWU_THR_W 31U

#define	CORE_AON_CFGTMRWU_THR_M 0x7FFFFFFFU

#define	CORE_AON_CFGTMRWU_THR_S 0U

#define	CORE_AON_CFGTMRWU_EN 0x80000000U

#define	CORE_AON_CFGTMRWU_EN_M 0x80000000U

#define	CORE_AON_CFGTMRWU_EN_S 31U

#define	CORE_AON_CFGWDT_THR_W 23U

#define	CORE_AON_CFGWDT_THR_M 0x7FFFFF00U

#define	CORE_AON_CFGWDT_THR_S 8U

#define	CORE_AON_CFGWDT_EN 0x80000000U

#define	CORE_AON_CFGWDT_EN_M 0x80000000U

#define	CORE_AON_CFGWDT_EN_S 31U

#define	CORE_AON_WUREQ_EVTVAL_W 25U

#define	CORE_AON_WUREQ_EVTVAL_M 0x01FFFFFFU

#define	CORE_AON_WUREQ_EVTVAL_S 0U

#define	CORE_AON_CFGSHSLP_CLKREQ 0x00000001U

#define	CORE_AON_CFGSHSLP_CLKREQ_M 0x00000001U

#define	CORE_AON_CFGSHSLP_CLKREQ_S 0U

#define	CORE_AON_FCLKARMCMD_VAL_W 16U

#define	CORE_AON_FCLKARMCMD_VAL_M 0x0000FFFFU

#define	CORE_AON_FCLKARMCMD_VAL_S 0U

#define	CORE_AON_SLPTIMSL_CLK_W 32U

#define	CORE_AON_SLPTIMSL_CLK_M 0xFFFFFFFFU

#define	CORE_AON_SLPTIMSL_CLK_S 0U

#define	CORE_AON_TMREN_VAL 0x00000001U

#define	CORE_AON_TMREN_VAL_M 0x00000001U

#define	CORE_AON_TMREN_VAL_S 0U

#define	CORE_AON_TMREN_TMRSWCTL 0x00000002U

#define	CORE_AON_TMREN_TMRSWCTL_M 0x00000002U

#define	CORE_AON_TMREN_TMRSWCTL_S 1U

#define	CORE_AON_TMREN_TMRSET 0x00000004U

#define	CORE_AON_TMREN_TMRSET_M 0x00000004U

#define	CORE_AON_TMREN_TMRSET_S 2U

#define	CORE_AON_TMREN_TMRRST 0x00000008U

#define	CORE_AON_TMREN_TMRRST_M 0x00000008U

#define	CORE_AON_TMREN_TMRRST_S 3U

#define	CORE_AON_TMREN_TMRLD 0x00010000U

#define	CORE_AON_TMREN_TMRLD_M 0x00010000U

#define	CORE_AON_TMREN_TMRLD_S 16U

#define	CORE_AON_CATLSELOV_EN 0x00000001U

#define	CORE_AON_CATLSELOV_EN_M 0x00000001U

#define	CORE_AON_CATLSELOV_EN_S 0U

#define	CORE_AON_CATLSELOV_VAL_W 4U

#define	CORE_AON_CATLSELOV_VAL_M 0x00000F00U

#define	CORE_AON_CATLSELOV_VAL_S 8U

#define	CORE_AON_SLPTIMFAST_CLK_W 11U

#define	CORE_AON_SLPTIMFAST_CLK_M 0x000007FFU

#define	CORE_AON_SLPTIMFAST_CLK_S 0U

#define	CORE_AON_IOWUANDIRQ_0T31BM_W 32U

#define	CORE_AON_IOWUANDIRQ_0T31BM_M 0xFFFFFFFFU

#define	CORE_AON_IOWUANDIRQ_0T31BM_S 0U

#define	CORE_AON_IOWUORIRQ_0T31BM_W 32U

#define	CORE_AON_IOWUORIRQ_0T31BM_M 0xFFFFFFFFU

#define	CORE_AON_IOWUORIRQ_0T31BM_S 0U

#define	CORE_AON_IOWUANDIRQ1_32T44BM_W 13U

#define	CORE_AON_IOWUANDIRQ1_32T44BM_M 0x00001FFFU

#define	CORE_AON_IOWUANDIRQ1_32T44BM_S 0U

#define	CORE_AON_IOWUORIRQ1_32T44BM_W 13U

#define	CORE_AON_IOWUORIRQ1_32T44BM_M 0x00001FFFU

#define	CORE_AON_IOWUORIRQ1_32T44BM_S 0U

#define	CORE_AON_TMRWUREQ_CLR 0x00000001U

#define	CORE_AON_TMRWUREQ_CLR_M 0x00000001U

#define	CORE_AON_TMRWUREQ_CLR_S 0U

#define	CORE_AON_WDTREQ_CLR 0x00000001U

#define	CORE_AON_WDTREQ_CLR_M 0x00000001U

#define	CORE_AON_WDTREQ_CLR_S 0U

#define	CORE_AON_FRCCR_ON 0x00000001U

#define	CORE_AON_FRCCR_ON_M 0x00000001U

#define	CORE_AON_FRCCR_ON_S 0U

#define	CORE_AON_CRICG_CLRTHR_W 3U

#define	CORE_AON_CRICG_CLRTHR_M 0x00000007U

#define	CORE_AON_CRICG_CLRTHR_S 0U

#define	CORE_AON_CRICG_SETTHR_W 3U

#define	CORE_AON_CRICG_SETTHR_M 0x00000700U

#define	CORE_AON_CRICG_SETTHR_S 8U

#define	CORE_AON_CRICG_OVEN 0x00000800U

#define	CORE_AON_CRICG_OVEN_M 0x00000800U

#define	CORE_AON_CRICG_OVEN_S 11U

#define	CORE_AON_CRICG_OVVAL 0x00001000U

#define	CORE_AON_CRICG_OVVAL_M 0x00001000U

#define	CORE_AON_CRICG_OVVAL_S 12U

#define	CORE_AON_CRWUC_STA_W 3U

#define	CORE_AON_CRWUC_STA_M 0x00000007U

#define	CORE_AON_CRWUC_STA_S 0U

#define	CORE_AON_NABHIRQCFG_POL 0x00000001U

#define	CORE_AON_NABHIRQCFG_POL_M 0x00000001U

#define	CORE_AON_NABHIRQCFG_POL_S 0U

#define	CORE_AON_IOTP0_VAL_W 32U

#define	CORE_AON_IOTP0_VAL_M 0xFFFFFFFFU

#define	CORE_AON_IOTP0_VAL_S 0U

#define	CORE_AON_IOTP1_VAL_W 13U

#define	CORE_AON_IOTP1_VAL_M 0x00001FFFU

#define	CORE_AON_IOTP1_VAL_S 0U

#define	CORE_AON_IOTP1_SRC_W 8U

#define	CORE_AON_IOTP1_SRC_M 0xFF000000U

#define	CORE_AON_IOTP1_SRC_S 24U

#define	CORE_AON_IOOENCFG0_VAL_W 32U

#define	CORE_AON_IOOENCFG0_VAL_M 0xFFFFFFFFU

#define	CORE_AON_IOOENCFG0_VAL_S 0U

#define	CORE_AON_IOOENCFG1_VAL_W 13U

#define	CORE_AON_IOOENCFG1_VAL_M 0x00001FFFU

#define	CORE_AON_IOOENCFG1_VAL_S 0U

Macro Definition Documentation

§ CORE_AON_O_INIT

#define CORE_AON_O_INIT 0x00000004U

§ CORE_AON_O_WUCSKP

#define CORE_AON_O_WUCSKP 0x00000008U

§ CORE_AON_O_CPUWAIT

#define CORE_AON_O_CPUWAIT 0x00000014U

§ CORE_AON_O_CRMBCTL

#define CORE_AON_O_CRMBCTL 0x00000018U

§ CORE_AON_O_CFGWUTP

#define CORE_AON_O_CFGWUTP 0x0000001CU

§ CORE_AON_O_CFGWICSNS

#define CORE_AON_O_CFGWICSNS 0x00000024U

§ CORE_AON_O_CFGTMRWU

#define CORE_AON_O_CFGTMRWU 0x0000002CU

§ CORE_AON_O_CFGWDT

#define CORE_AON_O_CFGWDT 0x00000034U

§ CORE_AON_O_WUREQ

#define CORE_AON_O_WUREQ 0x00000038U

§ CORE_AON_O_CFGSHSLP

#define CORE_AON_O_CFGSHSLP 0x00000040U

§ CORE_AON_O_FCLKARMCMD

#define CORE_AON_O_FCLKARMCMD 0x00000054U

§ CORE_AON_O_SLPTIMSL

#define CORE_AON_O_SLPTIMSL 0x00000058U

§ CORE_AON_O_TMREN

#define CORE_AON_O_TMREN 0x0000005CU

§ CORE_AON_O_CATLSELOV

#define CORE_AON_O_CATLSELOV 0x0000006CU

§ CORE_AON_O_SLPTIMFAST

#define CORE_AON_O_SLPTIMFAST 0x00000074U

§ CORE_AON_O_IOWUANDIRQ

#define CORE_AON_O_IOWUANDIRQ 0x0000009CU

§ CORE_AON_O_IOWUORIRQ

#define CORE_AON_O_IOWUORIRQ 0x000000A0U

§ CORE_AON_O_IOWUANDIRQ1

#define CORE_AON_O_IOWUANDIRQ1 0x000000A4U

§ CORE_AON_O_IOWUORIRQ1

#define CORE_AON_O_IOWUORIRQ1 0x000000A8U

§ CORE_AON_O_TMRWUREQ

#define CORE_AON_O_TMRWUREQ 0x000000ACU

§ CORE_AON_O_WDTREQ

#define CORE_AON_O_WDTREQ 0x000000B0U

§ CORE_AON_O_FRCCR

#define CORE_AON_O_FRCCR 0x000000D8U

§ CORE_AON_O_CRICG

#define CORE_AON_O_CRICG 0x000000DCU

§ CORE_AON_O_CRWUC

#define CORE_AON_O_CRWUC 0x000000E0U

§ CORE_AON_O_NABHIRQCFG

#define CORE_AON_O_NABHIRQCFG 0x000000E4U

§ CORE_AON_O_IOTP0

#define CORE_AON_O_IOTP0 0x000000E8U

§ CORE_AON_O_IOTP1

#define CORE_AON_O_IOTP1 0x000000ECU

§ CORE_AON_O_IOOENCFG0

#define CORE_AON_O_IOOENCFG0 0x000000F8U

§ CORE_AON_O_IOOENCFG1

#define CORE_AON_O_IOOENCFG1 0x000000FCU

§ CORE_AON_INIT_DISMMU

#define CORE_AON_INIT_DISMMU 0x00000001U

§ CORE_AON_INIT_DISMMU_M

#define CORE_AON_INIT_DISMMU_M 0x00000001U

§ CORE_AON_INIT_DISMMU_S

#define CORE_AON_INIT_DISMMU_S 0U

§ CORE_AON_INIT_TPDESCRF_W

#define CORE_AON_INIT_TPDESCRF_W 3U

§ CORE_AON_INIT_TPDESCRF_M

#define CORE_AON_INIT_TPDESCRF_M 0x00000070U

§ CORE_AON_INIT_TPDESCRF_S

#define CORE_AON_INIT_TPDESCRF_S 4U

§ CORE_AON_WUCSKP_PRCMVLD

#define CORE_AON_WUCSKP_PRCMVLD 0x00000001U

§ CORE_AON_WUCSKP_PRCMVLD_M

#define CORE_AON_WUCSKP_PRCMVLD_M 0x00000001U

§ CORE_AON_WUCSKP_PRCMVLD_S

#define CORE_AON_WUCSKP_PRCMVLD_S 0U

§ CORE_AON_WUCSKP_PDVLD

#define CORE_AON_WUCSKP_PDVLD 0x00000002U

§ CORE_AON_WUCSKP_PDVLD_M

#define CORE_AON_WUCSKP_PDVLD_M 0x00000002U

§ CORE_AON_WUCSKP_PDVLD_S

#define CORE_AON_WUCSKP_PDVLD_S 1U

§ CORE_AON_CPUWAIT_M3

#define CORE_AON_CPUWAIT_M3 0x00000001U

§ CORE_AON_CPUWAIT_M3_M

#define CORE_AON_CPUWAIT_M3_M 0x00000001U

§ CORE_AON_CPUWAIT_M3_S

#define CORE_AON_CPUWAIT_M3_S 0U

§ CORE_AON_CPUWAIT_OVSEL

#define CORE_AON_CPUWAIT_OVSEL 0x00000002U

§ CORE_AON_CPUWAIT_OVSEL_M

#define CORE_AON_CPUWAIT_OVSEL_M 0x00000002U

§ CORE_AON_CPUWAIT_OVSEL_S

#define CORE_AON_CPUWAIT_OVSEL_S 1U

§ CORE_AON_CRMBCTL_OVEN

#define CORE_AON_CRMBCTL_OVEN 0x00000001U

§ CORE_AON_CRMBCTL_OVEN_M

#define CORE_AON_CRMBCTL_OVEN_M 0x00000001U

§ CORE_AON_CRMBCTL_OVEN_S

#define CORE_AON_CRMBCTL_OVEN_S 0U

§ CORE_AON_CRMBCTL_OVVAL

#define CORE_AON_CRMBCTL_OVVAL 0x00000100U

§ CORE_AON_CRMBCTL_OVVAL_M

#define CORE_AON_CRMBCTL_OVVAL_M 0x00000100U

§ CORE_AON_CRMBCTL_OVVAL_S

#define CORE_AON_CRMBCTL_OVVAL_S 8U

§ CORE_AON_CFGWUTP_VAL_W

#define CORE_AON_CFGWUTP_VAL_W 25U

§ CORE_AON_CFGWUTP_VAL_M

#define CORE_AON_CFGWUTP_VAL_M 0x01FFFFFFU

§ CORE_AON_CFGWUTP_VAL_S

#define CORE_AON_CFGWUTP_VAL_S 0U

§ CORE_AON_CFGWICSNS_VAL_W

#define CORE_AON_CFGWICSNS_VAL_W 25U

§ CORE_AON_CFGWICSNS_VAL_M

#define CORE_AON_CFGWICSNS_VAL_M 0x01FFFFFFU

§ CORE_AON_CFGWICSNS_VAL_S

#define CORE_AON_CFGWICSNS_VAL_S 0U

§ CORE_AON_CFGTMRWU_THR_W

#define CORE_AON_CFGTMRWU_THR_W 31U

§ CORE_AON_CFGTMRWU_THR_M

#define CORE_AON_CFGTMRWU_THR_M 0x7FFFFFFFU

§ CORE_AON_CFGTMRWU_THR_S

#define CORE_AON_CFGTMRWU_THR_S 0U

§ CORE_AON_CFGTMRWU_EN

#define CORE_AON_CFGTMRWU_EN 0x80000000U

§ CORE_AON_CFGTMRWU_EN_M

#define CORE_AON_CFGTMRWU_EN_M 0x80000000U

§ CORE_AON_CFGTMRWU_EN_S

#define CORE_AON_CFGTMRWU_EN_S 31U

§ CORE_AON_CFGWDT_THR_W

#define CORE_AON_CFGWDT_THR_W 23U

§ CORE_AON_CFGWDT_THR_M

#define CORE_AON_CFGWDT_THR_M 0x7FFFFF00U

§ CORE_AON_CFGWDT_THR_S

#define CORE_AON_CFGWDT_THR_S 8U

§ CORE_AON_CFGWDT_EN

#define CORE_AON_CFGWDT_EN 0x80000000U

§ CORE_AON_CFGWDT_EN_M

#define CORE_AON_CFGWDT_EN_M 0x80000000U

§ CORE_AON_CFGWDT_EN_S

#define CORE_AON_CFGWDT_EN_S 31U

§ CORE_AON_WUREQ_EVTVAL_W

#define CORE_AON_WUREQ_EVTVAL_W 25U

§ CORE_AON_WUREQ_EVTVAL_M

#define CORE_AON_WUREQ_EVTVAL_M 0x01FFFFFFU

§ CORE_AON_WUREQ_EVTVAL_S

#define CORE_AON_WUREQ_EVTVAL_S 0U

§ CORE_AON_CFGSHSLP_CLKREQ

#define CORE_AON_CFGSHSLP_CLKREQ 0x00000001U

§ CORE_AON_CFGSHSLP_CLKREQ_M

#define CORE_AON_CFGSHSLP_CLKREQ_M 0x00000001U

§ CORE_AON_CFGSHSLP_CLKREQ_S

#define CORE_AON_CFGSHSLP_CLKREQ_S 0U

§ CORE_AON_FCLKARMCMD_VAL_W

#define CORE_AON_FCLKARMCMD_VAL_W 16U

§ CORE_AON_FCLKARMCMD_VAL_M

#define CORE_AON_FCLKARMCMD_VAL_M 0x0000FFFFU

§ CORE_AON_FCLKARMCMD_VAL_S

#define CORE_AON_FCLKARMCMD_VAL_S 0U

§ CORE_AON_SLPTIMSL_CLK_W

#define CORE_AON_SLPTIMSL_CLK_W 32U

§ CORE_AON_SLPTIMSL_CLK_M

#define CORE_AON_SLPTIMSL_CLK_M 0xFFFFFFFFU

§ CORE_AON_SLPTIMSL_CLK_S

#define CORE_AON_SLPTIMSL_CLK_S 0U

§ CORE_AON_TMREN_VAL

#define CORE_AON_TMREN_VAL 0x00000001U

§ CORE_AON_TMREN_VAL_M

#define CORE_AON_TMREN_VAL_M 0x00000001U

§ CORE_AON_TMREN_VAL_S

#define CORE_AON_TMREN_VAL_S 0U

§ CORE_AON_TMREN_TMRSWCTL

#define CORE_AON_TMREN_TMRSWCTL 0x00000002U

§ CORE_AON_TMREN_TMRSWCTL_M

#define CORE_AON_TMREN_TMRSWCTL_M 0x00000002U

§ CORE_AON_TMREN_TMRSWCTL_S

#define CORE_AON_TMREN_TMRSWCTL_S 1U

§ CORE_AON_TMREN_TMRSET

#define CORE_AON_TMREN_TMRSET 0x00000004U

§ CORE_AON_TMREN_TMRSET_M

#define CORE_AON_TMREN_TMRSET_M 0x00000004U

§ CORE_AON_TMREN_TMRSET_S

#define CORE_AON_TMREN_TMRSET_S 2U

§ CORE_AON_TMREN_TMRRST

#define CORE_AON_TMREN_TMRRST 0x00000008U

§ CORE_AON_TMREN_TMRRST_M

#define CORE_AON_TMREN_TMRRST_M 0x00000008U

§ CORE_AON_TMREN_TMRRST_S

#define CORE_AON_TMREN_TMRRST_S 3U

§ CORE_AON_TMREN_TMRLD

#define CORE_AON_TMREN_TMRLD 0x00010000U

§ CORE_AON_TMREN_TMRLD_M

#define CORE_AON_TMREN_TMRLD_M 0x00010000U

§ CORE_AON_TMREN_TMRLD_S

#define CORE_AON_TMREN_TMRLD_S 16U

§ CORE_AON_CATLSELOV_EN

#define CORE_AON_CATLSELOV_EN 0x00000001U

§ CORE_AON_CATLSELOV_EN_M

#define CORE_AON_CATLSELOV_EN_M 0x00000001U

§ CORE_AON_CATLSELOV_EN_S

#define CORE_AON_CATLSELOV_EN_S 0U

§ CORE_AON_CATLSELOV_VAL_W

#define CORE_AON_CATLSELOV_VAL_W 4U

§ CORE_AON_CATLSELOV_VAL_M

#define CORE_AON_CATLSELOV_VAL_M 0x00000F00U

§ CORE_AON_CATLSELOV_VAL_S

#define CORE_AON_CATLSELOV_VAL_S 8U

§ CORE_AON_SLPTIMFAST_CLK_W

#define CORE_AON_SLPTIMFAST_CLK_W 11U

§ CORE_AON_SLPTIMFAST_CLK_M

#define CORE_AON_SLPTIMFAST_CLK_M 0x000007FFU

§ CORE_AON_SLPTIMFAST_CLK_S

#define CORE_AON_SLPTIMFAST_CLK_S 0U

§ CORE_AON_IOWUANDIRQ_0T31BM_W

#define CORE_AON_IOWUANDIRQ_0T31BM_W 32U

§ CORE_AON_IOWUANDIRQ_0T31BM_M

#define CORE_AON_IOWUANDIRQ_0T31BM_M 0xFFFFFFFFU

§ CORE_AON_IOWUANDIRQ_0T31BM_S

#define CORE_AON_IOWUANDIRQ_0T31BM_S 0U

§ CORE_AON_IOWUORIRQ_0T31BM_W

#define CORE_AON_IOWUORIRQ_0T31BM_W 32U

§ CORE_AON_IOWUORIRQ_0T31BM_M

#define CORE_AON_IOWUORIRQ_0T31BM_M 0xFFFFFFFFU

§ CORE_AON_IOWUORIRQ_0T31BM_S

#define CORE_AON_IOWUORIRQ_0T31BM_S 0U

§ CORE_AON_IOWUANDIRQ1_32T44BM_W

#define CORE_AON_IOWUANDIRQ1_32T44BM_W 13U

§ CORE_AON_IOWUANDIRQ1_32T44BM_M

#define CORE_AON_IOWUANDIRQ1_32T44BM_M 0x00001FFFU

§ CORE_AON_IOWUANDIRQ1_32T44BM_S

#define CORE_AON_IOWUANDIRQ1_32T44BM_S 0U

§ CORE_AON_IOWUORIRQ1_32T44BM_W

#define CORE_AON_IOWUORIRQ1_32T44BM_W 13U

§ CORE_AON_IOWUORIRQ1_32T44BM_M

#define CORE_AON_IOWUORIRQ1_32T44BM_M 0x00001FFFU

§ CORE_AON_IOWUORIRQ1_32T44BM_S

#define CORE_AON_IOWUORIRQ1_32T44BM_S 0U

§ CORE_AON_TMRWUREQ_CLR

#define CORE_AON_TMRWUREQ_CLR 0x00000001U

§ CORE_AON_TMRWUREQ_CLR_M

#define CORE_AON_TMRWUREQ_CLR_M 0x00000001U

§ CORE_AON_TMRWUREQ_CLR_S

#define CORE_AON_TMRWUREQ_CLR_S 0U

§ CORE_AON_WDTREQ_CLR

#define CORE_AON_WDTREQ_CLR 0x00000001U

§ CORE_AON_WDTREQ_CLR_M

#define CORE_AON_WDTREQ_CLR_M 0x00000001U

§ CORE_AON_WDTREQ_CLR_S

#define CORE_AON_WDTREQ_CLR_S 0U

§ CORE_AON_FRCCR_ON

#define CORE_AON_FRCCR_ON 0x00000001U

§ CORE_AON_FRCCR_ON_M

#define CORE_AON_FRCCR_ON_M 0x00000001U

§ CORE_AON_FRCCR_ON_S

#define CORE_AON_FRCCR_ON_S 0U

§ CORE_AON_CRICG_CLRTHR_W

#define CORE_AON_CRICG_CLRTHR_W 3U

§ CORE_AON_CRICG_CLRTHR_M

#define CORE_AON_CRICG_CLRTHR_M 0x00000007U

§ CORE_AON_CRICG_CLRTHR_S

#define CORE_AON_CRICG_CLRTHR_S 0U

§ CORE_AON_CRICG_SETTHR_W

#define CORE_AON_CRICG_SETTHR_W 3U

§ CORE_AON_CRICG_SETTHR_M

#define CORE_AON_CRICG_SETTHR_M 0x00000700U

§ CORE_AON_CRICG_SETTHR_S

#define CORE_AON_CRICG_SETTHR_S 8U

§ CORE_AON_CRICG_OVEN

#define CORE_AON_CRICG_OVEN 0x00000800U

§ CORE_AON_CRICG_OVEN_M

#define CORE_AON_CRICG_OVEN_M 0x00000800U

§ CORE_AON_CRICG_OVEN_S

#define CORE_AON_CRICG_OVEN_S 11U

§ CORE_AON_CRICG_OVVAL

#define CORE_AON_CRICG_OVVAL 0x00001000U

§ CORE_AON_CRICG_OVVAL_M

#define CORE_AON_CRICG_OVVAL_M 0x00001000U

§ CORE_AON_CRICG_OVVAL_S

#define CORE_AON_CRICG_OVVAL_S 12U

§ CORE_AON_CRWUC_STA_W

#define CORE_AON_CRWUC_STA_W 3U

§ CORE_AON_CRWUC_STA_M

#define CORE_AON_CRWUC_STA_M 0x00000007U

§ CORE_AON_CRWUC_STA_S

#define CORE_AON_CRWUC_STA_S 0U

§ CORE_AON_NABHIRQCFG_POL

#define CORE_AON_NABHIRQCFG_POL 0x00000001U

§ CORE_AON_NABHIRQCFG_POL_M

#define CORE_AON_NABHIRQCFG_POL_M 0x00000001U

§ CORE_AON_NABHIRQCFG_POL_S

#define CORE_AON_NABHIRQCFG_POL_S 0U

§ CORE_AON_IOTP0_VAL_W

#define CORE_AON_IOTP0_VAL_W 32U

§ CORE_AON_IOTP0_VAL_M

#define CORE_AON_IOTP0_VAL_M 0xFFFFFFFFU

§ CORE_AON_IOTP0_VAL_S

#define CORE_AON_IOTP0_VAL_S 0U

§ CORE_AON_IOTP1_VAL_W

#define CORE_AON_IOTP1_VAL_W 13U

§ CORE_AON_IOTP1_VAL_M

#define CORE_AON_IOTP1_VAL_M 0x00001FFFU

§ CORE_AON_IOTP1_VAL_S

#define CORE_AON_IOTP1_VAL_S 0U

§ CORE_AON_IOTP1_SRC_W

#define CORE_AON_IOTP1_SRC_W 8U

§ CORE_AON_IOTP1_SRC_M

#define CORE_AON_IOTP1_SRC_M 0xFF000000U

§ CORE_AON_IOTP1_SRC_S

#define CORE_AON_IOTP1_SRC_S 24U

§ CORE_AON_IOOENCFG0_VAL_W

#define CORE_AON_IOOENCFG0_VAL_W 32U

§ CORE_AON_IOOENCFG0_VAL_M

#define CORE_AON_IOOENCFG0_VAL_M 0xFFFFFFFFU

§ CORE_AON_IOOENCFG0_VAL_S

#define CORE_AON_IOOENCFG0_VAL_S 0U

§ CORE_AON_IOOENCFG1_VAL_W

#define CORE_AON_IOOENCFG1_VAL_W 13U

§ CORE_AON_IOOENCFG1_VAL_M

#define CORE_AON_IOOENCFG1_VAL_M 0x00001FFFU

§ CORE_AON_IOOENCFG1_VAL_S

#define CORE_AON_IOOENCFG1_VAL_S 0U

Macros