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Macros
#define	ADC_O_FSCTL0 0x00000000U

#define	ADC_O_FSCTL1 0x00000004U

#define	ADC_O_FSCTL2 0x00000008U

#define	ADC_O_FSCTL3 0x0000000CU

#define	ADC_O_REFBUF 0x00000010U

#define	ADC_O_ATB 0x00000014U

#define	ADC_O_INTEVT0IDX 0x00001020U

#define	ADC_O_INTEVT0BM 0x00001028U

#define	ADC_O_INTEVT0RIS 0x00001030U

#define	ADC_O_INTEVT0MIS 0x00001038U

#define	ADC_O_INTEVT0SET 0x00001040U

#define	ADC_O_INTEVT0CLR 0x00001048U

#define	ADC_O_INTEVT1IDX 0x00001050U

#define	ADC_O_INTEVT1BM 0x00001058U

#define	ADC_O_INTEVT1RIS 0x00001060U

#define	ADC_O_INTEVT1MIS 0x00001068U

#define	ADC_O_INTEVT1SET 0x00001070U

#define	ADC_O_INTEVT1CLR 0x00001078U

#define	ADC_O_INTEVT2IDX 0x00001080U

#define	ADC_O_INTEVT2BM 0x00001088U

#define	ADC_O_INTEVT2RIS 0x00001090U

#define	ADC_O_INTEVT2MIS 0x00001098U

#define	ADC_O_INTEVT2SET 0x000010A0U

#define	ADC_O_INTEVT2CLR 0x000010A8U

#define	ADC_O_EVTMOD 0x000010E0U

#define	ADC_O_DESC 0x000010FCU

#define	ADC_O_CTL0 0x00001100U

#define	ADC_O_CTL1 0x00001104U

#define	ADC_O_CTL2 0x00001108U

#define	ADC_O_CTL3 0x0000110CU

#define	ADC_O_CLKFREQ 0x00001110U

#define	ADC_O_SCOMP0 0x00001114U

#define	ADC_O_SCOMP1 0x00001118U

#define	ADC_O_REFCFG 0x0000111CU

#define	ADC_O_WCLOW 0x00001148U

#define	ADC_O_WCHI 0x00001150U

#define	ADC_O_FIFODATA 0x00001160U

#define	ADC_O_ASCRES 0x00001170U

#define	ADC_O_MEMCTL_0 0x00001180U

#define	ADC_O_MEMCTL_1 0x00001184U

#define	ADC_O_MEMCTL_2 0x00001188U

#define	ADC_O_MEMCTL_3 0x0000118CU

#define	ADC_O_MEMCTL_4 0x00001190U

#define	ADC_O_MEMCTL_5 0x00001194U

#define	ADC_O_MEMRES_0 0x00001280U

#define	ADC_O_MEMRES_1 0x00001284U

#define	ADC_O_MEMRES_2 0x00001288U

#define	ADC_O_MEMRES_3 0x0000128CU

#define	ADC_O_MEMRES_4 0x00001290U

#define	ADC_O_MEMRES_5 0x00001294U

#define	ADC_O_MEMRES_6 0x00001298U

#define	ADC_O_MEMRES_7 0x0000129CU

#define	ADC_O_MEMRES_8 0x000012A0U

#define	ADC_O_MEMRES_9 0x000012A4U

#define	ADC_O_MEMRES_10 0x000012A8U

#define	ADC_O_MEMRES_11 0x000012ACU

#define	ADC_O_MEMRES_12 0x000012B0U

#define	ADC_O_MEMRES_13 0x000012B4U

#define	ADC_O_MEMRES_14 0x000012B8U

#define	ADC_O_MEMRES_15 0x000012BCU

#define	ADC_O_STA 0x00001340U

#define	ADC_O_TEST0 0x00001E00U

#define	ADC_O_TEST1 0x00001E04U

#define	ADC_O_TEST2 0x00001E08U

#define	ADC_O_TEST3 0x00001E0CU

#define	ADC_O_TEST4 0x00001E10U

#define	ADC_O_TEST5 0x00001E14U

#define	ADC_O_TEST6 0x00001E18U

#define	ADC_O_DBG1 0x00001E20U

#define	ADC_O_DBG2 0x00001E24U

#define	ADC_O_DBG3 0x00001E28U

#define	ADC_O_DBG4 0x00001E2CU

#define	ADC_O_CONVCTL 0x00001F14U

#define	ADC_O_CTRL 0x00001F18U

#define	ADC_O_MODCTL 0x00001F1CU

#define	ADC_O_INTCHCTL 0x00001F20U

#define	ADC_O_STLTIM 0x00001F24U

#define	ADC_O_CLKCFG 0x00002000U

#define	ADC_FSCTL0_TRIM0_W 32U

#define	ADC_FSCTL0_TRIM0_M 0xFFFFFFFFU

#define	ADC_FSCTL0_TRIM0_S 0U

#define	ADC_FSCTL1_TRIM1_W 32U

#define	ADC_FSCTL1_TRIM1_M 0xFFFFFFFFU

#define	ADC_FSCTL1_TRIM1_S 0U

#define	ADC_FSCTL2_TRIM2_W 32U

#define	ADC_FSCTL2_TRIM2_M 0xFFFFFFFFU

#define	ADC_FSCTL2_TRIM2_S 0U

#define	ADC_FSCTL3_TRIM3_W 16U

#define	ADC_FSCTL3_TRIM3_M 0x0000FFFFU

#define	ADC_FSCTL3_TRIM3_S 0U

#define	ADC_REFBUF_CFG_W 32U

#define	ADC_REFBUF_CFG_M 0xFFFFFFFFU

#define	ADC_REFBUF_CFG_S 0U

#define	ADC_ATB_CTRL_W 8U

#define	ADC_ATB_CTRL_M 0x000000FFU

#define	ADC_ATB_CTRL_S 0U

#define	ADC_INTEVT0IDX_STAT_W 10U

#define	ADC_INTEVT0IDX_STAT_M 0x000003FFU

#define	ADC_INTEVT0IDX_STAT_S 0U

#define	ADC_INTEVT0IDX_STAT_NO_INTR 0x00000000U

#define	ADC_INTEVT0IDX_STAT_OVIFG 0x00000001U

#define	ADC_INTEVT0IDX_STAT_UVIFG 0x00000007U

#define	ADC_INTEVT0IDX_STAT_TOVIFG 0x00000002U

#define	ADC_INTEVT0IDX_STAT_HIGHIFG 0x00000003U

#define	ADC_INTEVT0IDX_STAT_LOWIFG 0x00000004U

#define	ADC_INTEVT0IDX_STAT_INIFG 0x00000005U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG0 0x00000009U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG1 0x0000000AU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG2 0x0000000BU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG3 0x0000000CU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG4 0x0000000DU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG5 0x0000000EU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG6 0x0000000FU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG7 0x00000010U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG8 0x00000011U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG9 0x00000012U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG10 0x00000013U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG11 0x00000014U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG12 0x00000015U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG13 0x00000016U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG14 0x00000017U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG15 0x00000018U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG16 0x00000019U

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG17 0x0000001AU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG18 0x0000001BU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG19 0x0000001CU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG20 0x0000001DU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG21 0x0000001EU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG22 0x0000001FU

#define	ADC_INTEVT0IDX_STAT_MEMRESIFG23 0x00000020U

#define	ADC_INTEVT0IDX_STAT_DMADONE 0x00000006U

#define	ADC_INTEVT0BM_OVIFG 0x00000001U

#define	ADC_INTEVT0BM_OVIFG_M 0x00000001U

#define	ADC_INTEVT0BM_OVIFG_S 0U

#define	ADC_INTEVT0BM_OVIFG_CLR 0x00000000U

#define	ADC_INTEVT0BM_OVIFG_SET 0x00000001U

#define	ADC_INTEVT0BM_TOVIFG 0x00000002U

#define	ADC_INTEVT0BM_TOVIFG_M 0x00000002U

#define	ADC_INTEVT0BM_TOVIFG_S 1U

#define	ADC_INTEVT0BM_TOVIFG_CLR 0x00000000U

#define	ADC_INTEVT0BM_TOVIFG_SET 0x00000002U

#define	ADC_INTEVT0BM_HIFG 0x00000004U

#define	ADC_INTEVT0BM_HIFG_M 0x00000004U

#define	ADC_INTEVT0BM_HIFG_S 2U

#define	ADC_INTEVT0BM_HIFG_CLR 0x00000000U

#define	ADC_INTEVT0BM_HIFG_SET 0x00000004U

#define	ADC_INTEVT0BM_LOFG 0x00000008U

#define	ADC_INTEVT0BM_LOFG_M 0x00000008U

#define	ADC_INTEVT0BM_LOFG_S 3U

#define	ADC_INTEVT0BM_LOFG_CLR 0x00000000U

#define	ADC_INTEVT0BM_LOFG_SET 0x00000008U

#define	ADC_INTEVT0BM_INIFG 0x00000010U

#define	ADC_INTEVT0BM_INIFG_M 0x00000010U

#define	ADC_INTEVT0BM_INIFG_S 4U

#define	ADC_INTEVT0BM_INIFG_CLR 0x00000000U

#define	ADC_INTEVT0BM_INIFG_SET 0x00000010U

#define	ADC_INTEVT0BM_DMADONE 0x00000020U

#define	ADC_INTEVT0BM_DMADONE_M 0x00000020U

#define	ADC_INTEVT0BM_DMADONE_S 5U

#define	ADC_INTEVT0BM_DMADONE_CLR 0x00000000U

#define	ADC_INTEVT0BM_DMADONE_SET 0x00000020U

#define	ADC_INTEVT0BM_UVIFG 0x00000040U

#define	ADC_INTEVT0BM_UVIFG_M 0x00000040U

#define	ADC_INTEVT0BM_UVIFG_S 6U

#define	ADC_INTEVT0BM_UVIFG_CLR 0x00000000U

#define	ADC_INTEVT0BM_UVIFG_SET 0x00000040U

#define	ADC_INTEVT0BM_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT0BM_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT0BM_MEMRESIFG0_S 8U

#define	ADC_INTEVT0BM_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT0BM_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT0BM_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT0BM_MEMRESIFG1_S 9U

#define	ADC_INTEVT0BM_MEMRESIFG1_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT0BM_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT0BM_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT0BM_MEMRESIFG2_S 10U

#define	ADC_INTEVT0BM_MEMRESIFG2_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT0BM_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT0BM_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT0BM_MEMRESIFG3_S 11U

#define	ADC_INTEVT0BM_MEMRESIFG3_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT0BM_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT0BM_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT0BM_MEMRESIFG4_S 12U

#define	ADC_INTEVT0BM_MEMRESIFG4_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT0BM_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT0BM_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT0BM_MEMRESIFG5_S 13U

#define	ADC_INTEVT0BM_MEMRESIFG5_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT0BM_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT0BM_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT0BM_MEMRESIFG6_S 14U

#define	ADC_INTEVT0BM_MEMRESIFG6_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT0BM_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT0BM_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT0BM_MEMRESIFG7_S 15U

#define	ADC_INTEVT0BM_MEMRESIFG7_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT0BM_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT0BM_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT0BM_MEMRESIFG8_S 16U

#define	ADC_INTEVT0BM_MEMRESIFG8_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT0BM_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT0BM_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT0BM_MEMRESIFG9_S 17U

#define	ADC_INTEVT0BM_MEMRESIFG9_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT0BM_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT0BM_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT0BM_MEMRESIFG10_S 18U

#define	ADC_INTEVT0BM_MEMRESIFG10_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT0BM_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT0BM_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT0BM_MEMRESIFG11_S 19U

#define	ADC_INTEVT0BM_MEMRESIFG11_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT0BM_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT0BM_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT0BM_MEMRESIFG12_S 20U

#define	ADC_INTEVT0BM_MEMRESIFG12_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT0BM_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT0BM_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT0BM_MEMRESIFG13_S 21U

#define	ADC_INTEVT0BM_MEMRESIFG13_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT0BM_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT0BM_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT0BM_MEMRESIFG14_S 22U

#define	ADC_INTEVT0BM_MEMRESIFG14_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT0BM_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT0BM_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT0BM_MEMRESIFG15_S 23U

#define	ADC_INTEVT0BM_MEMRESIFG15_CLR 0x00000000U

#define	ADC_INTEVT0BM_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT0RIS_OVIFG 0x00000001U

#define	ADC_INTEVT0RIS_OVIFG_M 0x00000001U

#define	ADC_INTEVT0RIS_OVIFG_S 0U

#define	ADC_INTEVT0RIS_OVIFG_CLR 0x00000000U

#define	ADC_INTEVT0RIS_OVIFG_SET 0x00000001U

#define	ADC_INTEVT0RIS_TOVIFG 0x00000002U

#define	ADC_INTEVT0RIS_TOVIFG_M 0x00000002U

#define	ADC_INTEVT0RIS_TOVIFG_S 1U

#define	ADC_INTEVT0RIS_TOVIFG_CLR 0x00000000U

#define	ADC_INTEVT0RIS_TOVIFG_SET 0x00000002U

#define	ADC_INTEVT0RIS_HIFG 0x00000004U

#define	ADC_INTEVT0RIS_HIFG_M 0x00000004U

#define	ADC_INTEVT0RIS_HIFG_S 2U

#define	ADC_INTEVT0RIS_HIFG_CLR 0x00000000U

#define	ADC_INTEVT0RIS_HIFG_SET 0x00000004U

#define	ADC_INTEVT0RIS_LOFG 0x00000008U

#define	ADC_INTEVT0RIS_LOFG_M 0x00000008U

#define	ADC_INTEVT0RIS_LOFG_S 3U

#define	ADC_INTEVT0RIS_LOFG_CLR 0x00000000U

#define	ADC_INTEVT0RIS_LOFG_SET 0x00000008U

#define	ADC_INTEVT0RIS_INIFG 0x00000010U

#define	ADC_INTEVT0RIS_INIFG_M 0x00000010U

#define	ADC_INTEVT0RIS_INIFG_S 4U

#define	ADC_INTEVT0RIS_INIFG_CLR 0x00000000U

#define	ADC_INTEVT0RIS_INIFG_SET 0x00000010U

#define	ADC_INTEVT0RIS_DMADONE 0x00000020U

#define	ADC_INTEVT0RIS_DMADONE_M 0x00000020U

#define	ADC_INTEVT0RIS_DMADONE_S 5U

#define	ADC_INTEVT0RIS_DMADONE_CLR 0x00000000U

#define	ADC_INTEVT0RIS_DMADONE_SET 0x00000020U

#define	ADC_INTEVT0RIS_UVIFG 0x00000040U

#define	ADC_INTEVT0RIS_UVIFG_M 0x00000040U

#define	ADC_INTEVT0RIS_UVIFG_S 6U

#define	ADC_INTEVT0RIS_UVIFG_CLR 0x00000000U

#define	ADC_INTEVT0RIS_UVIFG_SET 0x00000040U

#define	ADC_INTEVT0RIS_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT0RIS_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT0RIS_MEMRESIFG0_S 8U

#define	ADC_INTEVT0RIS_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT0RIS_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT0RIS_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT0RIS_MEMRESIFG1_S 9U

#define	ADC_INTEVT0RIS_MEMRESIFG1_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT0RIS_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT0RIS_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT0RIS_MEMRESIFG2_S 10U

#define	ADC_INTEVT0RIS_MEMRESIFG2_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT0RIS_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT0RIS_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT0RIS_MEMRESIFG3_S 11U

#define	ADC_INTEVT0RIS_MEMRESIFG3_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT0RIS_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT0RIS_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT0RIS_MEMRESIFG4_S 12U

#define	ADC_INTEVT0RIS_MEMRESIFG4_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT0RIS_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT0RIS_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT0RIS_MEMRESIFG5_S 13U

#define	ADC_INTEVT0RIS_MEMRESIFG5_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT0RIS_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT0RIS_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT0RIS_MEMRESIFG6_S 14U

#define	ADC_INTEVT0RIS_MEMRESIFG6_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT0RIS_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT0RIS_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT0RIS_MEMRESIFG7_S 15U

#define	ADC_INTEVT0RIS_MEMRESIFG7_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT0RIS_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT0RIS_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT0RIS_MEMRESIFG8_S 16U

#define	ADC_INTEVT0RIS_MEMRESIFG8_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT0RIS_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT0RIS_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT0RIS_MEMRESIFG9_S 17U

#define	ADC_INTEVT0RIS_MEMRESIFG9_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT0RIS_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT0RIS_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT0RIS_MEMRESIFG10_S 18U

#define	ADC_INTEVT0RIS_MEMRESIFG10_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT0RIS_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT0RIS_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT0RIS_MEMRESIFG11_S 19U

#define	ADC_INTEVT0RIS_MEMRESIFG11_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT0RIS_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT0RIS_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT0RIS_MEMRESIFG12_S 20U

#define	ADC_INTEVT0RIS_MEMRESIFG12_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT0RIS_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT0RIS_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT0RIS_MEMRESIFG13_S 21U

#define	ADC_INTEVT0RIS_MEMRESIFG13_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT0RIS_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT0RIS_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT0RIS_MEMRESIFG14_S 22U

#define	ADC_INTEVT0RIS_MEMRESIFG14_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT0RIS_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT0RIS_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT0RIS_MEMRESIFG15_S 23U

#define	ADC_INTEVT0RIS_MEMRESIFG15_CLR 0x00000000U

#define	ADC_INTEVT0RIS_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT0MIS_OVIFG 0x00000001U

#define	ADC_INTEVT0MIS_OVIFG_M 0x00000001U

#define	ADC_INTEVT0MIS_OVIFG_S 0U

#define	ADC_INTEVT0MIS_OVIFG_CLR 0x00000000U

#define	ADC_INTEVT0MIS_OVIFG_SET 0x00000001U

#define	ADC_INTEVT0MIS_TOVIFG 0x00000002U

#define	ADC_INTEVT0MIS_TOVIFG_M 0x00000002U

#define	ADC_INTEVT0MIS_TOVIFG_S 1U

#define	ADC_INTEVT0MIS_TOVIFG_CLR 0x00000000U

#define	ADC_INTEVT0MIS_TOVIFG_SET 0x00000002U

#define	ADC_INTEVT0MIS_HIFG 0x00000004U

#define	ADC_INTEVT0MIS_HIFG_M 0x00000004U

#define	ADC_INTEVT0MIS_HIFG_S 2U

#define	ADC_INTEVT0MIS_HIFG_CLR 0x00000000U

#define	ADC_INTEVT0MIS_HIFG_SET 0x00000004U

#define	ADC_INTEVT0MIS_LOFG 0x00000008U

#define	ADC_INTEVT0MIS_LOFG_M 0x00000008U

#define	ADC_INTEVT0MIS_LOFG_S 3U

#define	ADC_INTEVT0MIS_LOFG_CLR 0x00000000U

#define	ADC_INTEVT0MIS_LOFG_SET 0x00000008U

#define	ADC_INTEVT0MIS_INIFG 0x00000010U

#define	ADC_INTEVT0MIS_INIFG_M 0x00000010U

#define	ADC_INTEVT0MIS_INIFG_S 4U

#define	ADC_INTEVT0MIS_INIFG_CLR 0x00000000U

#define	ADC_INTEVT0MIS_INIFG_SET 0x00000010U

#define	ADC_INTEVT0MIS_DMADONE 0x00000020U

#define	ADC_INTEVT0MIS_DMADONE_M 0x00000020U

#define	ADC_INTEVT0MIS_DMADONE_S 5U

#define	ADC_INTEVT0MIS_DMADONE_CLR 0x00000000U

#define	ADC_INTEVT0MIS_DMADONE_SET 0x00000020U

#define	ADC_INTEVT0MIS_UVIFG 0x00000040U

#define	ADC_INTEVT0MIS_UVIFG_M 0x00000040U

#define	ADC_INTEVT0MIS_UVIFG_S 6U

#define	ADC_INTEVT0MIS_UVIFG_CLR 0x00000000U

#define	ADC_INTEVT0MIS_UVIFG_SET 0x00000040U

#define	ADC_INTEVT0MIS_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT0MIS_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT0MIS_MEMRESIFG0_S 8U

#define	ADC_INTEVT0MIS_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT0MIS_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT0MIS_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT0MIS_MEMRESIFG1_S 9U

#define	ADC_INTEVT0MIS_MEMRESIFG1_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT0MIS_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT0MIS_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT0MIS_MEMRESIFG2_S 10U

#define	ADC_INTEVT0MIS_MEMRESIFG2_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT0MIS_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT0MIS_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT0MIS_MEMRESIFG3_S 11U

#define	ADC_INTEVT0MIS_MEMRESIFG3_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT0MIS_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT0MIS_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT0MIS_MEMRESIFG4_S 12U

#define	ADC_INTEVT0MIS_MEMRESIFG4_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT0MIS_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT0MIS_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT0MIS_MEMRESIFG5_S 13U

#define	ADC_INTEVT0MIS_MEMRESIFG5_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT0MIS_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT0MIS_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT0MIS_MEMRESIFG6_S 14U

#define	ADC_INTEVT0MIS_MEMRESIFG6_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT0MIS_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT0MIS_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT0MIS_MEMRESIFG7_S 15U

#define	ADC_INTEVT0MIS_MEMRESIFG7_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT0MIS_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT0MIS_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT0MIS_MEMRESIFG8_S 16U

#define	ADC_INTEVT0MIS_MEMRESIFG8_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT0MIS_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT0MIS_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT0MIS_MEMRESIFG9_S 17U

#define	ADC_INTEVT0MIS_MEMRESIFG9_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT0MIS_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT0MIS_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT0MIS_MEMRESIFG10_S 18U

#define	ADC_INTEVT0MIS_MEMRESIFG10_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT0MIS_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT0MIS_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT0MIS_MEMRESIFG11_S 19U

#define	ADC_INTEVT0MIS_MEMRESIFG11_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT0MIS_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT0MIS_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT0MIS_MEMRESIFG12_S 20U

#define	ADC_INTEVT0MIS_MEMRESIFG12_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT0MIS_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT0MIS_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT0MIS_MEMRESIFG13_S 21U

#define	ADC_INTEVT0MIS_MEMRESIFG13_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT0MIS_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT0MIS_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT0MIS_MEMRESIFG14_S 22U

#define	ADC_INTEVT0MIS_MEMRESIFG14_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT0MIS_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT0MIS_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT0MIS_MEMRESIFG15_S 23U

#define	ADC_INTEVT0MIS_MEMRESIFG15_CLR 0x00000000U

#define	ADC_INTEVT0MIS_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT0SET_OVIFG 0x00000001U

#define	ADC_INTEVT0SET_OVIFG_M 0x00000001U

#define	ADC_INTEVT0SET_OVIFG_S 0U

#define	ADC_INTEVT0SET_OVIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_OVIFG_SET 0x00000001U

#define	ADC_INTEVT0SET_TOVIFG 0x00000002U

#define	ADC_INTEVT0SET_TOVIFG_M 0x00000002U

#define	ADC_INTEVT0SET_TOVIFG_S 1U

#define	ADC_INTEVT0SET_TOVIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_TOVIFG_SET 0x00000002U

#define	ADC_INTEVT0SET_HIFG 0x00000004U

#define	ADC_INTEVT0SET_HIFG_M 0x00000004U

#define	ADC_INTEVT0SET_HIFG_S 2U

#define	ADC_INTEVT0SET_HIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_HIFG_SET 0x00000004U

#define	ADC_INTEVT0SET_LOFG 0x00000008U

#define	ADC_INTEVT0SET_LOFG_M 0x00000008U

#define	ADC_INTEVT0SET_LOFG_S 3U

#define	ADC_INTEVT0SET_LOFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_LOFG_SET 0x00000008U

#define	ADC_INTEVT0SET_INIFG 0x00000010U

#define	ADC_INTEVT0SET_INIFG_M 0x00000010U

#define	ADC_INTEVT0SET_INIFG_S 4U

#define	ADC_INTEVT0SET_INIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_INIFG_SET 0x00000010U

#define	ADC_INTEVT0SET_DMADONE 0x00000020U

#define	ADC_INTEVT0SET_DMADONE_M 0x00000020U

#define	ADC_INTEVT0SET_DMADONE_S 5U

#define	ADC_INTEVT0SET_DMADONE_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_DMADONE_SET 0x00000020U

#define	ADC_INTEVT0SET_UVIFG 0x00000040U

#define	ADC_INTEVT0SET_UVIFG_M 0x00000040U

#define	ADC_INTEVT0SET_UVIFG_S 6U

#define	ADC_INTEVT0SET_UVIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_UVIFG_SET 0x00000040U

#define	ADC_INTEVT0SET_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT0SET_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT0SET_MEMRESIFG0_S 8U

#define	ADC_INTEVT0SET_MEMRESIFG0_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT0SET_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT0SET_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT0SET_MEMRESIFG1_S 9U

#define	ADC_INTEVT0SET_MEMRESIFG1_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT0SET_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT0SET_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT0SET_MEMRESIFG2_S 10U

#define	ADC_INTEVT0SET_MEMRESIFG2_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT0SET_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT0SET_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT0SET_MEMRESIFG3_S 11U

#define	ADC_INTEVT0SET_MEMRESIFG3_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT0SET_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT0SET_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT0SET_MEMRESIFG4_S 12U

#define	ADC_INTEVT0SET_MEMRESIFG4_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT0SET_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT0SET_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT0SET_MEMRESIFG5_S 13U

#define	ADC_INTEVT0SET_MEMRESIFG5_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT0SET_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT0SET_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT0SET_MEMRESIFG6_S 14U

#define	ADC_INTEVT0SET_MEMRESIFG6_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT0SET_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT0SET_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT0SET_MEMRESIFG7_S 15U

#define	ADC_INTEVT0SET_MEMRESIFG7_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT0SET_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT0SET_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT0SET_MEMRESIFG8_S 16U

#define	ADC_INTEVT0SET_MEMRESIFG8_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT0SET_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT0SET_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT0SET_MEMRESIFG9_S 17U

#define	ADC_INTEVT0SET_MEMRESIFG9_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT0SET_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT0SET_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT0SET_MEMRESIFG10_S 18U

#define	ADC_INTEVT0SET_MEMRESIFG10_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT0SET_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT0SET_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT0SET_MEMRESIFG11_S 19U

#define	ADC_INTEVT0SET_MEMRESIFG11_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT0SET_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT0SET_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT0SET_MEMRESIFG12_S 20U

#define	ADC_INTEVT0SET_MEMRESIFG12_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT0SET_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT0SET_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT0SET_MEMRESIFG13_S 21U

#define	ADC_INTEVT0SET_MEMRESIFG13_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT0SET_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT0SET_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT0SET_MEMRESIFG14_S 22U

#define	ADC_INTEVT0SET_MEMRESIFG14_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT0SET_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT0SET_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT0SET_MEMRESIFG15_S 23U

#define	ADC_INTEVT0SET_MEMRESIFG15_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0SET_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT0CLR_OVIFG 0x00000001U

#define	ADC_INTEVT0CLR_OVIFG_M 0x00000001U

#define	ADC_INTEVT0CLR_OVIFG_S 0U

#define	ADC_INTEVT0CLR_OVIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_OVIFG_CLR 0x00000001U

#define	ADC_INTEVT0CLR_TOVIFG 0x00000002U

#define	ADC_INTEVT0CLR_TOVIFG_M 0x00000002U

#define	ADC_INTEVT0CLR_TOVIFG_S 1U

#define	ADC_INTEVT0CLR_TOVIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_TOVIFG_CLR 0x00000002U

#define	ADC_INTEVT0CLR_HIFG 0x00000004U

#define	ADC_INTEVT0CLR_HIFG_M 0x00000004U

#define	ADC_INTEVT0CLR_HIFG_S 2U

#define	ADC_INTEVT0CLR_HIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_HIFG_CLR 0x00000004U

#define	ADC_INTEVT0CLR_LOFG 0x00000008U

#define	ADC_INTEVT0CLR_LOFG_M 0x00000008U

#define	ADC_INTEVT0CLR_LOFG_S 3U

#define	ADC_INTEVT0CLR_LOFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_LOFG_CLR 0x00000008U

#define	ADC_INTEVT0CLR_INIFG 0x00000010U

#define	ADC_INTEVT0CLR_INIFG_M 0x00000010U

#define	ADC_INTEVT0CLR_INIFG_S 4U

#define	ADC_INTEVT0CLR_INIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_INIFG_CLR 0x00000010U

#define	ADC_INTEVT0CLR_DMADONE 0x00000020U

#define	ADC_INTEVT0CLR_DMADONE_M 0x00000020U

#define	ADC_INTEVT0CLR_DMADONE_S 5U

#define	ADC_INTEVT0CLR_DMADONE_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_DMADONE_CLR 0x00000020U

#define	ADC_INTEVT0CLR_UVIFG 0x00000040U

#define	ADC_INTEVT0CLR_UVIFG_M 0x00000040U

#define	ADC_INTEVT0CLR_UVIFG_S 6U

#define	ADC_INTEVT0CLR_UVIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_UVIFG_CLR 0x00000040U

#define	ADC_INTEVT0CLR_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT0CLR_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT0CLR_MEMRESIFG0_S 8U

#define	ADC_INTEVT0CLR_MEMRESIFG0_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG0_CLR 0x00000100U

#define	ADC_INTEVT0CLR_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT0CLR_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT0CLR_MEMRESIFG1_S 9U

#define	ADC_INTEVT0CLR_MEMRESIFG1_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG1_CLR 0x00000200U

#define	ADC_INTEVT0CLR_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT0CLR_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT0CLR_MEMRESIFG2_S 10U

#define	ADC_INTEVT0CLR_MEMRESIFG2_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG2_CLR 0x00000400U

#define	ADC_INTEVT0CLR_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT0CLR_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT0CLR_MEMRESIFG3_S 11U

#define	ADC_INTEVT0CLR_MEMRESIFG3_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG3_CLR 0x00000800U

#define	ADC_INTEVT0CLR_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT0CLR_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT0CLR_MEMRESIFG4_S 12U

#define	ADC_INTEVT0CLR_MEMRESIFG4_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG4_CLR 0x00001000U

#define	ADC_INTEVT0CLR_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT0CLR_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT0CLR_MEMRESIFG5_S 13U

#define	ADC_INTEVT0CLR_MEMRESIFG5_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG5_CLR 0x00002000U

#define	ADC_INTEVT0CLR_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT0CLR_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT0CLR_MEMRESIFG6_S 14U

#define	ADC_INTEVT0CLR_MEMRESIFG6_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG6_CLR 0x00004000U

#define	ADC_INTEVT0CLR_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT0CLR_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT0CLR_MEMRESIFG7_S 15U

#define	ADC_INTEVT0CLR_MEMRESIFG7_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG7_CLR 0x00008000U

#define	ADC_INTEVT0CLR_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT0CLR_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT0CLR_MEMRESIFG8_S 16U

#define	ADC_INTEVT0CLR_MEMRESIFG8_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG8_CLR 0x00010000U

#define	ADC_INTEVT0CLR_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT0CLR_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT0CLR_MEMRESIFG9_S 17U

#define	ADC_INTEVT0CLR_MEMRESIFG9_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG9_CLR 0x00020000U

#define	ADC_INTEVT0CLR_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT0CLR_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT0CLR_MEMRESIFG10_S 18U

#define	ADC_INTEVT0CLR_MEMRESIFG10_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG10_CLR 0x00040000U

#define	ADC_INTEVT0CLR_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT0CLR_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT0CLR_MEMRESIFG11_S 19U

#define	ADC_INTEVT0CLR_MEMRESIFG11_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG11_CLR 0x00080000U

#define	ADC_INTEVT0CLR_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT0CLR_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT0CLR_MEMRESIFG12_S 20U

#define	ADC_INTEVT0CLR_MEMRESIFG12_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG12_CLR 0x00100000U

#define	ADC_INTEVT0CLR_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT0CLR_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT0CLR_MEMRESIFG13_S 21U

#define	ADC_INTEVT0CLR_MEMRESIFG13_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG13_CLR 0x00200000U

#define	ADC_INTEVT0CLR_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT0CLR_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT0CLR_MEMRESIFG14_S 22U

#define	ADC_INTEVT0CLR_MEMRESIFG14_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG14_CLR 0x00400000U

#define	ADC_INTEVT0CLR_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT0CLR_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT0CLR_MEMRESIFG15_S 23U

#define	ADC_INTEVT0CLR_MEMRESIFG15_NO_EFFECT 0x00000000U

#define	ADC_INTEVT0CLR_MEMRESIFG15_CLR 0x00800000U

#define	ADC_INTEVT1IDX_STAT_W 10U

#define	ADC_INTEVT1IDX_STAT_M 0x000003FFU

#define	ADC_INTEVT1IDX_STAT_S 0U

#define	ADC_INTEVT1IDX_STAT_NO_INTR 0x00000000U

#define	ADC_INTEVT1IDX_STAT_HIGHIFG 0x00000003U

#define	ADC_INTEVT1IDX_STAT_LOWIFG 0x00000004U

#define	ADC_INTEVT1IDX_STAT_INIFG 0x00000005U

#define	ADC_INTEVT1IDX_STAT_MEMRESIFG0 0x00000009U

#define	ADC_INTEVT1BM_HIFG 0x00000004U

#define	ADC_INTEVT1BM_HIFG_M 0x00000004U

#define	ADC_INTEVT1BM_HIFG_S 2U

#define	ADC_INTEVT1BM_HIFG_CLR 0x00000000U

#define	ADC_INTEVT1BM_HIFG_SET 0x00000004U

#define	ADC_INTEVT1BM_LOFG 0x00000008U

#define	ADC_INTEVT1BM_LOFG_M 0x00000008U

#define	ADC_INTEVT1BM_LOFG_S 3U

#define	ADC_INTEVT1BM_LOFG_CLR 0x00000000U

#define	ADC_INTEVT1BM_LOFG_SET 0x00000008U

#define	ADC_INTEVT1BM_INIFG 0x00000010U

#define	ADC_INTEVT1BM_INIFG_M 0x00000010U

#define	ADC_INTEVT1BM_INIFG_S 4U

#define	ADC_INTEVT1BM_INIFG_CLR 0x00000000U

#define	ADC_INTEVT1BM_INIFG_SET 0x00000010U

#define	ADC_INTEVT1BM_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT1BM_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT1BM_MEMRESIFG0_S 8U

#define	ADC_INTEVT1BM_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT1BM_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT1RIS_HIFG 0x00000004U

#define	ADC_INTEVT1RIS_HIFG_M 0x00000004U

#define	ADC_INTEVT1RIS_HIFG_S 2U

#define	ADC_INTEVT1RIS_HIFG_CLR 0x00000000U

#define	ADC_INTEVT1RIS_HIFG_SET 0x00000004U

#define	ADC_INTEVT1RIS_LOFG 0x00000008U

#define	ADC_INTEVT1RIS_LOFG_M 0x00000008U

#define	ADC_INTEVT1RIS_LOFG_S 3U

#define	ADC_INTEVT1RIS_LOFG_CLR 0x00000000U

#define	ADC_INTEVT1RIS_LOFG_SET 0x00000008U

#define	ADC_INTEVT1RIS_INIFG 0x00000010U

#define	ADC_INTEVT1RIS_INIFG_M 0x00000010U

#define	ADC_INTEVT1RIS_INIFG_S 4U

#define	ADC_INTEVT1RIS_INIFG_CLR 0x00000000U

#define	ADC_INTEVT1RIS_INIFG_SET 0x00000010U

#define	ADC_INTEVT1RIS_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT1RIS_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT1RIS_MEMRESIFG0_S 8U

#define	ADC_INTEVT1RIS_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT1RIS_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT1MIS_HIFG 0x00000004U

#define	ADC_INTEVT1MIS_HIFG_M 0x00000004U

#define	ADC_INTEVT1MIS_HIFG_S 2U

#define	ADC_INTEVT1MIS_HIFG_CLR 0x00000000U

#define	ADC_INTEVT1MIS_HIFG_SET 0x00000004U

#define	ADC_INTEVT1MIS_LOFG 0x00000008U

#define	ADC_INTEVT1MIS_LOFG_M 0x00000008U

#define	ADC_INTEVT1MIS_LOFG_S 3U

#define	ADC_INTEVT1MIS_LOFG_CLR 0x00000000U

#define	ADC_INTEVT1MIS_LOFG_SET 0x00000008U

#define	ADC_INTEVT1MIS_INIFG 0x00000010U

#define	ADC_INTEVT1MIS_INIFG_M 0x00000010U

#define	ADC_INTEVT1MIS_INIFG_S 4U

#define	ADC_INTEVT1MIS_INIFG_CLR 0x00000000U

#define	ADC_INTEVT1MIS_INIFG_SET 0x00000010U

#define	ADC_INTEVT1MIS_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT1MIS_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT1MIS_MEMRESIFG0_S 8U

#define	ADC_INTEVT1MIS_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT1MIS_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT1SET_HIFG 0x00000004U

#define	ADC_INTEVT1SET_HIFG_M 0x00000004U

#define	ADC_INTEVT1SET_HIFG_S 2U

#define	ADC_INTEVT1SET_HIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1SET_HIFG_SET 0x00000004U

#define	ADC_INTEVT1SET_LOFG 0x00000008U

#define	ADC_INTEVT1SET_LOFG_M 0x00000008U

#define	ADC_INTEVT1SET_LOFG_S 3U

#define	ADC_INTEVT1SET_LOFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1SET_LOFG_SET 0x00000008U

#define	ADC_INTEVT1SET_INIFG 0x00000010U

#define	ADC_INTEVT1SET_INIFG_M 0x00000010U

#define	ADC_INTEVT1SET_INIFG_S 4U

#define	ADC_INTEVT1SET_INIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1SET_INIFG_SET 0x00000010U

#define	ADC_INTEVT1SET_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT1SET_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT1SET_MEMRESIFG0_S 8U

#define	ADC_INTEVT1SET_MEMRESIFG0_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1SET_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT1CLR_HIFG 0x00000004U

#define	ADC_INTEVT1CLR_HIFG_M 0x00000004U

#define	ADC_INTEVT1CLR_HIFG_S 2U

#define	ADC_INTEVT1CLR_HIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1CLR_HIFG_CLR 0x00000004U

#define	ADC_INTEVT1CLR_LOFG 0x00000008U

#define	ADC_INTEVT1CLR_LOFG_M 0x00000008U

#define	ADC_INTEVT1CLR_LOFG_S 3U

#define	ADC_INTEVT1CLR_LOFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1CLR_LOFG_CLR 0x00000008U

#define	ADC_INTEVT1CLR_INIFG 0x00000010U

#define	ADC_INTEVT1CLR_INIFG_M 0x00000010U

#define	ADC_INTEVT1CLR_INIFG_S 4U

#define	ADC_INTEVT1CLR_INIFG_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1CLR_INIFG_CLR 0x00000010U

#define	ADC_INTEVT1CLR_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT1CLR_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT1CLR_MEMRESIFG0_S 8U

#define	ADC_INTEVT1CLR_MEMRESIFG0_NO_EFFECT 0x00000000U

#define	ADC_INTEVT1CLR_MEMRESIFG0_CLR 0x00000100U

#define	ADC_INTEVT2IDX_STAT_W 10U

#define	ADC_INTEVT2IDX_STAT_M 0x000003FFU

#define	ADC_INTEVT2IDX_STAT_S 0U

#define	ADC_INTEVT2IDX_STAT_NO_INTR 0x00000000U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG0 0x00000009U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG1 0x0000000AU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG2 0x0000000BU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG3 0x0000000CU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG4 0x0000000DU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG5 0x0000000EU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG6 0x0000000FU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG7 0x00000010U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG8 0x00000011U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG9 0x00000012U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG10 0x00000013U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG11 0x00000014U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG12 0x00000015U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG13 0x00000016U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG14 0x00000017U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG15 0x00000018U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG16 0x00000019U

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG17 0x0000001AU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG18 0x0000001BU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG19 0x0000001CU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG20 0x0000001DU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG21 0x0000001EU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG22 0x0000001FU

#define	ADC_INTEVT2IDX_STAT_MEMRESIFG23 0x00000020U

#define	ADC_INTEVT2BM_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT2BM_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT2BM_MEMRESIFG0_S 8U

#define	ADC_INTEVT2BM_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT2BM_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT2BM_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT2BM_MEMRESIFG1_S 9U

#define	ADC_INTEVT2BM_MEMRESIFG1_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT2BM_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT2BM_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT2BM_MEMRESIFG2_S 10U

#define	ADC_INTEVT2BM_MEMRESIFG2_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT2BM_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT2BM_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT2BM_MEMRESIFG3_S 11U

#define	ADC_INTEVT2BM_MEMRESIFG3_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT2BM_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT2BM_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT2BM_MEMRESIFG4_S 12U

#define	ADC_INTEVT2BM_MEMRESIFG4_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT2BM_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT2BM_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT2BM_MEMRESIFG5_S 13U

#define	ADC_INTEVT2BM_MEMRESIFG5_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT2BM_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT2BM_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT2BM_MEMRESIFG6_S 14U

#define	ADC_INTEVT2BM_MEMRESIFG6_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT2BM_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT2BM_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT2BM_MEMRESIFG7_S 15U

#define	ADC_INTEVT2BM_MEMRESIFG7_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT2BM_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT2BM_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT2BM_MEMRESIFG8_S 16U

#define	ADC_INTEVT2BM_MEMRESIFG8_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT2BM_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT2BM_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT2BM_MEMRESIFG9_S 17U

#define	ADC_INTEVT2BM_MEMRESIFG9_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT2BM_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT2BM_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT2BM_MEMRESIFG10_S 18U

#define	ADC_INTEVT2BM_MEMRESIFG10_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT2BM_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT2BM_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT2BM_MEMRESIFG11_S 19U

#define	ADC_INTEVT2BM_MEMRESIFG11_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT2BM_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT2BM_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT2BM_MEMRESIFG12_S 20U

#define	ADC_INTEVT2BM_MEMRESIFG12_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT2BM_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT2BM_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT2BM_MEMRESIFG13_S 21U

#define	ADC_INTEVT2BM_MEMRESIFG13_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT2BM_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT2BM_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT2BM_MEMRESIFG14_S 22U

#define	ADC_INTEVT2BM_MEMRESIFG14_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT2BM_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT2BM_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT2BM_MEMRESIFG15_S 23U

#define	ADC_INTEVT2BM_MEMRESIFG15_CLR 0x00000000U

#define	ADC_INTEVT2BM_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT2RIS_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT2RIS_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT2RIS_MEMRESIFG0_S 8U

#define	ADC_INTEVT2RIS_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT2RIS_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT2RIS_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT2RIS_MEMRESIFG1_S 9U

#define	ADC_INTEVT2RIS_MEMRESIFG1_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT2RIS_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT2RIS_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT2RIS_MEMRESIFG2_S 10U

#define	ADC_INTEVT2RIS_MEMRESIFG2_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT2RIS_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT2RIS_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT2RIS_MEMRESIFG3_S 11U

#define	ADC_INTEVT2RIS_MEMRESIFG3_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT2RIS_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT2RIS_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT2RIS_MEMRESIFG4_S 12U

#define	ADC_INTEVT2RIS_MEMRESIFG4_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT2RIS_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT2RIS_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT2RIS_MEMRESIFG5_S 13U

#define	ADC_INTEVT2RIS_MEMRESIFG5_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT2RIS_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT2RIS_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT2RIS_MEMRESIFG6_S 14U

#define	ADC_INTEVT2RIS_MEMRESIFG6_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT2RIS_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT2RIS_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT2RIS_MEMRESIFG7_S 15U

#define	ADC_INTEVT2RIS_MEMRESIFG7_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT2RIS_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT2RIS_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT2RIS_MEMRESIFG8_S 16U

#define	ADC_INTEVT2RIS_MEMRESIFG8_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT2RIS_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT2RIS_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT2RIS_MEMRESIFG9_S 17U

#define	ADC_INTEVT2RIS_MEMRESIFG9_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT2RIS_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT2RIS_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT2RIS_MEMRESIFG10_S 18U

#define	ADC_INTEVT2RIS_MEMRESIFG10_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT2RIS_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT2RIS_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT2RIS_MEMRESIFG11_S 19U

#define	ADC_INTEVT2RIS_MEMRESIFG11_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT2RIS_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT2RIS_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT2RIS_MEMRESIFG12_S 20U

#define	ADC_INTEVT2RIS_MEMRESIFG12_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT2RIS_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT2RIS_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT2RIS_MEMRESIFG13_S 21U

#define	ADC_INTEVT2RIS_MEMRESIFG13_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT2RIS_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT2RIS_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT2RIS_MEMRESIFG14_S 22U

#define	ADC_INTEVT2RIS_MEMRESIFG14_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT2RIS_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT2RIS_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT2RIS_MEMRESIFG15_S 23U

#define	ADC_INTEVT2RIS_MEMRESIFG15_CLR 0x00000000U

#define	ADC_INTEVT2RIS_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT2MIS_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT2MIS_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT2MIS_MEMRESIFG0_S 8U

#define	ADC_INTEVT2MIS_MEMRESIFG0_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT2MIS_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT2MIS_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT2MIS_MEMRESIFG1_S 9U

#define	ADC_INTEVT2MIS_MEMRESIFG1_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT2MIS_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT2MIS_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT2MIS_MEMRESIFG2_S 10U

#define	ADC_INTEVT2MIS_MEMRESIFG2_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT2MIS_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT2MIS_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT2MIS_MEMRESIFG3_S 11U

#define	ADC_INTEVT2MIS_MEMRESIFG3_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT2MIS_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT2MIS_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT2MIS_MEMRESIFG4_S 12U

#define	ADC_INTEVT2MIS_MEMRESIFG4_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT2MIS_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT2MIS_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT2MIS_MEMRESIFG5_S 13U

#define	ADC_INTEVT2MIS_MEMRESIFG5_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT2MIS_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT2MIS_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT2MIS_MEMRESIFG6_S 14U

#define	ADC_INTEVT2MIS_MEMRESIFG6_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT2MIS_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT2MIS_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT2MIS_MEMRESIFG7_S 15U

#define	ADC_INTEVT2MIS_MEMRESIFG7_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT2MIS_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT2MIS_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT2MIS_MEMRESIFG8_S 16U

#define	ADC_INTEVT2MIS_MEMRESIFG8_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT2MIS_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT2MIS_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT2MIS_MEMRESIFG9_S 17U

#define	ADC_INTEVT2MIS_MEMRESIFG9_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT2MIS_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT2MIS_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT2MIS_MEMRESIFG10_S 18U

#define	ADC_INTEVT2MIS_MEMRESIFG10_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT2MIS_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT2MIS_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT2MIS_MEMRESIFG11_S 19U

#define	ADC_INTEVT2MIS_MEMRESIFG11_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT2MIS_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT2MIS_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT2MIS_MEMRESIFG12_S 20U

#define	ADC_INTEVT2MIS_MEMRESIFG12_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT2MIS_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT2MIS_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT2MIS_MEMRESIFG13_S 21U

#define	ADC_INTEVT2MIS_MEMRESIFG13_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT2MIS_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT2MIS_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT2MIS_MEMRESIFG14_S 22U

#define	ADC_INTEVT2MIS_MEMRESIFG14_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT2MIS_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT2MIS_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT2MIS_MEMRESIFG15_S 23U

#define	ADC_INTEVT2MIS_MEMRESIFG15_CLR 0x00000000U

#define	ADC_INTEVT2MIS_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT2SET_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT2SET_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT2SET_MEMRESIFG0_S 8U

#define	ADC_INTEVT2SET_MEMRESIFG0_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG0_SET 0x00000100U

#define	ADC_INTEVT2SET_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT2SET_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT2SET_MEMRESIFG1_S 9U

#define	ADC_INTEVT2SET_MEMRESIFG1_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG1_SET 0x00000200U

#define	ADC_INTEVT2SET_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT2SET_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT2SET_MEMRESIFG2_S 10U

#define	ADC_INTEVT2SET_MEMRESIFG2_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG2_SET 0x00000400U

#define	ADC_INTEVT2SET_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT2SET_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT2SET_MEMRESIFG3_S 11U

#define	ADC_INTEVT2SET_MEMRESIFG3_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG3_SET 0x00000800U

#define	ADC_INTEVT2SET_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT2SET_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT2SET_MEMRESIFG4_S 12U

#define	ADC_INTEVT2SET_MEMRESIFG4_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG4_SET 0x00001000U

#define	ADC_INTEVT2SET_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT2SET_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT2SET_MEMRESIFG5_S 13U

#define	ADC_INTEVT2SET_MEMRESIFG5_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG5_SET 0x00002000U

#define	ADC_INTEVT2SET_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT2SET_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT2SET_MEMRESIFG6_S 14U

#define	ADC_INTEVT2SET_MEMRESIFG6_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG6_SET 0x00004000U

#define	ADC_INTEVT2SET_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT2SET_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT2SET_MEMRESIFG7_S 15U

#define	ADC_INTEVT2SET_MEMRESIFG7_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG7_SET 0x00008000U

#define	ADC_INTEVT2SET_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT2SET_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT2SET_MEMRESIFG8_S 16U

#define	ADC_INTEVT2SET_MEMRESIFG8_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG8_SET 0x00010000U

#define	ADC_INTEVT2SET_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT2SET_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT2SET_MEMRESIFG9_S 17U

#define	ADC_INTEVT2SET_MEMRESIFG9_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG9_SET 0x00020000U

#define	ADC_INTEVT2SET_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT2SET_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT2SET_MEMRESIFG10_S 18U

#define	ADC_INTEVT2SET_MEMRESIFG10_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG10_SET 0x00040000U

#define	ADC_INTEVT2SET_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT2SET_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT2SET_MEMRESIFG11_S 19U

#define	ADC_INTEVT2SET_MEMRESIFG11_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG11_SET 0x00080000U

#define	ADC_INTEVT2SET_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT2SET_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT2SET_MEMRESIFG12_S 20U

#define	ADC_INTEVT2SET_MEMRESIFG12_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG12_SET 0x00100000U

#define	ADC_INTEVT2SET_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT2SET_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT2SET_MEMRESIFG13_S 21U

#define	ADC_INTEVT2SET_MEMRESIFG13_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG13_SET 0x00200000U

#define	ADC_INTEVT2SET_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT2SET_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT2SET_MEMRESIFG14_S 22U

#define	ADC_INTEVT2SET_MEMRESIFG14_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG14_SET 0x00400000U

#define	ADC_INTEVT2SET_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT2SET_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT2SET_MEMRESIFG15_S 23U

#define	ADC_INTEVT2SET_MEMRESIFG15_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2SET_MEMRESIFG15_SET 0x00800000U

#define	ADC_INTEVT2CLR_MEMRESIFG0 0x00000100U

#define	ADC_INTEVT2CLR_MEMRESIFG0_M 0x00000100U

#define	ADC_INTEVT2CLR_MEMRESIFG0_S 8U

#define	ADC_INTEVT2CLR_MEMRESIFG0_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG0_CLR 0x00000100U

#define	ADC_INTEVT2CLR_MEMRESIFG1 0x00000200U

#define	ADC_INTEVT2CLR_MEMRESIFG1_M 0x00000200U

#define	ADC_INTEVT2CLR_MEMRESIFG1_S 9U

#define	ADC_INTEVT2CLR_MEMRESIFG1_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG1_CLR 0x00000200U

#define	ADC_INTEVT2CLR_MEMRESIFG2 0x00000400U

#define	ADC_INTEVT2CLR_MEMRESIFG2_M 0x00000400U

#define	ADC_INTEVT2CLR_MEMRESIFG2_S 10U

#define	ADC_INTEVT2CLR_MEMRESIFG2_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG2_CLR 0x00000400U

#define	ADC_INTEVT2CLR_MEMRESIFG3 0x00000800U

#define	ADC_INTEVT2CLR_MEMRESIFG3_M 0x00000800U

#define	ADC_INTEVT2CLR_MEMRESIFG3_S 11U

#define	ADC_INTEVT2CLR_MEMRESIFG3_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG3_CLR 0x00000800U

#define	ADC_INTEVT2CLR_MEMRESIFG4 0x00001000U

#define	ADC_INTEVT2CLR_MEMRESIFG4_M 0x00001000U

#define	ADC_INTEVT2CLR_MEMRESIFG4_S 12U

#define	ADC_INTEVT2CLR_MEMRESIFG4_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG4_CLR 0x00001000U

#define	ADC_INTEVT2CLR_MEMRESIFG5 0x00002000U

#define	ADC_INTEVT2CLR_MEMRESIFG5_M 0x00002000U

#define	ADC_INTEVT2CLR_MEMRESIFG5_S 13U

#define	ADC_INTEVT2CLR_MEMRESIFG5_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG5_CLR 0x00002000U

#define	ADC_INTEVT2CLR_MEMRESIFG6 0x00004000U

#define	ADC_INTEVT2CLR_MEMRESIFG6_M 0x00004000U

#define	ADC_INTEVT2CLR_MEMRESIFG6_S 14U

#define	ADC_INTEVT2CLR_MEMRESIFG6_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG6_CLR 0x00004000U

#define	ADC_INTEVT2CLR_MEMRESIFG7 0x00008000U

#define	ADC_INTEVT2CLR_MEMRESIFG7_M 0x00008000U

#define	ADC_INTEVT2CLR_MEMRESIFG7_S 15U

#define	ADC_INTEVT2CLR_MEMRESIFG7_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG7_CLR 0x00008000U

#define	ADC_INTEVT2CLR_MEMRESIFG8 0x00010000U

#define	ADC_INTEVT2CLR_MEMRESIFG8_M 0x00010000U

#define	ADC_INTEVT2CLR_MEMRESIFG8_S 16U

#define	ADC_INTEVT2CLR_MEMRESIFG8_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG8_CLR 0x00010000U

#define	ADC_INTEVT2CLR_MEMRESIFG9 0x00020000U

#define	ADC_INTEVT2CLR_MEMRESIFG9_M 0x00020000U

#define	ADC_INTEVT2CLR_MEMRESIFG9_S 17U

#define	ADC_INTEVT2CLR_MEMRESIFG9_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG9_CLR 0x00020000U

#define	ADC_INTEVT2CLR_MEMRESIFG10 0x00040000U

#define	ADC_INTEVT2CLR_MEMRESIFG10_M 0x00040000U

#define	ADC_INTEVT2CLR_MEMRESIFG10_S 18U

#define	ADC_INTEVT2CLR_MEMRESIFG10_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG10_CLR 0x00040000U

#define	ADC_INTEVT2CLR_MEMRESIFG11 0x00080000U

#define	ADC_INTEVT2CLR_MEMRESIFG11_M 0x00080000U

#define	ADC_INTEVT2CLR_MEMRESIFG11_S 19U

#define	ADC_INTEVT2CLR_MEMRESIFG11_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG11_CLR 0x00080000U

#define	ADC_INTEVT2CLR_MEMRESIFG12 0x00100000U

#define	ADC_INTEVT2CLR_MEMRESIFG12_M 0x00100000U

#define	ADC_INTEVT2CLR_MEMRESIFG12_S 20U

#define	ADC_INTEVT2CLR_MEMRESIFG12_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG12_CLR 0x00100000U

#define	ADC_INTEVT2CLR_MEMRESIFG13 0x00200000U

#define	ADC_INTEVT2CLR_MEMRESIFG13_M 0x00200000U

#define	ADC_INTEVT2CLR_MEMRESIFG13_S 21U

#define	ADC_INTEVT2CLR_MEMRESIFG13_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG13_CLR 0x00200000U

#define	ADC_INTEVT2CLR_MEMRESIFG14 0x00400000U

#define	ADC_INTEVT2CLR_MEMRESIFG14_M 0x00400000U

#define	ADC_INTEVT2CLR_MEMRESIFG14_S 22U

#define	ADC_INTEVT2CLR_MEMRESIFG14_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG14_CLR 0x00400000U

#define	ADC_INTEVT2CLR_MEMRESIFG15 0x00800000U

#define	ADC_INTEVT2CLR_MEMRESIFG15_M 0x00800000U

#define	ADC_INTEVT2CLR_MEMRESIFG15_S 23U

#define	ADC_INTEVT2CLR_MEMRESIFG15_NO_EFFECT 0x00000000U

#define	ADC_INTEVT2CLR_MEMRESIFG15_CLR 0x00800000U

#define	ADC_EVTMOD_INT0CFG_W 2U

#define	ADC_EVTMOD_INT0CFG_M 0x00000003U

#define	ADC_EVTMOD_INT0CFG_S 0U

#define	ADC_EVTMOD_INT0CFG_DISABLE 0x00000000U

#define	ADC_EVTMOD_INT0CFG_SOFTWARE 0x00000001U

#define	ADC_EVTMOD_INT0CFG_HARDWARE 0x00000002U

#define	ADC_EVTMOD_EVT1CFG_W 2U

#define	ADC_EVTMOD_EVT1CFG_M 0x0000000CU

#define	ADC_EVTMOD_EVT1CFG_S 2U

#define	ADC_EVTMOD_EVT1CFG_DISABLE 0x00000000U

#define	ADC_EVTMOD_EVT1CFG_SOFTWARE 0x00000004U

#define	ADC_EVTMOD_EVT1CFG_HARDWARE 0x00000008U

#define	ADC_DESC_MINREV_W 4U

#define	ADC_DESC_MINREV_M 0x0000000FU

#define	ADC_DESC_MINREV_S 0U

#define	ADC_DESC_MINREV_MINIMUM 0x00000000U

#define	ADC_DESC_MINREV_MAXIMUM 0x0000000FU

#define	ADC_DESC_MAJREV_W 4U

#define	ADC_DESC_MAJREV_M 0x000000F0U

#define	ADC_DESC_MAJREV_S 4U

#define	ADC_DESC_MAJREV_MINIMUM 0x00000000U

#define	ADC_DESC_MAJREV_MAXIMUM 0x000000F0U

#define	ADC_DESC_INSTNUM_W 4U

#define	ADC_DESC_INSTNUM_M 0x00000F00U

#define	ADC_DESC_INSTNUM_S 8U

#define	ADC_DESC_FEATUREVER_W 4U

#define	ADC_DESC_FEATUREVER_M 0x0000F000U

#define	ADC_DESC_FEATUREVER_S 12U

#define	ADC_DESC_FEATUREVER_MINIMUM 0x00000000U

#define	ADC_DESC_FEATUREVER_MAXIMUM 0x0000F000U

#define	ADC_DESC_MODULEID_W 16U

#define	ADC_DESC_MODULEID_M 0xFFFF0000U

#define	ADC_DESC_MODULEID_S 16U

#define	ADC_DESC_MODULEID_MINIMUM 0x00000000U

#define	ADC_DESC_MODULEID_MAXIMUM 0xFFFF0000U

#define	ADC_CTL0_ENC 0x00000001U

#define	ADC_CTL0_ENC_M 0x00000001U

#define	ADC_CTL0_ENC_S 0U

#define	ADC_CTL0_ENC_OFF 0x00000000U

#define	ADC_CTL0_ENC_ON 0x00000001U

#define	ADC_CTL0_PWRDN 0x00010000U

#define	ADC_CTL0_PWRDN_M 0x00010000U

#define	ADC_CTL0_PWRDN_S 16U

#define	ADC_CTL0_PWRDN_AUTO 0x00000000U

#define	ADC_CTL0_PWRDN_MANUAL 0x00010000U

#define	ADC_CTL0_SCLKDIV_W 3U

#define	ADC_CTL0_SCLKDIV_M 0x07000000U

#define	ADC_CTL0_SCLKDIV_S 24U

#define	ADC_CTL0_SCLKDIV_DIV_BY_1 0x00000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_2 0x01000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_4 0x02000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_8 0x03000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_16 0x04000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_24 0x05000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_32 0x06000000U

#define	ADC_CTL0_SCLKDIV_DIV_BY_48 0x07000000U

#define	ADC_CTL1_TRIGSRC 0x00000001U

#define	ADC_CTL1_TRIGSRC_M 0x00000001U

#define	ADC_CTL1_TRIGSRC_S 0U

#define	ADC_CTL1_TRIGSRC_SOFTWARE 0x00000000U

#define	ADC_CTL1_TRIGSRC_EVENT 0x00000001U

#define	ADC_CTL1_SC 0x00000100U

#define	ADC_CTL1_SC_M 0x00000100U

#define	ADC_CTL1_SC_S 8U

#define	ADC_CTL1_SC_START 0x00000100U

#define	ADC_CTL1_SC_STOP 0x00000000U

#define	ADC_CTL1_CONSEQ_W 2U

#define	ADC_CTL1_CONSEQ_M 0x00030000U

#define	ADC_CTL1_CONSEQ_S 16U

#define	ADC_CTL1_CONSEQ_SINGLE 0x00000000U

#define	ADC_CTL1_CONSEQ_SEQUENCE 0x00010000U

#define	ADC_CTL1_CONSEQ_REPEATSINGLE 0x00020000U

#define	ADC_CTL1_CONSEQ_REPEATSEQUENCE 0x00030000U

#define	ADC_CTL1_SAMPMODE 0x00100000U

#define	ADC_CTL1_SAMPMODE_M 0x00100000U

#define	ADC_CTL1_SAMPMODE_S 20U

#define	ADC_CTL1_SAMPMODE_AUTO 0x00000000U

#define	ADC_CTL1_SAMPMODE_MANUAL 0x00100000U

#define	ADC_CTL1_AVGN_W 3U

#define	ADC_CTL1_AVGN_M 0x07000000U

#define	ADC_CTL1_AVGN_S 24U

#define	ADC_CTL1_AVGN_DISABLE 0x00000000U

#define	ADC_CTL1_AVGN_AVG_2 0x01000000U

#define	ADC_CTL1_AVGN_AVG_4 0x02000000U

#define	ADC_CTL1_AVGN_AVG_8 0x03000000U

#define	ADC_CTL1_AVGN_AVG_16 0x04000000U

#define	ADC_CTL1_AVGN_AVG_32 0x05000000U

#define	ADC_CTL1_AVGN_AVG_64 0x06000000U

#define	ADC_CTL1_AVGN_AVG_128 0x07000000U

#define	ADC_CTL1_AVGD_W 3U

#define	ADC_CTL1_AVGD_M 0x70000000U

#define	ADC_CTL1_AVGD_S 28U

#define	ADC_CTL1_AVGD_SHIFT0 0x00000000U

#define	ADC_CTL1_AVGD_SHIFT1 0x10000000U

#define	ADC_CTL1_AVGD_SHIFT2 0x20000000U

#define	ADC_CTL1_AVGD_SHIFT3 0x30000000U

#define	ADC_CTL1_AVGD_SHIFT4 0x40000000U

#define	ADC_CTL1_AVGD_SHIFT5 0x50000000U

#define	ADC_CTL1_AVGD_SHIFT6 0x60000000U

#define	ADC_CTL1_AVGD_SHIFT7 0x70000000U

#define	ADC_CTL2_DF 0x00000001U

#define	ADC_CTL2_DF_M 0x00000001U

#define	ADC_CTL2_DF_S 0U

#define	ADC_CTL2_DF_UNSIGNED 0x00000000U

#define	ADC_CTL2_DF_SIGNED 0x00000001U

#define	ADC_CTL2_RES_W 2U

#define	ADC_CTL2_RES_M 0x00000006U

#define	ADC_CTL2_RES_S 1U

#define	ADC_CTL2_RES_BIT_12 0x00000000U

#define	ADC_CTL2_DMAEN 0x00000100U

#define	ADC_CTL2_DMAEN_M 0x00000100U

#define	ADC_CTL2_DMAEN_S 8U

#define	ADC_CTL2_DMAEN_DISABLE 0x00000000U

#define	ADC_CTL2_DMAEN_ENABLE 0x00000100U

#define	ADC_CTL2_FIFOEN 0x00000400U

#define	ADC_CTL2_FIFOEN_M 0x00000400U

#define	ADC_CTL2_FIFOEN_S 10U

#define	ADC_CTL2_FIFOEN_ENABLE 0x00000400U

#define	ADC_CTL2_FIFOEN_DISABLE 0x00000000U

#define	ADC_CTL2_STARTADD_W 5U

#define	ADC_CTL2_STARTADD_M 0x001F0000U

#define	ADC_CTL2_STARTADD_S 16U

#define	ADC_CTL2_STARTADD_ADDR_00 0x00000000U

#define	ADC_CTL2_STARTADD_ADDR_01 0x00010000U

#define	ADC_CTL2_STARTADD_ADDR_02 0x00020000U

#define	ADC_CTL2_STARTADD_ADDR_03 0x00030000U

#define	ADC_CTL2_STARTADD_ADDR_04 0x00040000U

#define	ADC_CTL2_STARTADD_ADDR_05 0x00050000U

#define	ADC_CTL2_STARTADD_ADDR_06 0x00060000U

#define	ADC_CTL2_STARTADD_ADDR_07 0x00070000U

#define	ADC_CTL2_STARTADD_ADDR_08 0x00080000U

#define	ADC_CTL2_STARTADD_ADDR_09 0x00090000U

#define	ADC_CTL2_STARTADD_ADDR_10 0x000A0000U

#define	ADC_CTL2_STARTADD_ADDR_11 0x000B0000U

#define	ADC_CTL2_STARTADD_ADDR_12 0x000C0000U

#define	ADC_CTL2_STARTADD_ADDR_13 0x000D0000U

#define	ADC_CTL2_STARTADD_ADDR_14 0x000E0000U

#define	ADC_CTL2_STARTADD_ADDR_15 0x000F0000U

#define	ADC_CTL2_STARTADD_ADDR_16 0x00100000U

#define	ADC_CTL2_STARTADD_ADDR_17 0x00110000U

#define	ADC_CTL2_STARTADD_ADDR_18 0x00120000U

#define	ADC_CTL2_STARTADD_ADDR_19 0x00130000U

#define	ADC_CTL2_STARTADD_ADDR_20 0x00140000U

#define	ADC_CTL2_STARTADD_ADDR_21 0x00150000U

#define	ADC_CTL2_STARTADD_ADDR_22 0x00160000U

#define	ADC_CTL2_STARTADD_ADDR_23 0x00170000U

#define	ADC_CTL2_STARTADD_ADDR_24 0x00180000U

#define	ADC_CTL2_STARTADD_ADDR_25 0x00190000U

#define	ADC_CTL2_STARTADD_ADDR_26 0x001A0000U

#define	ADC_CTL2_STARTADD_ADDR_31 0x001F0000U

#define	ADC_CTL2_STARTADD_ADDR_30 0x001E0000U

#define	ADC_CTL2_STARTADD_ADDR_29 0x001D0000U

#define	ADC_CTL2_STARTADD_ADDR_28 0x001C0000U

#define	ADC_CTL2_STARTADD_ADDR_27 0x001B0000U

#define	ADC_CTL2_ENDADD_W 5U

#define	ADC_CTL2_ENDADD_M 0x1F000000U

#define	ADC_CTL2_ENDADD_S 24U

#define	ADC_CTL2_ENDADD_ADDR_00 0x00000000U

#define	ADC_CTL2_ENDADD_ADDR_01 0x01000000U

#define	ADC_CTL2_ENDADD_ADDR_02 0x02000000U

#define	ADC_CTL2_ENDADD_ADDR_03 0x03000000U

#define	ADC_CTL2_ENDADD_ADDR_04 0x04000000U

#define	ADC_CTL2_ENDADD_ADDR_05 0x05000000U

#define	ADC_CTL2_ENDADD_ADDR_06 0x06000000U

#define	ADC_CTL2_ENDADD_ADDR_07 0x07000000U

#define	ADC_CTL2_ENDADD_ADDR_08 0x08000000U

#define	ADC_CTL2_ENDADD_ADDR_09 0x09000000U

#define	ADC_CTL2_ENDADD_ADDR_10 0x0A000000U

#define	ADC_CTL2_ENDADD_ADDR_11 0x0B000000U

#define	ADC_CTL2_ENDADD_ADDR_12 0x0C000000U

#define	ADC_CTL2_ENDADD_ADDR_13 0x0D000000U

#define	ADC_CTL2_ENDADD_ADDR_14 0x0E000000U

#define	ADC_CTL2_ENDADD_ADDR_15 0x0F000000U

#define	ADC_CTL2_ENDADD_ADDR_16 0x10000000U

#define	ADC_CTL2_ENDADD_ADDR_17 0x11000000U

#define	ADC_CTL2_ENDADD_ADDR_18 0x12000000U

#define	ADC_CTL2_ENDADD_ADDR_19 0x13000000U

#define	ADC_CTL2_ENDADD_ADDR_20 0x14000000U

#define	ADC_CTL2_ENDADD_ADDR_21 0x15000000U

#define	ADC_CTL2_ENDADD_ADDR_22 0x16000000U

#define	ADC_CTL2_ENDADD_ADDR_23 0x17000000U

#define	ADC_CTL2_ENDADD_ADDR_24 0x18000000U

#define	ADC_CTL2_ENDADD_ADDR_25 0x19000000U

#define	ADC_CTL2_ENDADD_ADDR_26 0x1A000000U

#define	ADC_CTL2_ENDADD_ADDR_27 0x1B000000U

#define	ADC_CTL2_ENDADD_ADDR_28 0x1C000000U

#define	ADC_CTL2_ENDADD_ADDR_29 0x1D000000U

#define	ADC_CTL2_ENDADD_ADDR_30 0x1E000000U

#define	ADC_CTL2_ENDADD_ADDR_31 0x1F000000U

#define	ADC_CTL3_ASCCHSEL_W 5U

#define	ADC_CTL3_ASCCHSEL_M 0x0000001FU

#define	ADC_CTL3_ASCCHSEL_S 0U

#define	ADC_CTL3_ASCCHSEL_CHAN_0 0x00000000U

#define	ADC_CTL3_ASCCHSEL_CHAN_1 0x00000001U

#define	ADC_CTL3_ASCCHSEL_CHAN_2 0x00000002U

#define	ADC_CTL3_ASCCHSEL_CHAN_3 0x00000003U

#define	ADC_CTL3_ASCCHSEL_CHAN_4 0x00000004U

#define	ADC_CTL3_ASCCHSEL_CHAN_5 0x00000005U

#define	ADC_CTL3_ASCCHSEL_CHAN_6 0x00000006U

#define	ADC_CTL3_ASCCHSEL_CHAN_7 0x00000007U

#define	ADC_CTL3_ASCCHSEL_CHAN_8 0x00000008U

#define	ADC_CTL3_ASCCHSEL_CHAN_9 0x00000009U

#define	ADC_CTL3_ASCCHSEL_CHAN_10 0x0000000AU

#define	ADC_CTL3_ASCCHSEL_CHAN_11 0x0000000BU

#define	ADC_CTL3_ASCCHSEL_CHAN_12 0x0000000CU

#define	ADC_CTL3_ASCCHSEL_CHAN_13 0x0000000DU

#define	ADC_CTL3_ASCCHSEL_CHAN_14 0x0000000EU

#define	ADC_CTL3_ASCCHSEL_CHAN_15 0x0000000FU

#define	ADC_CTL3_ASCCHSEL_CHAN_16 0x00000010U

#define	ADC_CTL3_ASCCHSEL_CHAN_17 0x00000011U

#define	ADC_CTL3_ASCCHSEL_CHAN_18 0x00000012U

#define	ADC_CTL3_ASCCHSEL_CHAN_19 0x00000013U

#define	ADC_CTL3_ASCCHSEL_CHAN_20 0x00000014U

#define	ADC_CTL3_ASCCHSEL_CHAN_21 0x00000015U

#define	ADC_CTL3_ASCCHSEL_CHAN_22 0x00000016U

#define	ADC_CTL3_ASCCHSEL_CHAN_23 0x00000017U

#define	ADC_CTL3_ASCCHSEL_CHAN_24 0x00000018U

#define	ADC_CTL3_ASCCHSEL_CHAN_25 0x00000019U

#define	ADC_CTL3_ASCCHSEL_CHAN_26 0x0000001AU

#define	ADC_CTL3_ASCCHSEL_CHAN_27 0x0000001BU

#define	ADC_CTL3_ASCCHSEL_CHAN_28 0x0000001CU

#define	ADC_CTL3_ASCCHSEL_CHAN_29 0x0000001DU

#define	ADC_CTL3_ASCCHSEL_CHAN_30 0x0000001EU

#define	ADC_CTL3_ASCCHSEL_CHAN_31 0x0000001FU

#define	ADC_CTL3_ASCSTIME 0x00000100U

#define	ADC_CTL3_ASCSTIME_M 0x00000100U

#define	ADC_CTL3_ASCSTIME_S 8U

#define	ADC_CTL3_ASCSTIME_SEL_SCOMP0 0x00000000U

#define	ADC_CTL3_ASCSTIME_SEL_SCOMP1 0x00000100U

#define	ADC_CTL3_ASCVRSEL_W 2U

#define	ADC_CTL3_ASCVRSEL_M 0x00003000U

#define	ADC_CTL3_ASCVRSEL_S 12U

#define	ADC_CTL3_ASCVRSEL_EXTREF 0x00001000U

#define	ADC_CTL3_ASCVRSEL_INTREF 0x00002000U

#define	ADC_CTL3_ASCFSR 0x00004000U

#define	ADC_CTL3_ASCFSR_M 0x00004000U

#define	ADC_CTL3_ASCFSR_S 14U

#define	ADC_CTL3_ASCMODE 0x00008000U

#define	ADC_CTL3_ASCMODE_M 0x00008000U

#define	ADC_CTL3_ASCMODE_S 15U

#define	ADC_CLKFREQ_FRANGE_W 3U

#define	ADC_CLKFREQ_FRANGE_M 0x00000007U

#define	ADC_CLKFREQ_FRANGE_S 0U

#define	ADC_CLKFREQ_FRANGE_RANGE1TO4 0x00000000U

#define	ADC_CLKFREQ_FRANGE_RANGE4TO8 0x00000001U

#define	ADC_CLKFREQ_FRANGE_RANGE8TO16 0x00000002U

#define	ADC_CLKFREQ_FRANGE_RANGE16TO20 0x00000003U

#define	ADC_CLKFREQ_FRANGE_RANGE20TO24 0x00000004U

#define	ADC_CLKFREQ_FRANGE_RANGE24TO32 0x00000005U

#define	ADC_CLKFREQ_FRANGE_RANGE32TO40 0x00000006U

#define	ADC_CLKFREQ_FRANGE_RANGE40TO48 0x00000007U

#define	ADC_SCOMP0_SMP_W 14U

#define	ADC_SCOMP0_SMP_M 0x00003FFFU

#define	ADC_SCOMP0_SMP_S 0U

#define	ADC_SCOMP1_SMP_W 14U

#define	ADC_SCOMP1_SMP_M 0x00003FFFU

#define	ADC_SCOMP1_SMP_S 0U

#define	ADC_REFCFG_REFEN 0x00000001U

#define	ADC_REFCFG_REFEN_M 0x00000001U

#define	ADC_REFCFG_REFEN_S 0U

#define	ADC_REFCFG_REFEN_DISABLE 0x00000000U

#define	ADC_REFCFG_REFEN_ENABLE 0x00000001U

#define	ADC_REFCFG_REFVSEL 0x00000002U

#define	ADC_REFCFG_REFVSEL_M 0x00000002U

#define	ADC_REFCFG_REFVSEL_S 1U

#define	ADC_REFCFG_REFVSEL_V1P4 0x00000000U

#define	ADC_REFCFG_IBEN 0x00000004U

#define	ADC_REFCFG_IBEN_M 0x00000004U

#define	ADC_REFCFG_IBEN_S 2U

#define	ADC_REFCFG_IBEN_DISABLE 0x00000000U

#define	ADC_REFCFG_IBEN_ENABLE 0x00000004U

#define	ADC_REFCFG_IBPROG_W 2U

#define	ADC_REFCFG_IBPROG_M 0x00000018U

#define	ADC_REFCFG_IBPROG_S 3U

#define	ADC_REFCFG_IBPROG_VAL0 0x00000000U

#define	ADC_REFCFG_IBPROG_VAL1 0x00000008U

#define	ADC_REFCFG_IBPROG_VAL2 0x00000010U

#define	ADC_REFCFG_IBPROG_VAL3 0x00000018U

#define	ADC_REFCFG_OSPRPWRDN 0x00000020U

#define	ADC_REFCFG_OSPRPWRDN_M 0x00000020U

#define	ADC_REFCFG_OSPRPWRDN_S 5U

#define	ADC_REFCFG_SPAR_W 2U

#define	ADC_REFCFG_SPAR_M 0x000000C0U

#define	ADC_REFCFG_SPAR_S 6U

#define	ADC_WCLOW_DATA_W 16U

#define	ADC_WCLOW_DATA_M 0x0000FFFFU

#define	ADC_WCLOW_DATA_S 0U

#define	ADC_WCHI_DATA_W 16U

#define	ADC_WCHI_DATA_M 0x0000FFFFU

#define	ADC_WCHI_DATA_S 0U

#define	ADC_FIFODATA_DATA_W 32U

#define	ADC_FIFODATA_DATA_M 0xFFFFFFFFU

#define	ADC_FIFODATA_DATA_S 0U

#define	ADC_ASCRES_DATA_W 16U

#define	ADC_ASCRES_DATA_M 0x0000FFFFU

#define	ADC_ASCRES_DATA_S 0U

#define	ADC_MEMCTL_0_CHANSEL_W 5U

#define	ADC_MEMCTL_0_CHANSEL_M 0x0000001FU

#define	ADC_MEMCTL_0_CHANSEL_S 0U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_0 0x00000000U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_1 0x00000001U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_2 0x00000002U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_3 0x00000003U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_4 0x00000004U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_5 0x00000005U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_6 0x00000006U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_7 0x00000007U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_8 0x00000008U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_9 0x00000009U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_10 0x0000000AU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_11 0x0000000BU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_12 0x0000000CU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_13 0x0000000DU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_14 0x0000000EU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_15 0x0000000FU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_16 0x00000010U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_17 0x00000011U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_18 0x00000012U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_19 0x00000013U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_20 0x00000014U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_21 0x00000015U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_22 0x00000016U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_23 0x00000017U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_24 0x00000018U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_25 0x00000019U

#define	ADC_MEMCTL_0_CHANSEL_CHAN_26 0x0000001AU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_27 0x0000001BU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_28 0x0000001CU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_29 0x0000001DU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_30 0x0000001EU

#define	ADC_MEMCTL_0_CHANSEL_CHAN_31 0x0000001FU

#define	ADC_MEMCTL_0_VRSEL_W 2U

#define	ADC_MEMCTL_0_VRSEL_M 0x00000300U

#define	ADC_MEMCTL_0_VRSEL_S 8U

#define	ADC_MEMCTL_0_VRSEL_EXTREF 0x00000100U

#define	ADC_MEMCTL_0_VRSEL_INTREF 0x00000200U

#define	ADC_MEMCTL_0_STIME 0x00001000U

#define	ADC_MEMCTL_0_STIME_M 0x00001000U

#define	ADC_MEMCTL_0_STIME_S 12U

#define	ADC_MEMCTL_0_STIME_SEL_SCOMP0 0x00000000U

#define	ADC_MEMCTL_0_STIME_SEL_SCOMP1 0x00001000U

#define	ADC_MEMCTL_0_AVGEN 0x00010000U

#define	ADC_MEMCTL_0_AVGEN_M 0x00010000U

#define	ADC_MEMCTL_0_AVGEN_S 16U

#define	ADC_MEMCTL_0_AVGEN_DISABLE 0x00000000U

#define	ADC_MEMCTL_0_AVGEN_ENABLE 0x00010000U

#define	ADC_MEMCTL_0_TRIG 0x01000000U

#define	ADC_MEMCTL_0_TRIG_M 0x01000000U

#define	ADC_MEMCTL_0_TRIG_S 24U

#define	ADC_MEMCTL_0_TRIG_AUTO_NEXT 0x00000000U

#define	ADC_MEMCTL_0_TRIG_TRIGGER_NEXT 0x01000000U

#define	ADC_MEMCTL_0_WINCOMP 0x10000000U

#define	ADC_MEMCTL_0_WINCOMP_M 0x10000000U

#define	ADC_MEMCTL_0_WINCOMP_S 28U

#define	ADC_MEMCTL_0_WINCOMP_DISABLE 0x00000000U

#define	ADC_MEMCTL_0_WINCOMP_ENABLE 0x10000000U

#define	ADC_MEMCTL_0_FSR 0x20000000U

#define	ADC_MEMCTL_0_FSR_M 0x20000000U

#define	ADC_MEMCTL_0_FSR_S 29U

#define	ADC_MEMCTL_0_MOD 0x40000000U

#define	ADC_MEMCTL_0_MOD_M 0x40000000U

#define	ADC_MEMCTL_0_MOD_S 30U

#define	ADC_MEMCTL_1_CHANSEL_W 5U

#define	ADC_MEMCTL_1_CHANSEL_M 0x0000001FU

#define	ADC_MEMCTL_1_CHANSEL_S 0U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_0 0x00000000U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_1 0x00000001U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_2 0x00000002U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_3 0x00000003U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_4 0x00000004U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_5 0x00000005U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_6 0x00000006U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_7 0x00000007U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_8 0x00000008U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_9 0x00000009U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_10 0x0000000AU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_11 0x0000000BU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_12 0x0000000CU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_13 0x0000000DU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_14 0x0000000EU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_15 0x0000000FU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_16 0x00000010U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_17 0x00000011U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_18 0x00000012U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_19 0x00000013U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_20 0x00000014U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_21 0x00000015U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_22 0x00000016U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_23 0x00000017U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_24 0x00000018U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_25 0x00000019U

#define	ADC_MEMCTL_1_CHANSEL_CHAN_26 0x0000001AU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_27 0x0000001BU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_28 0x0000001CU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_29 0x0000001DU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_30 0x0000001EU

#define	ADC_MEMCTL_1_CHANSEL_CHAN_31 0x0000001FU

#define	ADC_MEMCTL_1_VRSEL_W 2U

#define	ADC_MEMCTL_1_VRSEL_M 0x00000300U

#define	ADC_MEMCTL_1_VRSEL_S 8U

#define	ADC_MEMCTL_1_VRSEL_EXTREF 0x00000100U

#define	ADC_MEMCTL_1_VRSEL_INTREF 0x00000200U

#define	ADC_MEMCTL_1_STIME 0x00001000U

#define	ADC_MEMCTL_1_STIME_M 0x00001000U

#define	ADC_MEMCTL_1_STIME_S 12U

#define	ADC_MEMCTL_1_STIME_SEL_SCOMP0 0x00000000U

#define	ADC_MEMCTL_1_STIME_SEL_SCOMP1 0x00001000U

#define	ADC_MEMCTL_1_AVGEN 0x00010000U

#define	ADC_MEMCTL_1_AVGEN_M 0x00010000U

#define	ADC_MEMCTL_1_AVGEN_S 16U

#define	ADC_MEMCTL_1_AVGEN_DISABLE 0x00000000U

#define	ADC_MEMCTL_1_AVGEN_ENABLE 0x00010000U

#define	ADC_MEMCTL_1_TRIG 0x01000000U

#define	ADC_MEMCTL_1_TRIG_M 0x01000000U

#define	ADC_MEMCTL_1_TRIG_S 24U

#define	ADC_MEMCTL_1_TRIG_AUTO_NEXT 0x00000000U

#define	ADC_MEMCTL_1_TRIG_TRIGGER_NEXT 0x01000000U

#define	ADC_MEMCTL_1_WINCOMP 0x10000000U

#define	ADC_MEMCTL_1_WINCOMP_M 0x10000000U

#define	ADC_MEMCTL_1_WINCOMP_S 28U

#define	ADC_MEMCTL_1_WINCOMP_DISABLE 0x00000000U

#define	ADC_MEMCTL_1_WINCOMP_ENABLE 0x10000000U

#define	ADC_MEMCTL_1_FSR 0x20000000U

#define	ADC_MEMCTL_1_FSR_M 0x20000000U

#define	ADC_MEMCTL_1_FSR_S 29U

#define	ADC_MEMCTL_1_MOD 0x40000000U

#define	ADC_MEMCTL_1_MOD_M 0x40000000U

#define	ADC_MEMCTL_1_MOD_S 30U

#define	ADC_MEMCTL_2_CHANSEL_W 5U

#define	ADC_MEMCTL_2_CHANSEL_M 0x0000001FU

#define	ADC_MEMCTL_2_CHANSEL_S 0U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_0 0x00000000U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_1 0x00000001U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_2 0x00000002U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_3 0x00000003U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_4 0x00000004U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_5 0x00000005U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_6 0x00000006U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_7 0x00000007U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_8 0x00000008U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_9 0x00000009U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_10 0x0000000AU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_11 0x0000000BU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_12 0x0000000CU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_13 0x0000000DU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_14 0x0000000EU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_15 0x0000000FU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_16 0x00000010U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_17 0x00000011U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_18 0x00000012U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_19 0x00000013U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_20 0x00000014U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_21 0x00000015U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_22 0x00000016U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_23 0x00000017U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_24 0x00000018U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_25 0x00000019U

#define	ADC_MEMCTL_2_CHANSEL_CHAN_26 0x0000001AU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_27 0x0000001BU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_28 0x0000001CU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_29 0x0000001DU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_30 0x0000001EU

#define	ADC_MEMCTL_2_CHANSEL_CHAN_31 0x0000001FU

#define	ADC_MEMCTL_2_VRSEL_W 2U

#define	ADC_MEMCTL_2_VRSEL_M 0x00000300U

#define	ADC_MEMCTL_2_VRSEL_S 8U

#define	ADC_MEMCTL_2_VRSEL_EXTREF 0x00000100U

#define	ADC_MEMCTL_2_VRSEL_INTREF 0x00000200U

#define	ADC_MEMCTL_2_STIME 0x00001000U

#define	ADC_MEMCTL_2_STIME_M 0x00001000U

#define	ADC_MEMCTL_2_STIME_S 12U

#define	ADC_MEMCTL_2_STIME_SEL_SCOMP0 0x00000000U

#define	ADC_MEMCTL_2_STIME_SEL_SCOMP1 0x00001000U

#define	ADC_MEMCTL_2_AVGEN 0x00010000U

#define	ADC_MEMCTL_2_AVGEN_M 0x00010000U

#define	ADC_MEMCTL_2_AVGEN_S 16U

#define	ADC_MEMCTL_2_AVGEN_DISABLE 0x00000000U

#define	ADC_MEMCTL_2_AVGEN_ENABLE 0x00010000U

#define	ADC_MEMCTL_2_TRIG 0x01000000U

#define	ADC_MEMCTL_2_TRIG_M 0x01000000U

#define	ADC_MEMCTL_2_TRIG_S 24U

#define	ADC_MEMCTL_2_TRIG_AUTO_NEXT 0x00000000U

#define	ADC_MEMCTL_2_TRIG_TRIGGER_NEXT 0x01000000U

#define	ADC_MEMCTL_2_WINCOMP 0x10000000U

#define	ADC_MEMCTL_2_WINCOMP_M 0x10000000U

#define	ADC_MEMCTL_2_WINCOMP_S 28U

#define	ADC_MEMCTL_2_WINCOMP_DISABLE 0x00000000U

#define	ADC_MEMCTL_2_WINCOMP_ENABLE 0x10000000U

#define	ADC_MEMCTL_2_FSR 0x20000000U

#define	ADC_MEMCTL_2_FSR_M 0x20000000U

#define	ADC_MEMCTL_2_FSR_S 29U

#define	ADC_MEMCTL_2_MOD 0x40000000U

#define	ADC_MEMCTL_2_MOD_M 0x40000000U

#define	ADC_MEMCTL_2_MOD_S 30U

#define	ADC_MEMCTL_3_CHANSEL_W 5U

#define	ADC_MEMCTL_3_CHANSEL_M 0x0000001FU

#define	ADC_MEMCTL_3_CHANSEL_S 0U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_0 0x00000000U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_1 0x00000001U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_2 0x00000002U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_3 0x00000003U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_4 0x00000004U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_5 0x00000005U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_6 0x00000006U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_7 0x00000007U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_8 0x00000008U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_9 0x00000009U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_10 0x0000000AU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_11 0x0000000BU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_12 0x0000000CU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_13 0x0000000DU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_14 0x0000000EU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_15 0x0000000FU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_16 0x00000010U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_17 0x00000011U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_18 0x00000012U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_19 0x00000013U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_20 0x00000014U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_21 0x00000015U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_22 0x00000016U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_23 0x00000017U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_24 0x00000018U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_25 0x00000019U

#define	ADC_MEMCTL_3_CHANSEL_CHAN_26 0x0000001AU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_27 0x0000001BU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_28 0x0000001CU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_29 0x0000001DU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_30 0x0000001EU

#define	ADC_MEMCTL_3_CHANSEL_CHAN_31 0x0000001FU

#define	ADC_MEMCTL_3_VRSEL_W 2U

#define	ADC_MEMCTL_3_VRSEL_M 0x00000300U

#define	ADC_MEMCTL_3_VRSEL_S 8U

#define	ADC_MEMCTL_3_VRSEL_EXTREF 0x00000100U

#define	ADC_MEMCTL_3_VRSEL_INTREF 0x00000200U

#define	ADC_MEMCTL_3_STIME 0x00001000U

#define	ADC_MEMCTL_3_STIME_M 0x00001000U

#define	ADC_MEMCTL_3_STIME_S 12U

#define	ADC_MEMCTL_3_STIME_SEL_SCOMP0 0x00000000U

#define	ADC_MEMCTL_3_STIME_SEL_SCOMP1 0x00001000U

#define	ADC_MEMCTL_3_AVGEN 0x00010000U

#define	ADC_MEMCTL_3_AVGEN_M 0x00010000U

#define	ADC_MEMCTL_3_AVGEN_S 16U

#define	ADC_MEMCTL_3_AVGEN_DISABLE 0x00000000U

#define	ADC_MEMCTL_3_AVGEN_ENABLE 0x00010000U

#define	ADC_MEMCTL_3_TRIG 0x01000000U

#define	ADC_MEMCTL_3_TRIG_M 0x01000000U

#define	ADC_MEMCTL_3_TRIG_S 24U

#define	ADC_MEMCTL_3_TRIG_AUTO_NEXT 0x00000000U

#define	ADC_MEMCTL_3_TRIG_TRIGGER_NEXT 0x01000000U

#define	ADC_MEMCTL_3_WINCOMP 0x10000000U

#define	ADC_MEMCTL_3_WINCOMP_M 0x10000000U

#define	ADC_MEMCTL_3_WINCOMP_S 28U

#define	ADC_MEMCTL_3_WINCOMP_DISABLE 0x00000000U

#define	ADC_MEMCTL_3_WINCOMP_ENABLE 0x10000000U

#define	ADC_MEMCTL_3_FSR 0x20000000U

#define	ADC_MEMCTL_3_FSR_M 0x20000000U

#define	ADC_MEMCTL_3_FSR_S 29U

#define	ADC_MEMCTL_3_MOD 0x40000000U

#define	ADC_MEMCTL_3_MOD_M 0x40000000U

#define	ADC_MEMCTL_3_MOD_S 30U

#define	ADC_MEMCTL_4_CHANSEL_W 5U

#define	ADC_MEMCTL_4_CHANSEL_M 0x0000001FU

#define	ADC_MEMCTL_4_CHANSEL_S 0U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_0 0x00000000U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_1 0x00000001U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_2 0x00000002U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_3 0x00000003U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_4 0x00000004U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_5 0x00000005U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_6 0x00000006U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_7 0x00000007U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_8 0x00000008U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_9 0x00000009U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_10 0x0000000AU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_11 0x0000000BU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_12 0x0000000CU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_13 0x0000000DU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_14 0x0000000EU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_15 0x0000000FU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_16 0x00000010U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_17 0x00000011U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_18 0x00000012U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_19 0x00000013U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_20 0x00000014U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_21 0x00000015U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_22 0x00000016U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_23 0x00000017U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_24 0x00000018U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_25 0x00000019U

#define	ADC_MEMCTL_4_CHANSEL_CHAN_26 0x0000001AU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_27 0x0000001BU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_28 0x0000001CU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_29 0x0000001DU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_30 0x0000001EU

#define	ADC_MEMCTL_4_CHANSEL_CHAN_31 0x0000001FU

#define	ADC_MEMCTL_4_VRSEL_W 2U

#define	ADC_MEMCTL_4_VRSEL_M 0x00000300U

#define	ADC_MEMCTL_4_VRSEL_S 8U

#define	ADC_MEMCTL_4_VRSEL_EXTREF 0x00000100U

#define	ADC_MEMCTL_4_VRSEL_INTREF 0x00000200U

#define	ADC_MEMCTL_4_STIME 0x00001000U

#define	ADC_MEMCTL_4_STIME_M 0x00001000U

#define	ADC_MEMCTL_4_STIME_S 12U

#define	ADC_MEMCTL_4_STIME_SEL_SCOMP0 0x00000000U

#define	ADC_MEMCTL_4_STIME_SEL_SCOMP1 0x00001000U

#define	ADC_MEMCTL_4_AVGEN 0x00010000U

#define	ADC_MEMCTL_4_AVGEN_M 0x00010000U

#define	ADC_MEMCTL_4_AVGEN_S 16U

#define	ADC_MEMCTL_4_AVGEN_DISABLE 0x00000000U

#define	ADC_MEMCTL_4_AVGEN_ENABLE 0x00010000U

#define	ADC_MEMCTL_4_TRIG 0x01000000U

#define	ADC_MEMCTL_4_TRIG_M 0x01000000U

#define	ADC_MEMCTL_4_TRIG_S 24U

#define	ADC_MEMCTL_4_TRIG_AUTO_NEXT 0x00000000U

#define	ADC_MEMCTL_4_TRIG_TRIGGER_NEXT 0x01000000U

#define	ADC_MEMCTL_4_WINCOMP 0x10000000U

#define	ADC_MEMCTL_4_WINCOMP_M 0x10000000U

#define	ADC_MEMCTL_4_WINCOMP_S 28U

#define	ADC_MEMCTL_4_WINCOMP_DISABLE 0x00000000U

#define	ADC_MEMCTL_4_WINCOMP_ENABLE 0x10000000U

#define	ADC_MEMCTL_4_FSR 0x20000000U

#define	ADC_MEMCTL_4_FSR_M 0x20000000U

#define	ADC_MEMCTL_4_FSR_S 29U

#define	ADC_MEMCTL_4_MOD 0x40000000U

#define	ADC_MEMCTL_4_MOD_M 0x40000000U

#define	ADC_MEMCTL_4_MOD_S 30U

#define	ADC_MEMCTL_5_CHANSEL_W 5U

#define	ADC_MEMCTL_5_CHANSEL_M 0x0000001FU

#define	ADC_MEMCTL_5_CHANSEL_S 0U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_0 0x00000000U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_1 0x00000001U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_2 0x00000002U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_3 0x00000003U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_4 0x00000004U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_5 0x00000005U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_6 0x00000006U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_7 0x00000007U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_8 0x00000008U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_9 0x00000009U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_10 0x0000000AU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_11 0x0000000BU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_12 0x0000000CU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_13 0x0000000DU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_14 0x0000000EU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_15 0x0000000FU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_16 0x00000010U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_17 0x00000011U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_18 0x00000012U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_19 0x00000013U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_20 0x00000014U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_21 0x00000015U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_22 0x00000016U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_23 0x00000017U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_24 0x00000018U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_25 0x00000019U

#define	ADC_MEMCTL_5_CHANSEL_CHAN_26 0x0000001AU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_27 0x0000001BU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_28 0x0000001CU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_29 0x0000001DU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_30 0x0000001EU

#define	ADC_MEMCTL_5_CHANSEL_CHAN_31 0x0000001FU

#define	ADC_MEMCTL_5_VRSEL_W 2U

#define	ADC_MEMCTL_5_VRSEL_M 0x00000300U

#define	ADC_MEMCTL_5_VRSEL_S 8U

#define	ADC_MEMCTL_5_VRSEL_EXTREF 0x00000100U

#define	ADC_MEMCTL_5_VRSEL_INTREF 0x00000200U

#define	ADC_MEMCTL_5_STIME 0x00001000U

#define	ADC_MEMCTL_5_STIME_M 0x00001000U

#define	ADC_MEMCTL_5_STIME_S 12U

#define	ADC_MEMCTL_5_STIME_SEL_SCOMP0 0x00000000U

#define	ADC_MEMCTL_5_STIME_SEL_SCOMP1 0x00001000U

#define	ADC_MEMCTL_5_AVGEN 0x00010000U

#define	ADC_MEMCTL_5_AVGEN_M 0x00010000U

#define	ADC_MEMCTL_5_AVGEN_S 16U

#define	ADC_MEMCTL_5_AVGEN_DISABLE 0x00000000U

#define	ADC_MEMCTL_5_AVGEN_ENABLE 0x00010000U

#define	ADC_MEMCTL_5_TRIG 0x01000000U

#define	ADC_MEMCTL_5_TRIG_M 0x01000000U

#define	ADC_MEMCTL_5_TRIG_S 24U

#define	ADC_MEMCTL_5_TRIG_AUTO_NEXT 0x00000000U

#define	ADC_MEMCTL_5_TRIG_TRIGGER_NEXT 0x01000000U

#define	ADC_MEMCTL_5_WINCOMP 0x10000000U

#define	ADC_MEMCTL_5_WINCOMP_M 0x10000000U

#define	ADC_MEMCTL_5_WINCOMP_S 28U

#define	ADC_MEMCTL_5_WINCOMP_DISABLE 0x00000000U

#define	ADC_MEMCTL_5_WINCOMP_ENABLE 0x10000000U

#define	ADC_MEMCTL_5_FSR 0x20000000U

#define	ADC_MEMCTL_5_FSR_M 0x20000000U

#define	ADC_MEMCTL_5_FSR_S 29U

#define	ADC_MEMCTL_5_MOD 0x40000000U

#define	ADC_MEMCTL_5_MOD_M 0x40000000U

#define	ADC_MEMCTL_5_MOD_S 30U

#define	ADC_MEMRES_0_DATA_W 16U

#define	ADC_MEMRES_0_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_0_DATA_S 0U

#define	ADC_MEMRES_1_DATA_W 16U

#define	ADC_MEMRES_1_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_1_DATA_S 0U

#define	ADC_MEMRES_2_DATA_W 16U

#define	ADC_MEMRES_2_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_2_DATA_S 0U

#define	ADC_MEMRES_3_DATA_W 16U

#define	ADC_MEMRES_3_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_3_DATA_S 0U

#define	ADC_MEMRES_4_DATA_W 16U

#define	ADC_MEMRES_4_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_4_DATA_S 0U

#define	ADC_MEMRES_5_DATA_W 16U

#define	ADC_MEMRES_5_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_5_DATA_S 0U

#define	ADC_MEMRES_6_DATA_W 16U

#define	ADC_MEMRES_6_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_6_DATA_S 0U

#define	ADC_MEMRES_7_DATA_W 16U

#define	ADC_MEMRES_7_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_7_DATA_S 0U

#define	ADC_MEMRES_8_DATA_W 16U

#define	ADC_MEMRES_8_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_8_DATA_S 0U

#define	ADC_MEMRES_9_DATA_W 16U

#define	ADC_MEMRES_9_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_9_DATA_S 0U

#define	ADC_MEMRES_10_DATA_W 16U

#define	ADC_MEMRES_10_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_10_DATA_S 0U

#define	ADC_MEMRES_11_DATA_W 16U

#define	ADC_MEMRES_11_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_11_DATA_S 0U

#define	ADC_MEMRES_12_DATA_W 16U

#define	ADC_MEMRES_12_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_12_DATA_S 0U

#define	ADC_MEMRES_13_DATA_W 16U

#define	ADC_MEMRES_13_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_13_DATA_S 0U

#define	ADC_MEMRES_14_DATA_W 16U

#define	ADC_MEMRES_14_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_14_DATA_S 0U

#define	ADC_MEMRES_15_DATA_W 16U

#define	ADC_MEMRES_15_DATA_M 0x0000FFFFU

#define	ADC_MEMRES_15_DATA_S 0U

#define	ADC_STA_BUSY 0x00000001U

#define	ADC_STA_BUSY_M 0x00000001U

#define	ADC_STA_BUSY_S 0U

#define	ADC_STA_BUSY_ACTIVE 0x00000001U

#define	ADC_STA_BUSY_IDLE 0x00000000U

#define	ADC_STA_REFBUFRDY 0x00000002U

#define	ADC_STA_REFBUFRDY_M 0x00000002U

#define	ADC_STA_REFBUFRDY_S 1U

#define	ADC_STA_REFBUFRDY_READY 0x00000002U

#define	ADC_STA_REFBUFRDY_NOTREADY 0x00000000U

#define	ADC_STA_ASCACT 0x00000004U

#define	ADC_STA_ASCACT_M 0x00000004U

#define	ADC_STA_ASCACT_S 2U

#define	ADC_STA_ASCACT_ACTIVE 0x00000004U

#define	ADC_STA_ASCACT_IDLE 0x00000000U

#define	ADC_TEST0_AMBUFSEL_W 5U

#define	ADC_TEST0_AMBUFSEL_M 0x0000001FU

#define	ADC_TEST0_AMBUFSEL_S 0U

#define	ADC_TEST0_AMUNBUFSEL_W 5U

#define	ADC_TEST0_AMUNBUFSEL_M 0x00001F00U

#define	ADC_TEST0_AMUNBUFSEL_S 8U

#define	ADC_TEST0_ATBUNBUFEN 0x20000000U

#define	ADC_TEST0_ATBUNBUFEN_M 0x20000000U

#define	ADC_TEST0_ATBUNBUFEN_S 29U

#define	ADC_TEST0_ATBBUFEN 0x40000000U

#define	ADC_TEST0_ATBBUFEN_M 0x40000000U

#define	ADC_TEST0_ATBBUFEN_S 30U

#define	ADC_TEST1_DTBMSEL_W 5U

#define	ADC_TEST1_DTBMSEL_M 0x0000001FU

#define	ADC_TEST1_DTBMSEL_S 0U

#define	ADC_TEST2_MUXTSEL 0x00000100U

#define	ADC_TEST2_MUXTSEL_M 0x00000100U

#define	ADC_TEST2_MUXTSEL_S 8U

#define	ADC_TEST2_CMPGNTRIM 0x00100000U

#define	ADC_TEST2_CMPGNTRIM_M 0x00100000U

#define	ADC_TEST2_CMPGNTRIM_S 20U

#define	ADC_TEST2_LTRIMEN 0x01000000U

#define	ADC_TEST2_LTRIMEN_M 0x01000000U

#define	ADC_TEST2_LTRIMEN_S 24U

#define	ADC_TEST2_CDACOVSTEN 0x80000000U

#define	ADC_TEST2_CDACOVSTEN_M 0x80000000U

#define	ADC_TEST2_CDACOVSTEN_S 31U

#define	ADC_TEST3_CALACUML_W 32U

#define	ADC_TEST3_CALACUML_M 0xFFFFFFFFU

#define	ADC_TEST3_CALACUML_S 0U

#define	ADC_TEST4_CALSTPSEL_W 6U

#define	ADC_TEST4_CALSTPSEL_M 0x003F0000U

#define	ADC_TEST4_CALSTPSEL_S 16U

#define	ADC_TEST4_CALMODEN 0x01000000U

#define	ADC_TEST4_CALMODEN_M 0x01000000U

#define	ADC_TEST4_CALMODEN_S 24U

#define	ADC_TEST4_HWSTPSELDIS 0x80000000U

#define	ADC_TEST4_HWSTPSELDIS_M 0x80000000U

#define	ADC_TEST4_HWSTPSELDIS_S 31U

#define	ADC_TEST5_CALCAPCTL_W 10U

#define	ADC_TEST5_CALCAPCTL_M 0x000003FFU

#define	ADC_TEST5_CALCAPCTL_S 0U

#define	ADC_TEST6_ATBSEL_W 4U

#define	ADC_TEST6_ATBSEL_M 0x0000000FU

#define	ADC_TEST6_ATBSEL_S 0U

#define	ADC_TEST6_ATBSEL_VAL0 0x00000000U

#define	ADC_TEST6_ATBSEL_VAL1 0x00000001U

#define	ADC_TEST6_ATBSEL_VAL2 0x00000002U

#define	ADC_TEST6_ATBSEL_VAL4 0x00000004U

#define	ADC_TEST6_ATBSEL_VAL8 0x00000008U

#define	ADC_DBG1_CTRL_W 32U

#define	ADC_DBG1_CTRL_M 0xFFFFFFFFU

#define	ADC_DBG1_CTRL_S 0U

#define	ADC_DBG2_VTSTODEN 0x01000000U

#define	ADC_DBG2_VTSTODEN_M 0x01000000U

#define	ADC_DBG2_VTSTODEN_S 24U

#define	ADC_DBG2_VTOICTL_W 2U

#define	ADC_DBG2_VTOICTL_M 0x30000000U

#define	ADC_DBG2_VTOICTL_S 28U

#define	ADC_DBG3_BSTENZ 0x00000001U

#define	ADC_DBG3_BSTENZ_M 0x00000001U

#define	ADC_DBG3_BSTENZ_S 0U

#define	ADC_DBG3_DEC0DIS 0x00000010U

#define	ADC_DBG3_DEC0DIS_M 0x00000010U

#define	ADC_DBG3_DEC0DIS_S 4U

#define	ADC_DBG3_DEC1DIS 0x00000020U

#define	ADC_DBG3_DEC1DIS_M 0x00000020U

#define	ADC_DBG3_DEC1DIS_S 5U

#define	ADC_DBG4_ADCCTL0_W 16U

#define	ADC_DBG4_ADCCTL0_M 0x0000FFFFU

#define	ADC_DBG4_ADCCTL0_S 0U

#define	ADC_CONVCTL_DAC_W 3U

#define	ADC_CONVCTL_DAC_M 0x00000007U

#define	ADC_CONVCTL_DAC_S 0U

#define	ADC_CONVCTL_PREAMP_W 2U

#define	ADC_CONVCTL_PREAMP_M 0x00000018U

#define	ADC_CONVCTL_PREAMP_S 3U

#define	ADC_CONVCTL_HOLD_W 4U

#define	ADC_CONVCTL_HOLD_M 0x000001E0U

#define	ADC_CONVCTL_HOLD_S 5U

#define	ADC_CONVCTL_OV 0x00008000U

#define	ADC_CONVCTL_OV_M 0x00008000U

#define	ADC_CONVCTL_OV_S 15U

#define	ADC_CONVCTL_CONCLKSEL_W 2U

#define	ADC_CONVCTL_CONCLKSEL_M 0x00030000U

#define	ADC_CONVCTL_CONCLKSEL_S 16U

#define	ADC_CONVCTL_CONVCLKEN 0x00040000U

#define	ADC_CONVCTL_CONVCLKEN_M 0x00040000U

#define	ADC_CONVCTL_CONVCLKEN_S 18U

#define	ADC_CTRL_FSBIT0_W 9U

#define	ADC_CTRL_FSBIT0_M 0x000001FFU

#define	ADC_CTRL_FSBIT0_S 0U

#define	ADC_CTRL_FSBIT1_W 8U

#define	ADC_CTRL_FSBIT1_M 0x0001FE00U

#define	ADC_CTRL_FSBIT1_S 9U

#define	ADC_MODCTL_VREFRAN 0x00000001U

#define	ADC_MODCTL_VREFRAN_M 0x00000001U

#define	ADC_MODCTL_VREFRAN_S 0U

#define	ADC_MODCTL_SCASEL 0x00000002U

#define	ADC_MODCTL_SCASEL_M 0x00000002U

#define	ADC_MODCTL_SCASEL_S 1U

#define	ADC_INTCHCTL_RLVAL 0x00000001U

#define	ADC_INTCHCTL_RLVAL_M 0x00000001U

#define	ADC_INTCHCTL_RLVAL_S 0U

#define	ADC_INTCHCTL_RLOV 0x00000002U

#define	ADC_INTCHCTL_RLOV_M 0x00000002U

#define	ADC_INTCHCTL_RLOV_S 1U

#define	ADC_STLTIM_SWCTRLDEL_W 6U

#define	ADC_STLTIM_SWCTRLDEL_M 0x0000003FU

#define	ADC_STLTIM_SWCTRLDEL_S 0U

#define	ADC_STLTIM_RCSETDEL_W 10U

#define	ADC_STLTIM_RCSETDEL_M 0x03FF0000U

#define	ADC_STLTIM_RCSETDEL_S 16U

#define	ADC_CLKCFG_EN 0x00000001U

#define	ADC_CLKCFG_EN_M 0x00000001U

#define	ADC_CLKCFG_EN_S 0U

Macro Definition Documentation

§ ADC_O_FSCTL0

#define ADC_O_FSCTL0 0x00000000U

§ ADC_O_FSCTL1

#define ADC_O_FSCTL1 0x00000004U

§ ADC_O_FSCTL2

#define ADC_O_FSCTL2 0x00000008U

§ ADC_O_FSCTL3

#define ADC_O_FSCTL3 0x0000000CU

§ ADC_O_REFBUF

#define ADC_O_REFBUF 0x00000010U

§ ADC_O_ATB

#define ADC_O_ATB 0x00000014U

§ ADC_O_INTEVT0IDX

#define ADC_O_INTEVT0IDX 0x00001020U

§ ADC_O_INTEVT0BM

#define ADC_O_INTEVT0BM 0x00001028U

Referenced by ADCDisableInterrupt(), and ADCEnableInterrupt().

§ ADC_O_INTEVT0RIS

#define ADC_O_INTEVT0RIS 0x00001030U

Referenced by ADCRawInterruptStatus().

§ ADC_O_INTEVT0MIS

#define ADC_O_INTEVT0MIS 0x00001038U

Referenced by ADCMaskedInterruptStatus().

§ ADC_O_INTEVT0SET

#define ADC_O_INTEVT0SET 0x00001040U

§ ADC_O_INTEVT0CLR

#define ADC_O_INTEVT0CLR 0x00001048U

Referenced by ADCClearInterrupt().

§ ADC_O_INTEVT1IDX

#define ADC_O_INTEVT1IDX 0x00001050U

§ ADC_O_INTEVT1BM

#define ADC_O_INTEVT1BM 0x00001058U

§ ADC_O_INTEVT1RIS

#define ADC_O_INTEVT1RIS 0x00001060U

§ ADC_O_INTEVT1MIS

#define ADC_O_INTEVT1MIS 0x00001068U

§ ADC_O_INTEVT1SET

#define ADC_O_INTEVT1SET 0x00001070U

§ ADC_O_INTEVT1CLR

#define ADC_O_INTEVT1CLR 0x00001078U

§ ADC_O_INTEVT2IDX

#define ADC_O_INTEVT2IDX 0x00001080U

§ ADC_O_INTEVT2BM

#define ADC_O_INTEVT2BM 0x00001088U

§ ADC_O_INTEVT2RIS

#define ADC_O_INTEVT2RIS 0x00001090U

§ ADC_O_INTEVT2MIS

#define ADC_O_INTEVT2MIS 0x00001098U

§ ADC_O_INTEVT2SET

#define ADC_O_INTEVT2SET 0x000010A0U

§ ADC_O_INTEVT2CLR

#define ADC_O_INTEVT2CLR 0x000010A8U

§ ADC_O_EVTMOD

#define ADC_O_EVTMOD 0x000010E0U

§ ADC_O_DESC

#define ADC_O_DESC 0x000010FCU

§ ADC_O_CTL0

#define ADC_O_CTL0 0x00001100U

Referenced by ADCDisableConversion(), ADCEnableConversion(), ADCSetPowerDownPolicy(), and ADCSetSampleDuration().

§ ADC_O_CTL1

#define ADC_O_CTL1 0x00001104U

Referenced by ADCSetSamplingMode(), ADCSetSequence(), ADCSetTriggerSource(), ADCStartConversion(), and ADCStopConversion().

§ ADC_O_CTL2

#define ADC_O_CTL2 0x00001108U

Referenced by ADCDisableDmaTrigger(), ADCEnableDmaTrigger(), and ADCSetMemctlRange().

§ ADC_O_CTL3

#define ADC_O_CTL3 0x0000110CU

§ ADC_O_CLKFREQ

#define ADC_O_CLKFREQ 0x00001110U

§ ADC_O_SCOMP0

#define ADC_O_SCOMP0 0x00001114U

Referenced by ADCSetSampleDuration().

§ ADC_O_SCOMP1

#define ADC_O_SCOMP1 0x00001118U

§ ADC_O_REFCFG

#define ADC_O_REFCFG 0x0000111CU

Referenced by ADCSetInput().

§ ADC_O_WCLOW

#define ADC_O_WCLOW 0x00001148U

§ ADC_O_WCHI

#define ADC_O_WCHI 0x00001150U

§ ADC_O_FIFODATA

#define ADC_O_FIFODATA 0x00001160U

§ ADC_O_ASCRES

#define ADC_O_ASCRES 0x00001170U

§ ADC_O_MEMCTL_0

#define ADC_O_MEMCTL_0 0x00001180U

Referenced by ADCSetInput(), and ADCSetTriggerPolicy().

§ ADC_O_MEMCTL_1

#define ADC_O_MEMCTL_1 0x00001184U

§ ADC_O_MEMCTL_2

#define ADC_O_MEMCTL_2 0x00001188U

§ ADC_O_MEMCTL_3

#define ADC_O_MEMCTL_3 0x0000118CU

§ ADC_O_MEMCTL_4

#define ADC_O_MEMCTL_4 0x00001190U

§ ADC_O_MEMCTL_5

#define ADC_O_MEMCTL_5 0x00001194U

§ ADC_O_MEMRES_0

#define ADC_O_MEMRES_0 0x00001280U

Referenced by ADCReadResult(), and ADCReadResultNonBlocking().

§ ADC_O_MEMRES_1

#define ADC_O_MEMRES_1 0x00001284U

§ ADC_O_MEMRES_2

#define ADC_O_MEMRES_2 0x00001288U

§ ADC_O_MEMRES_3

#define ADC_O_MEMRES_3 0x0000128CU

§ ADC_O_MEMRES_4

#define ADC_O_MEMRES_4 0x00001290U

§ ADC_O_MEMRES_5

#define ADC_O_MEMRES_5 0x00001294U

§ ADC_O_MEMRES_6

#define ADC_O_MEMRES_6 0x00001298U

§ ADC_O_MEMRES_7

#define ADC_O_MEMRES_7 0x0000129CU

§ ADC_O_MEMRES_8

#define ADC_O_MEMRES_8 0x000012A0U

§ ADC_O_MEMRES_9

#define ADC_O_MEMRES_9 0x000012A4U

§ ADC_O_MEMRES_10

#define ADC_O_MEMRES_10 0x000012A8U

§ ADC_O_MEMRES_11

#define ADC_O_MEMRES_11 0x000012ACU

§ ADC_O_MEMRES_12

#define ADC_O_MEMRES_12 0x000012B0U

§ ADC_O_MEMRES_13

#define ADC_O_MEMRES_13 0x000012B4U

§ ADC_O_MEMRES_14

#define ADC_O_MEMRES_14 0x000012B8U

§ ADC_O_MEMRES_15

#define ADC_O_MEMRES_15 0x000012BCU

§ ADC_O_STA

#define ADC_O_STA 0x00001340U

Referenced by ADCIsBusy(), and ADCReadResult().

§ ADC_O_TEST0

#define ADC_O_TEST0 0x00001E00U

§ ADC_O_TEST1

#define ADC_O_TEST1 0x00001E04U

§ ADC_O_TEST2

#define ADC_O_TEST2 0x00001E08U

§ ADC_O_TEST3

#define ADC_O_TEST3 0x00001E0CU

§ ADC_O_TEST4

#define ADC_O_TEST4 0x00001E10U

§ ADC_O_TEST5

#define ADC_O_TEST5 0x00001E14U

§ ADC_O_TEST6

#define ADC_O_TEST6 0x00001E18U

§ ADC_O_DBG1

#define ADC_O_DBG1 0x00001E20U

§ ADC_O_DBG2

#define ADC_O_DBG2 0x00001E24U

§ ADC_O_DBG3

#define ADC_O_DBG3 0x00001E28U

§ ADC_O_DBG4

#define ADC_O_DBG4 0x00001E2CU

§ ADC_O_CONVCTL

#define ADC_O_CONVCTL 0x00001F14U

Referenced by ADCSetSamplingClk().

§ ADC_O_CTRL

#define ADC_O_CTRL 0x00001F18U

Referenced by ADCRestoreTrims().

§ ADC_O_MODCTL

#define ADC_O_MODCTL 0x00001F1CU

Referenced by ADCSetInput().

§ ADC_O_INTCHCTL

#define ADC_O_INTCHCTL 0x00001F20U

§ ADC_O_STLTIM

#define ADC_O_STLTIM 0x00001F24U

§ ADC_O_CLKCFG

#define ADC_O_CLKCFG 0x00002000U

§ ADC_FSCTL0_TRIM0_W

#define ADC_FSCTL0_TRIM0_W 32U

§ ADC_FSCTL0_TRIM0_M

#define ADC_FSCTL0_TRIM0_M 0xFFFFFFFFU

§ ADC_FSCTL0_TRIM0_S

#define ADC_FSCTL0_TRIM0_S 0U

§ ADC_FSCTL1_TRIM1_W

#define ADC_FSCTL1_TRIM1_W 32U

§ ADC_FSCTL1_TRIM1_M

#define ADC_FSCTL1_TRIM1_M 0xFFFFFFFFU

§ ADC_FSCTL1_TRIM1_S

#define ADC_FSCTL1_TRIM1_S 0U

§ ADC_FSCTL2_TRIM2_W

#define ADC_FSCTL2_TRIM2_W 32U

§ ADC_FSCTL2_TRIM2_M

#define ADC_FSCTL2_TRIM2_M 0xFFFFFFFFU

§ ADC_FSCTL2_TRIM2_S

#define ADC_FSCTL2_TRIM2_S 0U

§ ADC_FSCTL3_TRIM3_W

#define ADC_FSCTL3_TRIM3_W 16U

§ ADC_FSCTL3_TRIM3_M

#define ADC_FSCTL3_TRIM3_M 0x0000FFFFU

§ ADC_FSCTL3_TRIM3_S

#define ADC_FSCTL3_TRIM3_S 0U

§ ADC_REFBUF_CFG_W

#define ADC_REFBUF_CFG_W 32U

§ ADC_REFBUF_CFG_M

#define ADC_REFBUF_CFG_M 0xFFFFFFFFU

§ ADC_REFBUF_CFG_S

#define ADC_REFBUF_CFG_S 0U

§ ADC_ATB_CTRL_W

#define ADC_ATB_CTRL_W 8U

§ ADC_ATB_CTRL_M

#define ADC_ATB_CTRL_M 0x000000FFU

§ ADC_ATB_CTRL_S

#define ADC_ATB_CTRL_S 0U

§ ADC_INTEVT0IDX_STAT_W

#define ADC_INTEVT0IDX_STAT_W 10U

§ ADC_INTEVT0IDX_STAT_M

#define ADC_INTEVT0IDX_STAT_M 0x000003FFU

§ ADC_INTEVT0IDX_STAT_S

#define ADC_INTEVT0IDX_STAT_S 0U

§ ADC_INTEVT0IDX_STAT_NO_INTR

#define ADC_INTEVT0IDX_STAT_NO_INTR 0x00000000U

§ ADC_INTEVT0IDX_STAT_OVIFG

#define ADC_INTEVT0IDX_STAT_OVIFG 0x00000001U

§ ADC_INTEVT0IDX_STAT_UVIFG

#define ADC_INTEVT0IDX_STAT_UVIFG 0x00000007U

§ ADC_INTEVT0IDX_STAT_TOVIFG

#define ADC_INTEVT0IDX_STAT_TOVIFG 0x00000002U

§ ADC_INTEVT0IDX_STAT_HIGHIFG

#define ADC_INTEVT0IDX_STAT_HIGHIFG 0x00000003U

§ ADC_INTEVT0IDX_STAT_LOWIFG

#define ADC_INTEVT0IDX_STAT_LOWIFG 0x00000004U

§ ADC_INTEVT0IDX_STAT_INIFG

#define ADC_INTEVT0IDX_STAT_INIFG 0x00000005U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG0

#define ADC_INTEVT0IDX_STAT_MEMRESIFG0 0x00000009U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG1

#define ADC_INTEVT0IDX_STAT_MEMRESIFG1 0x0000000AU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG2

#define ADC_INTEVT0IDX_STAT_MEMRESIFG2 0x0000000BU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG3

#define ADC_INTEVT0IDX_STAT_MEMRESIFG3 0x0000000CU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG4

#define ADC_INTEVT0IDX_STAT_MEMRESIFG4 0x0000000DU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG5

#define ADC_INTEVT0IDX_STAT_MEMRESIFG5 0x0000000EU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG6

#define ADC_INTEVT0IDX_STAT_MEMRESIFG6 0x0000000FU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG7

#define ADC_INTEVT0IDX_STAT_MEMRESIFG7 0x00000010U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG8

#define ADC_INTEVT0IDX_STAT_MEMRESIFG8 0x00000011U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG9

#define ADC_INTEVT0IDX_STAT_MEMRESIFG9 0x00000012U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG10

#define ADC_INTEVT0IDX_STAT_MEMRESIFG10 0x00000013U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG11

#define ADC_INTEVT0IDX_STAT_MEMRESIFG11 0x00000014U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG12

#define ADC_INTEVT0IDX_STAT_MEMRESIFG12 0x00000015U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG13

#define ADC_INTEVT0IDX_STAT_MEMRESIFG13 0x00000016U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG14

#define ADC_INTEVT0IDX_STAT_MEMRESIFG14 0x00000017U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG15

#define ADC_INTEVT0IDX_STAT_MEMRESIFG15 0x00000018U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG16

#define ADC_INTEVT0IDX_STAT_MEMRESIFG16 0x00000019U

§ ADC_INTEVT0IDX_STAT_MEMRESIFG17

#define ADC_INTEVT0IDX_STAT_MEMRESIFG17 0x0000001AU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG18

#define ADC_INTEVT0IDX_STAT_MEMRESIFG18 0x0000001BU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG19

#define ADC_INTEVT0IDX_STAT_MEMRESIFG19 0x0000001CU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG20

#define ADC_INTEVT0IDX_STAT_MEMRESIFG20 0x0000001DU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG21

#define ADC_INTEVT0IDX_STAT_MEMRESIFG21 0x0000001EU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG22

#define ADC_INTEVT0IDX_STAT_MEMRESIFG22 0x0000001FU

§ ADC_INTEVT0IDX_STAT_MEMRESIFG23

#define ADC_INTEVT0IDX_STAT_MEMRESIFG23 0x00000020U

§ ADC_INTEVT0IDX_STAT_DMADONE

#define ADC_INTEVT0IDX_STAT_DMADONE 0x00000006U

§ ADC_INTEVT0BM_OVIFG

#define ADC_INTEVT0BM_OVIFG 0x00000001U

§ ADC_INTEVT0BM_OVIFG_M

#define ADC_INTEVT0BM_OVIFG_M 0x00000001U

§ ADC_INTEVT0BM_OVIFG_S

#define ADC_INTEVT0BM_OVIFG_S 0U

§ ADC_INTEVT0BM_OVIFG_CLR

#define ADC_INTEVT0BM_OVIFG_CLR 0x00000000U

§ ADC_INTEVT0BM_OVIFG_SET

#define ADC_INTEVT0BM_OVIFG_SET 0x00000001U

§ ADC_INTEVT0BM_TOVIFG

#define ADC_INTEVT0BM_TOVIFG 0x00000002U

§ ADC_INTEVT0BM_TOVIFG_M

#define ADC_INTEVT0BM_TOVIFG_M 0x00000002U

§ ADC_INTEVT0BM_TOVIFG_S

#define ADC_INTEVT0BM_TOVIFG_S 1U

§ ADC_INTEVT0BM_TOVIFG_CLR

#define ADC_INTEVT0BM_TOVIFG_CLR 0x00000000U

§ ADC_INTEVT0BM_TOVIFG_SET

#define ADC_INTEVT0BM_TOVIFG_SET 0x00000002U

§ ADC_INTEVT0BM_HIFG

#define ADC_INTEVT0BM_HIFG 0x00000004U

§ ADC_INTEVT0BM_HIFG_M

#define ADC_INTEVT0BM_HIFG_M 0x00000004U

§ ADC_INTEVT0BM_HIFG_S

#define ADC_INTEVT0BM_HIFG_S 2U

§ ADC_INTEVT0BM_HIFG_CLR

#define ADC_INTEVT0BM_HIFG_CLR 0x00000000U

§ ADC_INTEVT0BM_HIFG_SET

#define ADC_INTEVT0BM_HIFG_SET 0x00000004U

§ ADC_INTEVT0BM_LOFG

#define ADC_INTEVT0BM_LOFG 0x00000008U

§ ADC_INTEVT0BM_LOFG_M

#define ADC_INTEVT0BM_LOFG_M 0x00000008U

§ ADC_INTEVT0BM_LOFG_S

#define ADC_INTEVT0BM_LOFG_S 3U

§ ADC_INTEVT0BM_LOFG_CLR

#define ADC_INTEVT0BM_LOFG_CLR 0x00000000U

§ ADC_INTEVT0BM_LOFG_SET

#define ADC_INTEVT0BM_LOFG_SET 0x00000008U

§ ADC_INTEVT0BM_INIFG

#define ADC_INTEVT0BM_INIFG 0x00000010U

§ ADC_INTEVT0BM_INIFG_M

#define ADC_INTEVT0BM_INIFG_M 0x00000010U

§ ADC_INTEVT0BM_INIFG_S

#define ADC_INTEVT0BM_INIFG_S 4U

§ ADC_INTEVT0BM_INIFG_CLR

#define ADC_INTEVT0BM_INIFG_CLR 0x00000000U

§ ADC_INTEVT0BM_INIFG_SET

#define ADC_INTEVT0BM_INIFG_SET 0x00000010U

§ ADC_INTEVT0BM_DMADONE

#define ADC_INTEVT0BM_DMADONE 0x00000020U

§ ADC_INTEVT0BM_DMADONE_M

#define ADC_INTEVT0BM_DMADONE_M 0x00000020U

§ ADC_INTEVT0BM_DMADONE_S

#define ADC_INTEVT0BM_DMADONE_S 5U

§ ADC_INTEVT0BM_DMADONE_CLR

#define ADC_INTEVT0BM_DMADONE_CLR 0x00000000U

§ ADC_INTEVT0BM_DMADONE_SET

#define ADC_INTEVT0BM_DMADONE_SET 0x00000020U

§ ADC_INTEVT0BM_UVIFG

#define ADC_INTEVT0BM_UVIFG 0x00000040U

§ ADC_INTEVT0BM_UVIFG_M

#define ADC_INTEVT0BM_UVIFG_M 0x00000040U

§ ADC_INTEVT0BM_UVIFG_S

#define ADC_INTEVT0BM_UVIFG_S 6U

§ ADC_INTEVT0BM_UVIFG_CLR

#define ADC_INTEVT0BM_UVIFG_CLR 0x00000000U

§ ADC_INTEVT0BM_UVIFG_SET

#define ADC_INTEVT0BM_UVIFG_SET 0x00000040U

§ ADC_INTEVT0BM_MEMRESIFG0

#define ADC_INTEVT0BM_MEMRESIFG0 0x00000100U

§ ADC_INTEVT0BM_MEMRESIFG0_M

#define ADC_INTEVT0BM_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT0BM_MEMRESIFG0_S

#define ADC_INTEVT0BM_MEMRESIFG0_S 8U

§ ADC_INTEVT0BM_MEMRESIFG0_CLR

#define ADC_INTEVT0BM_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG0_SET

#define ADC_INTEVT0BM_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT0BM_MEMRESIFG1

#define ADC_INTEVT0BM_MEMRESIFG1 0x00000200U

§ ADC_INTEVT0BM_MEMRESIFG1_M

#define ADC_INTEVT0BM_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT0BM_MEMRESIFG1_S

#define ADC_INTEVT0BM_MEMRESIFG1_S 9U

§ ADC_INTEVT0BM_MEMRESIFG1_CLR

#define ADC_INTEVT0BM_MEMRESIFG1_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG1_SET

#define ADC_INTEVT0BM_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT0BM_MEMRESIFG2

#define ADC_INTEVT0BM_MEMRESIFG2 0x00000400U

§ ADC_INTEVT0BM_MEMRESIFG2_M

#define ADC_INTEVT0BM_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT0BM_MEMRESIFG2_S

#define ADC_INTEVT0BM_MEMRESIFG2_S 10U

§ ADC_INTEVT0BM_MEMRESIFG2_CLR

#define ADC_INTEVT0BM_MEMRESIFG2_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG2_SET

#define ADC_INTEVT0BM_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT0BM_MEMRESIFG3

#define ADC_INTEVT0BM_MEMRESIFG3 0x00000800U

§ ADC_INTEVT0BM_MEMRESIFG3_M

#define ADC_INTEVT0BM_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT0BM_MEMRESIFG3_S

#define ADC_INTEVT0BM_MEMRESIFG3_S 11U

§ ADC_INTEVT0BM_MEMRESIFG3_CLR

#define ADC_INTEVT0BM_MEMRESIFG3_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG3_SET

#define ADC_INTEVT0BM_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT0BM_MEMRESIFG4

#define ADC_INTEVT0BM_MEMRESIFG4 0x00001000U

§ ADC_INTEVT0BM_MEMRESIFG4_M

#define ADC_INTEVT0BM_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT0BM_MEMRESIFG4_S

#define ADC_INTEVT0BM_MEMRESIFG4_S 12U

§ ADC_INTEVT0BM_MEMRESIFG4_CLR

#define ADC_INTEVT0BM_MEMRESIFG4_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG4_SET

#define ADC_INTEVT0BM_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT0BM_MEMRESIFG5

#define ADC_INTEVT0BM_MEMRESIFG5 0x00002000U

§ ADC_INTEVT0BM_MEMRESIFG5_M

#define ADC_INTEVT0BM_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT0BM_MEMRESIFG5_S

#define ADC_INTEVT0BM_MEMRESIFG5_S 13U

§ ADC_INTEVT0BM_MEMRESIFG5_CLR

#define ADC_INTEVT0BM_MEMRESIFG5_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG5_SET

#define ADC_INTEVT0BM_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT0BM_MEMRESIFG6

#define ADC_INTEVT0BM_MEMRESIFG6 0x00004000U

§ ADC_INTEVT0BM_MEMRESIFG6_M

#define ADC_INTEVT0BM_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT0BM_MEMRESIFG6_S

#define ADC_INTEVT0BM_MEMRESIFG6_S 14U

§ ADC_INTEVT0BM_MEMRESIFG6_CLR

#define ADC_INTEVT0BM_MEMRESIFG6_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG6_SET

#define ADC_INTEVT0BM_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT0BM_MEMRESIFG7

#define ADC_INTEVT0BM_MEMRESIFG7 0x00008000U

§ ADC_INTEVT0BM_MEMRESIFG7_M

#define ADC_INTEVT0BM_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT0BM_MEMRESIFG7_S

#define ADC_INTEVT0BM_MEMRESIFG7_S 15U

§ ADC_INTEVT0BM_MEMRESIFG7_CLR

#define ADC_INTEVT0BM_MEMRESIFG7_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG7_SET

#define ADC_INTEVT0BM_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT0BM_MEMRESIFG8

#define ADC_INTEVT0BM_MEMRESIFG8 0x00010000U

§ ADC_INTEVT0BM_MEMRESIFG8_M

#define ADC_INTEVT0BM_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT0BM_MEMRESIFG8_S

#define ADC_INTEVT0BM_MEMRESIFG8_S 16U

§ ADC_INTEVT0BM_MEMRESIFG8_CLR

#define ADC_INTEVT0BM_MEMRESIFG8_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG8_SET

#define ADC_INTEVT0BM_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT0BM_MEMRESIFG9

#define ADC_INTEVT0BM_MEMRESIFG9 0x00020000U

§ ADC_INTEVT0BM_MEMRESIFG9_M

#define ADC_INTEVT0BM_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT0BM_MEMRESIFG9_S

#define ADC_INTEVT0BM_MEMRESIFG9_S 17U

§ ADC_INTEVT0BM_MEMRESIFG9_CLR

#define ADC_INTEVT0BM_MEMRESIFG9_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG9_SET

#define ADC_INTEVT0BM_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT0BM_MEMRESIFG10

#define ADC_INTEVT0BM_MEMRESIFG10 0x00040000U

§ ADC_INTEVT0BM_MEMRESIFG10_M

#define ADC_INTEVT0BM_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT0BM_MEMRESIFG10_S

#define ADC_INTEVT0BM_MEMRESIFG10_S 18U

§ ADC_INTEVT0BM_MEMRESIFG10_CLR

#define ADC_INTEVT0BM_MEMRESIFG10_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG10_SET

#define ADC_INTEVT0BM_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT0BM_MEMRESIFG11

#define ADC_INTEVT0BM_MEMRESIFG11 0x00080000U

§ ADC_INTEVT0BM_MEMRESIFG11_M

#define ADC_INTEVT0BM_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT0BM_MEMRESIFG11_S

#define ADC_INTEVT0BM_MEMRESIFG11_S 19U

§ ADC_INTEVT0BM_MEMRESIFG11_CLR

#define ADC_INTEVT0BM_MEMRESIFG11_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG11_SET

#define ADC_INTEVT0BM_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT0BM_MEMRESIFG12

#define ADC_INTEVT0BM_MEMRESIFG12 0x00100000U

§ ADC_INTEVT0BM_MEMRESIFG12_M

#define ADC_INTEVT0BM_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT0BM_MEMRESIFG12_S

#define ADC_INTEVT0BM_MEMRESIFG12_S 20U

§ ADC_INTEVT0BM_MEMRESIFG12_CLR

#define ADC_INTEVT0BM_MEMRESIFG12_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG12_SET

#define ADC_INTEVT0BM_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT0BM_MEMRESIFG13

#define ADC_INTEVT0BM_MEMRESIFG13 0x00200000U

§ ADC_INTEVT0BM_MEMRESIFG13_M

#define ADC_INTEVT0BM_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT0BM_MEMRESIFG13_S

#define ADC_INTEVT0BM_MEMRESIFG13_S 21U

§ ADC_INTEVT0BM_MEMRESIFG13_CLR

#define ADC_INTEVT0BM_MEMRESIFG13_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG13_SET

#define ADC_INTEVT0BM_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT0BM_MEMRESIFG14

#define ADC_INTEVT0BM_MEMRESIFG14 0x00400000U

§ ADC_INTEVT0BM_MEMRESIFG14_M

#define ADC_INTEVT0BM_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT0BM_MEMRESIFG14_S

#define ADC_INTEVT0BM_MEMRESIFG14_S 22U

§ ADC_INTEVT0BM_MEMRESIFG14_CLR

#define ADC_INTEVT0BM_MEMRESIFG14_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG14_SET

#define ADC_INTEVT0BM_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT0BM_MEMRESIFG15

#define ADC_INTEVT0BM_MEMRESIFG15 0x00800000U

§ ADC_INTEVT0BM_MEMRESIFG15_M

#define ADC_INTEVT0BM_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT0BM_MEMRESIFG15_S

#define ADC_INTEVT0BM_MEMRESIFG15_S 23U

§ ADC_INTEVT0BM_MEMRESIFG15_CLR

#define ADC_INTEVT0BM_MEMRESIFG15_CLR 0x00000000U

§ ADC_INTEVT0BM_MEMRESIFG15_SET

#define ADC_INTEVT0BM_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT0RIS_OVIFG

#define ADC_INTEVT0RIS_OVIFG 0x00000001U

§ ADC_INTEVT0RIS_OVIFG_M

#define ADC_INTEVT0RIS_OVIFG_M 0x00000001U

§ ADC_INTEVT0RIS_OVIFG_S

#define ADC_INTEVT0RIS_OVIFG_S 0U

§ ADC_INTEVT0RIS_OVIFG_CLR

#define ADC_INTEVT0RIS_OVIFG_CLR 0x00000000U

§ ADC_INTEVT0RIS_OVIFG_SET

#define ADC_INTEVT0RIS_OVIFG_SET 0x00000001U

§ ADC_INTEVT0RIS_TOVIFG

#define ADC_INTEVT0RIS_TOVIFG 0x00000002U

§ ADC_INTEVT0RIS_TOVIFG_M

#define ADC_INTEVT0RIS_TOVIFG_M 0x00000002U

§ ADC_INTEVT0RIS_TOVIFG_S

#define ADC_INTEVT0RIS_TOVIFG_S 1U

§ ADC_INTEVT0RIS_TOVIFG_CLR

#define ADC_INTEVT0RIS_TOVIFG_CLR 0x00000000U

§ ADC_INTEVT0RIS_TOVIFG_SET

#define ADC_INTEVT0RIS_TOVIFG_SET 0x00000002U

§ ADC_INTEVT0RIS_HIFG

#define ADC_INTEVT0RIS_HIFG 0x00000004U

§ ADC_INTEVT0RIS_HIFG_M

#define ADC_INTEVT0RIS_HIFG_M 0x00000004U

§ ADC_INTEVT0RIS_HIFG_S

#define ADC_INTEVT0RIS_HIFG_S 2U

§ ADC_INTEVT0RIS_HIFG_CLR

#define ADC_INTEVT0RIS_HIFG_CLR 0x00000000U

§ ADC_INTEVT0RIS_HIFG_SET

#define ADC_INTEVT0RIS_HIFG_SET 0x00000004U

§ ADC_INTEVT0RIS_LOFG

#define ADC_INTEVT0RIS_LOFG 0x00000008U

§ ADC_INTEVT0RIS_LOFG_M

#define ADC_INTEVT0RIS_LOFG_M 0x00000008U

§ ADC_INTEVT0RIS_LOFG_S

#define ADC_INTEVT0RIS_LOFG_S 3U

§ ADC_INTEVT0RIS_LOFG_CLR

#define ADC_INTEVT0RIS_LOFG_CLR 0x00000000U

§ ADC_INTEVT0RIS_LOFG_SET

#define ADC_INTEVT0RIS_LOFG_SET 0x00000008U

§ ADC_INTEVT0RIS_INIFG

#define ADC_INTEVT0RIS_INIFG 0x00000010U

§ ADC_INTEVT0RIS_INIFG_M

#define ADC_INTEVT0RIS_INIFG_M 0x00000010U

§ ADC_INTEVT0RIS_INIFG_S

#define ADC_INTEVT0RIS_INIFG_S 4U

§ ADC_INTEVT0RIS_INIFG_CLR

#define ADC_INTEVT0RIS_INIFG_CLR 0x00000000U

§ ADC_INTEVT0RIS_INIFG_SET

#define ADC_INTEVT0RIS_INIFG_SET 0x00000010U

§ ADC_INTEVT0RIS_DMADONE

#define ADC_INTEVT0RIS_DMADONE 0x00000020U

§ ADC_INTEVT0RIS_DMADONE_M

#define ADC_INTEVT0RIS_DMADONE_M 0x00000020U

§ ADC_INTEVT0RIS_DMADONE_S

#define ADC_INTEVT0RIS_DMADONE_S 5U

§ ADC_INTEVT0RIS_DMADONE_CLR

#define ADC_INTEVT0RIS_DMADONE_CLR 0x00000000U

§ ADC_INTEVT0RIS_DMADONE_SET

#define ADC_INTEVT0RIS_DMADONE_SET 0x00000020U

§ ADC_INTEVT0RIS_UVIFG

#define ADC_INTEVT0RIS_UVIFG 0x00000040U

§ ADC_INTEVT0RIS_UVIFG_M

#define ADC_INTEVT0RIS_UVIFG_M 0x00000040U

§ ADC_INTEVT0RIS_UVIFG_S

#define ADC_INTEVT0RIS_UVIFG_S 6U

§ ADC_INTEVT0RIS_UVIFG_CLR

#define ADC_INTEVT0RIS_UVIFG_CLR 0x00000000U

§ ADC_INTEVT0RIS_UVIFG_SET

#define ADC_INTEVT0RIS_UVIFG_SET 0x00000040U

§ ADC_INTEVT0RIS_MEMRESIFG0

#define ADC_INTEVT0RIS_MEMRESIFG0 0x00000100U

§ ADC_INTEVT0RIS_MEMRESIFG0_M

#define ADC_INTEVT0RIS_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT0RIS_MEMRESIFG0_S

#define ADC_INTEVT0RIS_MEMRESIFG0_S 8U

§ ADC_INTEVT0RIS_MEMRESIFG0_CLR

#define ADC_INTEVT0RIS_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG0_SET

#define ADC_INTEVT0RIS_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT0RIS_MEMRESIFG1

#define ADC_INTEVT0RIS_MEMRESIFG1 0x00000200U

§ ADC_INTEVT0RIS_MEMRESIFG1_M

#define ADC_INTEVT0RIS_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT0RIS_MEMRESIFG1_S

#define ADC_INTEVT0RIS_MEMRESIFG1_S 9U

§ ADC_INTEVT0RIS_MEMRESIFG1_CLR

#define ADC_INTEVT0RIS_MEMRESIFG1_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG1_SET

#define ADC_INTEVT0RIS_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT0RIS_MEMRESIFG2

#define ADC_INTEVT0RIS_MEMRESIFG2 0x00000400U

§ ADC_INTEVT0RIS_MEMRESIFG2_M

#define ADC_INTEVT0RIS_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT0RIS_MEMRESIFG2_S

#define ADC_INTEVT0RIS_MEMRESIFG2_S 10U

§ ADC_INTEVT0RIS_MEMRESIFG2_CLR

#define ADC_INTEVT0RIS_MEMRESIFG2_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG2_SET

#define ADC_INTEVT0RIS_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT0RIS_MEMRESIFG3

#define ADC_INTEVT0RIS_MEMRESIFG3 0x00000800U

§ ADC_INTEVT0RIS_MEMRESIFG3_M

#define ADC_INTEVT0RIS_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT0RIS_MEMRESIFG3_S

#define ADC_INTEVT0RIS_MEMRESIFG3_S 11U

§ ADC_INTEVT0RIS_MEMRESIFG3_CLR

#define ADC_INTEVT0RIS_MEMRESIFG3_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG3_SET

#define ADC_INTEVT0RIS_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT0RIS_MEMRESIFG4

#define ADC_INTEVT0RIS_MEMRESIFG4 0x00001000U

§ ADC_INTEVT0RIS_MEMRESIFG4_M

#define ADC_INTEVT0RIS_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT0RIS_MEMRESIFG4_S

#define ADC_INTEVT0RIS_MEMRESIFG4_S 12U

§ ADC_INTEVT0RIS_MEMRESIFG4_CLR

#define ADC_INTEVT0RIS_MEMRESIFG4_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG4_SET

#define ADC_INTEVT0RIS_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT0RIS_MEMRESIFG5

#define ADC_INTEVT0RIS_MEMRESIFG5 0x00002000U

§ ADC_INTEVT0RIS_MEMRESIFG5_M

#define ADC_INTEVT0RIS_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT0RIS_MEMRESIFG5_S

#define ADC_INTEVT0RIS_MEMRESIFG5_S 13U

§ ADC_INTEVT0RIS_MEMRESIFG5_CLR

#define ADC_INTEVT0RIS_MEMRESIFG5_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG5_SET

#define ADC_INTEVT0RIS_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT0RIS_MEMRESIFG6

#define ADC_INTEVT0RIS_MEMRESIFG6 0x00004000U

§ ADC_INTEVT0RIS_MEMRESIFG6_M

#define ADC_INTEVT0RIS_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT0RIS_MEMRESIFG6_S

#define ADC_INTEVT0RIS_MEMRESIFG6_S 14U

§ ADC_INTEVT0RIS_MEMRESIFG6_CLR

#define ADC_INTEVT0RIS_MEMRESIFG6_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG6_SET

#define ADC_INTEVT0RIS_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT0RIS_MEMRESIFG7

#define ADC_INTEVT0RIS_MEMRESIFG7 0x00008000U

§ ADC_INTEVT0RIS_MEMRESIFG7_M

#define ADC_INTEVT0RIS_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT0RIS_MEMRESIFG7_S

#define ADC_INTEVT0RIS_MEMRESIFG7_S 15U

§ ADC_INTEVT0RIS_MEMRESIFG7_CLR

#define ADC_INTEVT0RIS_MEMRESIFG7_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG7_SET

#define ADC_INTEVT0RIS_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT0RIS_MEMRESIFG8

#define ADC_INTEVT0RIS_MEMRESIFG8 0x00010000U

§ ADC_INTEVT0RIS_MEMRESIFG8_M

#define ADC_INTEVT0RIS_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT0RIS_MEMRESIFG8_S

#define ADC_INTEVT0RIS_MEMRESIFG8_S 16U

§ ADC_INTEVT0RIS_MEMRESIFG8_CLR

#define ADC_INTEVT0RIS_MEMRESIFG8_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG8_SET

#define ADC_INTEVT0RIS_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT0RIS_MEMRESIFG9

#define ADC_INTEVT0RIS_MEMRESIFG9 0x00020000U

§ ADC_INTEVT0RIS_MEMRESIFG9_M

#define ADC_INTEVT0RIS_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT0RIS_MEMRESIFG9_S

#define ADC_INTEVT0RIS_MEMRESIFG9_S 17U

§ ADC_INTEVT0RIS_MEMRESIFG9_CLR

#define ADC_INTEVT0RIS_MEMRESIFG9_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG9_SET

#define ADC_INTEVT0RIS_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT0RIS_MEMRESIFG10

#define ADC_INTEVT0RIS_MEMRESIFG10 0x00040000U

§ ADC_INTEVT0RIS_MEMRESIFG10_M

#define ADC_INTEVT0RIS_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT0RIS_MEMRESIFG10_S

#define ADC_INTEVT0RIS_MEMRESIFG10_S 18U

§ ADC_INTEVT0RIS_MEMRESIFG10_CLR

#define ADC_INTEVT0RIS_MEMRESIFG10_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG10_SET

#define ADC_INTEVT0RIS_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT0RIS_MEMRESIFG11

#define ADC_INTEVT0RIS_MEMRESIFG11 0x00080000U

§ ADC_INTEVT0RIS_MEMRESIFG11_M

#define ADC_INTEVT0RIS_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT0RIS_MEMRESIFG11_S

#define ADC_INTEVT0RIS_MEMRESIFG11_S 19U

§ ADC_INTEVT0RIS_MEMRESIFG11_CLR

#define ADC_INTEVT0RIS_MEMRESIFG11_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG11_SET

#define ADC_INTEVT0RIS_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT0RIS_MEMRESIFG12

#define ADC_INTEVT0RIS_MEMRESIFG12 0x00100000U

§ ADC_INTEVT0RIS_MEMRESIFG12_M

#define ADC_INTEVT0RIS_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT0RIS_MEMRESIFG12_S

#define ADC_INTEVT0RIS_MEMRESIFG12_S 20U

§ ADC_INTEVT0RIS_MEMRESIFG12_CLR

#define ADC_INTEVT0RIS_MEMRESIFG12_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG12_SET

#define ADC_INTEVT0RIS_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT0RIS_MEMRESIFG13

#define ADC_INTEVT0RIS_MEMRESIFG13 0x00200000U

§ ADC_INTEVT0RIS_MEMRESIFG13_M

#define ADC_INTEVT0RIS_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT0RIS_MEMRESIFG13_S

#define ADC_INTEVT0RIS_MEMRESIFG13_S 21U

§ ADC_INTEVT0RIS_MEMRESIFG13_CLR

#define ADC_INTEVT0RIS_MEMRESIFG13_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG13_SET

#define ADC_INTEVT0RIS_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT0RIS_MEMRESIFG14

#define ADC_INTEVT0RIS_MEMRESIFG14 0x00400000U

§ ADC_INTEVT0RIS_MEMRESIFG14_M

#define ADC_INTEVT0RIS_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT0RIS_MEMRESIFG14_S

#define ADC_INTEVT0RIS_MEMRESIFG14_S 22U

§ ADC_INTEVT0RIS_MEMRESIFG14_CLR

#define ADC_INTEVT0RIS_MEMRESIFG14_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG14_SET

#define ADC_INTEVT0RIS_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT0RIS_MEMRESIFG15

#define ADC_INTEVT0RIS_MEMRESIFG15 0x00800000U

§ ADC_INTEVT0RIS_MEMRESIFG15_M

#define ADC_INTEVT0RIS_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT0RIS_MEMRESIFG15_S

#define ADC_INTEVT0RIS_MEMRESIFG15_S 23U

§ ADC_INTEVT0RIS_MEMRESIFG15_CLR

#define ADC_INTEVT0RIS_MEMRESIFG15_CLR 0x00000000U

§ ADC_INTEVT0RIS_MEMRESIFG15_SET

#define ADC_INTEVT0RIS_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT0MIS_OVIFG

#define ADC_INTEVT0MIS_OVIFG 0x00000001U

§ ADC_INTEVT0MIS_OVIFG_M

#define ADC_INTEVT0MIS_OVIFG_M 0x00000001U

§ ADC_INTEVT0MIS_OVIFG_S

#define ADC_INTEVT0MIS_OVIFG_S 0U

§ ADC_INTEVT0MIS_OVIFG_CLR

#define ADC_INTEVT0MIS_OVIFG_CLR 0x00000000U

§ ADC_INTEVT0MIS_OVIFG_SET

#define ADC_INTEVT0MIS_OVIFG_SET 0x00000001U

§ ADC_INTEVT0MIS_TOVIFG

#define ADC_INTEVT0MIS_TOVIFG 0x00000002U

§ ADC_INTEVT0MIS_TOVIFG_M

#define ADC_INTEVT0MIS_TOVIFG_M 0x00000002U

§ ADC_INTEVT0MIS_TOVIFG_S

#define ADC_INTEVT0MIS_TOVIFG_S 1U

§ ADC_INTEVT0MIS_TOVIFG_CLR

#define ADC_INTEVT0MIS_TOVIFG_CLR 0x00000000U

§ ADC_INTEVT0MIS_TOVIFG_SET

#define ADC_INTEVT0MIS_TOVIFG_SET 0x00000002U

§ ADC_INTEVT0MIS_HIFG

#define ADC_INTEVT0MIS_HIFG 0x00000004U

§ ADC_INTEVT0MIS_HIFG_M

#define ADC_INTEVT0MIS_HIFG_M 0x00000004U

§ ADC_INTEVT0MIS_HIFG_S

#define ADC_INTEVT0MIS_HIFG_S 2U

§ ADC_INTEVT0MIS_HIFG_CLR

#define ADC_INTEVT0MIS_HIFG_CLR 0x00000000U

§ ADC_INTEVT0MIS_HIFG_SET

#define ADC_INTEVT0MIS_HIFG_SET 0x00000004U

§ ADC_INTEVT0MIS_LOFG

#define ADC_INTEVT0MIS_LOFG 0x00000008U

§ ADC_INTEVT0MIS_LOFG_M

#define ADC_INTEVT0MIS_LOFG_M 0x00000008U

§ ADC_INTEVT0MIS_LOFG_S

#define ADC_INTEVT0MIS_LOFG_S 3U

§ ADC_INTEVT0MIS_LOFG_CLR

#define ADC_INTEVT0MIS_LOFG_CLR 0x00000000U

§ ADC_INTEVT0MIS_LOFG_SET

#define ADC_INTEVT0MIS_LOFG_SET 0x00000008U

§ ADC_INTEVT0MIS_INIFG

#define ADC_INTEVT0MIS_INIFG 0x00000010U

§ ADC_INTEVT0MIS_INIFG_M

#define ADC_INTEVT0MIS_INIFG_M 0x00000010U

§ ADC_INTEVT0MIS_INIFG_S

#define ADC_INTEVT0MIS_INIFG_S 4U

§ ADC_INTEVT0MIS_INIFG_CLR

#define ADC_INTEVT0MIS_INIFG_CLR 0x00000000U

§ ADC_INTEVT0MIS_INIFG_SET

#define ADC_INTEVT0MIS_INIFG_SET 0x00000010U

§ ADC_INTEVT0MIS_DMADONE

#define ADC_INTEVT0MIS_DMADONE 0x00000020U

§ ADC_INTEVT0MIS_DMADONE_M

#define ADC_INTEVT0MIS_DMADONE_M 0x00000020U

§ ADC_INTEVT0MIS_DMADONE_S

#define ADC_INTEVT0MIS_DMADONE_S 5U

§ ADC_INTEVT0MIS_DMADONE_CLR

#define ADC_INTEVT0MIS_DMADONE_CLR 0x00000000U

§ ADC_INTEVT0MIS_DMADONE_SET

#define ADC_INTEVT0MIS_DMADONE_SET 0x00000020U

§ ADC_INTEVT0MIS_UVIFG

#define ADC_INTEVT0MIS_UVIFG 0x00000040U

§ ADC_INTEVT0MIS_UVIFG_M

#define ADC_INTEVT0MIS_UVIFG_M 0x00000040U

§ ADC_INTEVT0MIS_UVIFG_S

#define ADC_INTEVT0MIS_UVIFG_S 6U

§ ADC_INTEVT0MIS_UVIFG_CLR

#define ADC_INTEVT0MIS_UVIFG_CLR 0x00000000U

§ ADC_INTEVT0MIS_UVIFG_SET

#define ADC_INTEVT0MIS_UVIFG_SET 0x00000040U

§ ADC_INTEVT0MIS_MEMRESIFG0

#define ADC_INTEVT0MIS_MEMRESIFG0 0x00000100U

§ ADC_INTEVT0MIS_MEMRESIFG0_M

#define ADC_INTEVT0MIS_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT0MIS_MEMRESIFG0_S

#define ADC_INTEVT0MIS_MEMRESIFG0_S 8U

§ ADC_INTEVT0MIS_MEMRESIFG0_CLR

#define ADC_INTEVT0MIS_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG0_SET

#define ADC_INTEVT0MIS_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT0MIS_MEMRESIFG1

#define ADC_INTEVT0MIS_MEMRESIFG1 0x00000200U

§ ADC_INTEVT0MIS_MEMRESIFG1_M

#define ADC_INTEVT0MIS_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT0MIS_MEMRESIFG1_S

#define ADC_INTEVT0MIS_MEMRESIFG1_S 9U

§ ADC_INTEVT0MIS_MEMRESIFG1_CLR

#define ADC_INTEVT0MIS_MEMRESIFG1_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG1_SET

#define ADC_INTEVT0MIS_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT0MIS_MEMRESIFG2

#define ADC_INTEVT0MIS_MEMRESIFG2 0x00000400U

§ ADC_INTEVT0MIS_MEMRESIFG2_M

#define ADC_INTEVT0MIS_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT0MIS_MEMRESIFG2_S

#define ADC_INTEVT0MIS_MEMRESIFG2_S 10U

§ ADC_INTEVT0MIS_MEMRESIFG2_CLR

#define ADC_INTEVT0MIS_MEMRESIFG2_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG2_SET

#define ADC_INTEVT0MIS_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT0MIS_MEMRESIFG3

#define ADC_INTEVT0MIS_MEMRESIFG3 0x00000800U

§ ADC_INTEVT0MIS_MEMRESIFG3_M

#define ADC_INTEVT0MIS_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT0MIS_MEMRESIFG3_S

#define ADC_INTEVT0MIS_MEMRESIFG3_S 11U

§ ADC_INTEVT0MIS_MEMRESIFG3_CLR

#define ADC_INTEVT0MIS_MEMRESIFG3_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG3_SET

#define ADC_INTEVT0MIS_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT0MIS_MEMRESIFG4

#define ADC_INTEVT0MIS_MEMRESIFG4 0x00001000U

§ ADC_INTEVT0MIS_MEMRESIFG4_M

#define ADC_INTEVT0MIS_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT0MIS_MEMRESIFG4_S

#define ADC_INTEVT0MIS_MEMRESIFG4_S 12U

§ ADC_INTEVT0MIS_MEMRESIFG4_CLR

#define ADC_INTEVT0MIS_MEMRESIFG4_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG4_SET

#define ADC_INTEVT0MIS_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT0MIS_MEMRESIFG5

#define ADC_INTEVT0MIS_MEMRESIFG5 0x00002000U

§ ADC_INTEVT0MIS_MEMRESIFG5_M

#define ADC_INTEVT0MIS_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT0MIS_MEMRESIFG5_S

#define ADC_INTEVT0MIS_MEMRESIFG5_S 13U

§ ADC_INTEVT0MIS_MEMRESIFG5_CLR

#define ADC_INTEVT0MIS_MEMRESIFG5_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG5_SET

#define ADC_INTEVT0MIS_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT0MIS_MEMRESIFG6

#define ADC_INTEVT0MIS_MEMRESIFG6 0x00004000U

§ ADC_INTEVT0MIS_MEMRESIFG6_M

#define ADC_INTEVT0MIS_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT0MIS_MEMRESIFG6_S

#define ADC_INTEVT0MIS_MEMRESIFG6_S 14U

§ ADC_INTEVT0MIS_MEMRESIFG6_CLR

#define ADC_INTEVT0MIS_MEMRESIFG6_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG6_SET

#define ADC_INTEVT0MIS_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT0MIS_MEMRESIFG7

#define ADC_INTEVT0MIS_MEMRESIFG7 0x00008000U

§ ADC_INTEVT0MIS_MEMRESIFG7_M

#define ADC_INTEVT0MIS_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT0MIS_MEMRESIFG7_S

#define ADC_INTEVT0MIS_MEMRESIFG7_S 15U

§ ADC_INTEVT0MIS_MEMRESIFG7_CLR

#define ADC_INTEVT0MIS_MEMRESIFG7_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG7_SET

#define ADC_INTEVT0MIS_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT0MIS_MEMRESIFG8

#define ADC_INTEVT0MIS_MEMRESIFG8 0x00010000U

§ ADC_INTEVT0MIS_MEMRESIFG8_M

#define ADC_INTEVT0MIS_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT0MIS_MEMRESIFG8_S

#define ADC_INTEVT0MIS_MEMRESIFG8_S 16U

§ ADC_INTEVT0MIS_MEMRESIFG8_CLR

#define ADC_INTEVT0MIS_MEMRESIFG8_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG8_SET

#define ADC_INTEVT0MIS_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT0MIS_MEMRESIFG9

#define ADC_INTEVT0MIS_MEMRESIFG9 0x00020000U

§ ADC_INTEVT0MIS_MEMRESIFG9_M

#define ADC_INTEVT0MIS_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT0MIS_MEMRESIFG9_S

#define ADC_INTEVT0MIS_MEMRESIFG9_S 17U

§ ADC_INTEVT0MIS_MEMRESIFG9_CLR

#define ADC_INTEVT0MIS_MEMRESIFG9_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG9_SET

#define ADC_INTEVT0MIS_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT0MIS_MEMRESIFG10

#define ADC_INTEVT0MIS_MEMRESIFG10 0x00040000U

§ ADC_INTEVT0MIS_MEMRESIFG10_M

#define ADC_INTEVT0MIS_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT0MIS_MEMRESIFG10_S

#define ADC_INTEVT0MIS_MEMRESIFG10_S 18U

§ ADC_INTEVT0MIS_MEMRESIFG10_CLR

#define ADC_INTEVT0MIS_MEMRESIFG10_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG10_SET

#define ADC_INTEVT0MIS_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT0MIS_MEMRESIFG11

#define ADC_INTEVT0MIS_MEMRESIFG11 0x00080000U

§ ADC_INTEVT0MIS_MEMRESIFG11_M

#define ADC_INTEVT0MIS_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT0MIS_MEMRESIFG11_S

#define ADC_INTEVT0MIS_MEMRESIFG11_S 19U

§ ADC_INTEVT0MIS_MEMRESIFG11_CLR

#define ADC_INTEVT0MIS_MEMRESIFG11_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG11_SET

#define ADC_INTEVT0MIS_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT0MIS_MEMRESIFG12

#define ADC_INTEVT0MIS_MEMRESIFG12 0x00100000U

§ ADC_INTEVT0MIS_MEMRESIFG12_M

#define ADC_INTEVT0MIS_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT0MIS_MEMRESIFG12_S

#define ADC_INTEVT0MIS_MEMRESIFG12_S 20U

§ ADC_INTEVT0MIS_MEMRESIFG12_CLR

#define ADC_INTEVT0MIS_MEMRESIFG12_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG12_SET

#define ADC_INTEVT0MIS_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT0MIS_MEMRESIFG13

#define ADC_INTEVT0MIS_MEMRESIFG13 0x00200000U

§ ADC_INTEVT0MIS_MEMRESIFG13_M

#define ADC_INTEVT0MIS_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT0MIS_MEMRESIFG13_S

#define ADC_INTEVT0MIS_MEMRESIFG13_S 21U

§ ADC_INTEVT0MIS_MEMRESIFG13_CLR

#define ADC_INTEVT0MIS_MEMRESIFG13_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG13_SET

#define ADC_INTEVT0MIS_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT0MIS_MEMRESIFG14

#define ADC_INTEVT0MIS_MEMRESIFG14 0x00400000U

§ ADC_INTEVT0MIS_MEMRESIFG14_M

#define ADC_INTEVT0MIS_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT0MIS_MEMRESIFG14_S

#define ADC_INTEVT0MIS_MEMRESIFG14_S 22U

§ ADC_INTEVT0MIS_MEMRESIFG14_CLR

#define ADC_INTEVT0MIS_MEMRESIFG14_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG14_SET

#define ADC_INTEVT0MIS_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT0MIS_MEMRESIFG15

#define ADC_INTEVT0MIS_MEMRESIFG15 0x00800000U

§ ADC_INTEVT0MIS_MEMRESIFG15_M

#define ADC_INTEVT0MIS_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT0MIS_MEMRESIFG15_S

#define ADC_INTEVT0MIS_MEMRESIFG15_S 23U

§ ADC_INTEVT0MIS_MEMRESIFG15_CLR

#define ADC_INTEVT0MIS_MEMRESIFG15_CLR 0x00000000U

§ ADC_INTEVT0MIS_MEMRESIFG15_SET

#define ADC_INTEVT0MIS_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT0SET_OVIFG

#define ADC_INTEVT0SET_OVIFG 0x00000001U

§ ADC_INTEVT0SET_OVIFG_M

#define ADC_INTEVT0SET_OVIFG_M 0x00000001U

§ ADC_INTEVT0SET_OVIFG_S

#define ADC_INTEVT0SET_OVIFG_S 0U

§ ADC_INTEVT0SET_OVIFG_NO_EFFECT

#define ADC_INTEVT0SET_OVIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_OVIFG_SET

#define ADC_INTEVT0SET_OVIFG_SET 0x00000001U

§ ADC_INTEVT0SET_TOVIFG

#define ADC_INTEVT0SET_TOVIFG 0x00000002U

§ ADC_INTEVT0SET_TOVIFG_M

#define ADC_INTEVT0SET_TOVIFG_M 0x00000002U

§ ADC_INTEVT0SET_TOVIFG_S

#define ADC_INTEVT0SET_TOVIFG_S 1U

§ ADC_INTEVT0SET_TOVIFG_NO_EFFECT

#define ADC_INTEVT0SET_TOVIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_TOVIFG_SET

#define ADC_INTEVT0SET_TOVIFG_SET 0x00000002U

§ ADC_INTEVT0SET_HIFG

#define ADC_INTEVT0SET_HIFG 0x00000004U

§ ADC_INTEVT0SET_HIFG_M

#define ADC_INTEVT0SET_HIFG_M 0x00000004U

§ ADC_INTEVT0SET_HIFG_S

#define ADC_INTEVT0SET_HIFG_S 2U

§ ADC_INTEVT0SET_HIFG_NO_EFFECT

#define ADC_INTEVT0SET_HIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_HIFG_SET

#define ADC_INTEVT0SET_HIFG_SET 0x00000004U

§ ADC_INTEVT0SET_LOFG

#define ADC_INTEVT0SET_LOFG 0x00000008U

§ ADC_INTEVT0SET_LOFG_M

#define ADC_INTEVT0SET_LOFG_M 0x00000008U

§ ADC_INTEVT0SET_LOFG_S

#define ADC_INTEVT0SET_LOFG_S 3U

§ ADC_INTEVT0SET_LOFG_NO_EFFECT

#define ADC_INTEVT0SET_LOFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_LOFG_SET

#define ADC_INTEVT0SET_LOFG_SET 0x00000008U

§ ADC_INTEVT0SET_INIFG

#define ADC_INTEVT0SET_INIFG 0x00000010U

§ ADC_INTEVT0SET_INIFG_M

#define ADC_INTEVT0SET_INIFG_M 0x00000010U

§ ADC_INTEVT0SET_INIFG_S

#define ADC_INTEVT0SET_INIFG_S 4U

§ ADC_INTEVT0SET_INIFG_NO_EFFECT

#define ADC_INTEVT0SET_INIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_INIFG_SET

#define ADC_INTEVT0SET_INIFG_SET 0x00000010U

§ ADC_INTEVT0SET_DMADONE

#define ADC_INTEVT0SET_DMADONE 0x00000020U

§ ADC_INTEVT0SET_DMADONE_M

#define ADC_INTEVT0SET_DMADONE_M 0x00000020U

§ ADC_INTEVT0SET_DMADONE_S

#define ADC_INTEVT0SET_DMADONE_S 5U

§ ADC_INTEVT0SET_DMADONE_NO_EFFECT

#define ADC_INTEVT0SET_DMADONE_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_DMADONE_SET

#define ADC_INTEVT0SET_DMADONE_SET 0x00000020U

§ ADC_INTEVT0SET_UVIFG

#define ADC_INTEVT0SET_UVIFG 0x00000040U

§ ADC_INTEVT0SET_UVIFG_M

#define ADC_INTEVT0SET_UVIFG_M 0x00000040U

§ ADC_INTEVT0SET_UVIFG_S

#define ADC_INTEVT0SET_UVIFG_S 6U

§ ADC_INTEVT0SET_UVIFG_NO_EFFECT

#define ADC_INTEVT0SET_UVIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_UVIFG_SET

#define ADC_INTEVT0SET_UVIFG_SET 0x00000040U

§ ADC_INTEVT0SET_MEMRESIFG0

#define ADC_INTEVT0SET_MEMRESIFG0 0x00000100U

§ ADC_INTEVT0SET_MEMRESIFG0_M

#define ADC_INTEVT0SET_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT0SET_MEMRESIFG0_S

#define ADC_INTEVT0SET_MEMRESIFG0_S 8U

§ ADC_INTEVT0SET_MEMRESIFG0_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG0_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG0_SET

#define ADC_INTEVT0SET_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT0SET_MEMRESIFG1

#define ADC_INTEVT0SET_MEMRESIFG1 0x00000200U

§ ADC_INTEVT0SET_MEMRESIFG1_M

#define ADC_INTEVT0SET_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT0SET_MEMRESIFG1_S

#define ADC_INTEVT0SET_MEMRESIFG1_S 9U

§ ADC_INTEVT0SET_MEMRESIFG1_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG1_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG1_SET

#define ADC_INTEVT0SET_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT0SET_MEMRESIFG2

#define ADC_INTEVT0SET_MEMRESIFG2 0x00000400U

§ ADC_INTEVT0SET_MEMRESIFG2_M

#define ADC_INTEVT0SET_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT0SET_MEMRESIFG2_S

#define ADC_INTEVT0SET_MEMRESIFG2_S 10U

§ ADC_INTEVT0SET_MEMRESIFG2_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG2_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG2_SET

#define ADC_INTEVT0SET_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT0SET_MEMRESIFG3

#define ADC_INTEVT0SET_MEMRESIFG3 0x00000800U

§ ADC_INTEVT0SET_MEMRESIFG3_M

#define ADC_INTEVT0SET_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT0SET_MEMRESIFG3_S

#define ADC_INTEVT0SET_MEMRESIFG3_S 11U

§ ADC_INTEVT0SET_MEMRESIFG3_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG3_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG3_SET

#define ADC_INTEVT0SET_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT0SET_MEMRESIFG4

#define ADC_INTEVT0SET_MEMRESIFG4 0x00001000U

§ ADC_INTEVT0SET_MEMRESIFG4_M

#define ADC_INTEVT0SET_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT0SET_MEMRESIFG4_S

#define ADC_INTEVT0SET_MEMRESIFG4_S 12U

§ ADC_INTEVT0SET_MEMRESIFG4_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG4_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG4_SET

#define ADC_INTEVT0SET_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT0SET_MEMRESIFG5

#define ADC_INTEVT0SET_MEMRESIFG5 0x00002000U

§ ADC_INTEVT0SET_MEMRESIFG5_M

#define ADC_INTEVT0SET_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT0SET_MEMRESIFG5_S

#define ADC_INTEVT0SET_MEMRESIFG5_S 13U

§ ADC_INTEVT0SET_MEMRESIFG5_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG5_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG5_SET

#define ADC_INTEVT0SET_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT0SET_MEMRESIFG6

#define ADC_INTEVT0SET_MEMRESIFG6 0x00004000U

§ ADC_INTEVT0SET_MEMRESIFG6_M

#define ADC_INTEVT0SET_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT0SET_MEMRESIFG6_S

#define ADC_INTEVT0SET_MEMRESIFG6_S 14U

§ ADC_INTEVT0SET_MEMRESIFG6_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG6_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG6_SET

#define ADC_INTEVT0SET_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT0SET_MEMRESIFG7

#define ADC_INTEVT0SET_MEMRESIFG7 0x00008000U

§ ADC_INTEVT0SET_MEMRESIFG7_M

#define ADC_INTEVT0SET_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT0SET_MEMRESIFG7_S

#define ADC_INTEVT0SET_MEMRESIFG7_S 15U

§ ADC_INTEVT0SET_MEMRESIFG7_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG7_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG7_SET

#define ADC_INTEVT0SET_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT0SET_MEMRESIFG8

#define ADC_INTEVT0SET_MEMRESIFG8 0x00010000U

§ ADC_INTEVT0SET_MEMRESIFG8_M

#define ADC_INTEVT0SET_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT0SET_MEMRESIFG8_S

#define ADC_INTEVT0SET_MEMRESIFG8_S 16U

§ ADC_INTEVT0SET_MEMRESIFG8_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG8_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG8_SET

#define ADC_INTEVT0SET_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT0SET_MEMRESIFG9

#define ADC_INTEVT0SET_MEMRESIFG9 0x00020000U

§ ADC_INTEVT0SET_MEMRESIFG9_M

#define ADC_INTEVT0SET_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT0SET_MEMRESIFG9_S

#define ADC_INTEVT0SET_MEMRESIFG9_S 17U

§ ADC_INTEVT0SET_MEMRESIFG9_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG9_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG9_SET

#define ADC_INTEVT0SET_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT0SET_MEMRESIFG10

#define ADC_INTEVT0SET_MEMRESIFG10 0x00040000U

§ ADC_INTEVT0SET_MEMRESIFG10_M

#define ADC_INTEVT0SET_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT0SET_MEMRESIFG10_S

#define ADC_INTEVT0SET_MEMRESIFG10_S 18U

§ ADC_INTEVT0SET_MEMRESIFG10_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG10_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG10_SET

#define ADC_INTEVT0SET_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT0SET_MEMRESIFG11

#define ADC_INTEVT0SET_MEMRESIFG11 0x00080000U

§ ADC_INTEVT0SET_MEMRESIFG11_M

#define ADC_INTEVT0SET_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT0SET_MEMRESIFG11_S

#define ADC_INTEVT0SET_MEMRESIFG11_S 19U

§ ADC_INTEVT0SET_MEMRESIFG11_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG11_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG11_SET

#define ADC_INTEVT0SET_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT0SET_MEMRESIFG12

#define ADC_INTEVT0SET_MEMRESIFG12 0x00100000U

§ ADC_INTEVT0SET_MEMRESIFG12_M

#define ADC_INTEVT0SET_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT0SET_MEMRESIFG12_S

#define ADC_INTEVT0SET_MEMRESIFG12_S 20U

§ ADC_INTEVT0SET_MEMRESIFG12_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG12_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG12_SET

#define ADC_INTEVT0SET_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT0SET_MEMRESIFG13

#define ADC_INTEVT0SET_MEMRESIFG13 0x00200000U

§ ADC_INTEVT0SET_MEMRESIFG13_M

#define ADC_INTEVT0SET_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT0SET_MEMRESIFG13_S

#define ADC_INTEVT0SET_MEMRESIFG13_S 21U

§ ADC_INTEVT0SET_MEMRESIFG13_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG13_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG13_SET

#define ADC_INTEVT0SET_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT0SET_MEMRESIFG14

#define ADC_INTEVT0SET_MEMRESIFG14 0x00400000U

§ ADC_INTEVT0SET_MEMRESIFG14_M

#define ADC_INTEVT0SET_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT0SET_MEMRESIFG14_S

#define ADC_INTEVT0SET_MEMRESIFG14_S 22U

§ ADC_INTEVT0SET_MEMRESIFG14_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG14_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG14_SET

#define ADC_INTEVT0SET_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT0SET_MEMRESIFG15

#define ADC_INTEVT0SET_MEMRESIFG15 0x00800000U

§ ADC_INTEVT0SET_MEMRESIFG15_M

#define ADC_INTEVT0SET_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT0SET_MEMRESIFG15_S

#define ADC_INTEVT0SET_MEMRESIFG15_S 23U

§ ADC_INTEVT0SET_MEMRESIFG15_NO_EFFECT

#define ADC_INTEVT0SET_MEMRESIFG15_NO_EFFECT 0x00000000U

§ ADC_INTEVT0SET_MEMRESIFG15_SET

#define ADC_INTEVT0SET_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT0CLR_OVIFG

#define ADC_INTEVT0CLR_OVIFG 0x00000001U

§ ADC_INTEVT0CLR_OVIFG_M

#define ADC_INTEVT0CLR_OVIFG_M 0x00000001U

§ ADC_INTEVT0CLR_OVIFG_S

#define ADC_INTEVT0CLR_OVIFG_S 0U

§ ADC_INTEVT0CLR_OVIFG_NO_EFFECT

#define ADC_INTEVT0CLR_OVIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_OVIFG_CLR

#define ADC_INTEVT0CLR_OVIFG_CLR 0x00000001U

§ ADC_INTEVT0CLR_TOVIFG

#define ADC_INTEVT0CLR_TOVIFG 0x00000002U

§ ADC_INTEVT0CLR_TOVIFG_M

#define ADC_INTEVT0CLR_TOVIFG_M 0x00000002U

§ ADC_INTEVT0CLR_TOVIFG_S

#define ADC_INTEVT0CLR_TOVIFG_S 1U

§ ADC_INTEVT0CLR_TOVIFG_NO_EFFECT

#define ADC_INTEVT0CLR_TOVIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_TOVIFG_CLR

#define ADC_INTEVT0CLR_TOVIFG_CLR 0x00000002U

§ ADC_INTEVT0CLR_HIFG

#define ADC_INTEVT0CLR_HIFG 0x00000004U

§ ADC_INTEVT0CLR_HIFG_M

#define ADC_INTEVT0CLR_HIFG_M 0x00000004U

§ ADC_INTEVT0CLR_HIFG_S

#define ADC_INTEVT0CLR_HIFG_S 2U

§ ADC_INTEVT0CLR_HIFG_NO_EFFECT

#define ADC_INTEVT0CLR_HIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_HIFG_CLR

#define ADC_INTEVT0CLR_HIFG_CLR 0x00000004U

§ ADC_INTEVT0CLR_LOFG

#define ADC_INTEVT0CLR_LOFG 0x00000008U

§ ADC_INTEVT0CLR_LOFG_M

#define ADC_INTEVT0CLR_LOFG_M 0x00000008U

§ ADC_INTEVT0CLR_LOFG_S

#define ADC_INTEVT0CLR_LOFG_S 3U

§ ADC_INTEVT0CLR_LOFG_NO_EFFECT

#define ADC_INTEVT0CLR_LOFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_LOFG_CLR

#define ADC_INTEVT0CLR_LOFG_CLR 0x00000008U

§ ADC_INTEVT0CLR_INIFG

#define ADC_INTEVT0CLR_INIFG 0x00000010U

§ ADC_INTEVT0CLR_INIFG_M

#define ADC_INTEVT0CLR_INIFG_M 0x00000010U

§ ADC_INTEVT0CLR_INIFG_S

#define ADC_INTEVT0CLR_INIFG_S 4U

§ ADC_INTEVT0CLR_INIFG_NO_EFFECT

#define ADC_INTEVT0CLR_INIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_INIFG_CLR

#define ADC_INTEVT0CLR_INIFG_CLR 0x00000010U

§ ADC_INTEVT0CLR_DMADONE

#define ADC_INTEVT0CLR_DMADONE 0x00000020U

§ ADC_INTEVT0CLR_DMADONE_M

#define ADC_INTEVT0CLR_DMADONE_M 0x00000020U

§ ADC_INTEVT0CLR_DMADONE_S

#define ADC_INTEVT0CLR_DMADONE_S 5U

§ ADC_INTEVT0CLR_DMADONE_NO_EFFECT

#define ADC_INTEVT0CLR_DMADONE_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_DMADONE_CLR

#define ADC_INTEVT0CLR_DMADONE_CLR 0x00000020U

§ ADC_INTEVT0CLR_UVIFG

#define ADC_INTEVT0CLR_UVIFG 0x00000040U

§ ADC_INTEVT0CLR_UVIFG_M

#define ADC_INTEVT0CLR_UVIFG_M 0x00000040U

§ ADC_INTEVT0CLR_UVIFG_S

#define ADC_INTEVT0CLR_UVIFG_S 6U

§ ADC_INTEVT0CLR_UVIFG_NO_EFFECT

#define ADC_INTEVT0CLR_UVIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_UVIFG_CLR

#define ADC_INTEVT0CLR_UVIFG_CLR 0x00000040U

§ ADC_INTEVT0CLR_MEMRESIFG0

#define ADC_INTEVT0CLR_MEMRESIFG0 0x00000100U

§ ADC_INTEVT0CLR_MEMRESIFG0_M

#define ADC_INTEVT0CLR_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT0CLR_MEMRESIFG0_S

#define ADC_INTEVT0CLR_MEMRESIFG0_S 8U

§ ADC_INTEVT0CLR_MEMRESIFG0_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG0_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG0_CLR

#define ADC_INTEVT0CLR_MEMRESIFG0_CLR 0x00000100U

§ ADC_INTEVT0CLR_MEMRESIFG1

#define ADC_INTEVT0CLR_MEMRESIFG1 0x00000200U

§ ADC_INTEVT0CLR_MEMRESIFG1_M

#define ADC_INTEVT0CLR_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT0CLR_MEMRESIFG1_S

#define ADC_INTEVT0CLR_MEMRESIFG1_S 9U

§ ADC_INTEVT0CLR_MEMRESIFG1_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG1_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG1_CLR

#define ADC_INTEVT0CLR_MEMRESIFG1_CLR 0x00000200U

§ ADC_INTEVT0CLR_MEMRESIFG2

#define ADC_INTEVT0CLR_MEMRESIFG2 0x00000400U

§ ADC_INTEVT0CLR_MEMRESIFG2_M

#define ADC_INTEVT0CLR_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT0CLR_MEMRESIFG2_S

#define ADC_INTEVT0CLR_MEMRESIFG2_S 10U

§ ADC_INTEVT0CLR_MEMRESIFG2_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG2_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG2_CLR

#define ADC_INTEVT0CLR_MEMRESIFG2_CLR 0x00000400U

§ ADC_INTEVT0CLR_MEMRESIFG3

#define ADC_INTEVT0CLR_MEMRESIFG3 0x00000800U

§ ADC_INTEVT0CLR_MEMRESIFG3_M

#define ADC_INTEVT0CLR_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT0CLR_MEMRESIFG3_S

#define ADC_INTEVT0CLR_MEMRESIFG3_S 11U

§ ADC_INTEVT0CLR_MEMRESIFG3_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG3_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG3_CLR

#define ADC_INTEVT0CLR_MEMRESIFG3_CLR 0x00000800U

§ ADC_INTEVT0CLR_MEMRESIFG4

#define ADC_INTEVT0CLR_MEMRESIFG4 0x00001000U

§ ADC_INTEVT0CLR_MEMRESIFG4_M

#define ADC_INTEVT0CLR_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT0CLR_MEMRESIFG4_S

#define ADC_INTEVT0CLR_MEMRESIFG4_S 12U

§ ADC_INTEVT0CLR_MEMRESIFG4_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG4_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG4_CLR

#define ADC_INTEVT0CLR_MEMRESIFG4_CLR 0x00001000U

§ ADC_INTEVT0CLR_MEMRESIFG5

#define ADC_INTEVT0CLR_MEMRESIFG5 0x00002000U

§ ADC_INTEVT0CLR_MEMRESIFG5_M

#define ADC_INTEVT0CLR_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT0CLR_MEMRESIFG5_S

#define ADC_INTEVT0CLR_MEMRESIFG5_S 13U

§ ADC_INTEVT0CLR_MEMRESIFG5_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG5_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG5_CLR

#define ADC_INTEVT0CLR_MEMRESIFG5_CLR 0x00002000U

§ ADC_INTEVT0CLR_MEMRESIFG6

#define ADC_INTEVT0CLR_MEMRESIFG6 0x00004000U

§ ADC_INTEVT0CLR_MEMRESIFG6_M

#define ADC_INTEVT0CLR_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT0CLR_MEMRESIFG6_S

#define ADC_INTEVT0CLR_MEMRESIFG6_S 14U

§ ADC_INTEVT0CLR_MEMRESIFG6_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG6_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG6_CLR

#define ADC_INTEVT0CLR_MEMRESIFG6_CLR 0x00004000U

§ ADC_INTEVT0CLR_MEMRESIFG7

#define ADC_INTEVT0CLR_MEMRESIFG7 0x00008000U

§ ADC_INTEVT0CLR_MEMRESIFG7_M

#define ADC_INTEVT0CLR_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT0CLR_MEMRESIFG7_S

#define ADC_INTEVT0CLR_MEMRESIFG7_S 15U

§ ADC_INTEVT0CLR_MEMRESIFG7_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG7_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG7_CLR

#define ADC_INTEVT0CLR_MEMRESIFG7_CLR 0x00008000U

§ ADC_INTEVT0CLR_MEMRESIFG8

#define ADC_INTEVT0CLR_MEMRESIFG8 0x00010000U

§ ADC_INTEVT0CLR_MEMRESIFG8_M

#define ADC_INTEVT0CLR_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT0CLR_MEMRESIFG8_S

#define ADC_INTEVT0CLR_MEMRESIFG8_S 16U

§ ADC_INTEVT0CLR_MEMRESIFG8_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG8_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG8_CLR

#define ADC_INTEVT0CLR_MEMRESIFG8_CLR 0x00010000U

§ ADC_INTEVT0CLR_MEMRESIFG9

#define ADC_INTEVT0CLR_MEMRESIFG9 0x00020000U

§ ADC_INTEVT0CLR_MEMRESIFG9_M

#define ADC_INTEVT0CLR_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT0CLR_MEMRESIFG9_S

#define ADC_INTEVT0CLR_MEMRESIFG9_S 17U

§ ADC_INTEVT0CLR_MEMRESIFG9_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG9_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG9_CLR

#define ADC_INTEVT0CLR_MEMRESIFG9_CLR 0x00020000U

§ ADC_INTEVT0CLR_MEMRESIFG10

#define ADC_INTEVT0CLR_MEMRESIFG10 0x00040000U

§ ADC_INTEVT0CLR_MEMRESIFG10_M

#define ADC_INTEVT0CLR_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT0CLR_MEMRESIFG10_S

#define ADC_INTEVT0CLR_MEMRESIFG10_S 18U

§ ADC_INTEVT0CLR_MEMRESIFG10_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG10_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG10_CLR

#define ADC_INTEVT0CLR_MEMRESIFG10_CLR 0x00040000U

§ ADC_INTEVT0CLR_MEMRESIFG11

#define ADC_INTEVT0CLR_MEMRESIFG11 0x00080000U

§ ADC_INTEVT0CLR_MEMRESIFG11_M

#define ADC_INTEVT0CLR_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT0CLR_MEMRESIFG11_S

#define ADC_INTEVT0CLR_MEMRESIFG11_S 19U

§ ADC_INTEVT0CLR_MEMRESIFG11_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG11_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG11_CLR

#define ADC_INTEVT0CLR_MEMRESIFG11_CLR 0x00080000U

§ ADC_INTEVT0CLR_MEMRESIFG12

#define ADC_INTEVT0CLR_MEMRESIFG12 0x00100000U

§ ADC_INTEVT0CLR_MEMRESIFG12_M

#define ADC_INTEVT0CLR_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT0CLR_MEMRESIFG12_S

#define ADC_INTEVT0CLR_MEMRESIFG12_S 20U

§ ADC_INTEVT0CLR_MEMRESIFG12_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG12_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG12_CLR

#define ADC_INTEVT0CLR_MEMRESIFG12_CLR 0x00100000U

§ ADC_INTEVT0CLR_MEMRESIFG13

#define ADC_INTEVT0CLR_MEMRESIFG13 0x00200000U

§ ADC_INTEVT0CLR_MEMRESIFG13_M

#define ADC_INTEVT0CLR_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT0CLR_MEMRESIFG13_S

#define ADC_INTEVT0CLR_MEMRESIFG13_S 21U

§ ADC_INTEVT0CLR_MEMRESIFG13_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG13_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG13_CLR

#define ADC_INTEVT0CLR_MEMRESIFG13_CLR 0x00200000U

§ ADC_INTEVT0CLR_MEMRESIFG14

#define ADC_INTEVT0CLR_MEMRESIFG14 0x00400000U

§ ADC_INTEVT0CLR_MEMRESIFG14_M

#define ADC_INTEVT0CLR_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT0CLR_MEMRESIFG14_S

#define ADC_INTEVT0CLR_MEMRESIFG14_S 22U

§ ADC_INTEVT0CLR_MEMRESIFG14_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG14_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG14_CLR

#define ADC_INTEVT0CLR_MEMRESIFG14_CLR 0x00400000U

§ ADC_INTEVT0CLR_MEMRESIFG15

#define ADC_INTEVT0CLR_MEMRESIFG15 0x00800000U

§ ADC_INTEVT0CLR_MEMRESIFG15_M

#define ADC_INTEVT0CLR_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT0CLR_MEMRESIFG15_S

#define ADC_INTEVT0CLR_MEMRESIFG15_S 23U

§ ADC_INTEVT0CLR_MEMRESIFG15_NO_EFFECT

#define ADC_INTEVT0CLR_MEMRESIFG15_NO_EFFECT 0x00000000U

§ ADC_INTEVT0CLR_MEMRESIFG15_CLR

#define ADC_INTEVT0CLR_MEMRESIFG15_CLR 0x00800000U

§ ADC_INTEVT1IDX_STAT_W

#define ADC_INTEVT1IDX_STAT_W 10U

§ ADC_INTEVT1IDX_STAT_M

#define ADC_INTEVT1IDX_STAT_M 0x000003FFU

§ ADC_INTEVT1IDX_STAT_S

#define ADC_INTEVT1IDX_STAT_S 0U

§ ADC_INTEVT1IDX_STAT_NO_INTR

#define ADC_INTEVT1IDX_STAT_NO_INTR 0x00000000U

§ ADC_INTEVT1IDX_STAT_HIGHIFG

#define ADC_INTEVT1IDX_STAT_HIGHIFG 0x00000003U

§ ADC_INTEVT1IDX_STAT_LOWIFG

#define ADC_INTEVT1IDX_STAT_LOWIFG 0x00000004U

§ ADC_INTEVT1IDX_STAT_INIFG

#define ADC_INTEVT1IDX_STAT_INIFG 0x00000005U

§ ADC_INTEVT1IDX_STAT_MEMRESIFG0

#define ADC_INTEVT1IDX_STAT_MEMRESIFG0 0x00000009U

§ ADC_INTEVT1BM_HIFG

#define ADC_INTEVT1BM_HIFG 0x00000004U

§ ADC_INTEVT1BM_HIFG_M

#define ADC_INTEVT1BM_HIFG_M 0x00000004U

§ ADC_INTEVT1BM_HIFG_S

#define ADC_INTEVT1BM_HIFG_S 2U

§ ADC_INTEVT1BM_HIFG_CLR

#define ADC_INTEVT1BM_HIFG_CLR 0x00000000U

§ ADC_INTEVT1BM_HIFG_SET

#define ADC_INTEVT1BM_HIFG_SET 0x00000004U

§ ADC_INTEVT1BM_LOFG

#define ADC_INTEVT1BM_LOFG 0x00000008U

§ ADC_INTEVT1BM_LOFG_M

#define ADC_INTEVT1BM_LOFG_M 0x00000008U

§ ADC_INTEVT1BM_LOFG_S

#define ADC_INTEVT1BM_LOFG_S 3U

§ ADC_INTEVT1BM_LOFG_CLR

#define ADC_INTEVT1BM_LOFG_CLR 0x00000000U

§ ADC_INTEVT1BM_LOFG_SET

#define ADC_INTEVT1BM_LOFG_SET 0x00000008U

§ ADC_INTEVT1BM_INIFG

#define ADC_INTEVT1BM_INIFG 0x00000010U

§ ADC_INTEVT1BM_INIFG_M

#define ADC_INTEVT1BM_INIFG_M 0x00000010U

§ ADC_INTEVT1BM_INIFG_S

#define ADC_INTEVT1BM_INIFG_S 4U

§ ADC_INTEVT1BM_INIFG_CLR

#define ADC_INTEVT1BM_INIFG_CLR 0x00000000U

§ ADC_INTEVT1BM_INIFG_SET

#define ADC_INTEVT1BM_INIFG_SET 0x00000010U

§ ADC_INTEVT1BM_MEMRESIFG0

#define ADC_INTEVT1BM_MEMRESIFG0 0x00000100U

§ ADC_INTEVT1BM_MEMRESIFG0_M

#define ADC_INTEVT1BM_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT1BM_MEMRESIFG0_S

#define ADC_INTEVT1BM_MEMRESIFG0_S 8U

§ ADC_INTEVT1BM_MEMRESIFG0_CLR

#define ADC_INTEVT1BM_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT1BM_MEMRESIFG0_SET

#define ADC_INTEVT1BM_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT1RIS_HIFG

#define ADC_INTEVT1RIS_HIFG 0x00000004U

§ ADC_INTEVT1RIS_HIFG_M

#define ADC_INTEVT1RIS_HIFG_M 0x00000004U

§ ADC_INTEVT1RIS_HIFG_S

#define ADC_INTEVT1RIS_HIFG_S 2U

§ ADC_INTEVT1RIS_HIFG_CLR

#define ADC_INTEVT1RIS_HIFG_CLR 0x00000000U

§ ADC_INTEVT1RIS_HIFG_SET

#define ADC_INTEVT1RIS_HIFG_SET 0x00000004U

§ ADC_INTEVT1RIS_LOFG

#define ADC_INTEVT1RIS_LOFG 0x00000008U

§ ADC_INTEVT1RIS_LOFG_M

#define ADC_INTEVT1RIS_LOFG_M 0x00000008U

§ ADC_INTEVT1RIS_LOFG_S

#define ADC_INTEVT1RIS_LOFG_S 3U

§ ADC_INTEVT1RIS_LOFG_CLR

#define ADC_INTEVT1RIS_LOFG_CLR 0x00000000U

§ ADC_INTEVT1RIS_LOFG_SET

#define ADC_INTEVT1RIS_LOFG_SET 0x00000008U

§ ADC_INTEVT1RIS_INIFG

#define ADC_INTEVT1RIS_INIFG 0x00000010U

§ ADC_INTEVT1RIS_INIFG_M

#define ADC_INTEVT1RIS_INIFG_M 0x00000010U

§ ADC_INTEVT1RIS_INIFG_S

#define ADC_INTEVT1RIS_INIFG_S 4U

§ ADC_INTEVT1RIS_INIFG_CLR

#define ADC_INTEVT1RIS_INIFG_CLR 0x00000000U

§ ADC_INTEVT1RIS_INIFG_SET

#define ADC_INTEVT1RIS_INIFG_SET 0x00000010U

§ ADC_INTEVT1RIS_MEMRESIFG0

#define ADC_INTEVT1RIS_MEMRESIFG0 0x00000100U

§ ADC_INTEVT1RIS_MEMRESIFG0_M

#define ADC_INTEVT1RIS_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT1RIS_MEMRESIFG0_S

#define ADC_INTEVT1RIS_MEMRESIFG0_S 8U

§ ADC_INTEVT1RIS_MEMRESIFG0_CLR

#define ADC_INTEVT1RIS_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT1RIS_MEMRESIFG0_SET

#define ADC_INTEVT1RIS_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT1MIS_HIFG

#define ADC_INTEVT1MIS_HIFG 0x00000004U

§ ADC_INTEVT1MIS_HIFG_M

#define ADC_INTEVT1MIS_HIFG_M 0x00000004U

§ ADC_INTEVT1MIS_HIFG_S

#define ADC_INTEVT1MIS_HIFG_S 2U

§ ADC_INTEVT1MIS_HIFG_CLR

#define ADC_INTEVT1MIS_HIFG_CLR 0x00000000U

§ ADC_INTEVT1MIS_HIFG_SET

#define ADC_INTEVT1MIS_HIFG_SET 0x00000004U

§ ADC_INTEVT1MIS_LOFG

#define ADC_INTEVT1MIS_LOFG 0x00000008U

§ ADC_INTEVT1MIS_LOFG_M

#define ADC_INTEVT1MIS_LOFG_M 0x00000008U

§ ADC_INTEVT1MIS_LOFG_S

#define ADC_INTEVT1MIS_LOFG_S 3U

§ ADC_INTEVT1MIS_LOFG_CLR

#define ADC_INTEVT1MIS_LOFG_CLR 0x00000000U

§ ADC_INTEVT1MIS_LOFG_SET

#define ADC_INTEVT1MIS_LOFG_SET 0x00000008U

§ ADC_INTEVT1MIS_INIFG

#define ADC_INTEVT1MIS_INIFG 0x00000010U

§ ADC_INTEVT1MIS_INIFG_M

#define ADC_INTEVT1MIS_INIFG_M 0x00000010U

§ ADC_INTEVT1MIS_INIFG_S

#define ADC_INTEVT1MIS_INIFG_S 4U

§ ADC_INTEVT1MIS_INIFG_CLR

#define ADC_INTEVT1MIS_INIFG_CLR 0x00000000U

§ ADC_INTEVT1MIS_INIFG_SET

#define ADC_INTEVT1MIS_INIFG_SET 0x00000010U

§ ADC_INTEVT1MIS_MEMRESIFG0

#define ADC_INTEVT1MIS_MEMRESIFG0 0x00000100U

§ ADC_INTEVT1MIS_MEMRESIFG0_M

#define ADC_INTEVT1MIS_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT1MIS_MEMRESIFG0_S

#define ADC_INTEVT1MIS_MEMRESIFG0_S 8U

§ ADC_INTEVT1MIS_MEMRESIFG0_CLR

#define ADC_INTEVT1MIS_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT1MIS_MEMRESIFG0_SET

#define ADC_INTEVT1MIS_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT1SET_HIFG

#define ADC_INTEVT1SET_HIFG 0x00000004U

§ ADC_INTEVT1SET_HIFG_M

#define ADC_INTEVT1SET_HIFG_M 0x00000004U

§ ADC_INTEVT1SET_HIFG_S

#define ADC_INTEVT1SET_HIFG_S 2U

§ ADC_INTEVT1SET_HIFG_NO_EFFECT

#define ADC_INTEVT1SET_HIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT1SET_HIFG_SET

#define ADC_INTEVT1SET_HIFG_SET 0x00000004U

§ ADC_INTEVT1SET_LOFG

#define ADC_INTEVT1SET_LOFG 0x00000008U

§ ADC_INTEVT1SET_LOFG_M

#define ADC_INTEVT1SET_LOFG_M 0x00000008U

§ ADC_INTEVT1SET_LOFG_S

#define ADC_INTEVT1SET_LOFG_S 3U

§ ADC_INTEVT1SET_LOFG_NO_EFFECT

#define ADC_INTEVT1SET_LOFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT1SET_LOFG_SET

#define ADC_INTEVT1SET_LOFG_SET 0x00000008U

§ ADC_INTEVT1SET_INIFG

#define ADC_INTEVT1SET_INIFG 0x00000010U

§ ADC_INTEVT1SET_INIFG_M

#define ADC_INTEVT1SET_INIFG_M 0x00000010U

§ ADC_INTEVT1SET_INIFG_S

#define ADC_INTEVT1SET_INIFG_S 4U

§ ADC_INTEVT1SET_INIFG_NO_EFFECT

#define ADC_INTEVT1SET_INIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT1SET_INIFG_SET

#define ADC_INTEVT1SET_INIFG_SET 0x00000010U

§ ADC_INTEVT1SET_MEMRESIFG0

#define ADC_INTEVT1SET_MEMRESIFG0 0x00000100U

§ ADC_INTEVT1SET_MEMRESIFG0_M

#define ADC_INTEVT1SET_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT1SET_MEMRESIFG0_S

#define ADC_INTEVT1SET_MEMRESIFG0_S 8U

§ ADC_INTEVT1SET_MEMRESIFG0_NO_EFFECT

#define ADC_INTEVT1SET_MEMRESIFG0_NO_EFFECT 0x00000000U

§ ADC_INTEVT1SET_MEMRESIFG0_SET

#define ADC_INTEVT1SET_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT1CLR_HIFG

#define ADC_INTEVT1CLR_HIFG 0x00000004U

§ ADC_INTEVT1CLR_HIFG_M

#define ADC_INTEVT1CLR_HIFG_M 0x00000004U

§ ADC_INTEVT1CLR_HIFG_S

#define ADC_INTEVT1CLR_HIFG_S 2U

§ ADC_INTEVT1CLR_HIFG_NO_EFFECT

#define ADC_INTEVT1CLR_HIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT1CLR_HIFG_CLR

#define ADC_INTEVT1CLR_HIFG_CLR 0x00000004U

§ ADC_INTEVT1CLR_LOFG

#define ADC_INTEVT1CLR_LOFG 0x00000008U

§ ADC_INTEVT1CLR_LOFG_M

#define ADC_INTEVT1CLR_LOFG_M 0x00000008U

§ ADC_INTEVT1CLR_LOFG_S

#define ADC_INTEVT1CLR_LOFG_S 3U

§ ADC_INTEVT1CLR_LOFG_NO_EFFECT

#define ADC_INTEVT1CLR_LOFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT1CLR_LOFG_CLR

#define ADC_INTEVT1CLR_LOFG_CLR 0x00000008U

§ ADC_INTEVT1CLR_INIFG

#define ADC_INTEVT1CLR_INIFG 0x00000010U

§ ADC_INTEVT1CLR_INIFG_M

#define ADC_INTEVT1CLR_INIFG_M 0x00000010U

§ ADC_INTEVT1CLR_INIFG_S

#define ADC_INTEVT1CLR_INIFG_S 4U

§ ADC_INTEVT1CLR_INIFG_NO_EFFECT

#define ADC_INTEVT1CLR_INIFG_NO_EFFECT 0x00000000U

§ ADC_INTEVT1CLR_INIFG_CLR

#define ADC_INTEVT1CLR_INIFG_CLR 0x00000010U

§ ADC_INTEVT1CLR_MEMRESIFG0

#define ADC_INTEVT1CLR_MEMRESIFG0 0x00000100U

§ ADC_INTEVT1CLR_MEMRESIFG0_M

#define ADC_INTEVT1CLR_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT1CLR_MEMRESIFG0_S

#define ADC_INTEVT1CLR_MEMRESIFG0_S 8U

§ ADC_INTEVT1CLR_MEMRESIFG0_NO_EFFECT

#define ADC_INTEVT1CLR_MEMRESIFG0_NO_EFFECT 0x00000000U

§ ADC_INTEVT1CLR_MEMRESIFG0_CLR

#define ADC_INTEVT1CLR_MEMRESIFG0_CLR 0x00000100U

§ ADC_INTEVT2IDX_STAT_W

#define ADC_INTEVT2IDX_STAT_W 10U

§ ADC_INTEVT2IDX_STAT_M

#define ADC_INTEVT2IDX_STAT_M 0x000003FFU

§ ADC_INTEVT2IDX_STAT_S

#define ADC_INTEVT2IDX_STAT_S 0U

§ ADC_INTEVT2IDX_STAT_NO_INTR

#define ADC_INTEVT2IDX_STAT_NO_INTR 0x00000000U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG0

#define ADC_INTEVT2IDX_STAT_MEMRESIFG0 0x00000009U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG1

#define ADC_INTEVT2IDX_STAT_MEMRESIFG1 0x0000000AU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG2

#define ADC_INTEVT2IDX_STAT_MEMRESIFG2 0x0000000BU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG3

#define ADC_INTEVT2IDX_STAT_MEMRESIFG3 0x0000000CU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG4

#define ADC_INTEVT2IDX_STAT_MEMRESIFG4 0x0000000DU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG5

#define ADC_INTEVT2IDX_STAT_MEMRESIFG5 0x0000000EU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG6

#define ADC_INTEVT2IDX_STAT_MEMRESIFG6 0x0000000FU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG7

#define ADC_INTEVT2IDX_STAT_MEMRESIFG7 0x00000010U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG8

#define ADC_INTEVT2IDX_STAT_MEMRESIFG8 0x00000011U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG9

#define ADC_INTEVT2IDX_STAT_MEMRESIFG9 0x00000012U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG10

#define ADC_INTEVT2IDX_STAT_MEMRESIFG10 0x00000013U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG11

#define ADC_INTEVT2IDX_STAT_MEMRESIFG11 0x00000014U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG12

#define ADC_INTEVT2IDX_STAT_MEMRESIFG12 0x00000015U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG13

#define ADC_INTEVT2IDX_STAT_MEMRESIFG13 0x00000016U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG14

#define ADC_INTEVT2IDX_STAT_MEMRESIFG14 0x00000017U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG15

#define ADC_INTEVT2IDX_STAT_MEMRESIFG15 0x00000018U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG16

#define ADC_INTEVT2IDX_STAT_MEMRESIFG16 0x00000019U

§ ADC_INTEVT2IDX_STAT_MEMRESIFG17

#define ADC_INTEVT2IDX_STAT_MEMRESIFG17 0x0000001AU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG18

#define ADC_INTEVT2IDX_STAT_MEMRESIFG18 0x0000001BU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG19

#define ADC_INTEVT2IDX_STAT_MEMRESIFG19 0x0000001CU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG20

#define ADC_INTEVT2IDX_STAT_MEMRESIFG20 0x0000001DU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG21

#define ADC_INTEVT2IDX_STAT_MEMRESIFG21 0x0000001EU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG22

#define ADC_INTEVT2IDX_STAT_MEMRESIFG22 0x0000001FU

§ ADC_INTEVT2IDX_STAT_MEMRESIFG23

#define ADC_INTEVT2IDX_STAT_MEMRESIFG23 0x00000020U

§ ADC_INTEVT2BM_MEMRESIFG0

#define ADC_INTEVT2BM_MEMRESIFG0 0x00000100U

§ ADC_INTEVT2BM_MEMRESIFG0_M

#define ADC_INTEVT2BM_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT2BM_MEMRESIFG0_S

#define ADC_INTEVT2BM_MEMRESIFG0_S 8U

§ ADC_INTEVT2BM_MEMRESIFG0_CLR

#define ADC_INTEVT2BM_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG0_SET

#define ADC_INTEVT2BM_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT2BM_MEMRESIFG1

#define ADC_INTEVT2BM_MEMRESIFG1 0x00000200U

§ ADC_INTEVT2BM_MEMRESIFG1_M

#define ADC_INTEVT2BM_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT2BM_MEMRESIFG1_S

#define ADC_INTEVT2BM_MEMRESIFG1_S 9U

§ ADC_INTEVT2BM_MEMRESIFG1_CLR

#define ADC_INTEVT2BM_MEMRESIFG1_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG1_SET

#define ADC_INTEVT2BM_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT2BM_MEMRESIFG2

#define ADC_INTEVT2BM_MEMRESIFG2 0x00000400U

§ ADC_INTEVT2BM_MEMRESIFG2_M

#define ADC_INTEVT2BM_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT2BM_MEMRESIFG2_S

#define ADC_INTEVT2BM_MEMRESIFG2_S 10U

§ ADC_INTEVT2BM_MEMRESIFG2_CLR

#define ADC_INTEVT2BM_MEMRESIFG2_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG2_SET

#define ADC_INTEVT2BM_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT2BM_MEMRESIFG3

#define ADC_INTEVT2BM_MEMRESIFG3 0x00000800U

§ ADC_INTEVT2BM_MEMRESIFG3_M

#define ADC_INTEVT2BM_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT2BM_MEMRESIFG3_S

#define ADC_INTEVT2BM_MEMRESIFG3_S 11U

§ ADC_INTEVT2BM_MEMRESIFG3_CLR

#define ADC_INTEVT2BM_MEMRESIFG3_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG3_SET

#define ADC_INTEVT2BM_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT2BM_MEMRESIFG4

#define ADC_INTEVT2BM_MEMRESIFG4 0x00001000U

§ ADC_INTEVT2BM_MEMRESIFG4_M

#define ADC_INTEVT2BM_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT2BM_MEMRESIFG4_S

#define ADC_INTEVT2BM_MEMRESIFG4_S 12U

§ ADC_INTEVT2BM_MEMRESIFG4_CLR

#define ADC_INTEVT2BM_MEMRESIFG4_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG4_SET

#define ADC_INTEVT2BM_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT2BM_MEMRESIFG5

#define ADC_INTEVT2BM_MEMRESIFG5 0x00002000U

§ ADC_INTEVT2BM_MEMRESIFG5_M

#define ADC_INTEVT2BM_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT2BM_MEMRESIFG5_S

#define ADC_INTEVT2BM_MEMRESIFG5_S 13U

§ ADC_INTEVT2BM_MEMRESIFG5_CLR

#define ADC_INTEVT2BM_MEMRESIFG5_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG5_SET

#define ADC_INTEVT2BM_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT2BM_MEMRESIFG6

#define ADC_INTEVT2BM_MEMRESIFG6 0x00004000U

§ ADC_INTEVT2BM_MEMRESIFG6_M

#define ADC_INTEVT2BM_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT2BM_MEMRESIFG6_S

#define ADC_INTEVT2BM_MEMRESIFG6_S 14U

§ ADC_INTEVT2BM_MEMRESIFG6_CLR

#define ADC_INTEVT2BM_MEMRESIFG6_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG6_SET

#define ADC_INTEVT2BM_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT2BM_MEMRESIFG7

#define ADC_INTEVT2BM_MEMRESIFG7 0x00008000U

§ ADC_INTEVT2BM_MEMRESIFG7_M

#define ADC_INTEVT2BM_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT2BM_MEMRESIFG7_S

#define ADC_INTEVT2BM_MEMRESIFG7_S 15U

§ ADC_INTEVT2BM_MEMRESIFG7_CLR

#define ADC_INTEVT2BM_MEMRESIFG7_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG7_SET

#define ADC_INTEVT2BM_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT2BM_MEMRESIFG8

#define ADC_INTEVT2BM_MEMRESIFG8 0x00010000U

§ ADC_INTEVT2BM_MEMRESIFG8_M

#define ADC_INTEVT2BM_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT2BM_MEMRESIFG8_S

#define ADC_INTEVT2BM_MEMRESIFG8_S 16U

§ ADC_INTEVT2BM_MEMRESIFG8_CLR

#define ADC_INTEVT2BM_MEMRESIFG8_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG8_SET

#define ADC_INTEVT2BM_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT2BM_MEMRESIFG9

#define ADC_INTEVT2BM_MEMRESIFG9 0x00020000U

§ ADC_INTEVT2BM_MEMRESIFG9_M

#define ADC_INTEVT2BM_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT2BM_MEMRESIFG9_S

#define ADC_INTEVT2BM_MEMRESIFG9_S 17U

§ ADC_INTEVT2BM_MEMRESIFG9_CLR

#define ADC_INTEVT2BM_MEMRESIFG9_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG9_SET

#define ADC_INTEVT2BM_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT2BM_MEMRESIFG10

#define ADC_INTEVT2BM_MEMRESIFG10 0x00040000U

§ ADC_INTEVT2BM_MEMRESIFG10_M

#define ADC_INTEVT2BM_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT2BM_MEMRESIFG10_S

#define ADC_INTEVT2BM_MEMRESIFG10_S 18U

§ ADC_INTEVT2BM_MEMRESIFG10_CLR

#define ADC_INTEVT2BM_MEMRESIFG10_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG10_SET

#define ADC_INTEVT2BM_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT2BM_MEMRESIFG11

#define ADC_INTEVT2BM_MEMRESIFG11 0x00080000U

§ ADC_INTEVT2BM_MEMRESIFG11_M

#define ADC_INTEVT2BM_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT2BM_MEMRESIFG11_S

#define ADC_INTEVT2BM_MEMRESIFG11_S 19U

§ ADC_INTEVT2BM_MEMRESIFG11_CLR

#define ADC_INTEVT2BM_MEMRESIFG11_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG11_SET

#define ADC_INTEVT2BM_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT2BM_MEMRESIFG12

#define ADC_INTEVT2BM_MEMRESIFG12 0x00100000U

§ ADC_INTEVT2BM_MEMRESIFG12_M

#define ADC_INTEVT2BM_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT2BM_MEMRESIFG12_S

#define ADC_INTEVT2BM_MEMRESIFG12_S 20U

§ ADC_INTEVT2BM_MEMRESIFG12_CLR

#define ADC_INTEVT2BM_MEMRESIFG12_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG12_SET

#define ADC_INTEVT2BM_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT2BM_MEMRESIFG13

#define ADC_INTEVT2BM_MEMRESIFG13 0x00200000U

§ ADC_INTEVT2BM_MEMRESIFG13_M

#define ADC_INTEVT2BM_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT2BM_MEMRESIFG13_S

#define ADC_INTEVT2BM_MEMRESIFG13_S 21U

§ ADC_INTEVT2BM_MEMRESIFG13_CLR

#define ADC_INTEVT2BM_MEMRESIFG13_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG13_SET

#define ADC_INTEVT2BM_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT2BM_MEMRESIFG14

#define ADC_INTEVT2BM_MEMRESIFG14 0x00400000U

§ ADC_INTEVT2BM_MEMRESIFG14_M

#define ADC_INTEVT2BM_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT2BM_MEMRESIFG14_S

#define ADC_INTEVT2BM_MEMRESIFG14_S 22U

§ ADC_INTEVT2BM_MEMRESIFG14_CLR

#define ADC_INTEVT2BM_MEMRESIFG14_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG14_SET

#define ADC_INTEVT2BM_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT2BM_MEMRESIFG15

#define ADC_INTEVT2BM_MEMRESIFG15 0x00800000U

§ ADC_INTEVT2BM_MEMRESIFG15_M

#define ADC_INTEVT2BM_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT2BM_MEMRESIFG15_S

#define ADC_INTEVT2BM_MEMRESIFG15_S 23U

§ ADC_INTEVT2BM_MEMRESIFG15_CLR

#define ADC_INTEVT2BM_MEMRESIFG15_CLR 0x00000000U

§ ADC_INTEVT2BM_MEMRESIFG15_SET

#define ADC_INTEVT2BM_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT2RIS_MEMRESIFG0

#define ADC_INTEVT2RIS_MEMRESIFG0 0x00000100U

§ ADC_INTEVT2RIS_MEMRESIFG0_M

#define ADC_INTEVT2RIS_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT2RIS_MEMRESIFG0_S

#define ADC_INTEVT2RIS_MEMRESIFG0_S 8U

§ ADC_INTEVT2RIS_MEMRESIFG0_CLR

#define ADC_INTEVT2RIS_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG0_SET

#define ADC_INTEVT2RIS_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT2RIS_MEMRESIFG1

#define ADC_INTEVT2RIS_MEMRESIFG1 0x00000200U

§ ADC_INTEVT2RIS_MEMRESIFG1_M

#define ADC_INTEVT2RIS_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT2RIS_MEMRESIFG1_S

#define ADC_INTEVT2RIS_MEMRESIFG1_S 9U

§ ADC_INTEVT2RIS_MEMRESIFG1_CLR

#define ADC_INTEVT2RIS_MEMRESIFG1_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG1_SET

#define ADC_INTEVT2RIS_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT2RIS_MEMRESIFG2

#define ADC_INTEVT2RIS_MEMRESIFG2 0x00000400U

§ ADC_INTEVT2RIS_MEMRESIFG2_M

#define ADC_INTEVT2RIS_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT2RIS_MEMRESIFG2_S

#define ADC_INTEVT2RIS_MEMRESIFG2_S 10U

§ ADC_INTEVT2RIS_MEMRESIFG2_CLR

#define ADC_INTEVT2RIS_MEMRESIFG2_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG2_SET

#define ADC_INTEVT2RIS_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT2RIS_MEMRESIFG3

#define ADC_INTEVT2RIS_MEMRESIFG3 0x00000800U

§ ADC_INTEVT2RIS_MEMRESIFG3_M

#define ADC_INTEVT2RIS_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT2RIS_MEMRESIFG3_S

#define ADC_INTEVT2RIS_MEMRESIFG3_S 11U

§ ADC_INTEVT2RIS_MEMRESIFG3_CLR

#define ADC_INTEVT2RIS_MEMRESIFG3_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG3_SET

#define ADC_INTEVT2RIS_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT2RIS_MEMRESIFG4

#define ADC_INTEVT2RIS_MEMRESIFG4 0x00001000U

§ ADC_INTEVT2RIS_MEMRESIFG4_M

#define ADC_INTEVT2RIS_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT2RIS_MEMRESIFG4_S

#define ADC_INTEVT2RIS_MEMRESIFG4_S 12U

§ ADC_INTEVT2RIS_MEMRESIFG4_CLR

#define ADC_INTEVT2RIS_MEMRESIFG4_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG4_SET

#define ADC_INTEVT2RIS_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT2RIS_MEMRESIFG5

#define ADC_INTEVT2RIS_MEMRESIFG5 0x00002000U

§ ADC_INTEVT2RIS_MEMRESIFG5_M

#define ADC_INTEVT2RIS_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT2RIS_MEMRESIFG5_S

#define ADC_INTEVT2RIS_MEMRESIFG5_S 13U

§ ADC_INTEVT2RIS_MEMRESIFG5_CLR

#define ADC_INTEVT2RIS_MEMRESIFG5_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG5_SET

#define ADC_INTEVT2RIS_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT2RIS_MEMRESIFG6

#define ADC_INTEVT2RIS_MEMRESIFG6 0x00004000U

§ ADC_INTEVT2RIS_MEMRESIFG6_M

#define ADC_INTEVT2RIS_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT2RIS_MEMRESIFG6_S

#define ADC_INTEVT2RIS_MEMRESIFG6_S 14U

§ ADC_INTEVT2RIS_MEMRESIFG6_CLR

#define ADC_INTEVT2RIS_MEMRESIFG6_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG6_SET

#define ADC_INTEVT2RIS_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT2RIS_MEMRESIFG7

#define ADC_INTEVT2RIS_MEMRESIFG7 0x00008000U

§ ADC_INTEVT2RIS_MEMRESIFG7_M

#define ADC_INTEVT2RIS_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT2RIS_MEMRESIFG7_S

#define ADC_INTEVT2RIS_MEMRESIFG7_S 15U

§ ADC_INTEVT2RIS_MEMRESIFG7_CLR

#define ADC_INTEVT2RIS_MEMRESIFG7_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG7_SET

#define ADC_INTEVT2RIS_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT2RIS_MEMRESIFG8

#define ADC_INTEVT2RIS_MEMRESIFG8 0x00010000U

§ ADC_INTEVT2RIS_MEMRESIFG8_M

#define ADC_INTEVT2RIS_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT2RIS_MEMRESIFG8_S

#define ADC_INTEVT2RIS_MEMRESIFG8_S 16U

§ ADC_INTEVT2RIS_MEMRESIFG8_CLR

#define ADC_INTEVT2RIS_MEMRESIFG8_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG8_SET

#define ADC_INTEVT2RIS_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT2RIS_MEMRESIFG9

#define ADC_INTEVT2RIS_MEMRESIFG9 0x00020000U

§ ADC_INTEVT2RIS_MEMRESIFG9_M

#define ADC_INTEVT2RIS_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT2RIS_MEMRESIFG9_S

#define ADC_INTEVT2RIS_MEMRESIFG9_S 17U

§ ADC_INTEVT2RIS_MEMRESIFG9_CLR

#define ADC_INTEVT2RIS_MEMRESIFG9_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG9_SET

#define ADC_INTEVT2RIS_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT2RIS_MEMRESIFG10

#define ADC_INTEVT2RIS_MEMRESIFG10 0x00040000U

§ ADC_INTEVT2RIS_MEMRESIFG10_M

#define ADC_INTEVT2RIS_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT2RIS_MEMRESIFG10_S

#define ADC_INTEVT2RIS_MEMRESIFG10_S 18U

§ ADC_INTEVT2RIS_MEMRESIFG10_CLR

#define ADC_INTEVT2RIS_MEMRESIFG10_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG10_SET

#define ADC_INTEVT2RIS_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT2RIS_MEMRESIFG11

#define ADC_INTEVT2RIS_MEMRESIFG11 0x00080000U

§ ADC_INTEVT2RIS_MEMRESIFG11_M

#define ADC_INTEVT2RIS_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT2RIS_MEMRESIFG11_S

#define ADC_INTEVT2RIS_MEMRESIFG11_S 19U

§ ADC_INTEVT2RIS_MEMRESIFG11_CLR

#define ADC_INTEVT2RIS_MEMRESIFG11_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG11_SET

#define ADC_INTEVT2RIS_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT2RIS_MEMRESIFG12

#define ADC_INTEVT2RIS_MEMRESIFG12 0x00100000U

§ ADC_INTEVT2RIS_MEMRESIFG12_M

#define ADC_INTEVT2RIS_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT2RIS_MEMRESIFG12_S

#define ADC_INTEVT2RIS_MEMRESIFG12_S 20U

§ ADC_INTEVT2RIS_MEMRESIFG12_CLR

#define ADC_INTEVT2RIS_MEMRESIFG12_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG12_SET

#define ADC_INTEVT2RIS_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT2RIS_MEMRESIFG13

#define ADC_INTEVT2RIS_MEMRESIFG13 0x00200000U

§ ADC_INTEVT2RIS_MEMRESIFG13_M

#define ADC_INTEVT2RIS_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT2RIS_MEMRESIFG13_S

#define ADC_INTEVT2RIS_MEMRESIFG13_S 21U

§ ADC_INTEVT2RIS_MEMRESIFG13_CLR

#define ADC_INTEVT2RIS_MEMRESIFG13_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG13_SET

#define ADC_INTEVT2RIS_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT2RIS_MEMRESIFG14

#define ADC_INTEVT2RIS_MEMRESIFG14 0x00400000U

§ ADC_INTEVT2RIS_MEMRESIFG14_M

#define ADC_INTEVT2RIS_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT2RIS_MEMRESIFG14_S

#define ADC_INTEVT2RIS_MEMRESIFG14_S 22U

§ ADC_INTEVT2RIS_MEMRESIFG14_CLR

#define ADC_INTEVT2RIS_MEMRESIFG14_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG14_SET

#define ADC_INTEVT2RIS_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT2RIS_MEMRESIFG15

#define ADC_INTEVT2RIS_MEMRESIFG15 0x00800000U

§ ADC_INTEVT2RIS_MEMRESIFG15_M

#define ADC_INTEVT2RIS_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT2RIS_MEMRESIFG15_S

#define ADC_INTEVT2RIS_MEMRESIFG15_S 23U

§ ADC_INTEVT2RIS_MEMRESIFG15_CLR

#define ADC_INTEVT2RIS_MEMRESIFG15_CLR 0x00000000U

§ ADC_INTEVT2RIS_MEMRESIFG15_SET

#define ADC_INTEVT2RIS_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT2MIS_MEMRESIFG0

#define ADC_INTEVT2MIS_MEMRESIFG0 0x00000100U

§ ADC_INTEVT2MIS_MEMRESIFG0_M

#define ADC_INTEVT2MIS_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT2MIS_MEMRESIFG0_S

#define ADC_INTEVT2MIS_MEMRESIFG0_S 8U

§ ADC_INTEVT2MIS_MEMRESIFG0_CLR

#define ADC_INTEVT2MIS_MEMRESIFG0_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG0_SET

#define ADC_INTEVT2MIS_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT2MIS_MEMRESIFG1

#define ADC_INTEVT2MIS_MEMRESIFG1 0x00000200U

§ ADC_INTEVT2MIS_MEMRESIFG1_M

#define ADC_INTEVT2MIS_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT2MIS_MEMRESIFG1_S

#define ADC_INTEVT2MIS_MEMRESIFG1_S 9U

§ ADC_INTEVT2MIS_MEMRESIFG1_CLR

#define ADC_INTEVT2MIS_MEMRESIFG1_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG1_SET

#define ADC_INTEVT2MIS_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT2MIS_MEMRESIFG2

#define ADC_INTEVT2MIS_MEMRESIFG2 0x00000400U

§ ADC_INTEVT2MIS_MEMRESIFG2_M

#define ADC_INTEVT2MIS_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT2MIS_MEMRESIFG2_S

#define ADC_INTEVT2MIS_MEMRESIFG2_S 10U

§ ADC_INTEVT2MIS_MEMRESIFG2_CLR

#define ADC_INTEVT2MIS_MEMRESIFG2_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG2_SET

#define ADC_INTEVT2MIS_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT2MIS_MEMRESIFG3

#define ADC_INTEVT2MIS_MEMRESIFG3 0x00000800U

§ ADC_INTEVT2MIS_MEMRESIFG3_M

#define ADC_INTEVT2MIS_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT2MIS_MEMRESIFG3_S

#define ADC_INTEVT2MIS_MEMRESIFG3_S 11U

§ ADC_INTEVT2MIS_MEMRESIFG3_CLR

#define ADC_INTEVT2MIS_MEMRESIFG3_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG3_SET

#define ADC_INTEVT2MIS_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT2MIS_MEMRESIFG4

#define ADC_INTEVT2MIS_MEMRESIFG4 0x00001000U

§ ADC_INTEVT2MIS_MEMRESIFG4_M

#define ADC_INTEVT2MIS_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT2MIS_MEMRESIFG4_S

#define ADC_INTEVT2MIS_MEMRESIFG4_S 12U

§ ADC_INTEVT2MIS_MEMRESIFG4_CLR

#define ADC_INTEVT2MIS_MEMRESIFG4_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG4_SET

#define ADC_INTEVT2MIS_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT2MIS_MEMRESIFG5

#define ADC_INTEVT2MIS_MEMRESIFG5 0x00002000U

§ ADC_INTEVT2MIS_MEMRESIFG5_M

#define ADC_INTEVT2MIS_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT2MIS_MEMRESIFG5_S

#define ADC_INTEVT2MIS_MEMRESIFG5_S 13U

§ ADC_INTEVT2MIS_MEMRESIFG5_CLR

#define ADC_INTEVT2MIS_MEMRESIFG5_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG5_SET

#define ADC_INTEVT2MIS_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT2MIS_MEMRESIFG6

#define ADC_INTEVT2MIS_MEMRESIFG6 0x00004000U

§ ADC_INTEVT2MIS_MEMRESIFG6_M

#define ADC_INTEVT2MIS_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT2MIS_MEMRESIFG6_S

#define ADC_INTEVT2MIS_MEMRESIFG6_S 14U

§ ADC_INTEVT2MIS_MEMRESIFG6_CLR

#define ADC_INTEVT2MIS_MEMRESIFG6_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG6_SET

#define ADC_INTEVT2MIS_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT2MIS_MEMRESIFG7

#define ADC_INTEVT2MIS_MEMRESIFG7 0x00008000U

§ ADC_INTEVT2MIS_MEMRESIFG7_M

#define ADC_INTEVT2MIS_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT2MIS_MEMRESIFG7_S

#define ADC_INTEVT2MIS_MEMRESIFG7_S 15U

§ ADC_INTEVT2MIS_MEMRESIFG7_CLR

#define ADC_INTEVT2MIS_MEMRESIFG7_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG7_SET

#define ADC_INTEVT2MIS_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT2MIS_MEMRESIFG8

#define ADC_INTEVT2MIS_MEMRESIFG8 0x00010000U

§ ADC_INTEVT2MIS_MEMRESIFG8_M

#define ADC_INTEVT2MIS_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT2MIS_MEMRESIFG8_S

#define ADC_INTEVT2MIS_MEMRESIFG8_S 16U

§ ADC_INTEVT2MIS_MEMRESIFG8_CLR

#define ADC_INTEVT2MIS_MEMRESIFG8_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG8_SET

#define ADC_INTEVT2MIS_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT2MIS_MEMRESIFG9

#define ADC_INTEVT2MIS_MEMRESIFG9 0x00020000U

§ ADC_INTEVT2MIS_MEMRESIFG9_M

#define ADC_INTEVT2MIS_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT2MIS_MEMRESIFG9_S

#define ADC_INTEVT2MIS_MEMRESIFG9_S 17U

§ ADC_INTEVT2MIS_MEMRESIFG9_CLR

#define ADC_INTEVT2MIS_MEMRESIFG9_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG9_SET

#define ADC_INTEVT2MIS_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT2MIS_MEMRESIFG10

#define ADC_INTEVT2MIS_MEMRESIFG10 0x00040000U

§ ADC_INTEVT2MIS_MEMRESIFG10_M

#define ADC_INTEVT2MIS_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT2MIS_MEMRESIFG10_S

#define ADC_INTEVT2MIS_MEMRESIFG10_S 18U

§ ADC_INTEVT2MIS_MEMRESIFG10_CLR

#define ADC_INTEVT2MIS_MEMRESIFG10_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG10_SET

#define ADC_INTEVT2MIS_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT2MIS_MEMRESIFG11

#define ADC_INTEVT2MIS_MEMRESIFG11 0x00080000U

§ ADC_INTEVT2MIS_MEMRESIFG11_M

#define ADC_INTEVT2MIS_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT2MIS_MEMRESIFG11_S

#define ADC_INTEVT2MIS_MEMRESIFG11_S 19U

§ ADC_INTEVT2MIS_MEMRESIFG11_CLR

#define ADC_INTEVT2MIS_MEMRESIFG11_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG11_SET

#define ADC_INTEVT2MIS_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT2MIS_MEMRESIFG12

#define ADC_INTEVT2MIS_MEMRESIFG12 0x00100000U

§ ADC_INTEVT2MIS_MEMRESIFG12_M

#define ADC_INTEVT2MIS_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT2MIS_MEMRESIFG12_S

#define ADC_INTEVT2MIS_MEMRESIFG12_S 20U

§ ADC_INTEVT2MIS_MEMRESIFG12_CLR

#define ADC_INTEVT2MIS_MEMRESIFG12_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG12_SET

#define ADC_INTEVT2MIS_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT2MIS_MEMRESIFG13

#define ADC_INTEVT2MIS_MEMRESIFG13 0x00200000U

§ ADC_INTEVT2MIS_MEMRESIFG13_M

#define ADC_INTEVT2MIS_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT2MIS_MEMRESIFG13_S

#define ADC_INTEVT2MIS_MEMRESIFG13_S 21U

§ ADC_INTEVT2MIS_MEMRESIFG13_CLR

#define ADC_INTEVT2MIS_MEMRESIFG13_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG13_SET

#define ADC_INTEVT2MIS_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT2MIS_MEMRESIFG14

#define ADC_INTEVT2MIS_MEMRESIFG14 0x00400000U

§ ADC_INTEVT2MIS_MEMRESIFG14_M

#define ADC_INTEVT2MIS_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT2MIS_MEMRESIFG14_S

#define ADC_INTEVT2MIS_MEMRESIFG14_S 22U

§ ADC_INTEVT2MIS_MEMRESIFG14_CLR

#define ADC_INTEVT2MIS_MEMRESIFG14_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG14_SET

#define ADC_INTEVT2MIS_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT2MIS_MEMRESIFG15

#define ADC_INTEVT2MIS_MEMRESIFG15 0x00800000U

§ ADC_INTEVT2MIS_MEMRESIFG15_M

#define ADC_INTEVT2MIS_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT2MIS_MEMRESIFG15_S

#define ADC_INTEVT2MIS_MEMRESIFG15_S 23U

§ ADC_INTEVT2MIS_MEMRESIFG15_CLR

#define ADC_INTEVT2MIS_MEMRESIFG15_CLR 0x00000000U

§ ADC_INTEVT2MIS_MEMRESIFG15_SET

#define ADC_INTEVT2MIS_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT2SET_MEMRESIFG0

#define ADC_INTEVT2SET_MEMRESIFG0 0x00000100U

§ ADC_INTEVT2SET_MEMRESIFG0_M

#define ADC_INTEVT2SET_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT2SET_MEMRESIFG0_S

#define ADC_INTEVT2SET_MEMRESIFG0_S 8U

§ ADC_INTEVT2SET_MEMRESIFG0_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG0_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG0_SET

#define ADC_INTEVT2SET_MEMRESIFG0_SET 0x00000100U

§ ADC_INTEVT2SET_MEMRESIFG1

#define ADC_INTEVT2SET_MEMRESIFG1 0x00000200U

§ ADC_INTEVT2SET_MEMRESIFG1_M

#define ADC_INTEVT2SET_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT2SET_MEMRESIFG1_S

#define ADC_INTEVT2SET_MEMRESIFG1_S 9U

§ ADC_INTEVT2SET_MEMRESIFG1_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG1_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG1_SET

#define ADC_INTEVT2SET_MEMRESIFG1_SET 0x00000200U

§ ADC_INTEVT2SET_MEMRESIFG2

#define ADC_INTEVT2SET_MEMRESIFG2 0x00000400U

§ ADC_INTEVT2SET_MEMRESIFG2_M

#define ADC_INTEVT2SET_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT2SET_MEMRESIFG2_S

#define ADC_INTEVT2SET_MEMRESIFG2_S 10U

§ ADC_INTEVT2SET_MEMRESIFG2_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG2_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG2_SET

#define ADC_INTEVT2SET_MEMRESIFG2_SET 0x00000400U

§ ADC_INTEVT2SET_MEMRESIFG3

#define ADC_INTEVT2SET_MEMRESIFG3 0x00000800U

§ ADC_INTEVT2SET_MEMRESIFG3_M

#define ADC_INTEVT2SET_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT2SET_MEMRESIFG3_S

#define ADC_INTEVT2SET_MEMRESIFG3_S 11U

§ ADC_INTEVT2SET_MEMRESIFG3_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG3_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG3_SET

#define ADC_INTEVT2SET_MEMRESIFG3_SET 0x00000800U

§ ADC_INTEVT2SET_MEMRESIFG4

#define ADC_INTEVT2SET_MEMRESIFG4 0x00001000U

§ ADC_INTEVT2SET_MEMRESIFG4_M

#define ADC_INTEVT2SET_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT2SET_MEMRESIFG4_S

#define ADC_INTEVT2SET_MEMRESIFG4_S 12U

§ ADC_INTEVT2SET_MEMRESIFG4_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG4_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG4_SET

#define ADC_INTEVT2SET_MEMRESIFG4_SET 0x00001000U

§ ADC_INTEVT2SET_MEMRESIFG5

#define ADC_INTEVT2SET_MEMRESIFG5 0x00002000U

§ ADC_INTEVT2SET_MEMRESIFG5_M

#define ADC_INTEVT2SET_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT2SET_MEMRESIFG5_S

#define ADC_INTEVT2SET_MEMRESIFG5_S 13U

§ ADC_INTEVT2SET_MEMRESIFG5_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG5_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG5_SET

#define ADC_INTEVT2SET_MEMRESIFG5_SET 0x00002000U

§ ADC_INTEVT2SET_MEMRESIFG6

#define ADC_INTEVT2SET_MEMRESIFG6 0x00004000U

§ ADC_INTEVT2SET_MEMRESIFG6_M

#define ADC_INTEVT2SET_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT2SET_MEMRESIFG6_S

#define ADC_INTEVT2SET_MEMRESIFG6_S 14U

§ ADC_INTEVT2SET_MEMRESIFG6_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG6_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG6_SET

#define ADC_INTEVT2SET_MEMRESIFG6_SET 0x00004000U

§ ADC_INTEVT2SET_MEMRESIFG7

#define ADC_INTEVT2SET_MEMRESIFG7 0x00008000U

§ ADC_INTEVT2SET_MEMRESIFG7_M

#define ADC_INTEVT2SET_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT2SET_MEMRESIFG7_S

#define ADC_INTEVT2SET_MEMRESIFG7_S 15U

§ ADC_INTEVT2SET_MEMRESIFG7_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG7_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG7_SET

#define ADC_INTEVT2SET_MEMRESIFG7_SET 0x00008000U

§ ADC_INTEVT2SET_MEMRESIFG8

#define ADC_INTEVT2SET_MEMRESIFG8 0x00010000U

§ ADC_INTEVT2SET_MEMRESIFG8_M

#define ADC_INTEVT2SET_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT2SET_MEMRESIFG8_S

#define ADC_INTEVT2SET_MEMRESIFG8_S 16U

§ ADC_INTEVT2SET_MEMRESIFG8_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG8_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG8_SET

#define ADC_INTEVT2SET_MEMRESIFG8_SET 0x00010000U

§ ADC_INTEVT2SET_MEMRESIFG9

#define ADC_INTEVT2SET_MEMRESIFG9 0x00020000U

§ ADC_INTEVT2SET_MEMRESIFG9_M

#define ADC_INTEVT2SET_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT2SET_MEMRESIFG9_S

#define ADC_INTEVT2SET_MEMRESIFG9_S 17U

§ ADC_INTEVT2SET_MEMRESIFG9_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG9_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG9_SET

#define ADC_INTEVT2SET_MEMRESIFG9_SET 0x00020000U

§ ADC_INTEVT2SET_MEMRESIFG10

#define ADC_INTEVT2SET_MEMRESIFG10 0x00040000U

§ ADC_INTEVT2SET_MEMRESIFG10_M

#define ADC_INTEVT2SET_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT2SET_MEMRESIFG10_S

#define ADC_INTEVT2SET_MEMRESIFG10_S 18U

§ ADC_INTEVT2SET_MEMRESIFG10_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG10_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG10_SET

#define ADC_INTEVT2SET_MEMRESIFG10_SET 0x00040000U

§ ADC_INTEVT2SET_MEMRESIFG11

#define ADC_INTEVT2SET_MEMRESIFG11 0x00080000U

§ ADC_INTEVT2SET_MEMRESIFG11_M

#define ADC_INTEVT2SET_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT2SET_MEMRESIFG11_S

#define ADC_INTEVT2SET_MEMRESIFG11_S 19U

§ ADC_INTEVT2SET_MEMRESIFG11_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG11_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG11_SET

#define ADC_INTEVT2SET_MEMRESIFG11_SET 0x00080000U

§ ADC_INTEVT2SET_MEMRESIFG12

#define ADC_INTEVT2SET_MEMRESIFG12 0x00100000U

§ ADC_INTEVT2SET_MEMRESIFG12_M

#define ADC_INTEVT2SET_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT2SET_MEMRESIFG12_S

#define ADC_INTEVT2SET_MEMRESIFG12_S 20U

§ ADC_INTEVT2SET_MEMRESIFG12_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG12_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG12_SET

#define ADC_INTEVT2SET_MEMRESIFG12_SET 0x00100000U

§ ADC_INTEVT2SET_MEMRESIFG13

#define ADC_INTEVT2SET_MEMRESIFG13 0x00200000U

§ ADC_INTEVT2SET_MEMRESIFG13_M

#define ADC_INTEVT2SET_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT2SET_MEMRESIFG13_S

#define ADC_INTEVT2SET_MEMRESIFG13_S 21U

§ ADC_INTEVT2SET_MEMRESIFG13_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG13_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG13_SET

#define ADC_INTEVT2SET_MEMRESIFG13_SET 0x00200000U

§ ADC_INTEVT2SET_MEMRESIFG14

#define ADC_INTEVT2SET_MEMRESIFG14 0x00400000U

§ ADC_INTEVT2SET_MEMRESIFG14_M

#define ADC_INTEVT2SET_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT2SET_MEMRESIFG14_S

#define ADC_INTEVT2SET_MEMRESIFG14_S 22U

§ ADC_INTEVT2SET_MEMRESIFG14_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG14_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG14_SET

#define ADC_INTEVT2SET_MEMRESIFG14_SET 0x00400000U

§ ADC_INTEVT2SET_MEMRESIFG15

#define ADC_INTEVT2SET_MEMRESIFG15 0x00800000U

§ ADC_INTEVT2SET_MEMRESIFG15_M

#define ADC_INTEVT2SET_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT2SET_MEMRESIFG15_S

#define ADC_INTEVT2SET_MEMRESIFG15_S 23U

§ ADC_INTEVT2SET_MEMRESIFG15_NO_EFFECT

#define ADC_INTEVT2SET_MEMRESIFG15_NO_EFFECT 0x00000000U

§ ADC_INTEVT2SET_MEMRESIFG15_SET

#define ADC_INTEVT2SET_MEMRESIFG15_SET 0x00800000U

§ ADC_INTEVT2CLR_MEMRESIFG0

#define ADC_INTEVT2CLR_MEMRESIFG0 0x00000100U

§ ADC_INTEVT2CLR_MEMRESIFG0_M

#define ADC_INTEVT2CLR_MEMRESIFG0_M 0x00000100U

§ ADC_INTEVT2CLR_MEMRESIFG0_S

#define ADC_INTEVT2CLR_MEMRESIFG0_S 8U

§ ADC_INTEVT2CLR_MEMRESIFG0_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG0_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG0_CLR

#define ADC_INTEVT2CLR_MEMRESIFG0_CLR 0x00000100U

§ ADC_INTEVT2CLR_MEMRESIFG1

#define ADC_INTEVT2CLR_MEMRESIFG1 0x00000200U

§ ADC_INTEVT2CLR_MEMRESIFG1_M

#define ADC_INTEVT2CLR_MEMRESIFG1_M 0x00000200U

§ ADC_INTEVT2CLR_MEMRESIFG1_S

#define ADC_INTEVT2CLR_MEMRESIFG1_S 9U

§ ADC_INTEVT2CLR_MEMRESIFG1_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG1_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG1_CLR

#define ADC_INTEVT2CLR_MEMRESIFG1_CLR 0x00000200U

§ ADC_INTEVT2CLR_MEMRESIFG2

#define ADC_INTEVT2CLR_MEMRESIFG2 0x00000400U

§ ADC_INTEVT2CLR_MEMRESIFG2_M

#define ADC_INTEVT2CLR_MEMRESIFG2_M 0x00000400U

§ ADC_INTEVT2CLR_MEMRESIFG2_S

#define ADC_INTEVT2CLR_MEMRESIFG2_S 10U

§ ADC_INTEVT2CLR_MEMRESIFG2_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG2_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG2_CLR

#define ADC_INTEVT2CLR_MEMRESIFG2_CLR 0x00000400U

§ ADC_INTEVT2CLR_MEMRESIFG3

#define ADC_INTEVT2CLR_MEMRESIFG3 0x00000800U

§ ADC_INTEVT2CLR_MEMRESIFG3_M

#define ADC_INTEVT2CLR_MEMRESIFG3_M 0x00000800U

§ ADC_INTEVT2CLR_MEMRESIFG3_S

#define ADC_INTEVT2CLR_MEMRESIFG3_S 11U

§ ADC_INTEVT2CLR_MEMRESIFG3_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG3_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG3_CLR

#define ADC_INTEVT2CLR_MEMRESIFG3_CLR 0x00000800U

§ ADC_INTEVT2CLR_MEMRESIFG4

#define ADC_INTEVT2CLR_MEMRESIFG4 0x00001000U

§ ADC_INTEVT2CLR_MEMRESIFG4_M

#define ADC_INTEVT2CLR_MEMRESIFG4_M 0x00001000U

§ ADC_INTEVT2CLR_MEMRESIFG4_S

#define ADC_INTEVT2CLR_MEMRESIFG4_S 12U

§ ADC_INTEVT2CLR_MEMRESIFG4_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG4_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG4_CLR

#define ADC_INTEVT2CLR_MEMRESIFG4_CLR 0x00001000U

§ ADC_INTEVT2CLR_MEMRESIFG5

#define ADC_INTEVT2CLR_MEMRESIFG5 0x00002000U

§ ADC_INTEVT2CLR_MEMRESIFG5_M

#define ADC_INTEVT2CLR_MEMRESIFG5_M 0x00002000U

§ ADC_INTEVT2CLR_MEMRESIFG5_S

#define ADC_INTEVT2CLR_MEMRESIFG5_S 13U

§ ADC_INTEVT2CLR_MEMRESIFG5_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG5_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG5_CLR

#define ADC_INTEVT2CLR_MEMRESIFG5_CLR 0x00002000U

§ ADC_INTEVT2CLR_MEMRESIFG6

#define ADC_INTEVT2CLR_MEMRESIFG6 0x00004000U

§ ADC_INTEVT2CLR_MEMRESIFG6_M

#define ADC_INTEVT2CLR_MEMRESIFG6_M 0x00004000U

§ ADC_INTEVT2CLR_MEMRESIFG6_S

#define ADC_INTEVT2CLR_MEMRESIFG6_S 14U

§ ADC_INTEVT2CLR_MEMRESIFG6_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG6_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG6_CLR

#define ADC_INTEVT2CLR_MEMRESIFG6_CLR 0x00004000U

§ ADC_INTEVT2CLR_MEMRESIFG7

#define ADC_INTEVT2CLR_MEMRESIFG7 0x00008000U

§ ADC_INTEVT2CLR_MEMRESIFG7_M

#define ADC_INTEVT2CLR_MEMRESIFG7_M 0x00008000U

§ ADC_INTEVT2CLR_MEMRESIFG7_S

#define ADC_INTEVT2CLR_MEMRESIFG7_S 15U

§ ADC_INTEVT2CLR_MEMRESIFG7_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG7_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG7_CLR

#define ADC_INTEVT2CLR_MEMRESIFG7_CLR 0x00008000U

§ ADC_INTEVT2CLR_MEMRESIFG8

#define ADC_INTEVT2CLR_MEMRESIFG8 0x00010000U

§ ADC_INTEVT2CLR_MEMRESIFG8_M

#define ADC_INTEVT2CLR_MEMRESIFG8_M 0x00010000U

§ ADC_INTEVT2CLR_MEMRESIFG8_S

#define ADC_INTEVT2CLR_MEMRESIFG8_S 16U

§ ADC_INTEVT2CLR_MEMRESIFG8_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG8_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG8_CLR

#define ADC_INTEVT2CLR_MEMRESIFG8_CLR 0x00010000U

§ ADC_INTEVT2CLR_MEMRESIFG9

#define ADC_INTEVT2CLR_MEMRESIFG9 0x00020000U

§ ADC_INTEVT2CLR_MEMRESIFG9_M

#define ADC_INTEVT2CLR_MEMRESIFG9_M 0x00020000U

§ ADC_INTEVT2CLR_MEMRESIFG9_S

#define ADC_INTEVT2CLR_MEMRESIFG9_S 17U

§ ADC_INTEVT2CLR_MEMRESIFG9_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG9_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG9_CLR

#define ADC_INTEVT2CLR_MEMRESIFG9_CLR 0x00020000U

§ ADC_INTEVT2CLR_MEMRESIFG10

#define ADC_INTEVT2CLR_MEMRESIFG10 0x00040000U

§ ADC_INTEVT2CLR_MEMRESIFG10_M

#define ADC_INTEVT2CLR_MEMRESIFG10_M 0x00040000U

§ ADC_INTEVT2CLR_MEMRESIFG10_S

#define ADC_INTEVT2CLR_MEMRESIFG10_S 18U

§ ADC_INTEVT2CLR_MEMRESIFG10_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG10_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG10_CLR

#define ADC_INTEVT2CLR_MEMRESIFG10_CLR 0x00040000U

§ ADC_INTEVT2CLR_MEMRESIFG11

#define ADC_INTEVT2CLR_MEMRESIFG11 0x00080000U

§ ADC_INTEVT2CLR_MEMRESIFG11_M

#define ADC_INTEVT2CLR_MEMRESIFG11_M 0x00080000U

§ ADC_INTEVT2CLR_MEMRESIFG11_S

#define ADC_INTEVT2CLR_MEMRESIFG11_S 19U

§ ADC_INTEVT2CLR_MEMRESIFG11_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG11_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG11_CLR

#define ADC_INTEVT2CLR_MEMRESIFG11_CLR 0x00080000U

§ ADC_INTEVT2CLR_MEMRESIFG12

#define ADC_INTEVT2CLR_MEMRESIFG12 0x00100000U

§ ADC_INTEVT2CLR_MEMRESIFG12_M

#define ADC_INTEVT2CLR_MEMRESIFG12_M 0x00100000U

§ ADC_INTEVT2CLR_MEMRESIFG12_S

#define ADC_INTEVT2CLR_MEMRESIFG12_S 20U

§ ADC_INTEVT2CLR_MEMRESIFG12_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG12_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG12_CLR

#define ADC_INTEVT2CLR_MEMRESIFG12_CLR 0x00100000U

§ ADC_INTEVT2CLR_MEMRESIFG13

#define ADC_INTEVT2CLR_MEMRESIFG13 0x00200000U

§ ADC_INTEVT2CLR_MEMRESIFG13_M

#define ADC_INTEVT2CLR_MEMRESIFG13_M 0x00200000U

§ ADC_INTEVT2CLR_MEMRESIFG13_S

#define ADC_INTEVT2CLR_MEMRESIFG13_S 21U

§ ADC_INTEVT2CLR_MEMRESIFG13_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG13_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG13_CLR

#define ADC_INTEVT2CLR_MEMRESIFG13_CLR 0x00200000U

§ ADC_INTEVT2CLR_MEMRESIFG14

#define ADC_INTEVT2CLR_MEMRESIFG14 0x00400000U

§ ADC_INTEVT2CLR_MEMRESIFG14_M

#define ADC_INTEVT2CLR_MEMRESIFG14_M 0x00400000U

§ ADC_INTEVT2CLR_MEMRESIFG14_S

#define ADC_INTEVT2CLR_MEMRESIFG14_S 22U

§ ADC_INTEVT2CLR_MEMRESIFG14_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG14_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG14_CLR

#define ADC_INTEVT2CLR_MEMRESIFG14_CLR 0x00400000U

§ ADC_INTEVT2CLR_MEMRESIFG15

#define ADC_INTEVT2CLR_MEMRESIFG15 0x00800000U

§ ADC_INTEVT2CLR_MEMRESIFG15_M

#define ADC_INTEVT2CLR_MEMRESIFG15_M 0x00800000U

§ ADC_INTEVT2CLR_MEMRESIFG15_S

#define ADC_INTEVT2CLR_MEMRESIFG15_S 23U

§ ADC_INTEVT2CLR_MEMRESIFG15_NO_EFFECT

#define ADC_INTEVT2CLR_MEMRESIFG15_NO_EFFECT 0x00000000U

§ ADC_INTEVT2CLR_MEMRESIFG15_CLR

#define ADC_INTEVT2CLR_MEMRESIFG15_CLR 0x00800000U

§ ADC_EVTMOD_INT0CFG_W

#define ADC_EVTMOD_INT0CFG_W 2U

§ ADC_EVTMOD_INT0CFG_M

#define ADC_EVTMOD_INT0CFG_M 0x00000003U

§ ADC_EVTMOD_INT0CFG_S

#define ADC_EVTMOD_INT0CFG_S 0U

§ ADC_EVTMOD_INT0CFG_DISABLE

#define ADC_EVTMOD_INT0CFG_DISABLE 0x00000000U

§ ADC_EVTMOD_INT0CFG_SOFTWARE

#define ADC_EVTMOD_INT0CFG_SOFTWARE 0x00000001U

§ ADC_EVTMOD_INT0CFG_HARDWARE

#define ADC_EVTMOD_INT0CFG_HARDWARE 0x00000002U

§ ADC_EVTMOD_EVT1CFG_W

#define ADC_EVTMOD_EVT1CFG_W 2U

§ ADC_EVTMOD_EVT1CFG_M

#define ADC_EVTMOD_EVT1CFG_M 0x0000000CU

§ ADC_EVTMOD_EVT1CFG_S

#define ADC_EVTMOD_EVT1CFG_S 2U

§ ADC_EVTMOD_EVT1CFG_DISABLE

#define ADC_EVTMOD_EVT1CFG_DISABLE 0x00000000U

§ ADC_EVTMOD_EVT1CFG_SOFTWARE

#define ADC_EVTMOD_EVT1CFG_SOFTWARE 0x00000004U

§ ADC_EVTMOD_EVT1CFG_HARDWARE

#define ADC_EVTMOD_EVT1CFG_HARDWARE 0x00000008U

§ ADC_DESC_MINREV_W

#define ADC_DESC_MINREV_W 4U

§ ADC_DESC_MINREV_M

#define ADC_DESC_MINREV_M 0x0000000FU

§ ADC_DESC_MINREV_S

#define ADC_DESC_MINREV_S 0U

§ ADC_DESC_MINREV_MINIMUM

#define ADC_DESC_MINREV_MINIMUM 0x00000000U

§ ADC_DESC_MINREV_MAXIMUM

#define ADC_DESC_MINREV_MAXIMUM 0x0000000FU

§ ADC_DESC_MAJREV_W

#define ADC_DESC_MAJREV_W 4U

§ ADC_DESC_MAJREV_M

#define ADC_DESC_MAJREV_M 0x000000F0U

§ ADC_DESC_MAJREV_S

#define ADC_DESC_MAJREV_S 4U

§ ADC_DESC_MAJREV_MINIMUM

#define ADC_DESC_MAJREV_MINIMUM 0x00000000U

§ ADC_DESC_MAJREV_MAXIMUM

#define ADC_DESC_MAJREV_MAXIMUM 0x000000F0U

§ ADC_DESC_INSTNUM_W

#define ADC_DESC_INSTNUM_W 4U

§ ADC_DESC_INSTNUM_M

#define ADC_DESC_INSTNUM_M 0x00000F00U

§ ADC_DESC_INSTNUM_S

#define ADC_DESC_INSTNUM_S 8U

§ ADC_DESC_FEATUREVER_W

#define ADC_DESC_FEATUREVER_W 4U

§ ADC_DESC_FEATUREVER_M

#define ADC_DESC_FEATUREVER_M 0x0000F000U

§ ADC_DESC_FEATUREVER_S

#define ADC_DESC_FEATUREVER_S 12U

§ ADC_DESC_FEATUREVER_MINIMUM

#define ADC_DESC_FEATUREVER_MINIMUM 0x00000000U

§ ADC_DESC_FEATUREVER_MAXIMUM

#define ADC_DESC_FEATUREVER_MAXIMUM 0x0000F000U

§ ADC_DESC_MODULEID_W

#define ADC_DESC_MODULEID_W 16U

§ ADC_DESC_MODULEID_M

#define ADC_DESC_MODULEID_M 0xFFFF0000U

§ ADC_DESC_MODULEID_S

#define ADC_DESC_MODULEID_S 16U

§ ADC_DESC_MODULEID_MINIMUM

#define ADC_DESC_MODULEID_MINIMUM 0x00000000U

§ ADC_DESC_MODULEID_MAXIMUM

#define ADC_DESC_MODULEID_MAXIMUM 0xFFFF0000U

§ ADC_CTL0_ENC

#define ADC_CTL0_ENC 0x00000001U

§ ADC_CTL0_ENC_M

#define ADC_CTL0_ENC_M 0x00000001U

Referenced by ADCDisableConversion().

§ ADC_CTL0_ENC_S

#define ADC_CTL0_ENC_S 0U

§ ADC_CTL0_ENC_OFF

#define ADC_CTL0_ENC_OFF 0x00000000U

§ ADC_CTL0_ENC_ON

#define ADC_CTL0_ENC_ON 0x00000001U

Referenced by ADCEnableConversion().

§ ADC_CTL0_PWRDN

#define ADC_CTL0_PWRDN 0x00010000U

§ ADC_CTL0_PWRDN_M

#define ADC_CTL0_PWRDN_M 0x00010000U

Referenced by ADCSetPowerDownPolicy().

§ ADC_CTL0_PWRDN_S

#define ADC_CTL0_PWRDN_S 16U

§ ADC_CTL0_PWRDN_AUTO

#define ADC_CTL0_PWRDN_AUTO 0x00000000U

§ ADC_CTL0_PWRDN_MANUAL

#define ADC_CTL0_PWRDN_MANUAL 0x00010000U

§ ADC_CTL0_SCLKDIV_W

#define ADC_CTL0_SCLKDIV_W 3U

§ ADC_CTL0_SCLKDIV_M

#define ADC_CTL0_SCLKDIV_M 0x07000000U

Referenced by ADCSetSampleDuration().

§ ADC_CTL0_SCLKDIV_S

#define ADC_CTL0_SCLKDIV_S 24U

§ ADC_CTL0_SCLKDIV_DIV_BY_1

#define ADC_CTL0_SCLKDIV_DIV_BY_1 0x00000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_2

#define ADC_CTL0_SCLKDIV_DIV_BY_2 0x01000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_4

#define ADC_CTL0_SCLKDIV_DIV_BY_4 0x02000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_8

#define ADC_CTL0_SCLKDIV_DIV_BY_8 0x03000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_16

#define ADC_CTL0_SCLKDIV_DIV_BY_16 0x04000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_24

#define ADC_CTL0_SCLKDIV_DIV_BY_24 0x05000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_32

#define ADC_CTL0_SCLKDIV_DIV_BY_32 0x06000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_48

#define ADC_CTL0_SCLKDIV_DIV_BY_48 0x07000000U

§ ADC_CTL1_TRIGSRC

#define ADC_CTL1_TRIGSRC 0x00000001U

§ ADC_CTL1_TRIGSRC_M

#define ADC_CTL1_TRIGSRC_M 0x00000001U

Referenced by ADCSetTriggerSource().

§ ADC_CTL1_TRIGSRC_S

#define ADC_CTL1_TRIGSRC_S 0U

§ ADC_CTL1_TRIGSRC_SOFTWARE

#define ADC_CTL1_TRIGSRC_SOFTWARE 0x00000000U

§ ADC_CTL1_TRIGSRC_EVENT

#define ADC_CTL1_TRIGSRC_EVENT 0x00000001U

§ ADC_CTL1_SC

#define ADC_CTL1_SC 0x00000100U

§ ADC_CTL1_SC_M

#define ADC_CTL1_SC_M 0x00000100U

Referenced by ADCSetTriggerSource(), and ADCStopConversion().

§ ADC_CTL1_SC_S

#define ADC_CTL1_SC_S 8U

§ ADC_CTL1_SC_START

#define ADC_CTL1_SC_START 0x00000100U

Referenced by ADCStartConversion().

§ ADC_CTL1_SC_STOP

#define ADC_CTL1_SC_STOP 0x00000000U

§ ADC_CTL1_CONSEQ_W

#define ADC_CTL1_CONSEQ_W 2U

§ ADC_CTL1_CONSEQ_M

#define ADC_CTL1_CONSEQ_M 0x00030000U

Referenced by ADCSetSequence().

§ ADC_CTL1_CONSEQ_S

#define ADC_CTL1_CONSEQ_S 16U

§ ADC_CTL1_CONSEQ_SINGLE

#define ADC_CTL1_CONSEQ_SINGLE 0x00000000U

§ ADC_CTL1_CONSEQ_SEQUENCE

#define ADC_CTL1_CONSEQ_SEQUENCE 0x00010000U

§ ADC_CTL1_CONSEQ_REPEATSINGLE

#define ADC_CTL1_CONSEQ_REPEATSINGLE 0x00020000U

§ ADC_CTL1_CONSEQ_REPEATSEQUENCE

#define ADC_CTL1_CONSEQ_REPEATSEQUENCE 0x00030000U

§ ADC_CTL1_SAMPMODE

#define ADC_CTL1_SAMPMODE 0x00100000U

§ ADC_CTL1_SAMPMODE_M

#define ADC_CTL1_SAMPMODE_M 0x00100000U

Referenced by ADCSetSamplingMode().

§ ADC_CTL1_SAMPMODE_S

#define ADC_CTL1_SAMPMODE_S 20U

§ ADC_CTL1_SAMPMODE_AUTO

#define ADC_CTL1_SAMPMODE_AUTO 0x00000000U

§ ADC_CTL1_SAMPMODE_MANUAL

#define ADC_CTL1_SAMPMODE_MANUAL 0x00100000U

§ ADC_CTL1_AVGN_W

#define ADC_CTL1_AVGN_W 3U

§ ADC_CTL1_AVGN_M

#define ADC_CTL1_AVGN_M 0x07000000U

§ ADC_CTL1_AVGN_S

#define ADC_CTL1_AVGN_S 24U

§ ADC_CTL1_AVGN_DISABLE

#define ADC_CTL1_AVGN_DISABLE 0x00000000U

§ ADC_CTL1_AVGN_AVG_2

#define ADC_CTL1_AVGN_AVG_2 0x01000000U

§ ADC_CTL1_AVGN_AVG_4

#define ADC_CTL1_AVGN_AVG_4 0x02000000U

§ ADC_CTL1_AVGN_AVG_8

#define ADC_CTL1_AVGN_AVG_8 0x03000000U

§ ADC_CTL1_AVGN_AVG_16

#define ADC_CTL1_AVGN_AVG_16 0x04000000U

§ ADC_CTL1_AVGN_AVG_32

#define ADC_CTL1_AVGN_AVG_32 0x05000000U

§ ADC_CTL1_AVGN_AVG_64

#define ADC_CTL1_AVGN_AVG_64 0x06000000U

§ ADC_CTL1_AVGN_AVG_128

#define ADC_CTL1_AVGN_AVG_128 0x07000000U

§ ADC_CTL1_AVGD_W

#define ADC_CTL1_AVGD_W 3U

§ ADC_CTL1_AVGD_M

#define ADC_CTL1_AVGD_M 0x70000000U

§ ADC_CTL1_AVGD_S

#define ADC_CTL1_AVGD_S 28U

§ ADC_CTL1_AVGD_SHIFT0

#define ADC_CTL1_AVGD_SHIFT0 0x00000000U

§ ADC_CTL1_AVGD_SHIFT1

#define ADC_CTL1_AVGD_SHIFT1 0x10000000U

§ ADC_CTL1_AVGD_SHIFT2

#define ADC_CTL1_AVGD_SHIFT2 0x20000000U

§ ADC_CTL1_AVGD_SHIFT3

#define ADC_CTL1_AVGD_SHIFT3 0x30000000U

§ ADC_CTL1_AVGD_SHIFT4

#define ADC_CTL1_AVGD_SHIFT4 0x40000000U

§ ADC_CTL1_AVGD_SHIFT5

#define ADC_CTL1_AVGD_SHIFT5 0x50000000U

§ ADC_CTL1_AVGD_SHIFT6

#define ADC_CTL1_AVGD_SHIFT6 0x60000000U

§ ADC_CTL1_AVGD_SHIFT7

#define ADC_CTL1_AVGD_SHIFT7 0x70000000U

§ ADC_CTL2_DF

#define ADC_CTL2_DF 0x00000001U

§ ADC_CTL2_DF_M

#define ADC_CTL2_DF_M 0x00000001U

§ ADC_CTL2_DF_S

#define ADC_CTL2_DF_S 0U

§ ADC_CTL2_DF_UNSIGNED

#define ADC_CTL2_DF_UNSIGNED 0x00000000U

§ ADC_CTL2_DF_SIGNED

#define ADC_CTL2_DF_SIGNED 0x00000001U

§ ADC_CTL2_RES_W

#define ADC_CTL2_RES_W 2U

§ ADC_CTL2_RES_M

#define ADC_CTL2_RES_M 0x00000006U

§ ADC_CTL2_RES_S

#define ADC_CTL2_RES_S 1U

§ ADC_CTL2_RES_BIT_12

#define ADC_CTL2_RES_BIT_12 0x00000000U

§ ADC_CTL2_DMAEN

#define ADC_CTL2_DMAEN 0x00000100U

§ ADC_CTL2_DMAEN_M

#define ADC_CTL2_DMAEN_M 0x00000100U

Referenced by ADCDisableDmaTrigger().

§ ADC_CTL2_DMAEN_S

#define ADC_CTL2_DMAEN_S 8U

§ ADC_CTL2_DMAEN_DISABLE

#define ADC_CTL2_DMAEN_DISABLE 0x00000000U

§ ADC_CTL2_DMAEN_ENABLE

#define ADC_CTL2_DMAEN_ENABLE 0x00000100U

Referenced by ADCEnableDmaTrigger().

§ ADC_CTL2_FIFOEN

#define ADC_CTL2_FIFOEN 0x00000400U

§ ADC_CTL2_FIFOEN_M

#define ADC_CTL2_FIFOEN_M 0x00000400U

§ ADC_CTL2_FIFOEN_S

#define ADC_CTL2_FIFOEN_S 10U

§ ADC_CTL2_FIFOEN_ENABLE

#define ADC_CTL2_FIFOEN_ENABLE 0x00000400U

§ ADC_CTL2_FIFOEN_DISABLE

#define ADC_CTL2_FIFOEN_DISABLE 0x00000000U

§ ADC_CTL2_STARTADD_W

#define ADC_CTL2_STARTADD_W 5U

§ ADC_CTL2_STARTADD_M

#define ADC_CTL2_STARTADD_M 0x001F0000U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_STARTADD_S

#define ADC_CTL2_STARTADD_S 16U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_STARTADD_ADDR_00

#define ADC_CTL2_STARTADD_ADDR_00 0x00000000U

§ ADC_CTL2_STARTADD_ADDR_01

#define ADC_CTL2_STARTADD_ADDR_01 0x00010000U

§ ADC_CTL2_STARTADD_ADDR_02

#define ADC_CTL2_STARTADD_ADDR_02 0x00020000U

§ ADC_CTL2_STARTADD_ADDR_03

#define ADC_CTL2_STARTADD_ADDR_03 0x00030000U

§ ADC_CTL2_STARTADD_ADDR_04

#define ADC_CTL2_STARTADD_ADDR_04 0x00040000U

§ ADC_CTL2_STARTADD_ADDR_05

#define ADC_CTL2_STARTADD_ADDR_05 0x00050000U

§ ADC_CTL2_STARTADD_ADDR_06

#define ADC_CTL2_STARTADD_ADDR_06 0x00060000U

§ ADC_CTL2_STARTADD_ADDR_07

#define ADC_CTL2_STARTADD_ADDR_07 0x00070000U

§ ADC_CTL2_STARTADD_ADDR_08

#define ADC_CTL2_STARTADD_ADDR_08 0x00080000U

§ ADC_CTL2_STARTADD_ADDR_09

#define ADC_CTL2_STARTADD_ADDR_09 0x00090000U

§ ADC_CTL2_STARTADD_ADDR_10

#define ADC_CTL2_STARTADD_ADDR_10 0x000A0000U

§ ADC_CTL2_STARTADD_ADDR_11

#define ADC_CTL2_STARTADD_ADDR_11 0x000B0000U

§ ADC_CTL2_STARTADD_ADDR_12

#define ADC_CTL2_STARTADD_ADDR_12 0x000C0000U

§ ADC_CTL2_STARTADD_ADDR_13

#define ADC_CTL2_STARTADD_ADDR_13 0x000D0000U

§ ADC_CTL2_STARTADD_ADDR_14

#define ADC_CTL2_STARTADD_ADDR_14 0x000E0000U

§ ADC_CTL2_STARTADD_ADDR_15

#define ADC_CTL2_STARTADD_ADDR_15 0x000F0000U

§ ADC_CTL2_STARTADD_ADDR_16

#define ADC_CTL2_STARTADD_ADDR_16 0x00100000U

§ ADC_CTL2_STARTADD_ADDR_17

#define ADC_CTL2_STARTADD_ADDR_17 0x00110000U

§ ADC_CTL2_STARTADD_ADDR_18

#define ADC_CTL2_STARTADD_ADDR_18 0x00120000U

§ ADC_CTL2_STARTADD_ADDR_19

#define ADC_CTL2_STARTADD_ADDR_19 0x00130000U

§ ADC_CTL2_STARTADD_ADDR_20

#define ADC_CTL2_STARTADD_ADDR_20 0x00140000U

§ ADC_CTL2_STARTADD_ADDR_21

#define ADC_CTL2_STARTADD_ADDR_21 0x00150000U

§ ADC_CTL2_STARTADD_ADDR_22

#define ADC_CTL2_STARTADD_ADDR_22 0x00160000U

§ ADC_CTL2_STARTADD_ADDR_23

#define ADC_CTL2_STARTADD_ADDR_23 0x00170000U

§ ADC_CTL2_STARTADD_ADDR_24

#define ADC_CTL2_STARTADD_ADDR_24 0x00180000U

§ ADC_CTL2_STARTADD_ADDR_25

#define ADC_CTL2_STARTADD_ADDR_25 0x00190000U

§ ADC_CTL2_STARTADD_ADDR_26

#define ADC_CTL2_STARTADD_ADDR_26 0x001A0000U

§ ADC_CTL2_STARTADD_ADDR_31

#define ADC_CTL2_STARTADD_ADDR_31 0x001F0000U

§ ADC_CTL2_STARTADD_ADDR_30

#define ADC_CTL2_STARTADD_ADDR_30 0x001E0000U

§ ADC_CTL2_STARTADD_ADDR_29

#define ADC_CTL2_STARTADD_ADDR_29 0x001D0000U

§ ADC_CTL2_STARTADD_ADDR_28

#define ADC_CTL2_STARTADD_ADDR_28 0x001C0000U

§ ADC_CTL2_STARTADD_ADDR_27

#define ADC_CTL2_STARTADD_ADDR_27 0x001B0000U

§ ADC_CTL2_ENDADD_W

#define ADC_CTL2_ENDADD_W 5U

§ ADC_CTL2_ENDADD_M

#define ADC_CTL2_ENDADD_M 0x1F000000U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_ENDADD_S

#define ADC_CTL2_ENDADD_S 24U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_ENDADD_ADDR_00

#define ADC_CTL2_ENDADD_ADDR_00 0x00000000U

§ ADC_CTL2_ENDADD_ADDR_01

#define ADC_CTL2_ENDADD_ADDR_01 0x01000000U

§ ADC_CTL2_ENDADD_ADDR_02

#define ADC_CTL2_ENDADD_ADDR_02 0x02000000U

§ ADC_CTL2_ENDADD_ADDR_03

#define ADC_CTL2_ENDADD_ADDR_03 0x03000000U

§ ADC_CTL2_ENDADD_ADDR_04

#define ADC_CTL2_ENDADD_ADDR_04 0x04000000U

§ ADC_CTL2_ENDADD_ADDR_05

#define ADC_CTL2_ENDADD_ADDR_05 0x05000000U

§ ADC_CTL2_ENDADD_ADDR_06

#define ADC_CTL2_ENDADD_ADDR_06 0x06000000U

§ ADC_CTL2_ENDADD_ADDR_07

#define ADC_CTL2_ENDADD_ADDR_07 0x07000000U

§ ADC_CTL2_ENDADD_ADDR_08

#define ADC_CTL2_ENDADD_ADDR_08 0x08000000U

§ ADC_CTL2_ENDADD_ADDR_09

#define ADC_CTL2_ENDADD_ADDR_09 0x09000000U

§ ADC_CTL2_ENDADD_ADDR_10

#define ADC_CTL2_ENDADD_ADDR_10 0x0A000000U

§ ADC_CTL2_ENDADD_ADDR_11

#define ADC_CTL2_ENDADD_ADDR_11 0x0B000000U

§ ADC_CTL2_ENDADD_ADDR_12

#define ADC_CTL2_ENDADD_ADDR_12 0x0C000000U

§ ADC_CTL2_ENDADD_ADDR_13

#define ADC_CTL2_ENDADD_ADDR_13 0x0D000000U

§ ADC_CTL2_ENDADD_ADDR_14

#define ADC_CTL2_ENDADD_ADDR_14 0x0E000000U

§ ADC_CTL2_ENDADD_ADDR_15

#define ADC_CTL2_ENDADD_ADDR_15 0x0F000000U

§ ADC_CTL2_ENDADD_ADDR_16

#define ADC_CTL2_ENDADD_ADDR_16 0x10000000U

§ ADC_CTL2_ENDADD_ADDR_17

#define ADC_CTL2_ENDADD_ADDR_17 0x11000000U

§ ADC_CTL2_ENDADD_ADDR_18

#define ADC_CTL2_ENDADD_ADDR_18 0x12000000U

§ ADC_CTL2_ENDADD_ADDR_19

#define ADC_CTL2_ENDADD_ADDR_19 0x13000000U

§ ADC_CTL2_ENDADD_ADDR_20

#define ADC_CTL2_ENDADD_ADDR_20 0x14000000U

§ ADC_CTL2_ENDADD_ADDR_21

#define ADC_CTL2_ENDADD_ADDR_21 0x15000000U

§ ADC_CTL2_ENDADD_ADDR_22

#define ADC_CTL2_ENDADD_ADDR_22 0x16000000U

§ ADC_CTL2_ENDADD_ADDR_23

#define ADC_CTL2_ENDADD_ADDR_23 0x17000000U

§ ADC_CTL2_ENDADD_ADDR_24

#define ADC_CTL2_ENDADD_ADDR_24 0x18000000U

§ ADC_CTL2_ENDADD_ADDR_25

#define ADC_CTL2_ENDADD_ADDR_25 0x19000000U

§ ADC_CTL2_ENDADD_ADDR_26

#define ADC_CTL2_ENDADD_ADDR_26 0x1A000000U

§ ADC_CTL2_ENDADD_ADDR_27

#define ADC_CTL2_ENDADD_ADDR_27 0x1B000000U

§ ADC_CTL2_ENDADD_ADDR_28

#define ADC_CTL2_ENDADD_ADDR_28 0x1C000000U

§ ADC_CTL2_ENDADD_ADDR_29

#define ADC_CTL2_ENDADD_ADDR_29 0x1D000000U

§ ADC_CTL2_ENDADD_ADDR_30

#define ADC_CTL2_ENDADD_ADDR_30 0x1E000000U

§ ADC_CTL2_ENDADD_ADDR_31

#define ADC_CTL2_ENDADD_ADDR_31 0x1F000000U

§ ADC_CTL3_ASCCHSEL_W

#define ADC_CTL3_ASCCHSEL_W 5U

§ ADC_CTL3_ASCCHSEL_M

#define ADC_CTL3_ASCCHSEL_M 0x0000001FU

§ ADC_CTL3_ASCCHSEL_S

#define ADC_CTL3_ASCCHSEL_S 0U

§ ADC_CTL3_ASCCHSEL_CHAN_0

#define ADC_CTL3_ASCCHSEL_CHAN_0 0x00000000U

§ ADC_CTL3_ASCCHSEL_CHAN_1

#define ADC_CTL3_ASCCHSEL_CHAN_1 0x00000001U

§ ADC_CTL3_ASCCHSEL_CHAN_2

#define ADC_CTL3_ASCCHSEL_CHAN_2 0x00000002U

§ ADC_CTL3_ASCCHSEL_CHAN_3

#define ADC_CTL3_ASCCHSEL_CHAN_3 0x00000003U

§ ADC_CTL3_ASCCHSEL_CHAN_4

#define ADC_CTL3_ASCCHSEL_CHAN_4 0x00000004U

§ ADC_CTL3_ASCCHSEL_CHAN_5

#define ADC_CTL3_ASCCHSEL_CHAN_5 0x00000005U

§ ADC_CTL3_ASCCHSEL_CHAN_6

#define ADC_CTL3_ASCCHSEL_CHAN_6 0x00000006U

§ ADC_CTL3_ASCCHSEL_CHAN_7

#define ADC_CTL3_ASCCHSEL_CHAN_7 0x00000007U

§ ADC_CTL3_ASCCHSEL_CHAN_8

#define ADC_CTL3_ASCCHSEL_CHAN_8 0x00000008U

§ ADC_CTL3_ASCCHSEL_CHAN_9

#define ADC_CTL3_ASCCHSEL_CHAN_9 0x00000009U

§ ADC_CTL3_ASCCHSEL_CHAN_10

#define ADC_CTL3_ASCCHSEL_CHAN_10 0x0000000AU

§ ADC_CTL3_ASCCHSEL_CHAN_11

#define ADC_CTL3_ASCCHSEL_CHAN_11 0x0000000BU

§ ADC_CTL3_ASCCHSEL_CHAN_12

#define ADC_CTL3_ASCCHSEL_CHAN_12 0x0000000CU

§ ADC_CTL3_ASCCHSEL_CHAN_13

#define ADC_CTL3_ASCCHSEL_CHAN_13 0x0000000DU

§ ADC_CTL3_ASCCHSEL_CHAN_14

#define ADC_CTL3_ASCCHSEL_CHAN_14 0x0000000EU

§ ADC_CTL3_ASCCHSEL_CHAN_15

#define ADC_CTL3_ASCCHSEL_CHAN_15 0x0000000FU

§ ADC_CTL3_ASCCHSEL_CHAN_16

#define ADC_CTL3_ASCCHSEL_CHAN_16 0x00000010U

§ ADC_CTL3_ASCCHSEL_CHAN_17

#define ADC_CTL3_ASCCHSEL_CHAN_17 0x00000011U

§ ADC_CTL3_ASCCHSEL_CHAN_18

#define ADC_CTL3_ASCCHSEL_CHAN_18 0x00000012U

§ ADC_CTL3_ASCCHSEL_CHAN_19

#define ADC_CTL3_ASCCHSEL_CHAN_19 0x00000013U

§ ADC_CTL3_ASCCHSEL_CHAN_20

#define ADC_CTL3_ASCCHSEL_CHAN_20 0x00000014U

§ ADC_CTL3_ASCCHSEL_CHAN_21

#define ADC_CTL3_ASCCHSEL_CHAN_21 0x00000015U

§ ADC_CTL3_ASCCHSEL_CHAN_22

#define ADC_CTL3_ASCCHSEL_CHAN_22 0x00000016U

§ ADC_CTL3_ASCCHSEL_CHAN_23

#define ADC_CTL3_ASCCHSEL_CHAN_23 0x00000017U

§ ADC_CTL3_ASCCHSEL_CHAN_24

#define ADC_CTL3_ASCCHSEL_CHAN_24 0x00000018U

§ ADC_CTL3_ASCCHSEL_CHAN_25

#define ADC_CTL3_ASCCHSEL_CHAN_25 0x00000019U

§ ADC_CTL3_ASCCHSEL_CHAN_26

#define ADC_CTL3_ASCCHSEL_CHAN_26 0x0000001AU

§ ADC_CTL3_ASCCHSEL_CHAN_27

#define ADC_CTL3_ASCCHSEL_CHAN_27 0x0000001BU

§ ADC_CTL3_ASCCHSEL_CHAN_28

#define ADC_CTL3_ASCCHSEL_CHAN_28 0x0000001CU

§ ADC_CTL3_ASCCHSEL_CHAN_29

#define ADC_CTL3_ASCCHSEL_CHAN_29 0x0000001DU

§ ADC_CTL3_ASCCHSEL_CHAN_30

#define ADC_CTL3_ASCCHSEL_CHAN_30 0x0000001EU

§ ADC_CTL3_ASCCHSEL_CHAN_31

#define ADC_CTL3_ASCCHSEL_CHAN_31 0x0000001FU

§ ADC_CTL3_ASCSTIME

#define ADC_CTL3_ASCSTIME 0x00000100U

§ ADC_CTL3_ASCSTIME_M

#define ADC_CTL3_ASCSTIME_M 0x00000100U

§ ADC_CTL3_ASCSTIME_S

#define ADC_CTL3_ASCSTIME_S 8U

§ ADC_CTL3_ASCSTIME_SEL_SCOMP0

#define ADC_CTL3_ASCSTIME_SEL_SCOMP0 0x00000000U

§ ADC_CTL3_ASCSTIME_SEL_SCOMP1

#define ADC_CTL3_ASCSTIME_SEL_SCOMP1 0x00000100U

§ ADC_CTL3_ASCVRSEL_W

#define ADC_CTL3_ASCVRSEL_W 2U

§ ADC_CTL3_ASCVRSEL_M

#define ADC_CTL3_ASCVRSEL_M 0x00003000U

§ ADC_CTL3_ASCVRSEL_S

#define ADC_CTL3_ASCVRSEL_S 12U

§ ADC_CTL3_ASCVRSEL_EXTREF

#define ADC_CTL3_ASCVRSEL_EXTREF 0x00001000U

§ ADC_CTL3_ASCVRSEL_INTREF

#define ADC_CTL3_ASCVRSEL_INTREF 0x00002000U

§ ADC_CTL3_ASCFSR

#define ADC_CTL3_ASCFSR 0x00004000U

§ ADC_CTL3_ASCFSR_M

#define ADC_CTL3_ASCFSR_M 0x00004000U

§ ADC_CTL3_ASCFSR_S

#define ADC_CTL3_ASCFSR_S 14U

§ ADC_CTL3_ASCMODE

#define ADC_CTL3_ASCMODE 0x00008000U

§ ADC_CTL3_ASCMODE_M

#define ADC_CTL3_ASCMODE_M 0x00008000U

§ ADC_CTL3_ASCMODE_S

#define ADC_CTL3_ASCMODE_S 15U

§ ADC_CLKFREQ_FRANGE_W

#define ADC_CLKFREQ_FRANGE_W 3U

§ ADC_CLKFREQ_FRANGE_M

#define ADC_CLKFREQ_FRANGE_M 0x00000007U

§ ADC_CLKFREQ_FRANGE_S

#define ADC_CLKFREQ_FRANGE_S 0U

§ ADC_CLKFREQ_FRANGE_RANGE1TO4

#define ADC_CLKFREQ_FRANGE_RANGE1TO4 0x00000000U

§ ADC_CLKFREQ_FRANGE_RANGE4TO8

#define ADC_CLKFREQ_FRANGE_RANGE4TO8 0x00000001U

§ ADC_CLKFREQ_FRANGE_RANGE8TO16

#define ADC_CLKFREQ_FRANGE_RANGE8TO16 0x00000002U

§ ADC_CLKFREQ_FRANGE_RANGE16TO20

#define ADC_CLKFREQ_FRANGE_RANGE16TO20 0x00000003U

§ ADC_CLKFREQ_FRANGE_RANGE20TO24

#define ADC_CLKFREQ_FRANGE_RANGE20TO24 0x00000004U

§ ADC_CLKFREQ_FRANGE_RANGE24TO32

#define ADC_CLKFREQ_FRANGE_RANGE24TO32 0x00000005U

§ ADC_CLKFREQ_FRANGE_RANGE32TO40

#define ADC_CLKFREQ_FRANGE_RANGE32TO40 0x00000006U

§ ADC_CLKFREQ_FRANGE_RANGE40TO48

#define ADC_CLKFREQ_FRANGE_RANGE40TO48 0x00000007U

§ ADC_SCOMP0_SMP_W

#define ADC_SCOMP0_SMP_W 14U

§ ADC_SCOMP0_SMP_M

#define ADC_SCOMP0_SMP_M 0x00003FFFU

Referenced by ADCSetSampleDuration().

§ ADC_SCOMP0_SMP_S

#define ADC_SCOMP0_SMP_S 0U

§ ADC_SCOMP1_SMP_W

#define ADC_SCOMP1_SMP_W 14U

§ ADC_SCOMP1_SMP_M

#define ADC_SCOMP1_SMP_M 0x00003FFFU

§ ADC_SCOMP1_SMP_S

#define ADC_SCOMP1_SMP_S 0U

§ ADC_REFCFG_REFEN

#define ADC_REFCFG_REFEN 0x00000001U

§ ADC_REFCFG_REFEN_M

#define ADC_REFCFG_REFEN_M 0x00000001U

§ ADC_REFCFG_REFEN_S

#define ADC_REFCFG_REFEN_S 0U

§ ADC_REFCFG_REFEN_DISABLE

#define ADC_REFCFG_REFEN_DISABLE 0x00000000U

Referenced by ADCSetInput().

§ ADC_REFCFG_REFEN_ENABLE

#define ADC_REFCFG_REFEN_ENABLE 0x00000001U

Referenced by ADCSetInput().

§ ADC_REFCFG_REFVSEL

#define ADC_REFCFG_REFVSEL 0x00000002U

§ ADC_REFCFG_REFVSEL_M

#define ADC_REFCFG_REFVSEL_M 0x00000002U

§ ADC_REFCFG_REFVSEL_S

#define ADC_REFCFG_REFVSEL_S 1U

§ ADC_REFCFG_REFVSEL_V1P4

#define ADC_REFCFG_REFVSEL_V1P4 0x00000000U

Referenced by ADCSetInput().

§ ADC_REFCFG_IBEN

#define ADC_REFCFG_IBEN 0x00000004U

§ ADC_REFCFG_IBEN_M

#define ADC_REFCFG_IBEN_M 0x00000004U

§ ADC_REFCFG_IBEN_S

#define ADC_REFCFG_IBEN_S 2U

§ ADC_REFCFG_IBEN_DISABLE

#define ADC_REFCFG_IBEN_DISABLE 0x00000000U

§ ADC_REFCFG_IBEN_ENABLE

#define ADC_REFCFG_IBEN_ENABLE 0x00000004U

§ ADC_REFCFG_IBPROG_W

#define ADC_REFCFG_IBPROG_W 2U

§ ADC_REFCFG_IBPROG_M

#define ADC_REFCFG_IBPROG_M 0x00000018U

§ ADC_REFCFG_IBPROG_S

#define ADC_REFCFG_IBPROG_S 3U

§ ADC_REFCFG_IBPROG_VAL0

#define ADC_REFCFG_IBPROG_VAL0 0x00000000U

Referenced by ADCSetInput().

§ ADC_REFCFG_IBPROG_VAL1

#define ADC_REFCFG_IBPROG_VAL1 0x00000008U

§ ADC_REFCFG_IBPROG_VAL2

#define ADC_REFCFG_IBPROG_VAL2 0x00000010U

§ ADC_REFCFG_IBPROG_VAL3

#define ADC_REFCFG_IBPROG_VAL3 0x00000018U

§ ADC_REFCFG_OSPRPWRDN

#define ADC_REFCFG_OSPRPWRDN 0x00000020U

§ ADC_REFCFG_OSPRPWRDN_M

#define ADC_REFCFG_OSPRPWRDN_M 0x00000020U

§ ADC_REFCFG_OSPRPWRDN_S

#define ADC_REFCFG_OSPRPWRDN_S 5U

§ ADC_REFCFG_SPAR_W

#define ADC_REFCFG_SPAR_W 2U

§ ADC_REFCFG_SPAR_M

#define ADC_REFCFG_SPAR_M 0x000000C0U

§ ADC_REFCFG_SPAR_S

#define ADC_REFCFG_SPAR_S 6U

§ ADC_WCLOW_DATA_W

#define ADC_WCLOW_DATA_W 16U

§ ADC_WCLOW_DATA_M

#define ADC_WCLOW_DATA_M 0x0000FFFFU

§ ADC_WCLOW_DATA_S

#define ADC_WCLOW_DATA_S 0U

§ ADC_WCHI_DATA_W

#define ADC_WCHI_DATA_W 16U

§ ADC_WCHI_DATA_M

#define ADC_WCHI_DATA_M 0x0000FFFFU

§ ADC_WCHI_DATA_S

#define ADC_WCHI_DATA_S 0U

§ ADC_FIFODATA_DATA_W

#define ADC_FIFODATA_DATA_W 32U

§ ADC_FIFODATA_DATA_M

#define ADC_FIFODATA_DATA_M 0xFFFFFFFFU

§ ADC_FIFODATA_DATA_S

#define ADC_FIFODATA_DATA_S 0U

§ ADC_ASCRES_DATA_W

#define ADC_ASCRES_DATA_W 16U

§ ADC_ASCRES_DATA_M

#define ADC_ASCRES_DATA_M 0x0000FFFFU

§ ADC_ASCRES_DATA_S

#define ADC_ASCRES_DATA_S 0U

§ ADC_MEMCTL_0_CHANSEL_W

#define ADC_MEMCTL_0_CHANSEL_W 5U

§ ADC_MEMCTL_0_CHANSEL_M

#define ADC_MEMCTL_0_CHANSEL_M 0x0000001FU

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_CHANSEL_S

#define ADC_MEMCTL_0_CHANSEL_S 0U

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_CHANSEL_CHAN_0

#define ADC_MEMCTL_0_CHANSEL_CHAN_0 0x00000000U

§ ADC_MEMCTL_0_CHANSEL_CHAN_1

#define ADC_MEMCTL_0_CHANSEL_CHAN_1 0x00000001U

§ ADC_MEMCTL_0_CHANSEL_CHAN_2

#define ADC_MEMCTL_0_CHANSEL_CHAN_2 0x00000002U

§ ADC_MEMCTL_0_CHANSEL_CHAN_3

#define ADC_MEMCTL_0_CHANSEL_CHAN_3 0x00000003U

§ ADC_MEMCTL_0_CHANSEL_CHAN_4

#define ADC_MEMCTL_0_CHANSEL_CHAN_4 0x00000004U

§ ADC_MEMCTL_0_CHANSEL_CHAN_5

#define ADC_MEMCTL_0_CHANSEL_CHAN_5 0x00000005U

§ ADC_MEMCTL_0_CHANSEL_CHAN_6

#define ADC_MEMCTL_0_CHANSEL_CHAN_6 0x00000006U

§ ADC_MEMCTL_0_CHANSEL_CHAN_7

#define ADC_MEMCTL_0_CHANSEL_CHAN_7 0x00000007U

§ ADC_MEMCTL_0_CHANSEL_CHAN_8

#define ADC_MEMCTL_0_CHANSEL_CHAN_8 0x00000008U

§ ADC_MEMCTL_0_CHANSEL_CHAN_9

#define ADC_MEMCTL_0_CHANSEL_CHAN_9 0x00000009U

§ ADC_MEMCTL_0_CHANSEL_CHAN_10

#define ADC_MEMCTL_0_CHANSEL_CHAN_10 0x0000000AU

§ ADC_MEMCTL_0_CHANSEL_CHAN_11

#define ADC_MEMCTL_0_CHANSEL_CHAN_11 0x0000000BU

§ ADC_MEMCTL_0_CHANSEL_CHAN_12

#define ADC_MEMCTL_0_CHANSEL_CHAN_12 0x0000000CU

§ ADC_MEMCTL_0_CHANSEL_CHAN_13

#define ADC_MEMCTL_0_CHANSEL_CHAN_13 0x0000000DU

§ ADC_MEMCTL_0_CHANSEL_CHAN_14

#define ADC_MEMCTL_0_CHANSEL_CHAN_14 0x0000000EU

§ ADC_MEMCTL_0_CHANSEL_CHAN_15

#define ADC_MEMCTL_0_CHANSEL_CHAN_15 0x0000000FU

§ ADC_MEMCTL_0_CHANSEL_CHAN_16

#define ADC_MEMCTL_0_CHANSEL_CHAN_16 0x00000010U

§ ADC_MEMCTL_0_CHANSEL_CHAN_17

#define ADC_MEMCTL_0_CHANSEL_CHAN_17 0x00000011U

§ ADC_MEMCTL_0_CHANSEL_CHAN_18

#define ADC_MEMCTL_0_CHANSEL_CHAN_18 0x00000012U

§ ADC_MEMCTL_0_CHANSEL_CHAN_19

#define ADC_MEMCTL_0_CHANSEL_CHAN_19 0x00000013U

§ ADC_MEMCTL_0_CHANSEL_CHAN_20

#define ADC_MEMCTL_0_CHANSEL_CHAN_20 0x00000014U

§ ADC_MEMCTL_0_CHANSEL_CHAN_21

#define ADC_MEMCTL_0_CHANSEL_CHAN_21 0x00000015U

§ ADC_MEMCTL_0_CHANSEL_CHAN_22

#define ADC_MEMCTL_0_CHANSEL_CHAN_22 0x00000016U

§ ADC_MEMCTL_0_CHANSEL_CHAN_23

#define ADC_MEMCTL_0_CHANSEL_CHAN_23 0x00000017U

§ ADC_MEMCTL_0_CHANSEL_CHAN_24

#define ADC_MEMCTL_0_CHANSEL_CHAN_24 0x00000018U

§ ADC_MEMCTL_0_CHANSEL_CHAN_25

#define ADC_MEMCTL_0_CHANSEL_CHAN_25 0x00000019U

§ ADC_MEMCTL_0_CHANSEL_CHAN_26

#define ADC_MEMCTL_0_CHANSEL_CHAN_26 0x0000001AU

§ ADC_MEMCTL_0_CHANSEL_CHAN_27

#define ADC_MEMCTL_0_CHANSEL_CHAN_27 0x0000001BU

§ ADC_MEMCTL_0_CHANSEL_CHAN_28

#define ADC_MEMCTL_0_CHANSEL_CHAN_28 0x0000001CU

§ ADC_MEMCTL_0_CHANSEL_CHAN_29

#define ADC_MEMCTL_0_CHANSEL_CHAN_29 0x0000001DU

§ ADC_MEMCTL_0_CHANSEL_CHAN_30

#define ADC_MEMCTL_0_CHANSEL_CHAN_30 0x0000001EU

§ ADC_MEMCTL_0_CHANSEL_CHAN_31

#define ADC_MEMCTL_0_CHANSEL_CHAN_31 0x0000001FU

§ ADC_MEMCTL_0_VRSEL_W

#define ADC_MEMCTL_0_VRSEL_W 2U

§ ADC_MEMCTL_0_VRSEL_M

#define ADC_MEMCTL_0_VRSEL_M 0x00000300U

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_VRSEL_S

#define ADC_MEMCTL_0_VRSEL_S 8U

§ ADC_MEMCTL_0_VRSEL_EXTREF

#define ADC_MEMCTL_0_VRSEL_EXTREF 0x00000100U

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_VRSEL_INTREF

#define ADC_MEMCTL_0_VRSEL_INTREF 0x00000200U

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_STIME

#define ADC_MEMCTL_0_STIME 0x00001000U

§ ADC_MEMCTL_0_STIME_M

#define ADC_MEMCTL_0_STIME_M 0x00001000U

§ ADC_MEMCTL_0_STIME_S

#define ADC_MEMCTL_0_STIME_S 12U

§ ADC_MEMCTL_0_STIME_SEL_SCOMP0

#define ADC_MEMCTL_0_STIME_SEL_SCOMP0 0x00000000U

§ ADC_MEMCTL_0_STIME_SEL_SCOMP1

#define ADC_MEMCTL_0_STIME_SEL_SCOMP1 0x00001000U

§ ADC_MEMCTL_0_AVGEN

#define ADC_MEMCTL_0_AVGEN 0x00010000U

§ ADC_MEMCTL_0_AVGEN_M

#define ADC_MEMCTL_0_AVGEN_M 0x00010000U

§ ADC_MEMCTL_0_AVGEN_S

#define ADC_MEMCTL_0_AVGEN_S 16U

§ ADC_MEMCTL_0_AVGEN_DISABLE

#define ADC_MEMCTL_0_AVGEN_DISABLE 0x00000000U

§ ADC_MEMCTL_0_AVGEN_ENABLE

#define ADC_MEMCTL_0_AVGEN_ENABLE 0x00010000U

§ ADC_MEMCTL_0_TRIG

#define ADC_MEMCTL_0_TRIG 0x01000000U

§ ADC_MEMCTL_0_TRIG_M

#define ADC_MEMCTL_0_TRIG_M 0x01000000U

Referenced by ADCSetTriggerPolicy().

§ ADC_MEMCTL_0_TRIG_S

#define ADC_MEMCTL_0_TRIG_S 24U

§ ADC_MEMCTL_0_TRIG_AUTO_NEXT

#define ADC_MEMCTL_0_TRIG_AUTO_NEXT 0x00000000U

§ ADC_MEMCTL_0_TRIG_TRIGGER_NEXT

#define ADC_MEMCTL_0_TRIG_TRIGGER_NEXT 0x01000000U

§ ADC_MEMCTL_0_WINCOMP

#define ADC_MEMCTL_0_WINCOMP 0x10000000U

§ ADC_MEMCTL_0_WINCOMP_M

#define ADC_MEMCTL_0_WINCOMP_M 0x10000000U

§ ADC_MEMCTL_0_WINCOMP_S

#define ADC_MEMCTL_0_WINCOMP_S 28U

§ ADC_MEMCTL_0_WINCOMP_DISABLE

#define ADC_MEMCTL_0_WINCOMP_DISABLE 0x00000000U

§ ADC_MEMCTL_0_WINCOMP_ENABLE

#define ADC_MEMCTL_0_WINCOMP_ENABLE 0x10000000U

§ ADC_MEMCTL_0_FSR

#define ADC_MEMCTL_0_FSR 0x20000000U

§ ADC_MEMCTL_0_FSR_M

#define ADC_MEMCTL_0_FSR_M 0x20000000U

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_FSR_S

#define ADC_MEMCTL_0_FSR_S 29U

§ ADC_MEMCTL_0_MOD

#define ADC_MEMCTL_0_MOD 0x40000000U

§ ADC_MEMCTL_0_MOD_M

#define ADC_MEMCTL_0_MOD_M 0x40000000U

Referenced by ADCSetInput().

§ ADC_MEMCTL_0_MOD_S

#define ADC_MEMCTL_0_MOD_S 30U

§ ADC_MEMCTL_1_CHANSEL_W

#define ADC_MEMCTL_1_CHANSEL_W 5U

§ ADC_MEMCTL_1_CHANSEL_M

#define ADC_MEMCTL_1_CHANSEL_M 0x0000001FU

§ ADC_MEMCTL_1_CHANSEL_S

#define ADC_MEMCTL_1_CHANSEL_S 0U

§ ADC_MEMCTL_1_CHANSEL_CHAN_0

#define ADC_MEMCTL_1_CHANSEL_CHAN_0 0x00000000U

§ ADC_MEMCTL_1_CHANSEL_CHAN_1

#define ADC_MEMCTL_1_CHANSEL_CHAN_1 0x00000001U

§ ADC_MEMCTL_1_CHANSEL_CHAN_2

#define ADC_MEMCTL_1_CHANSEL_CHAN_2 0x00000002U

§ ADC_MEMCTL_1_CHANSEL_CHAN_3

#define ADC_MEMCTL_1_CHANSEL_CHAN_3 0x00000003U

§ ADC_MEMCTL_1_CHANSEL_CHAN_4

#define ADC_MEMCTL_1_CHANSEL_CHAN_4 0x00000004U

§ ADC_MEMCTL_1_CHANSEL_CHAN_5

#define ADC_MEMCTL_1_CHANSEL_CHAN_5 0x00000005U

§ ADC_MEMCTL_1_CHANSEL_CHAN_6

#define ADC_MEMCTL_1_CHANSEL_CHAN_6 0x00000006U

§ ADC_MEMCTL_1_CHANSEL_CHAN_7

#define ADC_MEMCTL_1_CHANSEL_CHAN_7 0x00000007U

§ ADC_MEMCTL_1_CHANSEL_CHAN_8

#define ADC_MEMCTL_1_CHANSEL_CHAN_8 0x00000008U

§ ADC_MEMCTL_1_CHANSEL_CHAN_9

#define ADC_MEMCTL_1_CHANSEL_CHAN_9 0x00000009U

§ ADC_MEMCTL_1_CHANSEL_CHAN_10

#define ADC_MEMCTL_1_CHANSEL_CHAN_10 0x0000000AU

§ ADC_MEMCTL_1_CHANSEL_CHAN_11

#define ADC_MEMCTL_1_CHANSEL_CHAN_11 0x0000000BU

§ ADC_MEMCTL_1_CHANSEL_CHAN_12

#define ADC_MEMCTL_1_CHANSEL_CHAN_12 0x0000000CU

§ ADC_MEMCTL_1_CHANSEL_CHAN_13

#define ADC_MEMCTL_1_CHANSEL_CHAN_13 0x0000000DU

§ ADC_MEMCTL_1_CHANSEL_CHAN_14

#define ADC_MEMCTL_1_CHANSEL_CHAN_14 0x0000000EU

§ ADC_MEMCTL_1_CHANSEL_CHAN_15

#define ADC_MEMCTL_1_CHANSEL_CHAN_15 0x0000000FU

§ ADC_MEMCTL_1_CHANSEL_CHAN_16

#define ADC_MEMCTL_1_CHANSEL_CHAN_16 0x00000010U

§ ADC_MEMCTL_1_CHANSEL_CHAN_17

#define ADC_MEMCTL_1_CHANSEL_CHAN_17 0x00000011U

§ ADC_MEMCTL_1_CHANSEL_CHAN_18

#define ADC_MEMCTL_1_CHANSEL_CHAN_18 0x00000012U

§ ADC_MEMCTL_1_CHANSEL_CHAN_19

#define ADC_MEMCTL_1_CHANSEL_CHAN_19 0x00000013U

§ ADC_MEMCTL_1_CHANSEL_CHAN_20

#define ADC_MEMCTL_1_CHANSEL_CHAN_20 0x00000014U

§ ADC_MEMCTL_1_CHANSEL_CHAN_21

#define ADC_MEMCTL_1_CHANSEL_CHAN_21 0x00000015U

§ ADC_MEMCTL_1_CHANSEL_CHAN_22

#define ADC_MEMCTL_1_CHANSEL_CHAN_22 0x00000016U

§ ADC_MEMCTL_1_CHANSEL_CHAN_23

#define ADC_MEMCTL_1_CHANSEL_CHAN_23 0x00000017U

§ ADC_MEMCTL_1_CHANSEL_CHAN_24

#define ADC_MEMCTL_1_CHANSEL_CHAN_24 0x00000018U

§ ADC_MEMCTL_1_CHANSEL_CHAN_25

#define ADC_MEMCTL_1_CHANSEL_CHAN_25 0x00000019U

§ ADC_MEMCTL_1_CHANSEL_CHAN_26

#define ADC_MEMCTL_1_CHANSEL_CHAN_26 0x0000001AU

§ ADC_MEMCTL_1_CHANSEL_CHAN_27

#define ADC_MEMCTL_1_CHANSEL_CHAN_27 0x0000001BU

§ ADC_MEMCTL_1_CHANSEL_CHAN_28

#define ADC_MEMCTL_1_CHANSEL_CHAN_28 0x0000001CU

§ ADC_MEMCTL_1_CHANSEL_CHAN_29

#define ADC_MEMCTL_1_CHANSEL_CHAN_29 0x0000001DU

§ ADC_MEMCTL_1_CHANSEL_CHAN_30

#define ADC_MEMCTL_1_CHANSEL_CHAN_30 0x0000001EU

§ ADC_MEMCTL_1_CHANSEL_CHAN_31

#define ADC_MEMCTL_1_CHANSEL_CHAN_31 0x0000001FU

§ ADC_MEMCTL_1_VRSEL_W

#define ADC_MEMCTL_1_VRSEL_W 2U

§ ADC_MEMCTL_1_VRSEL_M

#define ADC_MEMCTL_1_VRSEL_M 0x00000300U

§ ADC_MEMCTL_1_VRSEL_S

#define ADC_MEMCTL_1_VRSEL_S 8U

§ ADC_MEMCTL_1_VRSEL_EXTREF

#define ADC_MEMCTL_1_VRSEL_EXTREF 0x00000100U

§ ADC_MEMCTL_1_VRSEL_INTREF

#define ADC_MEMCTL_1_VRSEL_INTREF 0x00000200U

§ ADC_MEMCTL_1_STIME

#define ADC_MEMCTL_1_STIME 0x00001000U

§ ADC_MEMCTL_1_STIME_M

#define ADC_MEMCTL_1_STIME_M 0x00001000U

§ ADC_MEMCTL_1_STIME_S

#define ADC_MEMCTL_1_STIME_S 12U

§ ADC_MEMCTL_1_STIME_SEL_SCOMP0

#define ADC_MEMCTL_1_STIME_SEL_SCOMP0 0x00000000U

§ ADC_MEMCTL_1_STIME_SEL_SCOMP1

#define ADC_MEMCTL_1_STIME_SEL_SCOMP1 0x00001000U

§ ADC_MEMCTL_1_AVGEN

#define ADC_MEMCTL_1_AVGEN 0x00010000U

§ ADC_MEMCTL_1_AVGEN_M

#define ADC_MEMCTL_1_AVGEN_M 0x00010000U

§ ADC_MEMCTL_1_AVGEN_S

#define ADC_MEMCTL_1_AVGEN_S 16U

§ ADC_MEMCTL_1_AVGEN_DISABLE

#define ADC_MEMCTL_1_AVGEN_DISABLE 0x00000000U

§ ADC_MEMCTL_1_AVGEN_ENABLE

#define ADC_MEMCTL_1_AVGEN_ENABLE 0x00010000U

§ ADC_MEMCTL_1_TRIG

#define ADC_MEMCTL_1_TRIG 0x01000000U

§ ADC_MEMCTL_1_TRIG_M

#define ADC_MEMCTL_1_TRIG_M 0x01000000U

§ ADC_MEMCTL_1_TRIG_S

#define ADC_MEMCTL_1_TRIG_S 24U

§ ADC_MEMCTL_1_TRIG_AUTO_NEXT

#define ADC_MEMCTL_1_TRIG_AUTO_NEXT 0x00000000U

§ ADC_MEMCTL_1_TRIG_TRIGGER_NEXT

#define ADC_MEMCTL_1_TRIG_TRIGGER_NEXT 0x01000000U

§ ADC_MEMCTL_1_WINCOMP

#define ADC_MEMCTL_1_WINCOMP 0x10000000U

§ ADC_MEMCTL_1_WINCOMP_M

#define ADC_MEMCTL_1_WINCOMP_M 0x10000000U

§ ADC_MEMCTL_1_WINCOMP_S

#define ADC_MEMCTL_1_WINCOMP_S 28U

§ ADC_MEMCTL_1_WINCOMP_DISABLE

#define ADC_MEMCTL_1_WINCOMP_DISABLE 0x00000000U

§ ADC_MEMCTL_1_WINCOMP_ENABLE

#define ADC_MEMCTL_1_WINCOMP_ENABLE 0x10000000U

§ ADC_MEMCTL_1_FSR

#define ADC_MEMCTL_1_FSR 0x20000000U

§ ADC_MEMCTL_1_FSR_M

#define ADC_MEMCTL_1_FSR_M 0x20000000U

§ ADC_MEMCTL_1_FSR_S

#define ADC_MEMCTL_1_FSR_S 29U

§ ADC_MEMCTL_1_MOD

#define ADC_MEMCTL_1_MOD 0x40000000U

§ ADC_MEMCTL_1_MOD_M

#define ADC_MEMCTL_1_MOD_M 0x40000000U

§ ADC_MEMCTL_1_MOD_S

#define ADC_MEMCTL_1_MOD_S 30U

§ ADC_MEMCTL_2_CHANSEL_W

#define ADC_MEMCTL_2_CHANSEL_W 5U

§ ADC_MEMCTL_2_CHANSEL_M

#define ADC_MEMCTL_2_CHANSEL_M 0x0000001FU

§ ADC_MEMCTL_2_CHANSEL_S

#define ADC_MEMCTL_2_CHANSEL_S 0U

§ ADC_MEMCTL_2_CHANSEL_CHAN_0

#define ADC_MEMCTL_2_CHANSEL_CHAN_0 0x00000000U

§ ADC_MEMCTL_2_CHANSEL_CHAN_1

#define ADC_MEMCTL_2_CHANSEL_CHAN_1 0x00000001U

§ ADC_MEMCTL_2_CHANSEL_CHAN_2

#define ADC_MEMCTL_2_CHANSEL_CHAN_2 0x00000002U

§ ADC_MEMCTL_2_CHANSEL_CHAN_3

#define ADC_MEMCTL_2_CHANSEL_CHAN_3 0x00000003U

§ ADC_MEMCTL_2_CHANSEL_CHAN_4

#define ADC_MEMCTL_2_CHANSEL_CHAN_4 0x00000004U

§ ADC_MEMCTL_2_CHANSEL_CHAN_5

#define ADC_MEMCTL_2_CHANSEL_CHAN_5 0x00000005U

§ ADC_MEMCTL_2_CHANSEL_CHAN_6

#define ADC_MEMCTL_2_CHANSEL_CHAN_6 0x00000006U

§ ADC_MEMCTL_2_CHANSEL_CHAN_7

#define ADC_MEMCTL_2_CHANSEL_CHAN_7 0x00000007U

§ ADC_MEMCTL_2_CHANSEL_CHAN_8

#define ADC_MEMCTL_2_CHANSEL_CHAN_8 0x00000008U

§ ADC_MEMCTL_2_CHANSEL_CHAN_9

#define ADC_MEMCTL_2_CHANSEL_CHAN_9 0x00000009U

§ ADC_MEMCTL_2_CHANSEL_CHAN_10

#define ADC_MEMCTL_2_CHANSEL_CHAN_10 0x0000000AU

§ ADC_MEMCTL_2_CHANSEL_CHAN_11

#define ADC_MEMCTL_2_CHANSEL_CHAN_11 0x0000000BU

§ ADC_MEMCTL_2_CHANSEL_CHAN_12

#define ADC_MEMCTL_2_CHANSEL_CHAN_12 0x0000000CU

§ ADC_MEMCTL_2_CHANSEL_CHAN_13

#define ADC_MEMCTL_2_CHANSEL_CHAN_13 0x0000000DU

§ ADC_MEMCTL_2_CHANSEL_CHAN_14

#define ADC_MEMCTL_2_CHANSEL_CHAN_14 0x0000000EU

§ ADC_MEMCTL_2_CHANSEL_CHAN_15

#define ADC_MEMCTL_2_CHANSEL_CHAN_15 0x0000000FU

§ ADC_MEMCTL_2_CHANSEL_CHAN_16

#define ADC_MEMCTL_2_CHANSEL_CHAN_16 0x00000010U

§ ADC_MEMCTL_2_CHANSEL_CHAN_17

#define ADC_MEMCTL_2_CHANSEL_CHAN_17 0x00000011U

§ ADC_MEMCTL_2_CHANSEL_CHAN_18

#define ADC_MEMCTL_2_CHANSEL_CHAN_18 0x00000012U

§ ADC_MEMCTL_2_CHANSEL_CHAN_19

#define ADC_MEMCTL_2_CHANSEL_CHAN_19 0x00000013U

§ ADC_MEMCTL_2_CHANSEL_CHAN_20

#define ADC_MEMCTL_2_CHANSEL_CHAN_20 0x00000014U

§ ADC_MEMCTL_2_CHANSEL_CHAN_21

#define ADC_MEMCTL_2_CHANSEL_CHAN_21 0x00000015U

§ ADC_MEMCTL_2_CHANSEL_CHAN_22

#define ADC_MEMCTL_2_CHANSEL_CHAN_22 0x00000016U

§ ADC_MEMCTL_2_CHANSEL_CHAN_23

#define ADC_MEMCTL_2_CHANSEL_CHAN_23 0x00000017U

§ ADC_MEMCTL_2_CHANSEL_CHAN_24

#define ADC_MEMCTL_2_CHANSEL_CHAN_24 0x00000018U

§ ADC_MEMCTL_2_CHANSEL_CHAN_25

#define ADC_MEMCTL_2_CHANSEL_CHAN_25 0x00000019U

§ ADC_MEMCTL_2_CHANSEL_CHAN_26

#define ADC_MEMCTL_2_CHANSEL_CHAN_26 0x0000001AU

§ ADC_MEMCTL_2_CHANSEL_CHAN_27

#define ADC_MEMCTL_2_CHANSEL_CHAN_27 0x0000001BU

§ ADC_MEMCTL_2_CHANSEL_CHAN_28

#define ADC_MEMCTL_2_CHANSEL_CHAN_28 0x0000001CU

§ ADC_MEMCTL_2_CHANSEL_CHAN_29

#define ADC_MEMCTL_2_CHANSEL_CHAN_29 0x0000001DU

§ ADC_MEMCTL_2_CHANSEL_CHAN_30

#define ADC_MEMCTL_2_CHANSEL_CHAN_30 0x0000001EU

§ ADC_MEMCTL_2_CHANSEL_CHAN_31

#define ADC_MEMCTL_2_CHANSEL_CHAN_31 0x0000001FU

§ ADC_MEMCTL_2_VRSEL_W

#define ADC_MEMCTL_2_VRSEL_W 2U

§ ADC_MEMCTL_2_VRSEL_M

#define ADC_MEMCTL_2_VRSEL_M 0x00000300U

§ ADC_MEMCTL_2_VRSEL_S

#define ADC_MEMCTL_2_VRSEL_S 8U

§ ADC_MEMCTL_2_VRSEL_EXTREF

#define ADC_MEMCTL_2_VRSEL_EXTREF 0x00000100U

§ ADC_MEMCTL_2_VRSEL_INTREF

#define ADC_MEMCTL_2_VRSEL_INTREF 0x00000200U

§ ADC_MEMCTL_2_STIME

#define ADC_MEMCTL_2_STIME 0x00001000U

§ ADC_MEMCTL_2_STIME_M

#define ADC_MEMCTL_2_STIME_M 0x00001000U

§ ADC_MEMCTL_2_STIME_S

#define ADC_MEMCTL_2_STIME_S 12U

§ ADC_MEMCTL_2_STIME_SEL_SCOMP0

#define ADC_MEMCTL_2_STIME_SEL_SCOMP0 0x00000000U

§ ADC_MEMCTL_2_STIME_SEL_SCOMP1

#define ADC_MEMCTL_2_STIME_SEL_SCOMP1 0x00001000U

§ ADC_MEMCTL_2_AVGEN

#define ADC_MEMCTL_2_AVGEN 0x00010000U

§ ADC_MEMCTL_2_AVGEN_M

#define ADC_MEMCTL_2_AVGEN_M 0x00010000U

§ ADC_MEMCTL_2_AVGEN_S

#define ADC_MEMCTL_2_AVGEN_S 16U

§ ADC_MEMCTL_2_AVGEN_DISABLE

#define ADC_MEMCTL_2_AVGEN_DISABLE 0x00000000U

§ ADC_MEMCTL_2_AVGEN_ENABLE

#define ADC_MEMCTL_2_AVGEN_ENABLE 0x00010000U

§ ADC_MEMCTL_2_TRIG

#define ADC_MEMCTL_2_TRIG 0x01000000U

§ ADC_MEMCTL_2_TRIG_M

#define ADC_MEMCTL_2_TRIG_M 0x01000000U

§ ADC_MEMCTL_2_TRIG_S

#define ADC_MEMCTL_2_TRIG_S 24U

§ ADC_MEMCTL_2_TRIG_AUTO_NEXT

#define ADC_MEMCTL_2_TRIG_AUTO_NEXT 0x00000000U

§ ADC_MEMCTL_2_TRIG_TRIGGER_NEXT

#define ADC_MEMCTL_2_TRIG_TRIGGER_NEXT 0x01000000U

§ ADC_MEMCTL_2_WINCOMP

#define ADC_MEMCTL_2_WINCOMP 0x10000000U

§ ADC_MEMCTL_2_WINCOMP_M

#define ADC_MEMCTL_2_WINCOMP_M 0x10000000U

§ ADC_MEMCTL_2_WINCOMP_S

#define ADC_MEMCTL_2_WINCOMP_S 28U

§ ADC_MEMCTL_2_WINCOMP_DISABLE

#define ADC_MEMCTL_2_WINCOMP_DISABLE 0x00000000U

§ ADC_MEMCTL_2_WINCOMP_ENABLE

#define ADC_MEMCTL_2_WINCOMP_ENABLE 0x10000000U

§ ADC_MEMCTL_2_FSR

#define ADC_MEMCTL_2_FSR 0x20000000U

§ ADC_MEMCTL_2_FSR_M

#define ADC_MEMCTL_2_FSR_M 0x20000000U

§ ADC_MEMCTL_2_FSR_S

#define ADC_MEMCTL_2_FSR_S 29U

§ ADC_MEMCTL_2_MOD

#define ADC_MEMCTL_2_MOD 0x40000000U

§ ADC_MEMCTL_2_MOD_M

#define ADC_MEMCTL_2_MOD_M 0x40000000U

§ ADC_MEMCTL_2_MOD_S

#define ADC_MEMCTL_2_MOD_S 30U

§ ADC_MEMCTL_3_CHANSEL_W

#define ADC_MEMCTL_3_CHANSEL_W 5U

§ ADC_MEMCTL_3_CHANSEL_M

#define ADC_MEMCTL_3_CHANSEL_M 0x0000001FU

§ ADC_MEMCTL_3_CHANSEL_S

#define ADC_MEMCTL_3_CHANSEL_S 0U

§ ADC_MEMCTL_3_CHANSEL_CHAN_0

#define ADC_MEMCTL_3_CHANSEL_CHAN_0 0x00000000U

§ ADC_MEMCTL_3_CHANSEL_CHAN_1

#define ADC_MEMCTL_3_CHANSEL_CHAN_1 0x00000001U

§ ADC_MEMCTL_3_CHANSEL_CHAN_2

#define ADC_MEMCTL_3_CHANSEL_CHAN_2 0x00000002U

§ ADC_MEMCTL_3_CHANSEL_CHAN_3

#define ADC_MEMCTL_3_CHANSEL_CHAN_3 0x00000003U

§ ADC_MEMCTL_3_CHANSEL_CHAN_4

#define ADC_MEMCTL_3_CHANSEL_CHAN_4 0x00000004U

§ ADC_MEMCTL_3_CHANSEL_CHAN_5

#define ADC_MEMCTL_3_CHANSEL_CHAN_5 0x00000005U

§ ADC_MEMCTL_3_CHANSEL_CHAN_6

#define ADC_MEMCTL_3_CHANSEL_CHAN_6 0x00000006U

§ ADC_MEMCTL_3_CHANSEL_CHAN_7

#define ADC_MEMCTL_3_CHANSEL_CHAN_7 0x00000007U

§ ADC_MEMCTL_3_CHANSEL_CHAN_8

#define ADC_MEMCTL_3_CHANSEL_CHAN_8 0x00000008U

§ ADC_MEMCTL_3_CHANSEL_CHAN_9

#define ADC_MEMCTL_3_CHANSEL_CHAN_9 0x00000009U

§ ADC_MEMCTL_3_CHANSEL_CHAN_10

#define ADC_MEMCTL_3_CHANSEL_CHAN_10 0x0000000AU

§ ADC_MEMCTL_3_CHANSEL_CHAN_11

#define ADC_MEMCTL_3_CHANSEL_CHAN_11 0x0000000BU

§ ADC_MEMCTL_3_CHANSEL_CHAN_12

#define ADC_MEMCTL_3_CHANSEL_CHAN_12 0x0000000CU

§ ADC_MEMCTL_3_CHANSEL_CHAN_13

#define ADC_MEMCTL_3_CHANSEL_CHAN_13 0x0000000DU

§ ADC_MEMCTL_3_CHANSEL_CHAN_14

#define ADC_MEMCTL_3_CHANSEL_CHAN_14 0x0000000EU

§ ADC_MEMCTL_3_CHANSEL_CHAN_15

#define ADC_MEMCTL_3_CHANSEL_CHAN_15 0x0000000FU

§ ADC_MEMCTL_3_CHANSEL_CHAN_16

#define ADC_MEMCTL_3_CHANSEL_CHAN_16 0x00000010U

§ ADC_MEMCTL_3_CHANSEL_CHAN_17

#define ADC_MEMCTL_3_CHANSEL_CHAN_17 0x00000011U

§ ADC_MEMCTL_3_CHANSEL_CHAN_18

#define ADC_MEMCTL_3_CHANSEL_CHAN_18 0x00000012U

§ ADC_MEMCTL_3_CHANSEL_CHAN_19

#define ADC_MEMCTL_3_CHANSEL_CHAN_19 0x00000013U

§ ADC_MEMCTL_3_CHANSEL_CHAN_20

#define ADC_MEMCTL_3_CHANSEL_CHAN_20 0x00000014U

§ ADC_MEMCTL_3_CHANSEL_CHAN_21

#define ADC_MEMCTL_3_CHANSEL_CHAN_21 0x00000015U

§ ADC_MEMCTL_3_CHANSEL_CHAN_22

#define ADC_MEMCTL_3_CHANSEL_CHAN_22 0x00000016U

§ ADC_MEMCTL_3_CHANSEL_CHAN_23

#define ADC_MEMCTL_3_CHANSEL_CHAN_23 0x00000017U

§ ADC_MEMCTL_3_CHANSEL_CHAN_24

#define ADC_MEMCTL_3_CHANSEL_CHAN_24 0x00000018U

§ ADC_MEMCTL_3_CHANSEL_CHAN_25

#define ADC_MEMCTL_3_CHANSEL_CHAN_25 0x00000019U

§ ADC_MEMCTL_3_CHANSEL_CHAN_26

#define ADC_MEMCTL_3_CHANSEL_CHAN_26 0x0000001AU

§ ADC_MEMCTL_3_CHANSEL_CHAN_27

#define ADC_MEMCTL_3_CHANSEL_CHAN_27 0x0000001BU

§ ADC_MEMCTL_3_CHANSEL_CHAN_28

#define ADC_MEMCTL_3_CHANSEL_CHAN_28 0x0000001CU

§ ADC_MEMCTL_3_CHANSEL_CHAN_29

#define ADC_MEMCTL_3_CHANSEL_CHAN_29 0x0000001DU

§ ADC_MEMCTL_3_CHANSEL_CHAN_30

#define ADC_MEMCTL_3_CHANSEL_CHAN_30 0x0000001EU

§ ADC_MEMCTL_3_CHANSEL_CHAN_31

#define ADC_MEMCTL_3_CHANSEL_CHAN_31 0x0000001FU

§ ADC_MEMCTL_3_VRSEL_W

#define ADC_MEMCTL_3_VRSEL_W 2U

§ ADC_MEMCTL_3_VRSEL_M

#define ADC_MEMCTL_3_VRSEL_M 0x00000300U

§ ADC_MEMCTL_3_VRSEL_S

#define ADC_MEMCTL_3_VRSEL_S 8U

§ ADC_MEMCTL_3_VRSEL_EXTREF

#define ADC_MEMCTL_3_VRSEL_EXTREF 0x00000100U

§ ADC_MEMCTL_3_VRSEL_INTREF

#define ADC_MEMCTL_3_VRSEL_INTREF 0x00000200U

§ ADC_MEMCTL_3_STIME

#define ADC_MEMCTL_3_STIME 0x00001000U

§ ADC_MEMCTL_3_STIME_M

#define ADC_MEMCTL_3_STIME_M 0x00001000U

§ ADC_MEMCTL_3_STIME_S

#define ADC_MEMCTL_3_STIME_S 12U

§ ADC_MEMCTL_3_STIME_SEL_SCOMP0

#define ADC_MEMCTL_3_STIME_SEL_SCOMP0 0x00000000U

§ ADC_MEMCTL_3_STIME_SEL_SCOMP1

#define ADC_MEMCTL_3_STIME_SEL_SCOMP1 0x00001000U

§ ADC_MEMCTL_3_AVGEN

#define ADC_MEMCTL_3_AVGEN 0x00010000U

§ ADC_MEMCTL_3_AVGEN_M

#define ADC_MEMCTL_3_AVGEN_M 0x00010000U

§ ADC_MEMCTL_3_AVGEN_S

#define ADC_MEMCTL_3_AVGEN_S 16U

§ ADC_MEMCTL_3_AVGEN_DISABLE

#define ADC_MEMCTL_3_AVGEN_DISABLE 0x00000000U

§ ADC_MEMCTL_3_AVGEN_ENABLE

#define ADC_MEMCTL_3_AVGEN_ENABLE 0x00010000U

§ ADC_MEMCTL_3_TRIG

#define ADC_MEMCTL_3_TRIG 0x01000000U

§ ADC_MEMCTL_3_TRIG_M

#define ADC_MEMCTL_3_TRIG_M 0x01000000U

§ ADC_MEMCTL_3_TRIG_S

#define ADC_MEMCTL_3_TRIG_S 24U

§ ADC_MEMCTL_3_TRIG_AUTO_NEXT

#define ADC_MEMCTL_3_TRIG_AUTO_NEXT 0x00000000U

§ ADC_MEMCTL_3_TRIG_TRIGGER_NEXT

#define ADC_MEMCTL_3_TRIG_TRIGGER_NEXT 0x01000000U

§ ADC_MEMCTL_3_WINCOMP

#define ADC_MEMCTL_3_WINCOMP 0x10000000U

§ ADC_MEMCTL_3_WINCOMP_M

#define ADC_MEMCTL_3_WINCOMP_M 0x10000000U

§ ADC_MEMCTL_3_WINCOMP_S

#define ADC_MEMCTL_3_WINCOMP_S 28U

§ ADC_MEMCTL_3_WINCOMP_DISABLE

#define ADC_MEMCTL_3_WINCOMP_DISABLE 0x00000000U

§ ADC_MEMCTL_3_WINCOMP_ENABLE

#define ADC_MEMCTL_3_WINCOMP_ENABLE 0x10000000U

§ ADC_MEMCTL_3_FSR

#define ADC_MEMCTL_3_FSR 0x20000000U

§ ADC_MEMCTL_3_FSR_M

#define ADC_MEMCTL_3_FSR_M 0x20000000U

§ ADC_MEMCTL_3_FSR_S

#define ADC_MEMCTL_3_FSR_S 29U

§ ADC_MEMCTL_3_MOD

#define ADC_MEMCTL_3_MOD 0x40000000U

§ ADC_MEMCTL_3_MOD_M

#define ADC_MEMCTL_3_MOD_M 0x40000000U

§ ADC_MEMCTL_3_MOD_S

#define ADC_MEMCTL_3_MOD_S 30U

§ ADC_MEMCTL_4_CHANSEL_W

#define ADC_MEMCTL_4_CHANSEL_W 5U

§ ADC_MEMCTL_4_CHANSEL_M

#define ADC_MEMCTL_4_CHANSEL_M 0x0000001FU

§ ADC_MEMCTL_4_CHANSEL_S

#define ADC_MEMCTL_4_CHANSEL_S 0U

§ ADC_MEMCTL_4_CHANSEL_CHAN_0

#define ADC_MEMCTL_4_CHANSEL_CHAN_0 0x00000000U

§ ADC_MEMCTL_4_CHANSEL_CHAN_1

#define ADC_MEMCTL_4_CHANSEL_CHAN_1 0x00000001U

§ ADC_MEMCTL_4_CHANSEL_CHAN_2

#define ADC_MEMCTL_4_CHANSEL_CHAN_2 0x00000002U

§ ADC_MEMCTL_4_CHANSEL_CHAN_3

#define ADC_MEMCTL_4_CHANSEL_CHAN_3 0x00000003U

§ ADC_MEMCTL_4_CHANSEL_CHAN_4

#define ADC_MEMCTL_4_CHANSEL_CHAN_4 0x00000004U

§ ADC_MEMCTL_4_CHANSEL_CHAN_5

#define ADC_MEMCTL_4_CHANSEL_CHAN_5 0x00000005U

§ ADC_MEMCTL_4_CHANSEL_CHAN_6

#define ADC_MEMCTL_4_CHANSEL_CHAN_6 0x00000006U

§ ADC_MEMCTL_4_CHANSEL_CHAN_7

#define ADC_MEMCTL_4_CHANSEL_CHAN_7 0x00000007U

§ ADC_MEMCTL_4_CHANSEL_CHAN_8

#define ADC_MEMCTL_4_CHANSEL_CHAN_8 0x00000008U

§ ADC_MEMCTL_4_CHANSEL_CHAN_9

#define ADC_MEMCTL_4_CHANSEL_CHAN_9 0x00000009U

§ ADC_MEMCTL_4_CHANSEL_CHAN_10

#define ADC_MEMCTL_4_CHANSEL_CHAN_10 0x0000000AU

§ ADC_MEMCTL_4_CHANSEL_CHAN_11

#define ADC_MEMCTL_4_CHANSEL_CHAN_11 0x0000000BU

§ ADC_MEMCTL_4_CHANSEL_CHAN_12

#define ADC_MEMCTL_4_CHANSEL_CHAN_12 0x0000000CU

§ ADC_MEMCTL_4_CHANSEL_CHAN_13

#define ADC_MEMCTL_4_CHANSEL_CHAN_13 0x0000000DU

§ ADC_MEMCTL_4_CHANSEL_CHAN_14

#define ADC_MEMCTL_4_CHANSEL_CHAN_14 0x0000000EU

§ ADC_MEMCTL_4_CHANSEL_CHAN_15

#define ADC_MEMCTL_4_CHANSEL_CHAN_15 0x0000000FU

§ ADC_MEMCTL_4_CHANSEL_CHAN_16

#define ADC_MEMCTL_4_CHANSEL_CHAN_16 0x00000010U

§ ADC_MEMCTL_4_CHANSEL_CHAN_17

#define ADC_MEMCTL_4_CHANSEL_CHAN_17 0x00000011U

§ ADC_MEMCTL_4_CHANSEL_CHAN_18

#define ADC_MEMCTL_4_CHANSEL_CHAN_18 0x00000012U

§ ADC_MEMCTL_4_CHANSEL_CHAN_19

#define ADC_MEMCTL_4_CHANSEL_CHAN_19 0x00000013U

§ ADC_MEMCTL_4_CHANSEL_CHAN_20

#define ADC_MEMCTL_4_CHANSEL_CHAN_20 0x00000014U

§ ADC_MEMCTL_4_CHANSEL_CHAN_21

#define ADC_MEMCTL_4_CHANSEL_CHAN_21 0x00000015U

§ ADC_MEMCTL_4_CHANSEL_CHAN_22

#define ADC_MEMCTL_4_CHANSEL_CHAN_22 0x00000016U

§ ADC_MEMCTL_4_CHANSEL_CHAN_23

#define ADC_MEMCTL_4_CHANSEL_CHAN_23 0x00000017U

§ ADC_MEMCTL_4_CHANSEL_CHAN_24

#define ADC_MEMCTL_4_CHANSEL_CHAN_24 0x00000018U

§ ADC_MEMCTL_4_CHANSEL_CHAN_25

#define ADC_MEMCTL_4_CHANSEL_CHAN_25 0x00000019U

§ ADC_MEMCTL_4_CHANSEL_CHAN_26

#define ADC_MEMCTL_4_CHANSEL_CHAN_26 0x0000001AU

§ ADC_MEMCTL_4_CHANSEL_CHAN_27

#define ADC_MEMCTL_4_CHANSEL_CHAN_27 0x0000001BU

§ ADC_MEMCTL_4_CHANSEL_CHAN_28

#define ADC_MEMCTL_4_CHANSEL_CHAN_28 0x0000001CU

§ ADC_MEMCTL_4_CHANSEL_CHAN_29

#define ADC_MEMCTL_4_CHANSEL_CHAN_29 0x0000001DU

§ ADC_MEMCTL_4_CHANSEL_CHAN_30

#define ADC_MEMCTL_4_CHANSEL_CHAN_30 0x0000001EU

§ ADC_MEMCTL_4_CHANSEL_CHAN_31

#define ADC_MEMCTL_4_CHANSEL_CHAN_31 0x0000001FU

§ ADC_MEMCTL_4_VRSEL_W

#define ADC_MEMCTL_4_VRSEL_W 2U

§ ADC_MEMCTL_4_VRSEL_M

#define ADC_MEMCTL_4_VRSEL_M 0x00000300U

§ ADC_MEMCTL_4_VRSEL_S

#define ADC_MEMCTL_4_VRSEL_S 8U

§ ADC_MEMCTL_4_VRSEL_EXTREF

#define ADC_MEMCTL_4_VRSEL_EXTREF 0x00000100U

§ ADC_MEMCTL_4_VRSEL_INTREF

#define ADC_MEMCTL_4_VRSEL_INTREF 0x00000200U

§ ADC_MEMCTL_4_STIME

#define ADC_MEMCTL_4_STIME 0x00001000U

§ ADC_MEMCTL_4_STIME_M

#define ADC_MEMCTL_4_STIME_M 0x00001000U

§ ADC_MEMCTL_4_STIME_S

#define ADC_MEMCTL_4_STIME_S 12U

§ ADC_MEMCTL_4_STIME_SEL_SCOMP0

#define ADC_MEMCTL_4_STIME_SEL_SCOMP0 0x00000000U

§ ADC_MEMCTL_4_STIME_SEL_SCOMP1

#define ADC_MEMCTL_4_STIME_SEL_SCOMP1 0x00001000U

§ ADC_MEMCTL_4_AVGEN

#define ADC_MEMCTL_4_AVGEN 0x00010000U

§ ADC_MEMCTL_4_AVGEN_M

#define ADC_MEMCTL_4_AVGEN_M 0x00010000U

§ ADC_MEMCTL_4_AVGEN_S

#define ADC_MEMCTL_4_AVGEN_S 16U

§ ADC_MEMCTL_4_AVGEN_DISABLE

#define ADC_MEMCTL_4_AVGEN_DISABLE 0x00000000U

§ ADC_MEMCTL_4_AVGEN_ENABLE

#define ADC_MEMCTL_4_AVGEN_ENABLE 0x00010000U

§ ADC_MEMCTL_4_TRIG

#define ADC_MEMCTL_4_TRIG 0x01000000U

§ ADC_MEMCTL_4_TRIG_M

#define ADC_MEMCTL_4_TRIG_M 0x01000000U

§ ADC_MEMCTL_4_TRIG_S

#define ADC_MEMCTL_4_TRIG_S 24U

§ ADC_MEMCTL_4_TRIG_AUTO_NEXT

#define ADC_MEMCTL_4_TRIG_AUTO_NEXT 0x00000000U

§ ADC_MEMCTL_4_TRIG_TRIGGER_NEXT

#define ADC_MEMCTL_4_TRIG_TRIGGER_NEXT 0x01000000U

§ ADC_MEMCTL_4_WINCOMP

#define ADC_MEMCTL_4_WINCOMP 0x10000000U

§ ADC_MEMCTL_4_WINCOMP_M

#define ADC_MEMCTL_4_WINCOMP_M 0x10000000U

§ ADC_MEMCTL_4_WINCOMP_S

#define ADC_MEMCTL_4_WINCOMP_S 28U

§ ADC_MEMCTL_4_WINCOMP_DISABLE

#define ADC_MEMCTL_4_WINCOMP_DISABLE 0x00000000U

§ ADC_MEMCTL_4_WINCOMP_ENABLE

#define ADC_MEMCTL_4_WINCOMP_ENABLE 0x10000000U

§ ADC_MEMCTL_4_FSR

#define ADC_MEMCTL_4_FSR 0x20000000U

§ ADC_MEMCTL_4_FSR_M

#define ADC_MEMCTL_4_FSR_M 0x20000000U

§ ADC_MEMCTL_4_FSR_S

#define ADC_MEMCTL_4_FSR_S 29U

§ ADC_MEMCTL_4_MOD

#define ADC_MEMCTL_4_MOD 0x40000000U

§ ADC_MEMCTL_4_MOD_M

#define ADC_MEMCTL_4_MOD_M 0x40000000U

§ ADC_MEMCTL_4_MOD_S

#define ADC_MEMCTL_4_MOD_S 30U

§ ADC_MEMCTL_5_CHANSEL_W

#define ADC_MEMCTL_5_CHANSEL_W 5U

§ ADC_MEMCTL_5_CHANSEL_M

#define ADC_MEMCTL_5_CHANSEL_M 0x0000001FU

§ ADC_MEMCTL_5_CHANSEL_S

#define ADC_MEMCTL_5_CHANSEL_S 0U

§ ADC_MEMCTL_5_CHANSEL_CHAN_0

#define ADC_MEMCTL_5_CHANSEL_CHAN_0 0x00000000U

§ ADC_MEMCTL_5_CHANSEL_CHAN_1

#define ADC_MEMCTL_5_CHANSEL_CHAN_1 0x00000001U

§ ADC_MEMCTL_5_CHANSEL_CHAN_2

#define ADC_MEMCTL_5_CHANSEL_CHAN_2 0x00000002U

§ ADC_MEMCTL_5_CHANSEL_CHAN_3

#define ADC_MEMCTL_5_CHANSEL_CHAN_3 0x00000003U

§ ADC_MEMCTL_5_CHANSEL_CHAN_4

#define ADC_MEMCTL_5_CHANSEL_CHAN_4 0x00000004U

§ ADC_MEMCTL_5_CHANSEL_CHAN_5

#define ADC_MEMCTL_5_CHANSEL_CHAN_5 0x00000005U

§ ADC_MEMCTL_5_CHANSEL_CHAN_6

#define ADC_MEMCTL_5_CHANSEL_CHAN_6 0x00000006U

§ ADC_MEMCTL_5_CHANSEL_CHAN_7

#define ADC_MEMCTL_5_CHANSEL_CHAN_7 0x00000007U

§ ADC_MEMCTL_5_CHANSEL_CHAN_8

#define ADC_MEMCTL_5_CHANSEL_CHAN_8 0x00000008U

§ ADC_MEMCTL_5_CHANSEL_CHAN_9

#define ADC_MEMCTL_5_CHANSEL_CHAN_9 0x00000009U

§ ADC_MEMCTL_5_CHANSEL_CHAN_10

#define ADC_MEMCTL_5_CHANSEL_CHAN_10 0x0000000AU

§ ADC_MEMCTL_5_CHANSEL_CHAN_11

#define ADC_MEMCTL_5_CHANSEL_CHAN_11 0x0000000BU

§ ADC_MEMCTL_5_CHANSEL_CHAN_12

#define ADC_MEMCTL_5_CHANSEL_CHAN_12 0x0000000CU

§ ADC_MEMCTL_5_CHANSEL_CHAN_13

#define ADC_MEMCTL_5_CHANSEL_CHAN_13 0x0000000DU

§ ADC_MEMCTL_5_CHANSEL_CHAN_14

#define ADC_MEMCTL_5_CHANSEL_CHAN_14 0x0000000EU

§ ADC_MEMCTL_5_CHANSEL_CHAN_15

#define ADC_MEMCTL_5_CHANSEL_CHAN_15 0x0000000FU

§ ADC_MEMCTL_5_CHANSEL_CHAN_16

#define ADC_MEMCTL_5_CHANSEL_CHAN_16 0x00000010U

§ ADC_MEMCTL_5_CHANSEL_CHAN_17

#define ADC_MEMCTL_5_CHANSEL_CHAN_17 0x00000011U

§ ADC_MEMCTL_5_CHANSEL_CHAN_18

#define ADC_MEMCTL_5_CHANSEL_CHAN_18 0x00000012U

§ ADC_MEMCTL_5_CHANSEL_CHAN_19

#define ADC_MEMCTL_5_CHANSEL_CHAN_19 0x00000013U

§ ADC_MEMCTL_5_CHANSEL_CHAN_20

#define ADC_MEMCTL_5_CHANSEL_CHAN_20 0x00000014U

§ ADC_MEMCTL_5_CHANSEL_CHAN_21

#define ADC_MEMCTL_5_CHANSEL_CHAN_21 0x00000015U

§ ADC_MEMCTL_5_CHANSEL_CHAN_22

#define ADC_MEMCTL_5_CHANSEL_CHAN_22 0x00000016U

§ ADC_MEMCTL_5_CHANSEL_CHAN_23

#define ADC_MEMCTL_5_CHANSEL_CHAN_23 0x00000017U

§ ADC_MEMCTL_5_CHANSEL_CHAN_24

#define ADC_MEMCTL_5_CHANSEL_CHAN_24 0x00000018U

§ ADC_MEMCTL_5_CHANSEL_CHAN_25

#define ADC_MEMCTL_5_CHANSEL_CHAN_25 0x00000019U

§ ADC_MEMCTL_5_CHANSEL_CHAN_26

#define ADC_MEMCTL_5_CHANSEL_CHAN_26 0x0000001AU

§ ADC_MEMCTL_5_CHANSEL_CHAN_27

#define ADC_MEMCTL_5_CHANSEL_CHAN_27 0x0000001BU

§ ADC_MEMCTL_5_CHANSEL_CHAN_28

#define ADC_MEMCTL_5_CHANSEL_CHAN_28 0x0000001CU

§ ADC_MEMCTL_5_CHANSEL_CHAN_29

#define ADC_MEMCTL_5_CHANSEL_CHAN_29 0x0000001DU

§ ADC_MEMCTL_5_CHANSEL_CHAN_30

#define ADC_MEMCTL_5_CHANSEL_CHAN_30 0x0000001EU

§ ADC_MEMCTL_5_CHANSEL_CHAN_31

#define ADC_MEMCTL_5_CHANSEL_CHAN_31 0x0000001FU

§ ADC_MEMCTL_5_VRSEL_W

#define ADC_MEMCTL_5_VRSEL_W 2U

§ ADC_MEMCTL_5_VRSEL_M

#define ADC_MEMCTL_5_VRSEL_M 0x00000300U

§ ADC_MEMCTL_5_VRSEL_S

#define ADC_MEMCTL_5_VRSEL_S 8U

§ ADC_MEMCTL_5_VRSEL_EXTREF

#define ADC_MEMCTL_5_VRSEL_EXTREF 0x00000100U

§ ADC_MEMCTL_5_VRSEL_INTREF

#define ADC_MEMCTL_5_VRSEL_INTREF 0x00000200U

§ ADC_MEMCTL_5_STIME

#define ADC_MEMCTL_5_STIME 0x00001000U

§ ADC_MEMCTL_5_STIME_M

#define ADC_MEMCTL_5_STIME_M 0x00001000U

§ ADC_MEMCTL_5_STIME_S

#define ADC_MEMCTL_5_STIME_S 12U

§ ADC_MEMCTL_5_STIME_SEL_SCOMP0

#define ADC_MEMCTL_5_STIME_SEL_SCOMP0 0x00000000U

§ ADC_MEMCTL_5_STIME_SEL_SCOMP1

#define ADC_MEMCTL_5_STIME_SEL_SCOMP1 0x00001000U

§ ADC_MEMCTL_5_AVGEN

#define ADC_MEMCTL_5_AVGEN 0x00010000U

§ ADC_MEMCTL_5_AVGEN_M

#define ADC_MEMCTL_5_AVGEN_M 0x00010000U

§ ADC_MEMCTL_5_AVGEN_S

#define ADC_MEMCTL_5_AVGEN_S 16U

§ ADC_MEMCTL_5_AVGEN_DISABLE

#define ADC_MEMCTL_5_AVGEN_DISABLE 0x00000000U

§ ADC_MEMCTL_5_AVGEN_ENABLE

#define ADC_MEMCTL_5_AVGEN_ENABLE 0x00010000U

§ ADC_MEMCTL_5_TRIG

#define ADC_MEMCTL_5_TRIG 0x01000000U

§ ADC_MEMCTL_5_TRIG_M

#define ADC_MEMCTL_5_TRIG_M 0x01000000U

§ ADC_MEMCTL_5_TRIG_S

#define ADC_MEMCTL_5_TRIG_S 24U

§ ADC_MEMCTL_5_TRIG_AUTO_NEXT

#define ADC_MEMCTL_5_TRIG_AUTO_NEXT 0x00000000U

§ ADC_MEMCTL_5_TRIG_TRIGGER_NEXT

#define ADC_MEMCTL_5_TRIG_TRIGGER_NEXT 0x01000000U

§ ADC_MEMCTL_5_WINCOMP

#define ADC_MEMCTL_5_WINCOMP 0x10000000U

§ ADC_MEMCTL_5_WINCOMP_M

#define ADC_MEMCTL_5_WINCOMP_M 0x10000000U

§ ADC_MEMCTL_5_WINCOMP_S

#define ADC_MEMCTL_5_WINCOMP_S 28U

§ ADC_MEMCTL_5_WINCOMP_DISABLE

#define ADC_MEMCTL_5_WINCOMP_DISABLE 0x00000000U

§ ADC_MEMCTL_5_WINCOMP_ENABLE

#define ADC_MEMCTL_5_WINCOMP_ENABLE 0x10000000U

§ ADC_MEMCTL_5_FSR

#define ADC_MEMCTL_5_FSR 0x20000000U

§ ADC_MEMCTL_5_FSR_M

#define ADC_MEMCTL_5_FSR_M 0x20000000U

§ ADC_MEMCTL_5_FSR_S

#define ADC_MEMCTL_5_FSR_S 29U

§ ADC_MEMCTL_5_MOD

#define ADC_MEMCTL_5_MOD 0x40000000U

§ ADC_MEMCTL_5_MOD_M

#define ADC_MEMCTL_5_MOD_M 0x40000000U

§ ADC_MEMCTL_5_MOD_S

#define ADC_MEMCTL_5_MOD_S 30U

§ ADC_MEMRES_0_DATA_W

#define ADC_MEMRES_0_DATA_W 16U

§ ADC_MEMRES_0_DATA_M

#define ADC_MEMRES_0_DATA_M 0x0000FFFFU

§ ADC_MEMRES_0_DATA_S

#define ADC_MEMRES_0_DATA_S 0U

§ ADC_MEMRES_1_DATA_W

#define ADC_MEMRES_1_DATA_W 16U

§ ADC_MEMRES_1_DATA_M

#define ADC_MEMRES_1_DATA_M 0x0000FFFFU

§ ADC_MEMRES_1_DATA_S

#define ADC_MEMRES_1_DATA_S 0U

§ ADC_MEMRES_2_DATA_W

#define ADC_MEMRES_2_DATA_W 16U

§ ADC_MEMRES_2_DATA_M

#define ADC_MEMRES_2_DATA_M 0x0000FFFFU

§ ADC_MEMRES_2_DATA_S

#define ADC_MEMRES_2_DATA_S 0U

§ ADC_MEMRES_3_DATA_W

#define ADC_MEMRES_3_DATA_W 16U

§ ADC_MEMRES_3_DATA_M

#define ADC_MEMRES_3_DATA_M 0x0000FFFFU

§ ADC_MEMRES_3_DATA_S

#define ADC_MEMRES_3_DATA_S 0U

§ ADC_MEMRES_4_DATA_W

#define ADC_MEMRES_4_DATA_W 16U

§ ADC_MEMRES_4_DATA_M

#define ADC_MEMRES_4_DATA_M 0x0000FFFFU

§ ADC_MEMRES_4_DATA_S

#define ADC_MEMRES_4_DATA_S 0U

§ ADC_MEMRES_5_DATA_W

#define ADC_MEMRES_5_DATA_W 16U

§ ADC_MEMRES_5_DATA_M

#define ADC_MEMRES_5_DATA_M 0x0000FFFFU

§ ADC_MEMRES_5_DATA_S

#define ADC_MEMRES_5_DATA_S 0U

§ ADC_MEMRES_6_DATA_W

#define ADC_MEMRES_6_DATA_W 16U

§ ADC_MEMRES_6_DATA_M

#define ADC_MEMRES_6_DATA_M 0x0000FFFFU

§ ADC_MEMRES_6_DATA_S

#define ADC_MEMRES_6_DATA_S 0U

§ ADC_MEMRES_7_DATA_W

#define ADC_MEMRES_7_DATA_W 16U

§ ADC_MEMRES_7_DATA_M

#define ADC_MEMRES_7_DATA_M 0x0000FFFFU

§ ADC_MEMRES_7_DATA_S

#define ADC_MEMRES_7_DATA_S 0U

§ ADC_MEMRES_8_DATA_W

#define ADC_MEMRES_8_DATA_W 16U

§ ADC_MEMRES_8_DATA_M

#define ADC_MEMRES_8_DATA_M 0x0000FFFFU

§ ADC_MEMRES_8_DATA_S

#define ADC_MEMRES_8_DATA_S 0U

§ ADC_MEMRES_9_DATA_W

#define ADC_MEMRES_9_DATA_W 16U

§ ADC_MEMRES_9_DATA_M

#define ADC_MEMRES_9_DATA_M 0x0000FFFFU

§ ADC_MEMRES_9_DATA_S

#define ADC_MEMRES_9_DATA_S 0U

§ ADC_MEMRES_10_DATA_W

#define ADC_MEMRES_10_DATA_W 16U

§ ADC_MEMRES_10_DATA_M

#define ADC_MEMRES_10_DATA_M 0x0000FFFFU

§ ADC_MEMRES_10_DATA_S

#define ADC_MEMRES_10_DATA_S 0U

§ ADC_MEMRES_11_DATA_W

#define ADC_MEMRES_11_DATA_W 16U

§ ADC_MEMRES_11_DATA_M

#define ADC_MEMRES_11_DATA_M 0x0000FFFFU

§ ADC_MEMRES_11_DATA_S

#define ADC_MEMRES_11_DATA_S 0U

§ ADC_MEMRES_12_DATA_W

#define ADC_MEMRES_12_DATA_W 16U

§ ADC_MEMRES_12_DATA_M

#define ADC_MEMRES_12_DATA_M 0x0000FFFFU

§ ADC_MEMRES_12_DATA_S

#define ADC_MEMRES_12_DATA_S 0U

§ ADC_MEMRES_13_DATA_W

#define ADC_MEMRES_13_DATA_W 16U

§ ADC_MEMRES_13_DATA_M

#define ADC_MEMRES_13_DATA_M 0x0000FFFFU

§ ADC_MEMRES_13_DATA_S

#define ADC_MEMRES_13_DATA_S 0U

§ ADC_MEMRES_14_DATA_W

#define ADC_MEMRES_14_DATA_W 16U

§ ADC_MEMRES_14_DATA_M

#define ADC_MEMRES_14_DATA_M 0x0000FFFFU

§ ADC_MEMRES_14_DATA_S

#define ADC_MEMRES_14_DATA_S 0U

§ ADC_MEMRES_15_DATA_W

#define ADC_MEMRES_15_DATA_W 16U

§ ADC_MEMRES_15_DATA_M

#define ADC_MEMRES_15_DATA_M 0x0000FFFFU

§ ADC_MEMRES_15_DATA_S

#define ADC_MEMRES_15_DATA_S 0U

§ ADC_STA_BUSY

#define ADC_STA_BUSY 0x00000001U

§ ADC_STA_BUSY_M

#define ADC_STA_BUSY_M 0x00000001U

§ ADC_STA_BUSY_S

#define ADC_STA_BUSY_S 0U

§ ADC_STA_BUSY_ACTIVE

#define ADC_STA_BUSY_ACTIVE 0x00000001U

Referenced by ADCIsBusy(), and ADCReadResult().

§ ADC_STA_BUSY_IDLE

#define ADC_STA_BUSY_IDLE 0x00000000U

§ ADC_STA_REFBUFRDY

#define ADC_STA_REFBUFRDY 0x00000002U

§ ADC_STA_REFBUFRDY_M

#define ADC_STA_REFBUFRDY_M 0x00000002U

§ ADC_STA_REFBUFRDY_S

#define ADC_STA_REFBUFRDY_S 1U

§ ADC_STA_REFBUFRDY_READY

#define ADC_STA_REFBUFRDY_READY 0x00000002U

§ ADC_STA_REFBUFRDY_NOTREADY

#define ADC_STA_REFBUFRDY_NOTREADY 0x00000000U

§ ADC_STA_ASCACT

#define ADC_STA_ASCACT 0x00000004U

§ ADC_STA_ASCACT_M

#define ADC_STA_ASCACT_M 0x00000004U

§ ADC_STA_ASCACT_S

#define ADC_STA_ASCACT_S 2U

§ ADC_STA_ASCACT_ACTIVE

#define ADC_STA_ASCACT_ACTIVE 0x00000004U

§ ADC_STA_ASCACT_IDLE

#define ADC_STA_ASCACT_IDLE 0x00000000U

§ ADC_TEST0_AMBUFSEL_W

#define ADC_TEST0_AMBUFSEL_W 5U

§ ADC_TEST0_AMBUFSEL_M

#define ADC_TEST0_AMBUFSEL_M 0x0000001FU

§ ADC_TEST0_AMBUFSEL_S

#define ADC_TEST0_AMBUFSEL_S 0U

§ ADC_TEST0_AMUNBUFSEL_W

#define ADC_TEST0_AMUNBUFSEL_W 5U

§ ADC_TEST0_AMUNBUFSEL_M

#define ADC_TEST0_AMUNBUFSEL_M 0x00001F00U

§ ADC_TEST0_AMUNBUFSEL_S

#define ADC_TEST0_AMUNBUFSEL_S 8U

§ ADC_TEST0_ATBUNBUFEN

#define ADC_TEST0_ATBUNBUFEN 0x20000000U

§ ADC_TEST0_ATBUNBUFEN_M

#define ADC_TEST0_ATBUNBUFEN_M 0x20000000U

§ ADC_TEST0_ATBUNBUFEN_S

#define ADC_TEST0_ATBUNBUFEN_S 29U

§ ADC_TEST0_ATBBUFEN

#define ADC_TEST0_ATBBUFEN 0x40000000U

§ ADC_TEST0_ATBBUFEN_M

#define ADC_TEST0_ATBBUFEN_M 0x40000000U

§ ADC_TEST0_ATBBUFEN_S

#define ADC_TEST0_ATBBUFEN_S 30U

§ ADC_TEST1_DTBMSEL_W

#define ADC_TEST1_DTBMSEL_W 5U

§ ADC_TEST1_DTBMSEL_M

#define ADC_TEST1_DTBMSEL_M 0x0000001FU

§ ADC_TEST1_DTBMSEL_S

#define ADC_TEST1_DTBMSEL_S 0U

§ ADC_TEST2_MUXTSEL

#define ADC_TEST2_MUXTSEL 0x00000100U

§ ADC_TEST2_MUXTSEL_M

#define ADC_TEST2_MUXTSEL_M 0x00000100U

§ ADC_TEST2_MUXTSEL_S

#define ADC_TEST2_MUXTSEL_S 8U

§ ADC_TEST2_CMPGNTRIM

#define ADC_TEST2_CMPGNTRIM 0x00100000U

§ ADC_TEST2_CMPGNTRIM_M

#define ADC_TEST2_CMPGNTRIM_M 0x00100000U

§ ADC_TEST2_CMPGNTRIM_S

#define ADC_TEST2_CMPGNTRIM_S 20U

§ ADC_TEST2_LTRIMEN

#define ADC_TEST2_LTRIMEN 0x01000000U

§ ADC_TEST2_LTRIMEN_M

#define ADC_TEST2_LTRIMEN_M 0x01000000U

§ ADC_TEST2_LTRIMEN_S

#define ADC_TEST2_LTRIMEN_S 24U

§ ADC_TEST2_CDACOVSTEN

#define ADC_TEST2_CDACOVSTEN 0x80000000U

§ ADC_TEST2_CDACOVSTEN_M

#define ADC_TEST2_CDACOVSTEN_M 0x80000000U

§ ADC_TEST2_CDACOVSTEN_S

#define ADC_TEST2_CDACOVSTEN_S 31U

§ ADC_TEST3_CALACUML_W

#define ADC_TEST3_CALACUML_W 32U

§ ADC_TEST3_CALACUML_M

#define ADC_TEST3_CALACUML_M 0xFFFFFFFFU

§ ADC_TEST3_CALACUML_S

#define ADC_TEST3_CALACUML_S 0U

§ ADC_TEST4_CALSTPSEL_W

#define ADC_TEST4_CALSTPSEL_W 6U

§ ADC_TEST4_CALSTPSEL_M

#define ADC_TEST4_CALSTPSEL_M 0x003F0000U

§ ADC_TEST4_CALSTPSEL_S

#define ADC_TEST4_CALSTPSEL_S 16U

§ ADC_TEST4_CALMODEN

#define ADC_TEST4_CALMODEN 0x01000000U

§ ADC_TEST4_CALMODEN_M

#define ADC_TEST4_CALMODEN_M 0x01000000U

§ ADC_TEST4_CALMODEN_S

#define ADC_TEST4_CALMODEN_S 24U

§ ADC_TEST4_HWSTPSELDIS

#define ADC_TEST4_HWSTPSELDIS 0x80000000U

§ ADC_TEST4_HWSTPSELDIS_M

#define ADC_TEST4_HWSTPSELDIS_M 0x80000000U

§ ADC_TEST4_HWSTPSELDIS_S

#define ADC_TEST4_HWSTPSELDIS_S 31U

§ ADC_TEST5_CALCAPCTL_W

#define ADC_TEST5_CALCAPCTL_W 10U

§ ADC_TEST5_CALCAPCTL_M

#define ADC_TEST5_CALCAPCTL_M 0x000003FFU

§ ADC_TEST5_CALCAPCTL_S

#define ADC_TEST5_CALCAPCTL_S 0U

§ ADC_TEST6_ATBSEL_W

#define ADC_TEST6_ATBSEL_W 4U

§ ADC_TEST6_ATBSEL_M

#define ADC_TEST6_ATBSEL_M 0x0000000FU

§ ADC_TEST6_ATBSEL_S

#define ADC_TEST6_ATBSEL_S 0U

§ ADC_TEST6_ATBSEL_VAL0

#define ADC_TEST6_ATBSEL_VAL0 0x00000000U

§ ADC_TEST6_ATBSEL_VAL1

#define ADC_TEST6_ATBSEL_VAL1 0x00000001U

§ ADC_TEST6_ATBSEL_VAL2

#define ADC_TEST6_ATBSEL_VAL2 0x00000002U

§ ADC_TEST6_ATBSEL_VAL4

#define ADC_TEST6_ATBSEL_VAL4 0x00000004U

§ ADC_TEST6_ATBSEL_VAL8

#define ADC_TEST6_ATBSEL_VAL8 0x00000008U

§ ADC_DBG1_CTRL_W

#define ADC_DBG1_CTRL_W 32U

§ ADC_DBG1_CTRL_M

#define ADC_DBG1_CTRL_M 0xFFFFFFFFU

§ ADC_DBG1_CTRL_S

#define ADC_DBG1_CTRL_S 0U

§ ADC_DBG2_VTSTODEN

#define ADC_DBG2_VTSTODEN 0x01000000U

§ ADC_DBG2_VTSTODEN_M

#define ADC_DBG2_VTSTODEN_M 0x01000000U

§ ADC_DBG2_VTSTODEN_S

#define ADC_DBG2_VTSTODEN_S 24U

§ ADC_DBG2_VTOICTL_W

#define ADC_DBG2_VTOICTL_W 2U

§ ADC_DBG2_VTOICTL_M

#define ADC_DBG2_VTOICTL_M 0x30000000U

§ ADC_DBG2_VTOICTL_S

#define ADC_DBG2_VTOICTL_S 28U

§ ADC_DBG3_BSTENZ

#define ADC_DBG3_BSTENZ 0x00000001U

§ ADC_DBG3_BSTENZ_M

#define ADC_DBG3_BSTENZ_M 0x00000001U

§ ADC_DBG3_BSTENZ_S

#define ADC_DBG3_BSTENZ_S 0U

§ ADC_DBG3_DEC0DIS

#define ADC_DBG3_DEC0DIS 0x00000010U

§ ADC_DBG3_DEC0DIS_M

#define ADC_DBG3_DEC0DIS_M 0x00000010U

§ ADC_DBG3_DEC0DIS_S

#define ADC_DBG3_DEC0DIS_S 4U

§ ADC_DBG3_DEC1DIS

#define ADC_DBG3_DEC1DIS 0x00000020U

§ ADC_DBG3_DEC1DIS_M

#define ADC_DBG3_DEC1DIS_M 0x00000020U

§ ADC_DBG3_DEC1DIS_S

#define ADC_DBG3_DEC1DIS_S 5U

§ ADC_DBG4_ADCCTL0_W

#define ADC_DBG4_ADCCTL0_W 16U

§ ADC_DBG4_ADCCTL0_M

#define ADC_DBG4_ADCCTL0_M 0x0000FFFFU

§ ADC_DBG4_ADCCTL0_S

#define ADC_DBG4_ADCCTL0_S 0U

§ ADC_CONVCTL_DAC_W

#define ADC_CONVCTL_DAC_W 3U

§ ADC_CONVCTL_DAC_M

#define ADC_CONVCTL_DAC_M 0x00000007U

§ ADC_CONVCTL_DAC_S

#define ADC_CONVCTL_DAC_S 0U

§ ADC_CONVCTL_PREAMP_W

#define ADC_CONVCTL_PREAMP_W 2U

§ ADC_CONVCTL_PREAMP_M

#define ADC_CONVCTL_PREAMP_M 0x00000018U

§ ADC_CONVCTL_PREAMP_S

#define ADC_CONVCTL_PREAMP_S 3U

§ ADC_CONVCTL_HOLD_W

#define ADC_CONVCTL_HOLD_W 4U

§ ADC_CONVCTL_HOLD_M

#define ADC_CONVCTL_HOLD_M 0x000001E0U

§ ADC_CONVCTL_HOLD_S

#define ADC_CONVCTL_HOLD_S 5U

§ ADC_CONVCTL_OV

#define ADC_CONVCTL_OV 0x00008000U

§ ADC_CONVCTL_OV_M

#define ADC_CONVCTL_OV_M 0x00008000U

§ ADC_CONVCTL_OV_S

#define ADC_CONVCTL_OV_S 15U

§ ADC_CONVCTL_CONCLKSEL_W

#define ADC_CONVCTL_CONCLKSEL_W 2U

§ ADC_CONVCTL_CONCLKSEL_M

#define ADC_CONVCTL_CONCLKSEL_M 0x00030000U

Referenced by ADCSetSamplingClk().

§ ADC_CONVCTL_CONCLKSEL_S

#define ADC_CONVCTL_CONCLKSEL_S 16U

Referenced by ADCSetSamplingClk().

§ ADC_CONVCTL_CONVCLKEN

#define ADC_CONVCTL_CONVCLKEN 0x00040000U

§ ADC_CONVCTL_CONVCLKEN_M

#define ADC_CONVCTL_CONVCLKEN_M 0x00040000U

Referenced by ADCSetSamplingClk().

§ ADC_CONVCTL_CONVCLKEN_S

#define ADC_CONVCTL_CONVCLKEN_S 18U

Referenced by ADCSetSamplingClk().

§ ADC_CTRL_FSBIT0_W

#define ADC_CTRL_FSBIT0_W 9U

§ ADC_CTRL_FSBIT0_M

#define ADC_CTRL_FSBIT0_M 0x000001FFU

§ ADC_CTRL_FSBIT0_S

#define ADC_CTRL_FSBIT0_S 0U

Referenced by ADCRestoreTrims().

§ ADC_CTRL_FSBIT1_W

#define ADC_CTRL_FSBIT1_W 8U

§ ADC_CTRL_FSBIT1_M

#define ADC_CTRL_FSBIT1_M 0x0001FE00U

§ ADC_CTRL_FSBIT1_S

#define ADC_CTRL_FSBIT1_S 9U

Referenced by ADCRestoreTrims().

§ ADC_MODCTL_VREFRAN

#define ADC_MODCTL_VREFRAN 0x00000001U

§ ADC_MODCTL_VREFRAN_M

#define ADC_MODCTL_VREFRAN_M 0x00000001U

Referenced by ADCSetInput().

§ ADC_MODCTL_VREFRAN_S

#define ADC_MODCTL_VREFRAN_S 0U

§ ADC_MODCTL_SCASEL

#define ADC_MODCTL_SCASEL 0x00000002U

§ ADC_MODCTL_SCASEL_M

#define ADC_MODCTL_SCASEL_M 0x00000002U

Referenced by ADCSetInput().

§ ADC_MODCTL_SCASEL_S

#define ADC_MODCTL_SCASEL_S 1U

§ ADC_INTCHCTL_RLVAL

#define ADC_INTCHCTL_RLVAL 0x00000001U

§ ADC_INTCHCTL_RLVAL_M

#define ADC_INTCHCTL_RLVAL_M 0x00000001U

§ ADC_INTCHCTL_RLVAL_S

#define ADC_INTCHCTL_RLVAL_S 0U

§ ADC_INTCHCTL_RLOV

#define ADC_INTCHCTL_RLOV 0x00000002U

§ ADC_INTCHCTL_RLOV_M

#define ADC_INTCHCTL_RLOV_M 0x00000002U

§ ADC_INTCHCTL_RLOV_S

#define ADC_INTCHCTL_RLOV_S 1U

§ ADC_STLTIM_SWCTRLDEL_W

#define ADC_STLTIM_SWCTRLDEL_W 6U

§ ADC_STLTIM_SWCTRLDEL_M

#define ADC_STLTIM_SWCTRLDEL_M 0x0000003FU

§ ADC_STLTIM_SWCTRLDEL_S

#define ADC_STLTIM_SWCTRLDEL_S 0U

§ ADC_STLTIM_RCSETDEL_W

#define ADC_STLTIM_RCSETDEL_W 10U

§ ADC_STLTIM_RCSETDEL_M

#define ADC_STLTIM_RCSETDEL_M 0x03FF0000U

§ ADC_STLTIM_RCSETDEL_S

#define ADC_STLTIM_RCSETDEL_S 16U

§ ADC_CLKCFG_EN

#define ADC_CLKCFG_EN 0x00000001U

§ ADC_CLKCFG_EN_M

#define ADC_CLKCFG_EN_M 0x00000001U

§ ADC_CLKCFG_EN_S

#define ADC_CLKCFG_EN_S 0U

Macros

Macro Definition Documentation

§ ADC_O_FSCTL0

§ ADC_O_FSCTL1

§ ADC_O_FSCTL2

§ ADC_O_FSCTL3

§ ADC_O_REFBUF

§ ADC_O_ATB

§ ADC_O_INTEVT0IDX

§ ADC_O_INTEVT0BM

§ ADC_O_INTEVT0RIS

§ ADC_O_INTEVT0MIS

§ ADC_O_INTEVT0SET

§ ADC_O_INTEVT0CLR

§ ADC_O_INTEVT1IDX

§ ADC_O_INTEVT1BM

§ ADC_O_INTEVT1RIS

§ ADC_O_INTEVT1MIS

§ ADC_O_INTEVT1SET

§ ADC_O_INTEVT1CLR

§ ADC_O_INTEVT2IDX

§ ADC_O_INTEVT2BM

§ ADC_O_INTEVT2RIS

§ ADC_O_INTEVT2MIS

§ ADC_O_INTEVT2SET

§ ADC_O_INTEVT2CLR

§ ADC_O_EVTMOD

§ ADC_O_DESC

§ ADC_O_CTL0

§ ADC_O_CTL1

§ ADC_O_CTL2

§ ADC_O_CTL3

§ ADC_O_CLKFREQ

§ ADC_O_SCOMP0

§ ADC_O_SCOMP1

§ ADC_O_REFCFG

§ ADC_O_WCLOW

§ ADC_O_WCHI

§ ADC_O_FIFODATA

§ ADC_O_ASCRES

§ ADC_O_MEMCTL_0

§ ADC_O_MEMCTL_1

§ ADC_O_MEMCTL_2

§ ADC_O_MEMCTL_3

§ ADC_O_MEMCTL_4

§ ADC_O_MEMCTL_5

§ ADC_O_MEMRES_0

§ ADC_O_MEMRES_1

§ ADC_O_MEMRES_2

§ ADC_O_MEMRES_3

§ ADC_O_MEMRES_4

§ ADC_O_MEMRES_5

§ ADC_O_MEMRES_6

§ ADC_O_MEMRES_7

§ ADC_O_MEMRES_8

§ ADC_O_MEMRES_9

§ ADC_O_MEMRES_10

§ ADC_O_MEMRES_11

§ ADC_O_MEMRES_12

§ ADC_O_MEMRES_13

§ ADC_O_MEMRES_14

§ ADC_O_MEMRES_15

§ ADC_O_STA

§ ADC_O_TEST0

§ ADC_O_TEST1

§ ADC_O_TEST2

§ ADC_O_TEST3

§ ADC_O_TEST4

§ ADC_O_TEST5

§ ADC_O_TEST6

§ ADC_O_DBG1

§ ADC_O_DBG2

§ ADC_O_DBG3

§ ADC_O_DBG4

§ ADC_O_CONVCTL

§ ADC_O_CTRL

§ ADC_O_MODCTL

§ ADC_O_INTCHCTL

§ ADC_O_STLTIM

§ ADC_O_CLKCFG