Collaboration diagram for [i2s.h] Inter-Integrated Circuit Sound:

Macros
#define	I2S_CLK_SRC_SOC_CLK I2S_CLKCFG_CLKSEL_SEL_1
	SOC clock. More...

#define	I2S_CLK_SRC_SOC_PLL_CLK I2S_CLKCFG_CLKSEL_SEL_2
	SOC PLL clock. More...

#define	I2S_CLK_SRC_HFXT_CLK I2S_CLKCFG_CLKSEL_SEL_3
	HFXT. More...

#define	I2S_SD0_DIS I2S_AIFDIRCFG_AD0_DIS
	SD0 is disabled. More...

#define	I2S_SD0_IN I2S_AIFDIRCFG_AD0_IN
	SD0 is an input. More...

#define	I2S_SD0_OUT I2S_AIFDIRCFG_AD0_OUT
	SD0 is an output. More...

#define	I2S_SD1_DIS I2S_AIFDIRCFG_AD1_DIS
	SD1 is disabled. More...

#define	I2S_SD1_IN I2S_AIFDIRCFG_AD1_IN
	SD1 is an input. More...

#define	I2S_SD1_OUT I2S_AIFDIRCFG_AD1_OUT
	SD1 is an output. More...

#define	I2S_CHAN0_MASK 0x00000001

#define	I2S_CHAN1_MASK 0x00000002

#define	I2S_CHAN2_MASK 0x00000004

#define	I2S_CHAN3_MASK 0x00000008

#define	I2S_CHAN4_MASK 0x00000010

#define	I2S_CHAN5_MASK 0x00000020

#define	I2S_CHAN6_MASK 0x00000040

#define	I2S_CHAN7_MASK 0x00000080

#define	I2S_MEM_LENGTH_16 I2S_AIFFMTCFG_LEN32__16BIT
	16 bit size of word in memory More...

#define	I2S_MEM_LENGTH_32 I2S_AIFFMTCFG_LEN32__32BIT
	32 bit size of word in memory More...

#define	I2S_POS_EDGE I2S_AIFFMTCFG_SMPLEDGE_POS
	Sample on positive edge. More...

#define	I2S_NEG_EDGE I2S_AIFFMTCFG_SMPLEDGE_NEG
	Sample on negative edge. More...

#define	I2S_STMP_SATURATION 0x0000FFFF
	The saturation value used when calculating the sample stamp. More...

#define	I2S_INT_XCNT_CAPTURE I2S_IRQFLAGS_XCNTCPT
	MCUCLK Capture. More...

#define	I2S_INT_DMA_IN I2S_IRQFLAGS_AIFDMAIN
	DMA output buffer full interrupt. More...

#define	I2S_INT_DMA_OUT I2S_IRQFLAGS_AIFDMAOUT
	DMA input buffer empty interrupt. More...

#define	I2S_INT_TIMEOUT I2S_IRQFLAGS_WCLKTOUT
	Word Clock Timeout. More...

#define	I2S_INT_BUS_ERR I2S_IRQFLAGS_BUSERR
	DMA Bus error. More...

#define	I2S_INT_WCLK_ERR I2S_IRQFLAGS_WCLKERR
	Word Clock error. More...

#define	I2S_INT_PTR_ERR I2S_IRQFLAGS_PTRERR
	Data pointer error (DMA data was not updated in time) More...

#define	I2S_INT_ALL
	All interrupts. More...

Functions
__STATIC_INLINE void	I2SEnableInt (uint32_t base, uint32_t intFlags)
	Enables individual I2S interrupt sources. More...

__STATIC_INLINE void	I2SDisableInt (uint32_t base, uint32_t intFlags)
	Disables individual I2S interrupt sources. More...

__STATIC_INLINE uint32_t	I2SIntStatus (uint32_t base, bool masked)
	Gets the current interrupt status. More...

__STATIC_INLINE void	I2SClearInt (uint32_t base, uint32_t intFlags)
	Clears I2S interrupt sources. More...

__STATIC_INLINE void	I2SEnableSampleStamp (uint32_t base)
	Enable the Sample Stamp generator. More...

__STATIC_INLINE void	I2SDisableSampleStamp (uint32_t base)
	Disable the Sample Stamp generator. More...

uint32_t	I2SGetSampleStamp (uint32_t base, uint32_t channel)
	Get the current value of a sample stamp counter. More...

__STATIC_INLINE void	I2SStart (uint32_t base, uint16_t dmaLength)
	Starts the I2S. More...

__STATIC_INLINE void	I2SStop (uint32_t base)
	Stops the I2S module for operation. More...

__STATIC_INLINE void	I2SConfigureFormat (uint32_t base, uint8_t dataDelay, uint32_t memoryLength, uint32_t samplingEdge, bool dualPhase, uint8_t bitsPerSample)
	Configure the serial format of the I2S module. More...

__STATIC_INLINE void	I2SConfigureFrame (uint32_t base, uint8_t sd0Usage, uint8_t sd0Channels, uint8_t sd1Usage, uint8_t sd1Channels)
	Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). More...

__STATIC_INLINE void	I2SConfigureClocks (uint32_t base, bool isController, bool invertWclk, bool dualPhase, uint32_t cclkDiv, uint32_t wclkDiv, uint32_t bclkDiv)
	Configure the I2S clocks (CCLK, WCLK and BCLK). More...

__STATIC_INLINE void	I2SEnableControllerClocks (uint32_t base)
	Enable the I2S controller clocks (CCLK, WCLK and BCLK). More...

__STATIC_INLINE void	I2SDisableControllerClocks (uint32_t base)
	Disable the I2S controller clocks (CCLK, WCLK and BCLK). More...

__STATIC_INLINE void	I2SSetInPointer (uint32_t base, uint32_t nextPointer)
	Set the next input buffer pointer. More...

__STATIC_INLINE void	I2SSetOutPointer (uint32_t base, uint32_t nextPointer)
	Set the next output buffer pointer. More...

__STATIC_INLINE uint32_t	I2SGetInPointerNext (uint32_t base)
	Get value of the next input pointer. More...

__STATIC_INLINE uint32_t	I2SGetOutPointerNext (uint32_t base)
	Get value of the next output pointer. More...

__STATIC_INLINE uint32_t	I2SGetInPointer (uint32_t base)
	Get value of the current input pointer. More...

__STATIC_INLINE uint32_t	I2SGetOutPointer (uint32_t base)
	Get value of the current output pointer. More...

__STATIC_INLINE void	I2SConfigureInSampleStampTrigger (uint32_t base, uint16_t trigValue)
	Configure the input sample stamp trigger. More...

__STATIC_INLINE void	I2SConfigureOutSampleStampTrigger (uint32_t base, uint16_t trigValue)
	Configure the output sample stamp trigger. More...

__STATIC_INLINE void	I2SConfigureWclkCounterPeriod (uint32_t base, uint16_t period)
	Configure the WCLK counter period. More...

__STATIC_INLINE void	I2SConfigureWclkCounter (uint32_t base, int16_t value)
	Confiugre the WCLK counter value. More...

__STATIC_INLINE void	I2SResetWclkCounter (uint32_t base)
	Reset the WCLK count. More...

__STATIC_INLINE void	I2SEnableClk (uint32_t base)
	Enables the clock source. More...

__STATIC_INLINE void	I2SDisableClk (uint32_t base)
	Disables the clock source. More...

__STATIC_INLINE void	I2SEnableAdfs (uint32_t base)
	Enables the ADFS (Adaptive Digital Frequency Synthesizer) module. More...

__STATIC_INLINE void	I2SSelectAdfsInputClk (uint32_t base, uint32_t source)
	Selects the ADFS inpt clock (Fref) More...

__STATIC_INLINE void	I2SConfigureAdfs (uint32_t base, uint32_t tref, uint32_t delta, uint32_t deltaSign, uint32_t div)
	Configures the Adaptive Digital Frequency Synthesizer (ADFS) module. More...

__STATIC_INLINE void	I2SDisableAdfs (uint32_t base)
	Disables the ADFS (Adaptive Digital Frequency Synthesizer) module. More...

Detailed Description

Macro Definition Documentation

§ I2S_CLK_SRC_SOC_CLK

#define I2S_CLK_SRC_SOC_CLK I2S_CLKCFG_CLKSEL_SEL_1

SOC clock.

§ I2S_CLK_SRC_SOC_PLL_CLK

#define I2S_CLK_SRC_SOC_PLL_CLK I2S_CLKCFG_CLKSEL_SEL_2

SOC PLL clock.

§ I2S_CLK_SRC_HFXT_CLK

#define I2S_CLK_SRC_HFXT_CLK I2S_CLKCFG_CLKSEL_SEL_3

HFXT.

§ I2S_SD0_DIS

#define I2S_SD0_DIS I2S_AIFDIRCFG_AD0_DIS

SD0 is disabled.

§ I2S_SD0_IN

#define I2S_SD0_IN I2S_AIFDIRCFG_AD0_IN

SD0 is an input.

§ I2S_SD0_OUT

#define I2S_SD0_OUT I2S_AIFDIRCFG_AD0_OUT

SD0 is an output.

§ I2S_SD1_DIS

#define I2S_SD1_DIS I2S_AIFDIRCFG_AD1_DIS

SD1 is disabled.

§ I2S_SD1_IN

#define I2S_SD1_IN I2S_AIFDIRCFG_AD1_IN

SD1 is an input.

§ I2S_SD1_OUT

#define I2S_SD1_OUT I2S_AIFDIRCFG_AD1_OUT

SD1 is an output.

§ I2S_CHAN0_MASK

#define I2S_CHAN0_MASK 0x00000001

§ I2S_CHAN1_MASK

#define I2S_CHAN1_MASK 0x00000002

§ I2S_CHAN2_MASK

#define I2S_CHAN2_MASK 0x00000004

§ I2S_CHAN3_MASK

#define I2S_CHAN3_MASK 0x00000008

§ I2S_CHAN4_MASK

#define I2S_CHAN4_MASK 0x00000010

§ I2S_CHAN5_MASK

#define I2S_CHAN5_MASK 0x00000020

§ I2S_CHAN6_MASK

#define I2S_CHAN6_MASK 0x00000040

§ I2S_CHAN7_MASK

#define I2S_CHAN7_MASK 0x00000080

§ I2S_MEM_LENGTH_16

#define I2S_MEM_LENGTH_16 I2S_AIFFMTCFG_LEN32__16BIT

16 bit size of word in memory

§ I2S_MEM_LENGTH_32

#define I2S_MEM_LENGTH_32 I2S_AIFFMTCFG_LEN32__32BIT

32 bit size of word in memory

§ I2S_POS_EDGE

#define I2S_POS_EDGE I2S_AIFFMTCFG_SMPLEDGE_POS

Sample on positive edge.

§ I2S_NEG_EDGE

#define I2S_NEG_EDGE I2S_AIFFMTCFG_SMPLEDGE_NEG

Sample on negative edge.

§ I2S_STMP_SATURATION

#define I2S_STMP_SATURATION 0x0000FFFF

The saturation value used when calculating the sample stamp.

Referenced by I2SGetSampleStamp().

§ I2S_INT_XCNT_CAPTURE

#define I2S_INT_XCNT_CAPTURE I2S_IRQFLAGS_XCNTCPT

MCUCLK Capture.

§ I2S_INT_DMA_IN

#define I2S_INT_DMA_IN I2S_IRQFLAGS_AIFDMAIN

DMA output buffer full interrupt.

§ I2S_INT_DMA_OUT

#define I2S_INT_DMA_OUT I2S_IRQFLAGS_AIFDMAOUT

DMA input buffer empty interrupt.

§ I2S_INT_TIMEOUT

#define I2S_INT_TIMEOUT I2S_IRQFLAGS_WCLKTOUT

Word Clock Timeout.

§ I2S_INT_BUS_ERR

#define I2S_INT_BUS_ERR I2S_IRQFLAGS_BUSERR

DMA Bus error.

§ I2S_INT_WCLK_ERR

#define I2S_INT_WCLK_ERR I2S_IRQFLAGS_WCLKERR

Word Clock error.

§ I2S_INT_PTR_ERR

#define I2S_INT_PTR_ERR I2S_IRQFLAGS_PTRERR

Data pointer error (DMA data was not updated in time)

§ I2S_INT_ALL

#define I2S_INT_ALL

Value:

I2S_INT_PTR_ERR)

I2S_INT_XCNT_CAPTURE

#define I2S_INT_XCNT_CAPTURE

MCUCLK Capture.

Definition: i2s.h:124

I2S_INT_TIMEOUT

#define I2S_INT_TIMEOUT

Word Clock Timeout.

Definition: i2s.h:127

I2S_INT_BUS_ERR

#define I2S_INT_BUS_ERR

DMA Bus error.

Definition: i2s.h:128

I2S_INT_DMA_IN

#define I2S_INT_DMA_IN

DMA output buffer full interrupt.

Definition: i2s.h:125

I2S_INT_WCLK_ERR

#define I2S_INT_WCLK_ERR

Word Clock error.

Definition: i2s.h:129

I2S_INT_DMA_OUT

#define I2S_INT_DMA_OUT

DMA input buffer empty interrupt.

Definition: i2s.h:126

All interrupts.

Function Documentation

§ I2SEnableInt()

__STATIC_INLINE void I2SEnableInt	(	uint32_t	base,
		uint32_t	intFlags
	)

Enables individual I2S interrupt sources.

This function enables the indicated I2S interrupt sources. Only the sources that are enabled can propagate to the processor interrupt; disabled sources have no effect on the processor.

Parameters

base	is the base address of the I2S module.
intFlags	is the bit mask of the interrupt sources to be enabled. The parameter is the bitwise OR of any of the following: I2S_INT_XCNT_CAPTURE I2S_INT_DMA_IN I2S_INT_DMA_OUT I2S_INT_TIMEOUT I2S_INT_BUS_ERR I2S_INT_WCLK_ERR I2S_INT_PTR_ERR I2S_INT_ALL (covers all the above)

Returns: None.

References ASSERT, HWREG, I2S_BASE, and I2S_O_IRQMASK.

§ I2SDisableInt()

__STATIC_INLINE void I2SDisableInt	(	uint32_t	base,
		uint32_t	intFlags
	)

Disables individual I2S interrupt sources.

This function disables the indicated I2S interrupt sources. Only the sources that are enabled propagate to the processor interrupt; disabled sources have no effect on the processor.

Parameters

base	is the base address of the I2S module.
intFlags	is the bit mask of the interrupt sources to be disabled. The parameter is the bitwise OR of any of the following: I2S_INT_XCNT_CAPTURE I2S_INT_DMA_IN I2S_INT_DMA_OUT I2S_INT_TIMEOUT I2S_INT_BUS_ERR I2S_INT_WCLK_ERR I2S_INT_PTR_ERR I2S_INT_ALL (covers all the above)

Returns: None.

References ASSERT, HWREG, I2S_BASE, and I2S_O_IRQMASK.

§ I2SIntStatus()

__STATIC_INLINE uint32_t I2SIntStatus	(	uint32_t	base,
		bool	masked
	)

Gets the current interrupt status.

This function returns the interrupt status for the specified I2S. Either the raw interrupt status or the status of interrupts that propagate to the processor can be returned.

Parameters

base	is the base address of the I2S module.
masked	selects between raw and masked interrupt status: `false` : Raw interrupt status is required. `true` : Masked interrupt status is required.

Returns

Returns the current interrupt status as a vector of:

References ASSERT, HWREG, I2S_BASE, I2S_O_IRQFLAGS, and I2S_O_IRQMASK.

§ I2SClearInt()

__STATIC_INLINE void I2SClearInt	(	uint32_t	base,
		uint32_t	intFlags
	)

Clears I2S interrupt sources.

The specified I2S interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being recognized again immediately upon exit.

Parameters

base	is the base address of the I2S module.
intFlags	is a bit mask of the interrupt sources to be cleared. The parameter is the bitwise OR of any of the following: I2S_INT_XCNT_CAPTURE I2S_INT_DMA_IN I2S_INT_DMA_OUT I2S_INT_TIMEOUT I2S_INT_BUS_ERR I2S_INT_WCLK_ERR I2S_INT_PTR_ERR I2S_INT_ALL (covers all the above)

Returns: None

References ASSERT, HWREG, I2S_BASE, and I2S_O_IRQCLR.

§ I2SEnableSampleStamp()

__STATIC_INLINE void I2SEnableSampleStamp ( uint32_t base )

Enable the Sample Stamp generator.

Use this function to enable the sample stamp generator.

Note: It is the user's responsibility to ensure that the sample stamp generator is properly configured before it is enabled. It is the setting of the Input and Output triggers configured using I2SConfigureInSampleStampTrigger() and I2SConfigureOutSampleStampTrigger() that triggers the start point of the audio streams.

Parameters

base	is the base address of the I2S module.

Returns: None.

References ASSERT, HWREG, I2S_BASE, I2S_O_STMPCTL, and I2S_STMPCTL_STMPEN_M.

§ I2SDisableSampleStamp()

__STATIC_INLINE void I2SDisableSampleStamp ( uint32_t base )

Disable the Sample Stamp generator.

Use this function to disable the sample stamp generator. When the sample stamp generator is disabled, the clock counters are automatically cleared.

Parameters

base	is the base address of the I2S module.

Returns: None

References ASSERT, HWREG, I2S_BASE, I2S_O_STMPCTL, I2S_STMPCTL_STMPEN_M, and I2SGetSampleStamp().

§ I2SGetSampleStamp()

uint32_t I2SGetSampleStamp	(	uint32_t	base,
		uint32_t	channel
	)

Get the current value of a sample stamp counter.

Parameters

base	is the base address of the I2S module.
channel	is the sample stamp counter to sample.

Returns: Returns the current value of the selected sample stamp channel.

References HWREG, I2S_BASE, I2S_O_STMPWCPT0, I2S_O_STMPXCPT0, I2S_O_STMPXPER, and I2S_STMP_SATURATION.

Referenced by I2SDisableSampleStamp().

§ I2SStart()

__STATIC_INLINE void I2SStart	(	uint32_t	base,
		uint16_t	dmaLength
	)

Starts the I2S.

I2S must be configured before it is started.

Note: Immediately after enabling the module the programmer must update the DMA data pointer registers using I2SSetInPointer() and I2SSetOutPointer() to ensure a new pointer is written before the DMA transfer completes. Failure to update the pointer in time will result in an I2S_INT_PTR_ERR.

Parameters

base	is the I2S module base address.
dmaLength	is the number of frames in the DMA buffer. This will allow the DMA to read `dmaLength` frames between two pointer refreshes. Valid values are integers in the range [2, 256], both included.

Returns: None.

See also: I2SStop()

References ASSERT, HWREG, I2S_AIFDMACFG_ENDFRAMIDX_M, I2S_BASE, and I2S_O_AIFDMACFG.

§ I2SStop()

__STATIC_INLINE void I2SStop ( uint32_t base )

Stops the I2S module for operation.

This function will immediately disable the I2S module. To ensure that all buffer operations are completed before shutting down, the correct procedure is:

Do not update the data pointers using I2SSetInPointer() and I2SSetOutPointer().
Wait until values returned by I2SGetInPointerNext(), I2SGetOutPointerNext(), I2SGetInPointer() and I2SGetOutPointer() are zero.
Disable the I2S using I2SStop() and clear the pointer error using I2SClearInt().
Disable bit clock source.

Parameters

base	is the I2S module base address.

Returns: None.

See also: I2SStart()

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFDMACFG.

§ I2SConfigureFormat()

__STATIC_INLINE void I2SConfigureFormat	(	uint32_t	base,
		uint8_t	dataDelay,
		uint32_t	memoryLength,
		uint32_t	samplingEdge,
		bool	dualPhase,
		uint8_t	bitsPerSample
	)

Configure the serial format of the I2S module.

The word length defines the size of the word transmitted on the data lines. For single phased formats bitsPerSample is the exact number of bits per word. In dual phased format this is the maximum number of bits per word.

Parameters

base	is the I2S module base address.
dataDelay	is the number of BCLK periods between the first WCLK edge and the MSB of the first audio channel data transferred during the phase. Valued values are integers in the range [0, 255], both included.
memoryLength	selects the memory length of the samples in memory. Possible values are: I2S_MEM_LENGTH_16 I2S_MEM_LENGTH_32
samplingEdge	selects if sampling on falling or rising edges. Possible values are: I2S_NEG_EDGE I2S_POS_EDGE
dualPhase	must be set to `true` for dual phase and to `false` for single phase. This must be the same value as configured in I2SConfigureClocks()
bitsPerSample	is the number of bits transmitted for each sample. Valued values are integers in the range [8, 24], both included. If this number does not match with the memory length selected (16 bits or 32 bits), samples will be truncated or padded.

Returns: None.

See also: I2SConfigureFrame()

References ASSERT, HWREGH, I2S_AIFFMTCFG_DATADELAY_S, I2S_AIFFMTCFG_DUALPHASE_S, I2S_AIFFMTCFG_WORDLEN_S, I2S_BASE, and I2S_O_AIFFMTCFG.

§ I2SConfigureFrame()

__STATIC_INLINE void I2SConfigureFrame	(	uint32_t	base,
		uint8_t	sd0Usage,
		uint8_t	sd0Channels,
		uint8_t	sd1Usage,
		uint8_t	sd1Channels
	)

Setup the two interfaces SD0 and SD1 (also called AD0 and AD1).

This function sets interface's direction and activated channels.

Parameters

base	is base address of the I2S module.
sd0Usage	defines the usage of SD0. Valid values are: I2S_SD0_DIS I2S_SD0_IN I2S_SD0_OUT
sd0Channels	defines the channel mask for SD0. Use a bitwise OR'ed combination of: I2S_CHAN0_MASK I2S_CHAN1_MASK I2S_CHAN2_MASK I2S_CHAN3_MASK I2S_CHAN4_MASK I2S_CHAN5_MASK I2S_CHAN6_MASK I2S_CHAN7_MASK
sd1Usage	defines the usage of SD1. Valid values are: I2S_SD1_DIS I2S_SD1_IN I2S_SD1_OUT
sd1Channels	defines the channel mask for SD1. Use a bitwise OR'ed combination of: I2S_CHAN0_MASK I2S_CHAN1_MASK I2S_CHAN2_MASK I2S_CHAN3_MASK I2S_CHAN4_MASK I2S_CHAN5_MASK I2S_CHAN6_MASK I2S_CHAN7_MASK

Returns: None.

See also: I2SConfigureFormat()

References ASSERT, HWREGB, I2S_BASE, I2S_O_AIFDIRCFG, I2S_O_AIFWMASK0, and I2S_O_AIFWMASK1.

§ I2SConfigureClocks()

__STATIC_INLINE void I2SConfigureClocks	(	uint32_t	base,
		bool	isController,
		bool	invertWclk,
		bool	dualPhase,
		uint32_t	cclkDiv,
		uint32_t	wclkDiv,
		uint32_t	bclkDiv
	)

Configure the I2S clocks (CCLK, WCLK and BCLK).

This function does the following:

Configure clocks to be either internal (Controller) or external (Target).
Configure the I2S module to internally invert WCLK if selected by invertWclk.
If isController is true, the I2S module will be configured to use internally generated clocks based on dualPhase, cclkDiv, wclkDiv and bclkDiv.

Note: This function will disable the I2S clocks if they were previously enabled. To enable the clocks use I2SEnableControllerClocks().

Parameters

base	is the base address of the I2S module.
isController	selects if the device is a Target or a Controller: `false:` the device is a Target (external clock). `true:` the device is a Controller (internal clock).
invertWclk	selects if the WCLK should be internally inverted: `false:` WCLK is not inverted. `true:` WCLK is internally inverted.
dualPhase	must be set to `true` for dual phase and to `false` for single phase. This must be the same value as configured in I2SConfigureFormat().
cclkDiv	is the desired controller clock (CCLK) divider. I.e. the number of ACLK periods in one CCLK period. Valid values are integers in the range [2, 1024], both included.
wclkDiv	is the desired word clock (WCLK) divider. The interpretation of this value depends on the value of `dualPhase:` `false` (single phase mode): `wclkDiv` is the number of BCLK periods in one WCLK period (rising edge to rising edge). Valid values for `wclkDiv` are integers in the range [2, 1024], both included. `true` (dual phase mode): `wclkDiv` is the number of BCLK periods in each phase (one edge to the next opposite edge). Meaning the period of WCLK will be 2 * `wclkDiv` BLCK periods. Valid values for `wclkDiv` are integers in the range [1, 1023], both included.
bclkDiv	is the desired bit clock (BCLK) divider. I.e. the number of ACLK periods in one BCLK period. Valid values are integers in the range [2, 1024], both included.

Returns: None.

References ASSERT, HWREG, HWREGB, I2S_AIFCLKCTL_WCLKPHASE_S, I2S_AIFWCLKSRC_WBCLKSRC_EXT, I2S_AIFWCLKSRC_WBCLKSRC_INT, I2S_AIFWCLKSRC_WCLKINV, I2S_BASE, I2S_O_AIFBCLKDIV, I2S_O_AIFCLKCTL, I2S_O_AIFMCLKDIV, I2S_O_AIFWCLKDIV, and I2S_O_AIFWCLKSRC.

§ I2SEnableControllerClocks()

__STATIC_INLINE void I2SEnableControllerClocks ( uint32_t base )

Enable the I2S controller clocks (CCLK, WCLK and BCLK).

Use this function to enable the controller clocks CCLK, WCLK and BCLK (internally generated).

Note: The internal I2S clocks must have been configured using I2SConfigureClocks() with the isController parameter set to true.

Returns: None.

References HWREG, I2S_AIFCLKCTL_MEN, I2S_AIFCLKCTL_WBEN, I2S_BASE, and I2S_O_AIFCLKCTL.

§ I2SDisableControllerClocks()

__STATIC_INLINE void I2SDisableControllerClocks ( uint32_t base )

Disable the I2S controller clocks (CCLK, WCLK and BCLK).

Use this function to disable the controller clocks CCLK, WCLK and BCLK (internally generated).

Returns: None.

References HWREG, I2S_AIFCLKCTL_MEN, I2S_AIFCLKCTL_WBEN, I2S_BASE, and I2S_O_AIFCLKCTL.

§ I2SSetInPointer()

__STATIC_INLINE void I2SSetInPointer	(	uint32_t	base,
		uint32_t	nextPointer
	)

Set the next input buffer pointer.

The next pointer should always be written while the DMA is using the previously written pointer. If not written in time, an I2S_INT_PTR_ERR will occur and all inputs and outputs will be disabled. This function assumes nextPointer is pointing to a valid address.

Note: It is recommended that the pointer update is done in an interrupt context to ensure that the update is performed before the buffer is full.

Parameters

base	is the base address of the I2S module.
nextPointer	is the address of the data.

Returns: None.

See also: I2SSetOutPointer()

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFINPTNXT.

§ I2SSetOutPointer()

__STATIC_INLINE void I2SSetOutPointer	(	uint32_t	base,
		uint32_t	nextPointer
	)

Set the next output buffer pointer.

The next pointer should always be written while the DMA is using the previously written pointer. If not written in time, an I2S_INT_PTR_ERR will occur and all inputs and outputs will be disabled. This function assumes nextPointer is pointing to a valid address.

Note: It is recommended that the pointer update is done in an interrupt context to ensure that the update is performed before the buffer is full.

Parameters

base	is the base address of the I2S module.
nextPointer	is the address of the data.

Returns: None.

See also: I2SSetInPointer()

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFOPTNXT.

§ I2SGetInPointerNext()

__STATIC_INLINE uint32_t I2SGetInPointerNext ( uint32_t base )

Get value of the next input pointer.

Parameters

base	is the base address of the I2S module.

Returns: the value of the next input pointer.

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFINPTNXT.

§ I2SGetOutPointerNext()

__STATIC_INLINE uint32_t I2SGetOutPointerNext ( uint32_t base )

Get value of the next output pointer.

Parameters

base	is the base address of the I2S module.

Returns: the value of the next output pointer.

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFOPTNXT.

§ I2SGetInPointer()

__STATIC_INLINE uint32_t I2SGetInPointer ( uint32_t base )

Get value of the current input pointer.

Parameters

base	is the base address of the I2S module.

Returns: the value of the current input pointer.

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFINPTR.

§ I2SGetOutPointer()

__STATIC_INLINE uint32_t I2SGetOutPointer ( uint32_t base )

Get value of the current output pointer.

Parameters

base	is the base address of the I2S module.

Returns: the value of the current output pointer.

References ASSERT, HWREG, I2S_BASE, and I2S_O_AIFOUTPTR.

§ I2SConfigureInSampleStampTrigger()

__STATIC_INLINE void I2SConfigureInSampleStampTrigger	(	uint32_t	base,
		uint16_t	trigValue
	)

Configure the input sample stamp trigger.

Use this function to configure the input sample stamp trigger.

Parameters

base	is the base address of the I2S module.
trigValue	value used to set the trigger.

Returns: None.

References ASSERT, HWREGH, I2S_BASE, and I2S_O_STMPINTRIG.

§ I2SConfigureOutSampleStampTrigger()

__STATIC_INLINE void I2SConfigureOutSampleStampTrigger	(	uint32_t	base,
		uint16_t	trigValue
	)

Configure the output sample stamp trigger.

Use this function to configure the output sample stamp trigger.

Parameters

base	is the base address of the I2S module.
trigValue	value used to set the trigger.

Returns: None.

References ASSERT, HWREGH, I2S_BASE, and I2S_O_STMPOTRIG.

§ I2SConfigureWclkCounterPeriod()

__STATIC_INLINE void I2SConfigureWclkCounterPeriod	(	uint32_t	base,
		uint16_t	period
	)

Configure the WCLK counter period.

Use this function to configure the period of the WCLK counter.

Parameters

base	is the base address of the I2S module.
period	value used to define when the WCLK counter should reset. This should be configured the size of the sample buffer, in number of frames.

Returns: None.

References ASSERT, HWREGH, I2S_BASE, and I2S_O_STMPWPER.

§ I2SConfigureWclkCounter()

__STATIC_INLINE void I2SConfigureWclkCounter	(	uint32_t	base,
		int16_t	value
	)

Confiugre the WCLK counter value.

Parameters

base	is the base address of the I2S module.
value	is the offset to add to the counter (this value can be negative).

Returns: None.

References ASSERT, HWREGH, I2S_BASE, I2S_O_STMPWADD, and I2S_O_STMPWPER.

§ I2SResetWclkCounter()

__STATIC_INLINE void I2SResetWclkCounter ( uint32_t base )

Reset the WCLK count.

Parameters

base	is the base address of the I2S module.

Returns: None.

References ASSERT, HWREGH, I2S_BASE, and I2S_O_STMPWSET.

§ I2SEnableClk()

__STATIC_INLINE void I2SEnableClk ( uint32_t base )

Enables the clock source.

Parameters

base	is the base address of the I2S module.

Returns: None.

References ASSERT, HWREG, I2S_BASE, I2S_CLKCFG_EN_M, and I2S_O_CLKCFG.

§ I2SDisableClk()

__STATIC_INLINE void I2SDisableClk ( uint32_t base )

Disables the clock source.

Parameters

base	is the base address of the I2S module.

Returns: None.

References ASSERT, HWREG, I2S_BASE, I2S_CLKCFG_EN_M, and I2S_O_CLKCFG.

§ I2SEnableAdfs()

__STATIC_INLINE void I2SEnableAdfs ( uint32_t base )

Enables the ADFS (Adaptive Digital Frequency Synthesizer) module.

Parameters

base	is the base address of the I2S module.

Precondition: ADFS must be configured using I2SConfigureAdfs().

Returns: None.

References ASSERT, HWREG, I2S_BASE, I2S_CLKCFG_ADFSEN_M, and I2S_O_CLKCFG.

§ I2SSelectAdfsInputClk()

__STATIC_INLINE void I2SSelectAdfsInputClk	(	uint32_t	base,
		uint32_t	source
	)

Selects the ADFS inpt clock (Fref)

Parameters

base	is the base address of the I2S module.
source	is the clock source to select: I2S_CLK_SRC_SOC_CLK I2S_CLK_SRC_SOC_PLL_CLK I2S_CLK_SRC_HFXT_CLK

Returns: None.

References ASSERT, HWREG, I2S_BASE, I2S_CLKCFG_CLKSEL_M, and I2S_O_CLKCFG.

§ I2SConfigureAdfs()

__STATIC_INLINE void I2SConfigureAdfs	(	uint32_t	base,
		uint32_t	tref,
		uint32_t	delta,
		uint32_t	deltaSign,
		uint32_t	div
	)

Configures the Adaptive Digital Frequency Synthesizer (ADFS) module.

The ADFS is used to generate arbitrary clock frequency from given input clock by division and adaptive swallowing pattern needed to achieve the required accuracy. The resultant clock frequency mean is equal to the desired value although a significant jitter may occur. The best results are achieved when there is a large factor between the input clock frequency (Fref) and the desired output frequency (Freq). The ADFS is configured with the following parameters:

Parameters

tref	is the Freq period in picoseconds, represented as a fixed-point number with 17 integer bits and 4 fractional bits.
div	is the divisor used to approximate the ratio between Fref and Freq. It is calculated to minimize the error (delta) between the actual and desired frequency ratios. Should be an integer higher or equal than 1.
delta	is the Error in picoseconds that quantifies how far the achieved period (using the chosen divider) deviates from the desired period. It is represented as a fixed-point number with 13 integer bits and 4 fractional bits.
deltaSign	it represents whether delta is negative (1) or non-negative (0).
base	is the base address of the I2S module.

The next equations can be used to compute the parameters:

tref = floor((1 / Fref) * 16)
div_temp1 = floor(Fref / Freq);
div_temp2 = ceil(Fref / Freq);
delta_temp1 = ((1/(Freq*div_temp1))-(1/Fref));
delta_temp2 = ((1/(Freq*div_temp2))-(1/Fref));
if (abs(delta_temp1) < abs(delta_temp2))
{
    div = div_temp1;
    delta = delta_temp1;
}
else
{
    div = div_temp2;
    delta = delta_temp2;
}
deltaSign = (delta < 0) ? 1 : 0;
delta = floor(abs(delta)*16)

Returns: None.

References ASSERT, HWREG, I2S_ADFSCTRL1_TREF_M, I2S_ADFSCTRL2_DELTA_M, I2S_ADFSCTRL2_DELTASIGN_M, I2S_ADFSCTRL2_DELTASIGN_S, I2S_ADFSCTRL2_DIV_M, I2S_ADFSCTRL2_DIV_S, I2S_BASE, I2S_O_ADFSCTRL1, and I2S_O_ADFSCTRL2.

§ I2SDisableAdfs()

__STATIC_INLINE void I2SDisableAdfs ( uint32_t base )

Disables the ADFS (Adaptive Digital Frequency Synthesizer) module.

Parameters

base	is the base address of the I2S module.

Returns: None.

References ASSERT, HWREG, I2S_BASE, I2S_CLKCFG_ADFSEN_M, and I2S_O_CLKCFG.

Macros

Functions

Detailed Description

Macro Definition Documentation

§ I2S_CLK_SRC_SOC_CLK

§ I2S_CLK_SRC_SOC_PLL_CLK

§ I2S_CLK_SRC_HFXT_CLK

§ I2S_SD0_DIS

§ I2S_SD0_IN

§ I2S_SD0_OUT

§ I2S_SD1_DIS

§ I2S_SD1_IN

§ I2S_SD1_OUT

§ I2S_CHAN0_MASK

§ I2S_CHAN1_MASK

§ I2S_CHAN2_MASK

§ I2S_CHAN3_MASK

§ I2S_CHAN4_MASK

§ I2S_CHAN5_MASK

§ I2S_CHAN6_MASK

§ I2S_CHAN7_MASK

§ I2S_MEM_LENGTH_16

§ I2S_MEM_LENGTH_32

§ I2S_POS_EDGE

§ I2S_NEG_EDGE

§ I2S_STMP_SATURATION

§ I2S_INT_XCNT_CAPTURE

§ I2S_INT_DMA_IN

§ I2S_INT_DMA_OUT

§ I2S_INT_TIMEOUT

§ I2S_INT_BUS_ERR

§ I2S_INT_WCLK_ERR

§ I2S_INT_PTR_ERR

§ I2S_INT_ALL

Function Documentation

§ I2SEnableInt()

§ I2SDisableInt()

§ I2SIntStatus()

§ I2SClearInt()

§ I2SEnableSampleStamp()

§ I2SDisableSampleStamp()

§ I2SGetSampleStamp()

§ I2SStart()

§ I2SStop()

§ I2SConfigureFormat()

§ I2SConfigureFrame()

§ I2SConfigureClocks()

§ I2SEnableControllerClocks()

§ I2SDisableControllerClocks()

§ I2SSetInPointer()

§ I2SSetOutPointer()

§ I2SGetInPointerNext()

§ I2SGetOutPointerNext()

§ I2SGetInPointer()

§ I2SGetOutPointer()

§ I2SConfigureInSampleStampTrigger()

§ I2SConfigureOutSampleStampTrigger()

§ I2SConfigureWclkCounterPeriod()

§ I2SConfigureWclkCounter()

§ I2SResetWclkCounter()

§ I2SEnableClk()

§ I2SDisableClk()

§ I2SEnableAdfs()

§ I2SSelectAdfsInputClk()

§ I2SConfigureAdfs()

§ I2SDisableAdfs()