[i2c.h] Inter-Integrated Circuit

Collaboration diagram for [i2c.h] Inter-Integrated Circuit:

Functions
void	I2CControllerInit (uint32_t base, uint32_t config, uint32_t mode)
	Initializes the I2C Controller module. More...
__STATIC_INLINE void	I2CControllerSetCommand (uint32_t base, uint32_t cmd, uint16_t transactionLength)
	Controls the state of the I2C Controller module. More...
__STATIC_INLINE void	I2CControllerSetTargetAddr (uint32_t base, uint32_t addressMode, uint16_t targetAddr, uint32_t direction)
	Sets the address that the I2C Controller will place on the bus. More...
__STATIC_INLINE void	I2CControllerEnable (uint32_t base)
	Enable the I2C Controller module. More...
__STATIC_INLINE void	I2CControllerDisable (uint32_t base)
	Disables the I2C controller module. More...
__STATIC_INLINE bool	I2CControllerIsBusy (uint32_t base)
	Indicates whether or not the I2C Controller is busy. More...
__STATIC_INLINE bool	I2CControllerIsBusBusy (uint32_t base)
	Indicates whether or not the I2C bus is busy. More...
uint32_t	I2CControllerGetError (uint32_t base)
	Gets the error status of the I2C Controller module. More...
__STATIC_INLINE uint32_t	I2CGetTxFifoCount (uint32_t base)
	Get the number of bytes in the TX FIFO. More...
__STATIC_INLINE uint32_t	I2CGetRxFifoCount (uint32_t base)
	Get the number of bytes in the RX FIFO. More...
__STATIC_INLINE bool	I2CIsTxFifoEmpty (uint32_t base)
	Check if TX FIFO is empty. More...
__STATIC_INLINE bool	I2CIsRxFifoEmpty (uint32_t base)
	Check if RX FIFO is empty. More...
__STATIC_INLINE bool	I2CIsTxFifoFull (uint32_t base)
	Check if TX FIFO is full. More...
__STATIC_INLINE bool	I2CIsRxFifoFull (uint32_t base)
	Check if RX FIFO is full. More...
__STATIC_INLINE void	I2CSetTxFifoTrigger (uint32_t base, uint8_t level)
	Set TX FIFO trigger level. More...
__STATIC_INLINE void	I2CSetRxFifoTrigger (uint32_t base, uint8_t level)
	Set RX FIFO trigger level. More...
__STATIC_INLINE void	I2CFlushTxFifo (uint32_t base)
	Flush the I2C TX FIFO. More...
__STATIC_INLINE void	I2CFlushRxFifo (uint32_t base)
	Flush the I2C RX FIFO. More...
__STATIC_INLINE void	I2CFlushFifos (uint32_t base)
	Flush the I2C TX and RX FIFOs. More...
__STATIC_INLINE void	I2CGetData (uint32_t base, uint8_t *data)
	Gets a data element from the I2C RX FIFO. More...
__STATIC_INLINE uint32_t	I2CGetDataNonBlocking (uint32_t base, uint8_t *data)
	Gets a data element from the I2C RX FIFO (non-blocking). More...
__STATIC_INLINE void	I2CPutData (uint32_t base, uint8_t data)
	Puts a data element into the I2C TX FIFO. More...
__STATIC_INLINE uint32_t	I2CPutDataNonBlocking (uint32_t base, uint8_t data)
	Puts a data element into the I2C TX FIFO (non-blocking). More...
__STATIC_INLINE void	I2CEnableInt (uint32_t base, uint32_t intFlags)
	Enables individual I2C interrupt sources. More...
__STATIC_INLINE void	I2CDisableInt (uint32_t base, uint32_t intFlags)
	Disables individual I2C interrupt sources. More...
__STATIC_INLINE void	I2CClearInt (uint32_t base, uint32_t intFlags)
	Clears I2C interrupt sources. More...
__STATIC_INLINE uint32_t	I2CIntStatus (uint32_t base, bool masked)
	Gets the current I2C interrupt status. More...

I2C Controller Commands
For usage details see description of I2CControllerSetCommand()
#define	I2C_CONTROLLER_CMD_SINGLE_SEND   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_STOP_EN_STOP)
#define	I2C_CONTROLLER_CMD_SINGLE_RECEIVE   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_STOP_EN_STOP)
#define	I2C_CONTROLLER_CMD_BURST_SEND_START   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START)
#define	I2C_CONTROLLER_CMD_BURST_SEND_CONT   (I2C_CCTR_BURSTRUN_EN)
#define	I2C_CONTROLLER_CMD_BURST_SEND_FINISH   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)
#define	I2C_CONTROLLER_CMD_BURST_RECEIVE_START   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_ACK_EN_ACK | I2C_CCTR_CACKOEN_EN)
#define	I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_ACK_EN_ACK | I2C_CCTR_CACKOEN_EN)
#define	I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)
#define	I2C_CONTROLLER_CMD_BURST_FINISH   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)

I2C Controller Transaction Length
For usage details see description of I2CControllerSetCommand()
#define	I2C_CONTROLLER_TRANSACTION_LENGTH_MAX   0xFFF
	The maximum length of a burst transaction. More...
#define	I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE   0x001
	The length of a single byte transaction. More...
#define	I2C_CONTROLLER_TRANSACTION_LENGTH_NONE   0x000
	The length to be used together with some commands that does not have any data associated with it. More...

I2C Controller Configurations
#define	I2C_CONTROLLER_CONFIG_DEFAULT   0
	Default configuration. More...
#define	I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION   I2C_CCR_CLKSTRETCH_EN
	Enables the clock stretching detection. More...
#define	I2C_CONTROLLER_CONFIG_MULTI_CONTROLLER_MODE   I2C_CCR_MCST_EN
	Enable Multicontroller mode. More...
#define	I2C_CONTROLLER_CONFIG_LOOPBACK   I2C_CCR_LPBK_EN
	The controller is in a test mode loopback configuration. More...

I2C Controller Transaction Direction
#define	I2C_CONTROLLER_DIR_RECEIVE   I2C_CSA_DIR_RECEIVE
	I2C Controller is initiating a read from the target. More...
#define	I2C_CONTROLLER_DIR_TRANSMIT   I2C_CSA_DIR_TRANSMIT
	I2C Controller is initiating a write to the target. More...

I2C Controller Error Status
#define	I2C_CONTROLLER_ERR_NONE   0
	No error. More...
#define	I2C_CONTROLLER_ERR_ADDR_ACK   I2C_CSR_ADRACK_SET
	The transmitted address was not acknowledged. More...
#define	I2C_CONTROLLER_ERR_DATA_ACK   I2C_CSR_DATACK_SET
	The transmitted data was not acknowledged. More...
#define	I2C_CONTROLLER_ERR_ARB_LOST   I2C_CSR_ARBLST_SET
	The controller lost arbitration. More...

I2C Interrupts
#define	I2C_INT_ALL   0xFFFFFFFF
	The collection of all interrupt sources for the I2C module. More...

I2C Controller Interrupts
#define	I2C_CONTROLLER_INT_RX_DONE   I2C_EVENT0_IMASK_CRXDONE
#define	I2C_CONTROLLER_INT_TX_DONE   I2C_EVENT0_IMASK_CTXDONE
#define	I2C_CONTROLLER_INT_RX_FIFO_TRIGGER   I2C_EVENT0_IMASK_RXFIFOTRGC
#define	I2C_CONTROLLER_INT_TX_FIFO_TRIGGER   I2C_EVENT0_IMASK_TXFIFOTRGC
#define	I2C_CONTROLLER_INT_RX_FIFO_FULL   I2C_EVENT0_IMASK_RXFIFOFULLC
#define	I2C_CONTROLLER_INT_TX_FIFO_FULL   I2C_EVENT0_IMASK_TXFIFOFULLC
#define	I2C_CONTROLLER_INT_TX_FIFO_EMPTY   I2C_EVENT0_IMASK_TXEMPTYC
#define	I2C_CONTROLLER_INT_NACK   I2C_EVENT0_IMASK_CNACK
#define	I2C_CONTROLLER_INT_START   I2C_EVENT0_IMASK_CSTART
#define	I2C_CONTROLLER_INT_STOP   I2C_EVENT0_IMASK_CSTOP
#define	I2C_CONTROLLER_INT_ARB_LOST   I2C_EVENT0_IMASK_CARBLOST

I2C Target Interrupts
#define	I2C_TARGET_INT_RX_DONE   I2C_EVENT0_IMASK_TRXDONE
#define	I2C_TARGET_INT_TX_DONE   I2C_EVENT0_IMASK_TTXDONE
#define	I2C_TARGET_INT_RX_FIFO_TRIGGER   I2C_EVENT0_IMASK_RXFIFOTRGT
#define	I2C_TARGET_INT_TX_FIFO_TRIGGER   I2C_EVENT0_IMASK_TXFIFOTRGT
#define	I2C_TARGET_INT_RX_FIFO_FULL   I2C_EVENT0_IMASK_RXFIFOFULLT
#define	I2C_TARGET_INT_TX_FIFO_FULL   I2C_EVENT0_IMASK_TXFIFOFULLT
#define	I2C_TARGET_INT_TX_FIFO_EMPTY   I2C_EVENT0_IMASK_TXEMPTYT
#define	I2C_TARGET_INT_START   I2C_EVENT0_IMASK_TSTART
#define	I2C_TARGET_INT_STOP   I2C_EVENT0_IMASK_TSTOP
#define	I2C_TARGET_INT_GEN_CALL   I2C_EVENT0_IMASK_TGENCALL
#define	I2C_TARGET_INT_TX_FIFO_UNDERFLOW   I2C_EVENT0_IMASK_TX_UNFL_T
#define	I2C_TARGET_INT_ARB_LOST   I2C_EVENT0_IMASK_CARBLOST

I2C Modes
#define	I2C_MODE_STANDARD   0
	Standard-mode (100kbit/s) More...
#define	I2C_MODE_FAST   1
	Fast-mode (400kbit/s) More...
#define	I2C_MODE_FAST_PLUS   2
	Fast-mode Plus (1Mbit/s) More...

I2C Controller Address modes
#define	I2C_CONTROLLER_ADDR_MODE_7_BIT   I2C_CSA_CMODE_SEVEN_BIT
	7-bit addressing More...
#define	I2C_CONTROLLER_ADDR_MODE_10_BIT   I2C_CSA_CMODE_TEN_BIT
	10-bit addressing More...

I2C Target Address modes
#define	I2C_TARGET_ADDR_MODE_7_BIT   I2C_TOAR_MODE_SEVEN_BIT
	7-bit addressing More...
#define	I2C_TARGET_ADDR_MODE_10_BIT   I2C_TOAR_MODE_TEN_BIT
	10-bit addressing More...

I2C FIFO Macros
#define	I2C_RX_FIFO_SIZE   (I2C_FIFOSR_RXFIFOCNT_MAXIMUM >> I2C_FIFOSR_RXFIFOCNT_S)
#define	I2C_TX_FIFO_SIZE   (I2C_FIFOSR_TXFIFOCNT_MAXIMUM >> I2C_FIFOSR_TXFIFOCNT_S)

Detailed Description

Macro Definition Documentation

I2C_CONTROLLER_CMD_SINGLE_SEND

#define I2C_CONTROLLER_CMD_SINGLE_SEND   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_STOP_EN_STOP)

Referenced by I2CControllerSetCommand().

I2C_CONTROLLER_CMD_SINGLE_RECEIVE

#define I2C_CONTROLLER_CMD_SINGLE_RECEIVE   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_STOP_EN_STOP)

I2C_CONTROLLER_CMD_BURST_SEND_START

#define I2C_CONTROLLER_CMD_BURST_SEND_START   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START)

Referenced by I2CControllerSetCommand().

I2C_CONTROLLER_CMD_BURST_SEND_CONT

#define I2C_CONTROLLER_CMD_BURST_SEND_CONT   (I2C_CCTR_BURSTRUN_EN)

Referenced by I2CControllerSetCommand().

I2C_CONTROLLER_CMD_BURST_SEND_FINISH

#define I2C_CONTROLLER_CMD_BURST_SEND_FINISH   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)

Referenced by I2CControllerSetCommand().

I2C_CONTROLLER_CMD_BURST_RECEIVE_START

#define I2C_CONTROLLER_CMD_BURST_RECEIVE_START   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_START_EN_START | I2C_CCTR_ACK_EN_ACK | I2C_CCTR_CACKOEN_EN)

Referenced by I2CControllerSetCommand().

I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT

#define I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_ACK_EN_ACK | I2C_CCTR_CACKOEN_EN)

Referenced by I2CControllerSetCommand().

I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH

#define I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)

I2C_CONTROLLER_CMD_BURST_FINISH

#define I2C_CONTROLLER_CMD_BURST_FINISH   (I2C_CCTR_BURSTRUN_EN | I2C_CCTR_STOP_EN_STOP)

I2C_CONTROLLER_TRANSACTION_LENGTH_MAX

#define I2C_CONTROLLER_TRANSACTION_LENGTH_MAX   0xFFF

The maximum length of a burst transaction.

I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE

#define I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE   0x001

The length of a single byte transaction.

I2C_CONTROLLER_TRANSACTION_LENGTH_NONE

#define I2C_CONTROLLER_TRANSACTION_LENGTH_NONE   0x000

The length to be used together with some commands that does not have any data associated with it.

I2C_CONTROLLER_CONFIG_DEFAULT

#define I2C_CONTROLLER_CONFIG_DEFAULT   0

Default configuration.

I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION

#define I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION   I2C_CCR_CLKSTRETCH_EN

Enables the clock stretching detection.

Referenced by I2CControllerInit().

I2C_CONTROLLER_CONFIG_MULTI_CONTROLLER_MODE

#define I2C_CONTROLLER_CONFIG_MULTI_CONTROLLER_MODE   I2C_CCR_MCST_EN

Enable Multicontroller mode.

Referenced by I2CControllerInit().

I2C_CONTROLLER_CONFIG_LOOPBACK

#define I2C_CONTROLLER_CONFIG_LOOPBACK   I2C_CCR_LPBK_EN

The controller is in a test mode loopback configuration.

Referenced by I2CControllerInit().

I2C_CONTROLLER_DIR_RECEIVE

#define I2C_CONTROLLER_DIR_RECEIVE   I2C_CSA_DIR_RECEIVE

I²C Controller is initiating a read from the target.

Referenced by I2CControllerSetTargetAddr().

I2C_CONTROLLER_DIR_TRANSMIT

#define I2C_CONTROLLER_DIR_TRANSMIT   I2C_CSA_DIR_TRANSMIT

I²C Controller is initiating a write to the target.

Referenced by I2CControllerSetTargetAddr().

I2C_CONTROLLER_ERR_NONE

#define I2C_CONTROLLER_ERR_NONE   0

No error.

Referenced by I2CControllerGetError().

I2C_CONTROLLER_ERR_ADDR_ACK

#define I2C_CONTROLLER_ERR_ADDR_ACK   I2C_CSR_ADRACK_SET

The transmitted address was not acknowledged.

I2C_CONTROLLER_ERR_DATA_ACK

#define I2C_CONTROLLER_ERR_DATA_ACK   I2C_CSR_DATACK_SET

The transmitted data was not acknowledged.

I2C_CONTROLLER_ERR_ARB_LOST

#define I2C_CONTROLLER_ERR_ARB_LOST   I2C_CSR_ARBLST_SET

The controller lost arbitration.

I2C_INT_ALL

#define I2C_INT_ALL   0xFFFFFFFF

The collection of all interrupt sources for the I²C module.

Can for example be used with I2CDisableInt() or I2CClearInt(), to disable or clear all interrupts.

I2C_CONTROLLER_INT_RX_DONE

#define I2C_CONTROLLER_INT_RX_DONE   I2C_EVENT0_IMASK_CRXDONE

I2C_CONTROLLER_INT_TX_DONE

#define I2C_CONTROLLER_INT_TX_DONE   I2C_EVENT0_IMASK_CTXDONE

I2C_CONTROLLER_INT_RX_FIFO_TRIGGER

#define I2C_CONTROLLER_INT_RX_FIFO_TRIGGER   I2C_EVENT0_IMASK_RXFIFOTRGC

I2C_CONTROLLER_INT_TX_FIFO_TRIGGER

#define I2C_CONTROLLER_INT_TX_FIFO_TRIGGER   I2C_EVENT0_IMASK_TXFIFOTRGC

I2C_CONTROLLER_INT_RX_FIFO_FULL

#define I2C_CONTROLLER_INT_RX_FIFO_FULL   I2C_EVENT0_IMASK_RXFIFOFULLC

I2C_CONTROLLER_INT_TX_FIFO_FULL

#define I2C_CONTROLLER_INT_TX_FIFO_FULL   I2C_EVENT0_IMASK_TXFIFOFULLC

I2C_CONTROLLER_INT_TX_FIFO_EMPTY

#define I2C_CONTROLLER_INT_TX_FIFO_EMPTY   I2C_EVENT0_IMASK_TXEMPTYC

I2C_CONTROLLER_INT_NACK

#define I2C_CONTROLLER_INT_NACK   I2C_EVENT0_IMASK_CNACK

I2C_CONTROLLER_INT_START

#define I2C_CONTROLLER_INT_START   I2C_EVENT0_IMASK_CSTART

I2C_CONTROLLER_INT_STOP

#define I2C_CONTROLLER_INT_STOP   I2C_EVENT0_IMASK_CSTOP

I2C_CONTROLLER_INT_ARB_LOST

#define I2C_CONTROLLER_INT_ARB_LOST   I2C_EVENT0_IMASK_CARBLOST

I2C_TARGET_INT_RX_DONE

#define I2C_TARGET_INT_RX_DONE   I2C_EVENT0_IMASK_TRXDONE

I2C_TARGET_INT_TX_DONE

#define I2C_TARGET_INT_TX_DONE   I2C_EVENT0_IMASK_TTXDONE

I2C_TARGET_INT_RX_FIFO_TRIGGER

#define I2C_TARGET_INT_RX_FIFO_TRIGGER   I2C_EVENT0_IMASK_RXFIFOTRGT

I2C_TARGET_INT_TX_FIFO_TRIGGER

#define I2C_TARGET_INT_TX_FIFO_TRIGGER   I2C_EVENT0_IMASK_TXFIFOTRGT

I2C_TARGET_INT_RX_FIFO_FULL

#define I2C_TARGET_INT_RX_FIFO_FULL   I2C_EVENT0_IMASK_RXFIFOFULLT

I2C_TARGET_INT_TX_FIFO_FULL

#define I2C_TARGET_INT_TX_FIFO_FULL   I2C_EVENT0_IMASK_TXFIFOFULLT

I2C_TARGET_INT_TX_FIFO_EMPTY

#define I2C_TARGET_INT_TX_FIFO_EMPTY   I2C_EVENT0_IMASK_TXEMPTYT

I2C_TARGET_INT_START

#define I2C_TARGET_INT_START   I2C_EVENT0_IMASK_TSTART

I2C_TARGET_INT_STOP

#define I2C_TARGET_INT_STOP   I2C_EVENT0_IMASK_TSTOP

I2C_TARGET_INT_GEN_CALL

#define I2C_TARGET_INT_GEN_CALL   I2C_EVENT0_IMASK_TGENCALL

I2C_TARGET_INT_TX_FIFO_UNDERFLOW

#define I2C_TARGET_INT_TX_FIFO_UNDERFLOW   I2C_EVENT0_IMASK_TX_UNFL_T

I2C_TARGET_INT_ARB_LOST

#define I2C_TARGET_INT_ARB_LOST   I2C_EVENT0_IMASK_CARBLOST

I2C_MODE_STANDARD

#define I2C_MODE_STANDARD   0

Standard-mode (100kbit/s)

Referenced by I2CControllerInit().

I2C_MODE_FAST

#define I2C_MODE_FAST   1

Fast-mode (400kbit/s)

Referenced by I2CControllerInit().

I2C_MODE_FAST_PLUS

#define I2C_MODE_FAST_PLUS   2

Fast-mode Plus (1Mbit/s)

Referenced by I2CControllerInit().

I2C_CONTROLLER_ADDR_MODE_7_BIT

#define I2C_CONTROLLER_ADDR_MODE_7_BIT   I2C_CSA_CMODE_SEVEN_BIT

7-bit addressing

Referenced by I2CControllerSetTargetAddr().

I2C_CONTROLLER_ADDR_MODE_10_BIT

#define I2C_CONTROLLER_ADDR_MODE_10_BIT   I2C_CSA_CMODE_TEN_BIT

10-bit addressing

Referenced by I2CControllerSetTargetAddr().

I2C_TARGET_ADDR_MODE_7_BIT

#define I2C_TARGET_ADDR_MODE_7_BIT   I2C_TOAR_MODE_SEVEN_BIT

7-bit addressing

I2C_TARGET_ADDR_MODE_10_BIT

#define I2C_TARGET_ADDR_MODE_10_BIT   I2C_TOAR_MODE_TEN_BIT

10-bit addressing

I2C_RX_FIFO_SIZE

#define I2C_RX_FIFO_SIZE   (I2C_FIFOSR_RXFIFOCNT_MAXIMUM >> I2C_FIFOSR_RXFIFOCNT_S)

I2C_TX_FIFO_SIZE

#define I2C_TX_FIFO_SIZE   (I2C_FIFOSR_TXFIFOCNT_MAXIMUM >> I2C_FIFOSR_TXFIFOCNT_S)

Function Documentation

I2CControllerInit()

void I2CControllerInit	(	uint32_t	base,
		uint32_t	config,
		uint32_t	mode
	)

Initializes the I²C Controller module.

This function initializes operation of the I²C Controller module. Upon successful initialization of the I²C module, this function will have set the bus speed for the controller, configured the glitch suppression filter for for the given bus speed and will have enabled the I²C Controller module.

Note

The I²C Controller will be enabled by this function.

Parameters

base	is the base address of the I2C module.
config	is the configuration to be used by the I2C Controller module The parameter is the bitwise OR of any of the following: I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION I2C_CONTROLLER_CONFIG_MULTI_CONTROLLER_MODE I2C_CONTROLLER_CONFIG_LOOPBACK Or: I2C_CONTROLLER_CONFIG_DEFAULT
mode	set up the I2C mode I2C_MODE_STANDARD I2C_MODE_FAST I2C_MODE_FAST_PLUS

Returns

None

References ASSERT, HWREG, I2C_CONTROLLER_CONFIG_CLOCK_STRETCHING_DETECTION, I2C_CONTROLLER_CONFIG_LOOPBACK, I2C_CONTROLLER_CONFIG_MULTI_CONTROLLER_MODE, I2C_FCLKDIV_FCLKDIV_BY_2, I2C_FCLKDIV_FCLKDIV_BY_20, I2C_FCLKDIV_FCLKDIV_BY_4, I2C_GFCTL_GFSEL_DIS, I2C_MODE_FAST, I2C_MODE_FAST_PLUS, I2C_MODE_STANDARD, I2C_O_CCR, I2C_O_CTPR, I2C_O_FCLKDIV, I2C_O_GFCTL, and I2CControllerEnable().

I2CControllerSetCommand()

__STATIC_INLINE void I2CControllerSetCommand	(	uint32_t	base,
		uint32_t	cmd,
		uint16_t	transactionLength
	)

Controls the state of the I²C Controller module.

This function is used to control the state of the Controller module send and receive operations.

To perform a single-byte transmit transaction:

• Put the byte to transmit in the TX FIFO
• Call this function with:
  • transactionLength: I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE
  • cmd: I2C_CONTROLLER_CMD_SINGLE_SEND
• Wait until the the command is done.

To perform a single-byte receive transaction:

• Call this function with:
  • transactionLength: I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE
  • cmd: I2C_CONTROLLER_CMD_SINGLE_RECEIVE
• Wait until the command is done.
• If the transaction was successful, the received byte can be read from the RX FIFO.

To perform a multi-byte transmit transaction:

• Fill the TX FIFO with the first bytes of the transaction.
• Call this function with:
  • transactionLength: The number of bytes in the transaction, but at max I2C_CONTROLLER_TRANSACTION_LENGTH_MAX.
  • cmd: I2C_CONTROLLER_CMD_BURST_SEND_START.
• While the command is executing, repeatedly fill the TX FIFO with the data of the transaction.
• The command is done when transactionLength bytes has been transmitted.
• If more data needs to be transmitted call this function with below parameters and then continue to fill the TX FIFO as described above:
  • transactionLength: The number of remaining bytes in the transaction, but at max I2C_CONTROLLER_TRANSACTION_LENGTH_MAX.
  • cmd: I2C_CONTROLLER_CMD_BURST_SEND_CONT
• If no more data needs to be transmitted, end the I²C transaction by calling this function with:
  • transactionLength: I2C_CONTROLLER_TRANSACTION_LENGTH_NONE
  • cmd: I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH or I2C_CONTROLLER_CMD_BURST_FINISH.
• Alternatively, a repeated start condition can be sent either using I2C_CONTROLLER_CMD_BURST_SEND_START or I2C_CONTROLLER_CMD_BURST_RECEIVE_START

To perform a multi-byte receive transaction:

• Call this function with:
  • transactionLength: The number of bytes in the transaction, but at max I2C_CONTROLLER_TRANSACTION_LENGTH_MAX.
  • cmd: I2C_CONTROLLER_CMD_BURST_RECEIVE_START.
• While the command is executing repeatedly read the received data from the RX FIFO.
• The command is done when transactionLength bytes has been received.
• If more data needs to be received call this function with below parameters and then continue to read the RX FIFO as described above:
  • transactionLength: The number of remaining bytes in the transaction, but at max I2C_CONTROLLER_TRANSACTION_LENGTH_MAX.
  • cmd: I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT
• If no more data needs to be received, end the I²C transaction by calling this function with:
  • transactionLength: I2C_CONTROLLER_TRANSACTION_LENGTH_NONE
  • cmd: I2C_CONTROLLER_CMD_BURST_SEND_FINISH or I2C_CONTROLLER_CMD_BURST_FINISH.
• Alternatively, a repeated start condition can be sent either using I2C_CONTROLLER_CMD_BURST_SEND_START or I2C_CONTROLLER_CMD_BURST_RECEIVE_START

Parameters

base	is the base address of the I2C module.
cmd	is the command to be issued by the I2C Controller module The parameter can be one of the following values: I2C_CONTROLLER_CMD_SINGLE_SEND I2C_CONTROLLER_CMD_SINGLE_RECEIVE I2C_CONTROLLER_CMD_BURST_SEND_START I2C_CONTROLLER_CMD_BURST_SEND_CONT I2C_CONTROLLER_CMD_BURST_SEND_FINISH I2C_CONTROLLER_CMD_BURST_RECEIVE_START I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH I2C_CONTROLLER_CMD_BURST_FINISH
transactionLength	Single transaction commands: I2C_CONTROLLER_TRANSACTION_LENGTH_SINGLE Burst start and continue transaction commands: The number of bytes in the transaction (Max: I2C_CONTROLLER_TRANSACTION_LENGTH_MAX ) Burst finish commands: I2C_CONTROLLER_TRANSACTION_LENGTH_NONE

Returns

None

References ASSERT, HWREG, I2C_CCTR_MBLEN_M, I2C_CCTR_MBLEN_S, I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT, I2C_CONTROLLER_CMD_BURST_RECEIVE_START, I2C_CONTROLLER_CMD_BURST_SEND_CONT, I2C_CONTROLLER_CMD_BURST_SEND_FINISH, I2C_CONTROLLER_CMD_BURST_SEND_START, I2C_CONTROLLER_CMD_SINGLE_SEND, and I2C_O_CCTR.

I2CControllerSetTargetAddr()

__STATIC_INLINE void I2CControllerSetTargetAddr	(	uint32_t	base,
		uint32_t	addressMode,
		uint16_t	targetAddr,
		uint32_t	direction
	)

Sets the address that the I²C Controller will place on the bus.

This function will set the address mode, address and direction that the I²C Controller will place on the bus when initiating a transaction.

Parameters

base	is the base address of the I2C module.
addressMode	specifies the address mode to be used by the I2C Controller. I2C_CONTROLLER_ADDR_MODE_7_BIT I2C_CONTROLLER_ADDR_MODE_10_BIT
targetAddr	is a 7-bit or 10-bit target address
direction	indicates the direction of the transaction. I2C_CONTROLLER_DIR_RECEIVE I2C_CONTROLLER_DIR_TRANSMIT

Returns

None

References ASSERT, HWREG, I2C_CONTROLLER_ADDR_MODE_10_BIT, I2C_CONTROLLER_ADDR_MODE_7_BIT, I2C_CONTROLLER_DIR_RECEIVE, I2C_CONTROLLER_DIR_TRANSMIT, I2C_CSA_TADDR_S, and I2C_O_CSA.

I2CControllerEnable()

__STATIC_INLINE void I2CControllerEnable

(

uint32_t

base

)

Enable the I²C Controller module.

This will enable operation of the I²C Controller module.

Warning

Do not call this function if the I²C Controller is already enabled. Otherwise transfer failures may occur.

Parameters

base	is the base address of the I2C module.

Returns

None

References ASSERT, HWREG, I2C_CCR_ACTIVE_EN, and I2C_O_CCR.

Referenced by I2CControllerInit().

I2CControllerDisable()

__STATIC_INLINE void I2CControllerDisable

(

uint32_t

base

)

Disables the I²C controller module.

This will disable operation of the I²C controller module.

Parameters

base	is the base address of the I2C module.

Returns

None

References ASSERT, HWREG, I2C_CCR_ACTIVE_EN, and I2C_O_CCR.

I2CControllerIsBusy()

__STATIC_INLINE bool I2CControllerIsBusy

(

uint32_t

base

)

Indicates whether or not the I²C Controller is busy.

This function returns an indication of whether or not the I²C Controller is busy transmitting or receiving data.

Parameters

base	is the base address of the I2C module.

Returns

Returns status of I²C Controller:

• true : I²C Controller is busy.
• false : I²C Controller is not busy.

References ASSERT, HWREG, I2C_CSR_BUSY_M, I2C_CSR_BUSY_SET, and I2C_O_CSR.

I2CControllerIsBusBusy()

__STATIC_INLINE bool I2CControllerIsBusBusy

(

uint32_t

base

)

Indicates whether or not the I²C bus is busy.

This function returns an indication of whether or not the I²C bus is busy. This function can be used in a multi-controller environment to determine if another controller is currently using the bus.

Parameters

base	is the base address of the I2C module.

Returns

Returns status of the I²C bus:

• true : I²C bus is busy.
• false : I²C bus is not busy.

References ASSERT, HWREG, I2C_CSR_BUSBSY_M, I2C_CSR_BUSBSY_SET, I2C_O_CSR, and I2CControllerGetError().

I2CControllerGetError()

uint32_t I2CControllerGetError

(

uint32_t

base

)

Gets the error status of the I²C Controller module.

This function is used to obtain the error status of the Controller module send and receive operations.

Parameters

base	is the base address of the I2C module.

Returns

Returns the error status of the Controller module:

• I2C_CONTROLLER_ERR_NONE
• I2C_CONTROLLER_ERR_ADDR_ACK
• I2C_CONTROLLER_ERR_DATA_ACK
• I2C_CONTROLLER_ERR_ARB_LOST

References ASSERT, HWREG, I2C_CONTROLLER_ERR_NONE, I2C_CSR_ADRACK_M, I2C_CSR_ARBLST_M, I2C_CSR_DATACK_M, I2C_CSR_ERR_M, and I2C_O_CSR.

Referenced by I2CControllerIsBusBusy().

I2CGetTxFifoCount()

__STATIC_INLINE uint32_t I2CGetTxFifoCount

(

uint32_t

base

)

Get the number of bytes in the TX FIFO.

Parameters

base	is the base address of the I2C module.

Returns

Returns the number of bytes in the TX FIFO

References ASSERT, HWREG, I2C_FIFOSR_TXFIFOCNT_M, I2C_FIFOSR_TXFIFOCNT_MAXIMUM, I2C_FIFOSR_TXFIFOCNT_S, and I2C_O_FIFOSR.

I2CGetRxFifoCount()

__STATIC_INLINE uint32_t I2CGetRxFifoCount

(

uint32_t

base

)

Get the number of bytes in the RX FIFO.

Parameters

base	is the base address of the I2C module.

Returns

Returns the number of bytes in the RX FIFO

References ASSERT, HWREG, I2C_FIFOSR_RXFIFOCNT_M, I2C_FIFOSR_RXFIFOCNT_S, and I2C_O_FIFOSR.

I2CIsTxFifoEmpty()

__STATIC_INLINE bool I2CIsTxFifoEmpty

(

uint32_t

base

)

Check if TX FIFO is empty.

Parameters

base	is the base address of the I2C module.

Returns

Returns true if the TX FIFO is empty otherwise false.

References ASSERT, HWREG, I2C_FIFOSR_TXFIFOCNT_M, I2C_FIFOSR_TXFIFOCNT_MAXIMUM, and I2C_O_FIFOSR.

Referenced by I2CFlushTxFifo().

I2CIsRxFifoEmpty()

__STATIC_INLINE bool I2CIsRxFifoEmpty

(

uint32_t

base

)

Check if RX FIFO is empty.

Parameters

base	is the base address of the I2C module.

Returns

Returns true if the RX FIFO is empty otherwise false.

References ASSERT, HWREG, I2C_FIFOSR_RXFIFOCNT_M, I2C_FIFOSR_RXFIFOCNT_MINIMUM, and I2C_O_FIFOSR.

Referenced by I2CFlushRxFifo(), I2CGetData(), and I2CGetDataNonBlocking().

I2CIsTxFifoFull()

__STATIC_INLINE bool I2CIsTxFifoFull

(

uint32_t

base

)

Check if TX FIFO is full.

Parameters

base	is the base address of the I2C module.

Returns

Returns true if the TX FIFO is full otherwise false.

References ASSERT, HWREG, I2C_FIFOSR_TXFIFOCNT_M, I2C_FIFOSR_TXFIFOCNT_MINIMUM, and I2C_O_FIFOSR.

Referenced by I2CPutData(), and I2CPutDataNonBlocking().

I2CIsRxFifoFull()

__STATIC_INLINE bool I2CIsRxFifoFull

(

uint32_t

base

)

Check if RX FIFO is full.

Parameters

base	is the base address of the I2C module.

Returns

Returns true of the RX FIFO is full otherwise false.

References ASSERT, HWREG, I2C_FIFOSR_RXFIFOCNT_M, I2C_FIFOSR_RXFIFOCNT_MAXIMUM, and I2C_O_FIFOSR.

I2CSetTxFifoTrigger()

__STATIC_INLINE void I2CSetTxFifoTrigger	(	uint32_t	base,
		uint8_t	level
	)

Set TX FIFO trigger level.

Indicates at what fill level in the TX FIFO a trigger will be generated. Trigger when TX FIFO contains <= level byte(s).

Parameters

base	is the base address of the I2C module.
level	is the trigger level. Must be in the interval [0, 7]

References ASSERT, HWREG, I2C_FIFOCTL_TXTRIG_M, I2C_FIFOCTL_TXTRIG_S, and I2C_O_FIFOCTL.

I2CSetRxFifoTrigger()

__STATIC_INLINE void I2CSetRxFifoTrigger	(	uint32_t	base,
		uint8_t	level
	)

Set RX FIFO trigger level.

Indicates at what fill level in the RX FIFO a trigger will be generated. Trigger when RX FIFO contains >= level byte(s).

Parameters

base	is the base address of the I2C module.
level	is the trigger level. Must be in the interval [1, 8]

References ASSERT, HWREG, I2C_FIFOCTL_RXTRIG_M, I2C_FIFOCTL_RXTRIG_S, and I2C_O_FIFOCTL.

I2CFlushTxFifo()

__STATIC_INLINE void I2CFlushTxFifo

(

uint32_t

base

)

Flush the I²C TX FIFO.

This function will instruct the I²C module to flush the TX FIFO and wait until the TX FIFO has been flushed.

Warning

The FIFOs must only be flushed when the I²C is in IDLE mode.

Precondition

The FIFO interrupts need to be disabled.

• I2C_CONTROLLER_INT_TX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_TX_FIFO_FULL
• I2C_CONTROLLER_INT_TX_FIFO_EMPTY
• I2C_TARGET_INT_TX_FIFO_TRIGGER
• I2C_TARGET_INT_TX_FIFO_FULL
• I2C_TARGET_INT_TX_FIFO_UNDERFLOW

Postcondition

The FIFO interrupt flags need to be checked.

Parameters

base	is the base address of the I2C module.

Returns

None

References ASSERT, HWREG, I2C_FIFOCTL_TXFLUSH_EN, I2C_O_FIFOCTL, and I2CIsTxFifoEmpty().

I2CFlushRxFifo()

__STATIC_INLINE void I2CFlushRxFifo

(

uint32_t

base

)

Flush the I²C RX FIFO.

This function will instruct the I²C module to flush the RX FIFO and wait until the RX FIFO has been flushed.

Warning

The FIFOs must only be flushed when the I²C is in IDLE mode.

Precondition

The FIFO interrupts need to be disabled.

• I2C_CONTROLLER_INT_RX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_TX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_RX_FIFO_FULL
• I2C_CONTROLLER_INT_TX_FIFO_FULL
• I2C_CONTROLLER_INT_TX_FIFO_EMPTY
• I2C_TARGET_INT_RX_FIFO_TRIGGER
• I2C_TARGET_INT_TX_FIFO_TRIGGER
• I2C_TARGET_INT_RX_FIFO_FULL
• I2C_TARGET_INT_TX_FIFO_FULL
• I2C_TARGET_INT_TX_FIFO_UNDERFLOW

Postcondition

The FIFO interrupt flags need to be checked.

Parameters

base	is the base address of the I2C module.

Returns

None

References ASSERT, HWREG, I2C_FIFOCTL_RXFLUSH_EN, I2C_O_FIFOCTL, and I2CIsRxFifoEmpty().

I2CFlushFifos()

__STATIC_INLINE void I2CFlushFifos

(

uint32_t

base

)

Flush the I²C TX and RX FIFOs.

This function will instruct the I²C module to flush the TX and RX FIFOs and wait until both FIFOs have been flushed. Using this function is slightly more efficient than sequentially using I2CFlushRxFifo and I2CFlushTxFifo

Warning

The FIFOs must only be flushed when the I²C is in IDLE mode.

Precondition

The FIFO interrupts need to be disabled.

• I2C_CONTROLLER_INT_RX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_TX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_RX_FIFO_FULL
• I2C_CONTROLLER_INT_TX_FIFO_FULL
• I2C_CONTROLLER_INT_TX_FIFO_EMPTY
• I2C_TARGET_INT_RX_FIFO_TRIGGER
• I2C_TARGET_INT_TX_FIFO_TRIGGER
• I2C_TARGET_INT_RX_FIFO_FULL
• I2C_TARGET_INT_TX_FIFO_FULL
• I2C_TARGET_INT_TX_FIFO_UNDERFLOW

Postcondition

The FIFO interrupt flags need to be checked.

Parameters

base	is the base address of the I2C module.

Returns

None

References ASSERT, HWREG, I2C_FIFOCTL_RXFLUSH_EN, I2C_FIFOCTL_TXFLUSH_EN, I2C_FIFOSR_RXFIFOCNT_M, I2C_FIFOSR_RXFIFOCNT_MINIMUM, I2C_FIFOSR_TXFIFOCNT_M, I2C_FIFOSR_TXFIFOCNT_MAXIMUM, I2C_O_FIFOCTL, and I2C_O_FIFOSR.

I2CGetData()

__STATIC_INLINE void I2CGetData	(	uint32_t	base,
		uint8_t *	data
	)

Gets a data element from the I²C RX FIFO.

This function reads a byte of data from the RX FIFO of the specified I²C module and places that data into the location specified by the data parameter. If there is no data in the RX FIFO, this function waits until a byte is available before returning.

Parameters

base	is the base address of the I2C module.
data	is a pointer to a storage location for the data read from the RX FIFO

Returns

None

References ASSERT, HWREGB, I2C_O_RXDATA, and I2CIsRxFifoEmpty().

I2CGetDataNonBlocking()

__STATIC_INLINE uint32_t I2CGetDataNonBlocking	(	uint32_t	base,
		uint8_t *	data
	)

Gets a data element from the I²C RX FIFO (non-blocking).

This function reads a byte of data from the RX FIFO of the specified I²C module and places that data into the location specified by the data parameter. If there is no data in the RX FIFO, this function returns a zero.

Parameters

base	is the base address of the I2C module.
data	is a pointer to a storage location for the data read from the RX FIFO

Returns

Returns the number of bytes read from the I²C RX FIFO (0 or 1).

References ASSERT, HWREGB, I2C_O_RXDATA, and I2CIsRxFifoEmpty().

I2CPutData()

__STATIC_INLINE void I2CPutData	(	uint32_t	base,
		uint8_t	data
	)

Puts a data element into the I²C TX FIFO.

This function places the supplied data into the TX FIFO of the specified I²C module. If there is no space available in the TX FIFO, this function waits until there is space available before returning.

Parameters

base	is the base address of the I2C module.
data	is the data to be written to the TX FIFO.

Returns

None

References ASSERT, HWREGB, I2C_O_TXDATA, and I2CIsTxFifoFull().

I2CPutDataNonBlocking()

__STATIC_INLINE uint32_t I2CPutDataNonBlocking	(	uint32_t	base,
		uint8_t	data
	)

Puts a data element into the I²C TX FIFO (non-blocking).

This function places the supplied data into the TX FIFO of the specified I²C module. If there is no space in the TX FIFO, this function returns a zero.

Parameters

base	is the base address of the I2C module.
data	is the data to be written to the TX FIFO.

Returns

Returns the number of bytes written to the I²C TX FIFO (0 or 1).

References ASSERT, HWREGB, I2C_O_TXDATA, and I2CIsTxFifoFull().

I2CEnableInt()

__STATIC_INLINE void I2CEnableInt	(	uint32_t	base,
		uint32_t	intFlags
	)

Enables individual I²C interrupt sources.

Enables the indicated I²C interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

Parameters

base

is the base address of the I2C module.

intFlags

is the bit mask of the interrupt sources to be enabled. The parameter is the bitwise OR of any of the following: I2C_CONTROLLER_INT_RX_DONE I2C_CONTROLLER_INT_TX_DONE I2C_CONTROLLER_INT_RX_FIFO_TRIGGER I2C_CONTROLLER_INT_TX_FIFO_TRIGGER I2C_CONTROLLER_INT_RX_FIFO_FULL I2C_CONTROLLER_INT_RX_FIFO_FULL I2C_CONTROLLER_INT_TX_FIFO_EMPTY I2C_CONTROLLER_INT_NACK I2C_CONTROLLER_INT_START I2C_CONTROLLER_INT_STOP I2C_CONTROLLER_INT_ARB_LOST I2C_TARGET_INT_RX_DONE I2C_TARGET_INT_TX_DONE I2C_TARGET_INT_RX_FIFO_TRIGGER I2C_TARGET_INT_TX_FIFO_TRIGGER I2C_TARGET_INT_RX_FIFO_FULL I2C_TARGET_INT_RX_FIFO_FULL I2C_TARGET_INT_TX_FIFO_EMPTY I2C_TARGET_INT_START I2C_TARGET_INT_STOP I2C_TARGET_INT_GEN_CALL I2C_TARGET_INT_TX_FIFO_UNDERFLOW I2C_TARGET_INT_ARB_LOST

Returns

None

References ASSERT, HWREG, and I2C_O_EVENT0_IMEN.

I2CDisableInt()

__STATIC_INLINE void I2CDisableInt	(	uint32_t	base,
		uint32_t	intFlags
	)

Disables individual I²C interrupt sources.

Disables the indicated I²C interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

Parameters

base

is the base address of the I2C module.

intFlags

is the bit mask of the interrupt sources to be disabled. The parameter is the bitwise OR of any of the following: I2C_CONTROLLER_INT_RX_DONE I2C_CONTROLLER_INT_TX_DONE I2C_CONTROLLER_INT_RX_FIFO_TRIGGER I2C_CONTROLLER_INT_TX_FIFO_TRIGGER I2C_CONTROLLER_INT_RX_FIFO_FULL I2C_CONTROLLER_INT_RX_FIFO_FULL I2C_CONTROLLER_INT_TX_FIFO_EMPTY I2C_CONTROLLER_INT_NACK I2C_CONTROLLER_INT_START I2C_CONTROLLER_INT_STOP I2C_CONTROLLER_INT_ARB_LOST I2C_TARGET_INT_RX_DONE I2C_TARGET_INT_TX_DONE I2C_TARGET_INT_RX_FIFO_TRIGGER I2C_TARGET_INT_TX_FIFO_TRIGGER I2C_TARGET_INT_RX_FIFO_FULL I2C_TARGET_INT_RX_FIFO_FULL I2C_TARGET_INT_TX_FIFO_EMPTY I2C_TARGET_INT_START I2C_TARGET_INT_STOP I2C_TARGET_INT_GEN_CALL I2C_TARGET_INT_TX_FIFO_UNDERFLOW I2C_TARGET_INT_ARB_LOST I2C_INT_ALL can be used to disable all interrupts

Returns

None

References ASSERT, HWREG, and I2C_O_EVENT0_IMDIS.

I2CClearInt()

__STATIC_INLINE void I2CClearInt	(	uint32_t	base,
		uint32_t	intFlags
	)

Clears I²C interrupt sources.

The specified I²C interrupt sources are cleared, so that they no longer assert. This must be done in the interrupt handler to keep it from being called again immediately upon exit.

TODO: Determine if below note is needed (LPRFXXWARE-845)

Note

Due to write buffers and synchronizers in the system it may take several clock cycles from a register write clearing an event in a module and until the event is actually cleared in the NVIC of the system CPU. It is recommended to clear the event source early in the interrupt service routine (ISR) to allow the event clear to propagate to the NVIC before returning from the ISR. At the same time, an early event clear allows new events of the same type to be pended instead of ignored if the event is cleared later in the ISR. It is the responsibility of the programmer to make sure that enough time has passed before returning from the ISR to avoid false re-triggering of the cleared event. A simple, although not necessarily optimal, way of clearing an event before returning from the ISR is:

1. Write to clear event (interrupt source). (buffered write)
2. Dummy read from the event source module. (making sure the write has propagated)
3. Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)

Parameters

base

is the base address of the I2C module.

intFlags

is a bit mask of the interrupt sources to be cleared. The parameter is the bitwise OR of any of the following: I2C_CONTROLLER_INT_RX_DONE I2C_CONTROLLER_INT_TX_DONE I2C_CONTROLLER_INT_RX_FIFO_TRIGGER I2C_CONTROLLER_INT_TX_FIFO_TRIGGER I2C_CONTROLLER_INT_RX_FIFO_FULL I2C_CONTROLLER_INT_RX_FIFO_FULL I2C_CONTROLLER_INT_TX_FIFO_EMPTY I2C_CONTROLLER_INT_NACK I2C_CONTROLLER_INT_START I2C_CONTROLLER_INT_STOP I2C_CONTROLLER_INT_ARB_LOST I2C_TARGET_INT_RX_DONE I2C_TARGET_INT_TX_DONE I2C_TARGET_INT_RX_FIFO_TRIGGER I2C_TARGET_INT_TX_FIFO_TRIGGER I2C_TARGET_INT_RX_FIFO_FULL I2C_TARGET_INT_RX_FIFO_FULL I2C_TARGET_INT_TX_FIFO_EMPTY I2C_TARGET_INT_START I2C_TARGET_INT_STOP I2C_TARGET_INT_GEN_CALL I2C_TARGET_INT_TX_FIFO_UNDERFLOW I2C_TARGET_INT_ARB_LOST I2C_INT_ALL can be used to clear all interrupts

Returns

None

References ASSERT, HWREG, and I2C_O_EVENT0_IDIS.

I2CIntStatus()

__STATIC_INLINE uint32_t I2CIntStatus	(	uint32_t	base,
		bool	masked
	)

Gets the current I²C interrupt status.

This returns the interrupt status for the I²C module. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Parameters

base	is the base address of the I2C module.
masked	selects either raw or masked interrupt status. false : Raw interrupt status is requested. true : Masked interrupt status is requested.

Returns

Returns the current interrupt status as an OR'ed combination of:

• I2C_CONTROLLER_INT_RX_DONE
• I2C_CONTROLLER_INT_TX_DONE
• I2C_CONTROLLER_INT_RX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_TX_FIFO_TRIGGER
• I2C_CONTROLLER_INT_RX_FIFO_FULL
• I2C_CONTROLLER_INT_RX_FIFO_FULL
• I2C_CONTROLLER_INT_TX_FIFO_EMPTY
• I2C_CONTROLLER_INT_NACK
• I2C_CONTROLLER_INT_START
• I2C_CONTROLLER_INT_STOP
• I2C_CONTROLLER_INT_ARB_LOST
• I2C_TARGET_INT_RX_DONE
• I2C_TARGET_INT_TX_DONE
• I2C_TARGET_INT_RX_FIFO_TRIGGER
• I2C_TARGET_INT_TX_FIFO_TRIGGER
• I2C_TARGET_INT_RX_FIFO_FULL
• I2C_TARGET_INT_RX_FIFO_FULL
• I2C_TARGET_INT_TX_FIFO_EMPTY
• I2C_TARGET_INT_START
• I2C_TARGET_INT_STOP
• I2C_TARGET_INT_GEN_CALL
• I2C_TARGET_INT_TX_FIFO_UNDERFLOW
• I2C_TARGET_INT_ARB_LOST

References ASSERT, HWREG, I2C_O_EVENT0_MIS, and I2C_O_EVENT0_RIS.