CC35xxDriverLibrary
core_armv8mml.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30  #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32 
33 #ifndef __CORE_ARMV8MML_H_GENERIC
34 #define __CORE_ARMV8MML_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
57 /*******************************************************************************
58  * CMSIS definitions
59  ******************************************************************************/
65 #include "cmsis_version.h"
66 
67 /* CMSIS Armv8MML definitions */
68 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
71  __ARMv8MML_CMSIS_VERSION_SUB )
73 #define __CORTEX_M (80U)
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81  #define __FPU_USED 1U
82  #else
83  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84  #define __FPU_USED 0U
85  #endif
86  #else
87  #define __FPU_USED 0U
88  #endif
89 
90  #if defined(__ARM_FEATURE_DSP)
91  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
92  #define __DSP_USED 1U
93  #else
94  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
95  #define __DSP_USED 0U
96  #endif
97  #else
98  #define __DSP_USED 0U
99  #endif
100 
101 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
102  #if defined __ARM_FP
103  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
104  #define __FPU_USED 1U
105  #else
106  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107  #define __FPU_USED 0U
108  #endif
109  #else
110  #define __FPU_USED 0U
111  #endif
112 
113  #if defined(__ARM_FEATURE_DSP)
114  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
115  #define __DSP_USED 1U
116  #else
117  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
118  #define __DSP_USED 0U
119  #endif
120  #else
121  #define __DSP_USED 0U
122  #endif
123 
124 #elif defined ( __GNUC__ )
125  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
126  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136  #if defined(__ARM_FEATURE_DSP)
137  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
138  #define __DSP_USED 1U
139  #else
140  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
141  #define __DSP_USED 0U
142  #endif
143  #else
144  #define __DSP_USED 0U
145  #endif
146 
147 #elif defined ( __ICCARM__ )
148  #if defined __ARMVFP__
149  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
150  #define __FPU_USED 1U
151  #else
152  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
153  #define __FPU_USED 0U
154  #endif
155  #else
156  #define __FPU_USED 0U
157  #endif
158 
159  #if defined(__ARM_FEATURE_DSP)
160  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
161  #define __DSP_USED 1U
162  #else
163  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
164  #define __DSP_USED 0U
165  #endif
166  #else
167  #define __DSP_USED 0U
168  #endif
169 
170 #elif defined ( __TI_ARM__ )
171  #if defined __TI_VFP_SUPPORT__
172  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
173  #define __FPU_USED 1U
174  #else
175  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
176  #define __FPU_USED 0U
177  #endif
178  #else
179  #define __FPU_USED 0U
180  #endif
181 
182 #elif defined ( __TASKING__ )
183  #if defined __FPU_VFP__
184  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
185  #define __FPU_USED 1U
186  #else
187  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
188  #define __FPU_USED 0U
189  #endif
190  #else
191  #define __FPU_USED 0U
192  #endif
193 
194 #elif defined ( __CSMC__ )
195  #if ( __CSMC__ & 0x400U)
196  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
197  #define __FPU_USED 1U
198  #else
199  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
200  #define __FPU_USED 0U
201  #endif
202  #else
203  #define __FPU_USED 0U
204  #endif
205 
206 #endif
207 
208 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
209 
210 
211 #ifdef __cplusplus
212 }
213 #endif
214 
215 #endif /* __CORE_ARMV8MML_H_GENERIC */
216 
217 #ifndef __CMSIS_GENERIC
218 
219 #ifndef __CORE_ARMV8MML_H_DEPENDANT
220 #define __CORE_ARMV8MML_H_DEPENDANT
221 
222 #ifdef __cplusplus
223  extern "C" {
224 #endif
225 
226 /* check device defines and use defaults */
227 #if defined __CHECK_DEVICE_DEFINES
228  #ifndef __ARMv8MML_REV
229  #define __ARMv8MML_REV 0x0000U
230  #warning "__ARMv8MML_REV not defined in device header file; using default!"
231  #endif
232 
233  #ifndef __FPU_PRESENT
234  #define __FPU_PRESENT 0U
235  #warning "__FPU_PRESENT not defined in device header file; using default!"
236  #endif
237 
238  #ifndef __MPU_PRESENT
239  #define __MPU_PRESENT 0U
240  #warning "__MPU_PRESENT not defined in device header file; using default!"
241  #endif
242 
243  #ifndef __SAUREGION_PRESENT
244  #define __SAUREGION_PRESENT 0U
245  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
246  #endif
247 
248  #ifndef __DSP_PRESENT
249  #define __DSP_PRESENT 0U
250  #warning "__DSP_PRESENT not defined in device header file; using default!"
251  #endif
252 
253  #ifndef __VTOR_PRESENT
254  #define __VTOR_PRESENT 1U
255  #warning "__VTOR_PRESENT not defined in device header file; using default!"
256  #endif
257 
258  #ifndef __NVIC_PRIO_BITS
259  #define __NVIC_PRIO_BITS 3U
260  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
261  #endif
262 
263  #ifndef __Vendor_SysTickConfig
264  #define __Vendor_SysTickConfig 0U
265  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
266  #endif
267 #endif
268 
269 /* IO definitions (access restrictions to peripheral registers) */
277 #ifdef __cplusplus
278  #define __I volatile
279 #else
280  #define __I volatile const
281 #endif
282 #define __O volatile
283 #define __IO volatile
285 /* following defines should be used for structure members */
286 #define __IM volatile const
287 #define __OM volatile
288 #define __IOM volatile
290 
294 /*******************************************************************************
295  * Register Abstraction
296  Core Register contain:
297  - Core Register
298  - Core NVIC Register
299  - Core SCB Register
300  - Core SysTick Register
301  - Core Debug Register
302  - Core MPU Register
303  - Core SAU Register
304  - Core FPU Register
305  ******************************************************************************/
306 
321 typedef union
322 {
323  struct
324  {
325  uint32_t _reserved0:16;
326  uint32_t GE:4;
327  uint32_t _reserved1:7;
328  uint32_t Q:1;
329  uint32_t V:1;
330  uint32_t C:1;
331  uint32_t Z:1;
332  uint32_t N:1;
333  } b;
334  uint32_t w;
335 } APSR_Type;
336 
337 /* APSR Register Definitions */
338 #define APSR_N_Pos 31U
339 #define APSR_N_Msk (1UL << APSR_N_Pos)
341 #define APSR_Z_Pos 30U
342 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
344 #define APSR_C_Pos 29U
345 #define APSR_C_Msk (1UL << APSR_C_Pos)
347 #define APSR_V_Pos 28U
348 #define APSR_V_Msk (1UL << APSR_V_Pos)
350 #define APSR_Q_Pos 27U
351 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
353 #define APSR_GE_Pos 16U
354 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
360 typedef union
361 {
362  struct
363  {
364  uint32_t ISR:9;
365  uint32_t _reserved0:23;
366  } b;
367  uint32_t w;
368 } IPSR_Type;
369 
370 /* IPSR Register Definitions */
371 #define IPSR_ISR_Pos 0U
372 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
378 typedef union
379 {
380  struct
381  {
382  uint32_t ISR:9;
383  uint32_t _reserved0:7;
384  uint32_t GE:4;
385  uint32_t _reserved1:4;
386  uint32_t T:1;
387  uint32_t IT:2;
388  uint32_t Q:1;
389  uint32_t V:1;
390  uint32_t C:1;
391  uint32_t Z:1;
392  uint32_t N:1;
393  } b;
394  uint32_t w;
395 } xPSR_Type;
396 
397 /* xPSR Register Definitions */
398 #define xPSR_N_Pos 31U
399 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
401 #define xPSR_Z_Pos 30U
402 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
404 #define xPSR_C_Pos 29U
405 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
407 #define xPSR_V_Pos 28U
408 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
410 #define xPSR_Q_Pos 27U
411 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
413 #define xPSR_IT_Pos 25U
414 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
416 #define xPSR_T_Pos 24U
417 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
419 #define xPSR_GE_Pos 16U
420 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
422 #define xPSR_ISR_Pos 0U
423 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
429 typedef union
430 {
431  struct
432  {
433  uint32_t nPRIV:1;
434  uint32_t SPSEL:1;
435  uint32_t FPCA:1;
436  uint32_t SFPA:1;
437  uint32_t _reserved1:28;
438  } b;
439  uint32_t w;
440 } CONTROL_Type;
441 
442 /* CONTROL Register Definitions */
443 #define CONTROL_SFPA_Pos 3U
444 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
446 #define CONTROL_FPCA_Pos 2U
447 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
449 #define CONTROL_SPSEL_Pos 1U
450 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
452 #define CONTROL_nPRIV_Pos 0U
453 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
455 
468 typedef struct
469 {
470  __IOM uint32_t ISER[16U];
471  uint32_t RESERVED0[16U];
472  __IOM uint32_t ICER[16U];
473  uint32_t RSERVED1[16U];
474  __IOM uint32_t ISPR[16U];
475  uint32_t RESERVED2[16U];
476  __IOM uint32_t ICPR[16U];
477  uint32_t RESERVED3[16U];
478  __IOM uint32_t IABR[16U];
479  uint32_t RESERVED4[16U];
480  __IOM uint32_t ITNS[16U];
481  uint32_t RESERVED5[16U];
482  __IOM uint8_t IPR[496U];
483  uint32_t RESERVED6[580U];
484  __OM uint32_t STIR;
485 } NVIC_Type;
486 
487 /* Software Triggered Interrupt Register Definitions */
488 #define NVIC_STIR_INTID_Pos 0U
489 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
491 
504 typedef struct
505 {
506  __IM uint32_t CPUID;
507  __IOM uint32_t ICSR;
508  __IOM uint32_t VTOR;
509  __IOM uint32_t AIRCR;
510  __IOM uint32_t SCR;
511  __IOM uint32_t CCR;
512  __IOM uint8_t SHPR[12U];
513  __IOM uint32_t SHCSR;
514  __IOM uint32_t CFSR;
515  __IOM uint32_t HFSR;
516  __IOM uint32_t DFSR;
517  __IOM uint32_t MMFAR;
518  __IOM uint32_t BFAR;
519  __IOM uint32_t AFSR;
520  __IM uint32_t ID_PFR[2U];
521  __IM uint32_t ID_DFR;
522  __IM uint32_t ID_ADR;
523  __IM uint32_t ID_MMFR[4U];
524  __IM uint32_t ID_ISAR[6U];
525  __IM uint32_t CLIDR;
526  __IM uint32_t CTR;
527  __IM uint32_t CCSIDR;
528  __IOM uint32_t CSSELR;
529  __IOM uint32_t CPACR;
530  __IOM uint32_t NSACR;
531  uint32_t RESERVED3[92U];
532  __OM uint32_t STIR;
533  uint32_t RESERVED4[15U];
534  __IM uint32_t MVFR0;
535  __IM uint32_t MVFR1;
536  __IM uint32_t MVFR2;
537  uint32_t RESERVED5[1U];
538  __OM uint32_t ICIALLU;
539  uint32_t RESERVED6[1U];
540  __OM uint32_t ICIMVAU;
541  __OM uint32_t DCIMVAC;
542  __OM uint32_t DCISW;
543  __OM uint32_t DCCMVAU;
544  __OM uint32_t DCCMVAC;
545  __OM uint32_t DCCSW;
546  __OM uint32_t DCCIMVAC;
547  __OM uint32_t DCCISW;
548 } SCB_Type;
549 
550 /* SCB CPUID Register Definitions */
551 #define SCB_CPUID_IMPLEMENTER_Pos 24U
552 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
554 #define SCB_CPUID_VARIANT_Pos 20U
555 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
557 #define SCB_CPUID_ARCHITECTURE_Pos 16U
558 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
560 #define SCB_CPUID_PARTNO_Pos 4U
561 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
563 #define SCB_CPUID_REVISION_Pos 0U
564 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
566 /* SCB Interrupt Control State Register Definitions */
567 #define SCB_ICSR_PENDNMISET_Pos 31U
568 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
570 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
571 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
573 #define SCB_ICSR_PENDNMICLR_Pos 30U
574 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
576 #define SCB_ICSR_PENDSVSET_Pos 28U
577 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
579 #define SCB_ICSR_PENDSVCLR_Pos 27U
580 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
582 #define SCB_ICSR_PENDSTSET_Pos 26U
583 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
585 #define SCB_ICSR_PENDSTCLR_Pos 25U
586 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
588 #define SCB_ICSR_STTNS_Pos 24U
589 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
591 #define SCB_ICSR_ISRPREEMPT_Pos 23U
592 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
594 #define SCB_ICSR_ISRPENDING_Pos 22U
595 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
597 #define SCB_ICSR_VECTPENDING_Pos 12U
598 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
600 #define SCB_ICSR_RETTOBASE_Pos 11U
601 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
603 #define SCB_ICSR_VECTACTIVE_Pos 0U
604 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
606 /* SCB Vector Table Offset Register Definitions */
607 #define SCB_VTOR_TBLOFF_Pos 7U
608 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
610 /* SCB Application Interrupt and Reset Control Register Definitions */
611 #define SCB_AIRCR_VECTKEY_Pos 16U
612 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
614 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
615 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
617 #define SCB_AIRCR_ENDIANESS_Pos 15U
618 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
620 #define SCB_AIRCR_PRIS_Pos 14U
621 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
623 #define SCB_AIRCR_BFHFNMINS_Pos 13U
624 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
626 #define SCB_AIRCR_PRIGROUP_Pos 8U
627 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
629 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
630 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
632 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
633 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
635 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
636 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
638 /* SCB System Control Register Definitions */
639 #define SCB_SCR_SEVONPEND_Pos 4U
640 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
642 #define SCB_SCR_SLEEPDEEPS_Pos 3U
643 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
645 #define SCB_SCR_SLEEPDEEP_Pos 2U
646 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
648 #define SCB_SCR_SLEEPONEXIT_Pos 1U
649 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
651 /* SCB Configuration Control Register Definitions */
652 #define SCB_CCR_BP_Pos 18U
653 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
655 #define SCB_CCR_IC_Pos 17U
656 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
658 #define SCB_CCR_DC_Pos 16U
659 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
661 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
662 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
664 #define SCB_CCR_BFHFNMIGN_Pos 8U
665 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
667 #define SCB_CCR_DIV_0_TRP_Pos 4U
668 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
670 #define SCB_CCR_UNALIGN_TRP_Pos 3U
671 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
673 #define SCB_CCR_USERSETMPEND_Pos 1U
674 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
676 /* SCB System Handler Control and State Register Definitions */
677 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
678 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
680 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
681 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
683 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
684 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
686 #define SCB_SHCSR_USGFAULTENA_Pos 18U
687 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
689 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
690 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
692 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
693 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
695 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
696 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
698 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
699 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
701 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
702 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
704 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
705 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
707 #define SCB_SHCSR_SYSTICKACT_Pos 11U
708 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
710 #define SCB_SHCSR_PENDSVACT_Pos 10U
711 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
713 #define SCB_SHCSR_MONITORACT_Pos 8U
714 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
716 #define SCB_SHCSR_SVCALLACT_Pos 7U
717 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
719 #define SCB_SHCSR_NMIACT_Pos 5U
720 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
722 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
723 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
725 #define SCB_SHCSR_USGFAULTACT_Pos 3U
726 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
728 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
729 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
731 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
732 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
734 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
735 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
737 /* SCB Configurable Fault Status Register Definitions */
738 #define SCB_CFSR_USGFAULTSR_Pos 16U
739 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
741 #define SCB_CFSR_BUSFAULTSR_Pos 8U
742 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
744 #define SCB_CFSR_MEMFAULTSR_Pos 0U
745 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
747 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
748 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
749 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
751 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
752 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
754 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
755 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
757 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
758 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
760 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
761 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
763 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
764 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
766 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
767 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
768 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
770 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
771 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
773 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
774 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
776 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
777 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
779 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
780 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
782 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
783 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
785 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
786 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
788 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
789 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
790 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
792 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
793 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
795 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
796 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
798 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
799 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
801 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
802 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
804 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
805 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
807 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
808 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
810 /* SCB Hard Fault Status Register Definitions */
811 #define SCB_HFSR_DEBUGEVT_Pos 31U
812 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
814 #define SCB_HFSR_FORCED_Pos 30U
815 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
817 #define SCB_HFSR_VECTTBL_Pos 1U
818 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
820 /* SCB Debug Fault Status Register Definitions */
821 #define SCB_DFSR_EXTERNAL_Pos 4U
822 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
824 #define SCB_DFSR_VCATCH_Pos 3U
825 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
827 #define SCB_DFSR_DWTTRAP_Pos 2U
828 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
830 #define SCB_DFSR_BKPT_Pos 1U
831 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
833 #define SCB_DFSR_HALTED_Pos 0U
834 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
836 /* SCB Non-Secure Access Control Register Definitions */
837 #define SCB_NSACR_CP11_Pos 11U
838 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
840 #define SCB_NSACR_CP10_Pos 10U
841 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
843 #define SCB_NSACR_CPn_Pos 0U
844 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
846 /* SCB Cache Level ID Register Definitions */
847 #define SCB_CLIDR_LOUU_Pos 27U
848 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
850 #define SCB_CLIDR_LOC_Pos 24U
851 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
853 /* SCB Cache Type Register Definitions */
854 #define SCB_CTR_FORMAT_Pos 29U
855 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
857 #define SCB_CTR_CWG_Pos 24U
858 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
860 #define SCB_CTR_ERG_Pos 20U
861 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
863 #define SCB_CTR_DMINLINE_Pos 16U
864 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
866 #define SCB_CTR_IMINLINE_Pos 0U
867 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
869 /* SCB Cache Size ID Register Definitions */
870 #define SCB_CCSIDR_WT_Pos 31U
871 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
873 #define SCB_CCSIDR_WB_Pos 30U
874 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
876 #define SCB_CCSIDR_RA_Pos 29U
877 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
879 #define SCB_CCSIDR_WA_Pos 28U
880 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
882 #define SCB_CCSIDR_NUMSETS_Pos 13U
883 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
885 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
886 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
888 #define SCB_CCSIDR_LINESIZE_Pos 0U
889 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
891 /* SCB Cache Size Selection Register Definitions */
892 #define SCB_CSSELR_LEVEL_Pos 1U
893 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
895 #define SCB_CSSELR_IND_Pos 0U
896 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
898 /* SCB Software Triggered Interrupt Register Definitions */
899 #define SCB_STIR_INTID_Pos 0U
900 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
902 /* SCB D-Cache Invalidate by Set-way Register Definitions */
903 #define SCB_DCISW_WAY_Pos 30U
904 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
906 #define SCB_DCISW_SET_Pos 5U
907 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
909 /* SCB D-Cache Clean by Set-way Register Definitions */
910 #define SCB_DCCSW_WAY_Pos 30U
911 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
913 #define SCB_DCCSW_SET_Pos 5U
914 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
916 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
917 #define SCB_DCCISW_WAY_Pos 30U
918 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
920 #define SCB_DCCISW_SET_Pos 5U
921 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
923 
936 typedef struct
937 {
938  uint32_t RESERVED0[1U];
939  __IM uint32_t ICTR;
940  __IOM uint32_t ACTLR;
941  __IOM uint32_t CPPWR;
942 } SCnSCB_Type;
943 
944 /* Interrupt Controller Type Register Definitions */
945 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
946 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
948 
961 typedef struct
962 {
963  __IOM uint32_t CTRL;
964  __IOM uint32_t LOAD;
965  __IOM uint32_t VAL;
966  __IM uint32_t CALIB;
967 } SysTick_Type;
968 
969 /* SysTick Control / Status Register Definitions */
970 #define SysTick_CTRL_COUNTFLAG_Pos 16U
971 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
973 #define SysTick_CTRL_CLKSOURCE_Pos 2U
974 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
976 #define SysTick_CTRL_TICKINT_Pos 1U
977 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
979 #define SysTick_CTRL_ENABLE_Pos 0U
980 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
982 /* SysTick Reload Register Definitions */
983 #define SysTick_LOAD_RELOAD_Pos 0U
984 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
986 /* SysTick Current Register Definitions */
987 #define SysTick_VAL_CURRENT_Pos 0U
988 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
990 /* SysTick Calibration Register Definitions */
991 #define SysTick_CALIB_NOREF_Pos 31U
992 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
994 #define SysTick_CALIB_SKEW_Pos 30U
995 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
997 #define SysTick_CALIB_TENMS_Pos 0U
998 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1000 
1013 typedef struct
1014 {
1015  __OM union
1016  {
1017  __OM uint8_t u8;
1018  __OM uint16_t u16;
1019  __OM uint32_t u32;
1020  } PORT [32U];
1021  uint32_t RESERVED0[864U];
1022  __IOM uint32_t TER;
1023  uint32_t RESERVED1[15U];
1024  __IOM uint32_t TPR;
1025  uint32_t RESERVED2[15U];
1026  __IOM uint32_t TCR;
1027  uint32_t RESERVED3[32U];
1028  uint32_t RESERVED4[43U];
1029  __OM uint32_t LAR;
1030  __IM uint32_t LSR;
1031  uint32_t RESERVED5[1U];
1032  __IM uint32_t DEVARCH;
1033  uint32_t RESERVED6[4U];
1034  __IM uint32_t PID4;
1035  __IM uint32_t PID5;
1036  __IM uint32_t PID6;
1037  __IM uint32_t PID7;
1038  __IM uint32_t PID0;
1039  __IM uint32_t PID1;
1040  __IM uint32_t PID2;
1041  __IM uint32_t PID3;
1042  __IM uint32_t CID0;
1043  __IM uint32_t CID1;
1044  __IM uint32_t CID2;
1045  __IM uint32_t CID3;
1046 } ITM_Type;
1047 
1048 /* ITM Stimulus Port Register Definitions */
1049 #define ITM_STIM_DISABLED_Pos 1U
1050 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1052 #define ITM_STIM_FIFOREADY_Pos 0U
1053 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1055 /* ITM Trace Privilege Register Definitions */
1056 #define ITM_TPR_PRIVMASK_Pos 0U
1057 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1059 /* ITM Trace Control Register Definitions */
1060 #define ITM_TCR_BUSY_Pos 23U
1061 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1063 #define ITM_TCR_TRACEBUSID_Pos 16U
1064 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1066 #define ITM_TCR_GTSFREQ_Pos 10U
1067 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1069 #define ITM_TCR_TSPRESCALE_Pos 8U
1070 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1072 #define ITM_TCR_STALLENA_Pos 5U
1073 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1075 #define ITM_TCR_SWOENA_Pos 4U
1076 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1078 #define ITM_TCR_DWTENA_Pos 3U
1079 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1081 #define ITM_TCR_SYNCENA_Pos 2U
1082 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1084 #define ITM_TCR_TSENA_Pos 1U
1085 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1087 #define ITM_TCR_ITMENA_Pos 0U
1088 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1090 /* ITM Lock Status Register Definitions */
1091 #define ITM_LSR_ByteAcc_Pos 2U
1092 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1094 #define ITM_LSR_Access_Pos 1U
1095 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1097 #define ITM_LSR_Present_Pos 0U
1098 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1100  /* end of group CMSIS_ITM */
1101 
1102 
1113 typedef struct
1114 {
1115  __IOM uint32_t CTRL;
1116  __IOM uint32_t CYCCNT;
1117  __IOM uint32_t CPICNT;
1118  __IOM uint32_t EXCCNT;
1119  __IOM uint32_t SLEEPCNT;
1120  __IOM uint32_t LSUCNT;
1121  __IOM uint32_t FOLDCNT;
1122  __IM uint32_t PCSR;
1123  __IOM uint32_t COMP0;
1124  uint32_t RESERVED1[1U];
1125  __IOM uint32_t FUNCTION0;
1126  uint32_t RESERVED2[1U];
1127  __IOM uint32_t COMP1;
1128  uint32_t RESERVED3[1U];
1129  __IOM uint32_t FUNCTION1;
1130  uint32_t RESERVED4[1U];
1131  __IOM uint32_t COMP2;
1132  uint32_t RESERVED5[1U];
1133  __IOM uint32_t FUNCTION2;
1134  uint32_t RESERVED6[1U];
1135  __IOM uint32_t COMP3;
1136  uint32_t RESERVED7[1U];
1137  __IOM uint32_t FUNCTION3;
1138  uint32_t RESERVED8[1U];
1139  __IOM uint32_t COMP4;
1140  uint32_t RESERVED9[1U];
1141  __IOM uint32_t FUNCTION4;
1142  uint32_t RESERVED10[1U];
1143  __IOM uint32_t COMP5;
1144  uint32_t RESERVED11[1U];
1145  __IOM uint32_t FUNCTION5;
1146  uint32_t RESERVED12[1U];
1147  __IOM uint32_t COMP6;
1148  uint32_t RESERVED13[1U];
1149  __IOM uint32_t FUNCTION6;
1150  uint32_t RESERVED14[1U];
1151  __IOM uint32_t COMP7;
1152  uint32_t RESERVED15[1U];
1153  __IOM uint32_t FUNCTION7;
1154  uint32_t RESERVED16[1U];
1155  __IOM uint32_t COMP8;
1156  uint32_t RESERVED17[1U];
1157  __IOM uint32_t FUNCTION8;
1158  uint32_t RESERVED18[1U];
1159  __IOM uint32_t COMP9;
1160  uint32_t RESERVED19[1U];
1161  __IOM uint32_t FUNCTION9;
1162  uint32_t RESERVED20[1U];
1163  __IOM uint32_t COMP10;
1164  uint32_t RESERVED21[1U];
1165  __IOM uint32_t FUNCTION10;
1166  uint32_t RESERVED22[1U];
1167  __IOM uint32_t COMP11;
1168  uint32_t RESERVED23[1U];
1169  __IOM uint32_t FUNCTION11;
1170  uint32_t RESERVED24[1U];
1171  __IOM uint32_t COMP12;
1172  uint32_t RESERVED25[1U];
1173  __IOM uint32_t FUNCTION12;
1174  uint32_t RESERVED26[1U];
1175  __IOM uint32_t COMP13;
1176  uint32_t RESERVED27[1U];
1177  __IOM uint32_t FUNCTION13;
1178  uint32_t RESERVED28[1U];
1179  __IOM uint32_t COMP14;
1180  uint32_t RESERVED29[1U];
1181  __IOM uint32_t FUNCTION14;
1182  uint32_t RESERVED30[1U];
1183  __IOM uint32_t COMP15;
1184  uint32_t RESERVED31[1U];
1185  __IOM uint32_t FUNCTION15;
1186  uint32_t RESERVED32[934U];
1187  __IM uint32_t LSR;
1188  uint32_t RESERVED33[1U];
1189  __IM uint32_t DEVARCH;
1190 } DWT_Type;
1191 
1192 /* DWT Control Register Definitions */
1193 #define DWT_CTRL_NUMCOMP_Pos 28U
1194 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1196 #define DWT_CTRL_NOTRCPKT_Pos 27U
1197 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1199 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1200 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1202 #define DWT_CTRL_NOCYCCNT_Pos 25U
1203 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1205 #define DWT_CTRL_NOPRFCNT_Pos 24U
1206 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1208 #define DWT_CTRL_CYCDISS_Pos 23U
1209 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1211 #define DWT_CTRL_CYCEVTENA_Pos 22U
1212 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1214 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1215 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1217 #define DWT_CTRL_LSUEVTENA_Pos 20U
1218 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1220 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1221 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1223 #define DWT_CTRL_EXCEVTENA_Pos 18U
1224 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1226 #define DWT_CTRL_CPIEVTENA_Pos 17U
1227 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1229 #define DWT_CTRL_EXCTRCENA_Pos 16U
1230 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1232 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1233 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1235 #define DWT_CTRL_SYNCTAP_Pos 10U
1236 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1238 #define DWT_CTRL_CYCTAP_Pos 9U
1239 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1241 #define DWT_CTRL_POSTINIT_Pos 5U
1242 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1244 #define DWT_CTRL_POSTPRESET_Pos 1U
1245 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1247 #define DWT_CTRL_CYCCNTENA_Pos 0U
1248 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1250 /* DWT CPI Count Register Definitions */
1251 #define DWT_CPICNT_CPICNT_Pos 0U
1252 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1254 /* DWT Exception Overhead Count Register Definitions */
1255 #define DWT_EXCCNT_EXCCNT_Pos 0U
1256 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1258 /* DWT Sleep Count Register Definitions */
1259 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1260 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1262 /* DWT LSU Count Register Definitions */
1263 #define DWT_LSUCNT_LSUCNT_Pos 0U
1264 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1266 /* DWT Folded-instruction Count Register Definitions */
1267 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1268 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1270 /* DWT Comparator Function Register Definitions */
1271 #define DWT_FUNCTION_ID_Pos 27U
1272 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1274 #define DWT_FUNCTION_MATCHED_Pos 24U
1275 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1277 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1278 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1280 #define DWT_FUNCTION_ACTION_Pos 4U
1281 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1283 #define DWT_FUNCTION_MATCH_Pos 0U
1284 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1286  /* end of group CMSIS_DWT */
1287 
1288 
1299 typedef struct
1300 {
1301  __IM uint32_t SSPSR;
1302  __IOM uint32_t CSPSR;
1303  uint32_t RESERVED0[2U];
1304  __IOM uint32_t ACPR;
1305  uint32_t RESERVED1[55U];
1306  __IOM uint32_t SPPR;
1307  uint32_t RESERVED2[131U];
1308  __IM uint32_t FFSR;
1309  __IOM uint32_t FFCR;
1310  __IOM uint32_t PSCR;
1311  uint32_t RESERVED3[809U];
1312  __OM uint32_t LAR;
1313  __IM uint32_t LSR;
1314  uint32_t RESERVED4[4U];
1315  __IM uint32_t TYPE;
1316  __IM uint32_t DEVTYPE;
1317 } TPI_Type;
1318 
1319 /* TPI Asynchronous Clock Prescaler Register Definitions */
1320 #define TPI_ACPR_SWOSCALER_Pos 0U
1321 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
1323 /* TPI Selected Pin Protocol Register Definitions */
1324 #define TPI_SPPR_TXMODE_Pos 0U
1325 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1327 /* TPI Formatter and Flush Status Register Definitions */
1328 #define TPI_FFSR_FtNonStop_Pos 3U
1329 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1331 #define TPI_FFSR_TCPresent_Pos 2U
1332 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1334 #define TPI_FFSR_FtStopped_Pos 1U
1335 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1337 #define TPI_FFSR_FlInProg_Pos 0U
1338 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1340 /* TPI Formatter and Flush Control Register Definitions */
1341 #define TPI_FFCR_TrigIn_Pos 8U
1342 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1344 #define TPI_FFCR_FOnMan_Pos 6U
1345 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1347 #define TPI_FFCR_EnFCont_Pos 1U
1348 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1350 /* TPI Periodic Synchronization Control Register Definitions */
1351 #define TPI_PSCR_PSCount_Pos 0U
1352 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
1354 /* TPI Software Lock Status Register Definitions */
1355 #define TPI_LSR_nTT_Pos 1U
1356 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
1358 #define TPI_LSR_SLK_Pos 1U
1359 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
1361 #define TPI_LSR_SLI_Pos 0U
1362 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
1364 /* TPI DEVID Register Definitions */
1365 #define TPI_DEVID_NRZVALID_Pos 11U
1366 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1368 #define TPI_DEVID_MANCVALID_Pos 10U
1369 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1371 #define TPI_DEVID_PTINVALID_Pos 9U
1372 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1374 #define TPI_DEVID_FIFOSZ_Pos 6U
1375 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1377 /* TPI DEVTYPE Register Definitions */
1378 #define TPI_DEVTYPE_SubType_Pos 4U
1379 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1381 #define TPI_DEVTYPE_MajorType_Pos 0U
1382 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1384  /* end of group CMSIS_TPI */
1385 
1386 
1387 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1388 
1398 typedef struct
1399 {
1400  __IM uint32_t TYPE;
1401  __IOM uint32_t CTRL;
1402  __IOM uint32_t RNR;
1403  __IOM uint32_t RBAR;
1404  __IOM uint32_t RLAR;
1405  __IOM uint32_t RBAR_A1;
1406  __IOM uint32_t RLAR_A1;
1407  __IOM uint32_t RBAR_A2;
1408  __IOM uint32_t RLAR_A2;
1409  __IOM uint32_t RBAR_A3;
1410  __IOM uint32_t RLAR_A3;
1411  uint32_t RESERVED0[1];
1412  union {
1413  __IOM uint32_t MAIR[2];
1414  struct {
1415  __IOM uint32_t MAIR0;
1416  __IOM uint32_t MAIR1;
1417  };
1418  };
1419 } MPU_Type;
1420 
1421 #define MPU_TYPE_RALIASES 4U
1422 
1423 /* MPU Type Register Definitions */
1424 #define MPU_TYPE_IREGION_Pos 16U
1425 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1427 #define MPU_TYPE_DREGION_Pos 8U
1428 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1430 #define MPU_TYPE_SEPARATE_Pos 0U
1431 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1433 /* MPU Control Register Definitions */
1434 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1435 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1437 #define MPU_CTRL_HFNMIENA_Pos 1U
1438 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1440 #define MPU_CTRL_ENABLE_Pos 0U
1441 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1443 /* MPU Region Number Register Definitions */
1444 #define MPU_RNR_REGION_Pos 0U
1445 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1447 /* MPU Region Base Address Register Definitions */
1448 #define MPU_RBAR_BASE_Pos 5U
1449 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1451 #define MPU_RBAR_SH_Pos 3U
1452 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1454 #define MPU_RBAR_AP_Pos 1U
1455 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1457 #define MPU_RBAR_XN_Pos 0U
1458 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1460 /* MPU Region Limit Address Register Definitions */
1461 #define MPU_RLAR_LIMIT_Pos 5U
1462 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1464 #define MPU_RLAR_AttrIndx_Pos 1U
1465 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1467 #define MPU_RLAR_EN_Pos 0U
1468 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1470 /* MPU Memory Attribute Indirection Register 0 Definitions */
1471 #define MPU_MAIR0_Attr3_Pos 24U
1472 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1474 #define MPU_MAIR0_Attr2_Pos 16U
1475 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1477 #define MPU_MAIR0_Attr1_Pos 8U
1478 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1480 #define MPU_MAIR0_Attr0_Pos 0U
1481 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1483 /* MPU Memory Attribute Indirection Register 1 Definitions */
1484 #define MPU_MAIR1_Attr7_Pos 24U
1485 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1487 #define MPU_MAIR1_Attr6_Pos 16U
1488 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1490 #define MPU_MAIR1_Attr5_Pos 8U
1491 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1493 #define MPU_MAIR1_Attr4_Pos 0U
1494 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1496 
1497 #endif
1498 
1499 
1500 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1501 
1511 typedef struct
1512 {
1513  __IOM uint32_t CTRL;
1514  __IM uint32_t TYPE;
1515 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1516  __IOM uint32_t RNR;
1517  __IOM uint32_t RBAR;
1518  __IOM uint32_t RLAR;
1519 #else
1520  uint32_t RESERVED0[3];
1521 #endif
1522  __IOM uint32_t SFSR;
1523  __IOM uint32_t SFAR;
1524 } SAU_Type;
1525 
1526 /* SAU Control Register Definitions */
1527 #define SAU_CTRL_ALLNS_Pos 1U
1528 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1530 #define SAU_CTRL_ENABLE_Pos 0U
1531 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1533 /* SAU Type Register Definitions */
1534 #define SAU_TYPE_SREGION_Pos 0U
1535 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1537 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1538 /* SAU Region Number Register Definitions */
1539 #define SAU_RNR_REGION_Pos 0U
1540 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1542 /* SAU Region Base Address Register Definitions */
1543 #define SAU_RBAR_BADDR_Pos 5U
1544 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1546 /* SAU Region Limit Address Register Definitions */
1547 #define SAU_RLAR_LADDR_Pos 5U
1548 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1550 #define SAU_RLAR_NSC_Pos 1U
1551 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1553 #define SAU_RLAR_ENABLE_Pos 0U
1554 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1556 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1557 
1558 /* Secure Fault Status Register Definitions */
1559 #define SAU_SFSR_LSERR_Pos 7U
1560 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1562 #define SAU_SFSR_SFARVALID_Pos 6U
1563 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1565 #define SAU_SFSR_LSPERR_Pos 5U
1566 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1568 #define SAU_SFSR_INVTRAN_Pos 4U
1569 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1571 #define SAU_SFSR_AUVIOL_Pos 3U
1572 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1574 #define SAU_SFSR_INVER_Pos 2U
1575 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1577 #define SAU_SFSR_INVIS_Pos 1U
1578 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1580 #define SAU_SFSR_INVEP_Pos 0U
1581 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1583 
1584 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1585 
1586 
1597 typedef struct
1598 {
1599  uint32_t RESERVED0[1U];
1600  __IOM uint32_t FPCCR;
1601  __IOM uint32_t FPCAR;
1602  __IOM uint32_t FPDSCR;
1603  __IM uint32_t MVFR0;
1604  __IM uint32_t MVFR1;
1605  __IM uint32_t MVFR2;
1606 } FPU_Type;
1607 
1608 /* Floating-Point Context Control Register Definitions */
1609 #define FPU_FPCCR_ASPEN_Pos 31U
1610 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1612 #define FPU_FPCCR_LSPEN_Pos 30U
1613 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1615 #define FPU_FPCCR_LSPENS_Pos 29U
1616 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1618 #define FPU_FPCCR_CLRONRET_Pos 28U
1619 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1621 #define FPU_FPCCR_CLRONRETS_Pos 27U
1622 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1624 #define FPU_FPCCR_TS_Pos 26U
1625 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1627 #define FPU_FPCCR_UFRDY_Pos 10U
1628 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1630 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
1631 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1633 #define FPU_FPCCR_MONRDY_Pos 8U
1634 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1636 #define FPU_FPCCR_SFRDY_Pos 7U
1637 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1639 #define FPU_FPCCR_BFRDY_Pos 6U
1640 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1642 #define FPU_FPCCR_MMRDY_Pos 5U
1643 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1645 #define FPU_FPCCR_HFRDY_Pos 4U
1646 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1648 #define FPU_FPCCR_THREAD_Pos 3U
1649 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1651 #define FPU_FPCCR_S_Pos 2U
1652 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1654 #define FPU_FPCCR_USER_Pos 1U
1655 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1657 #define FPU_FPCCR_LSPACT_Pos 0U
1658 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1660 /* Floating-Point Context Address Register Definitions */
1661 #define FPU_FPCAR_ADDRESS_Pos 3U
1662 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1664 /* Floating-Point Default Status Control Register Definitions */
1665 #define FPU_FPDSCR_AHP_Pos 26U
1666 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1668 #define FPU_FPDSCR_DN_Pos 25U
1669 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1671 #define FPU_FPDSCR_FZ_Pos 24U
1672 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1674 #define FPU_FPDSCR_RMode_Pos 22U
1675 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1677 /* Media and VFP Feature Register 0 Definitions */
1678 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1679 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1681 #define FPU_MVFR0_Short_vectors_Pos 24U
1682 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1684 #define FPU_MVFR0_Square_root_Pos 20U
1685 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1687 #define FPU_MVFR0_Divide_Pos 16U
1688 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1690 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1691 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1693 #define FPU_MVFR0_Double_precision_Pos 8U
1694 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1696 #define FPU_MVFR0_Single_precision_Pos 4U
1697 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1699 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1700 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1702 /* Media and VFP Feature Register 1 Definitions */
1703 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1704 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1706 #define FPU_MVFR1_FP_HPFP_Pos 24U
1707 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1709 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1710 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1712 #define FPU_MVFR1_FtZ_mode_Pos 0U
1713 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1715 /* Media and VFP Feature Register 2 Definitions */
1716 #define FPU_MVFR2_FPMisc_Pos 4U
1717 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
1719 
1721 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1722 
1732 typedef struct
1733 {
1734  __IOM uint32_t DHCSR;
1735  __OM uint32_t DCRSR;
1736  __IOM uint32_t DCRDR;
1737  __IOM uint32_t DEMCR;
1738  uint32_t RESERVED0[1U];
1739  __IOM uint32_t DAUTHCTRL;
1740  __IOM uint32_t DSCSR;
1741 } CoreDebug_Type;
1742 
1743 /* Debug Halting Control and Status Register Definitions */
1744 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1745 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1747 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1748 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1750 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1751 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1753 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1754 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1756 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1757 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1759 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1760 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1762 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1763 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1765 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1766 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1768 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1769 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1771 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1772 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1774 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1775 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1777 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1778 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1780 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1781 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1783 /* Debug Core Register Selector Register Definitions */
1784 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1785 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1787 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1788 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1790 /* Debug Exception and Monitor Control Register Definitions */
1791 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1792 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1794 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1795 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1797 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1798 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1800 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1801 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1803 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1804 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1806 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1807 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1809 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1810 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1812 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1813 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1815 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1816 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1818 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1819 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1821 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1822 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1824 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1825 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1827 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1828 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1830 /* Debug Authentication Control Register Definitions */
1831 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1832 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1834 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1835 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1837 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1838 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1840 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1841 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1843 /* Debug Security Control and Status Register Definitions */
1844 #define CoreDebug_DSCSR_CDS_Pos 16U
1845 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1847 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1848 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1850 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1851 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1853 
1866 typedef struct
1867 {
1868  __IOM uint32_t DHCSR;
1869  __OM uint32_t DCRSR;
1870  __IOM uint32_t DCRDR;
1871  __IOM uint32_t DEMCR;
1872  uint32_t RESERVED0[1U];
1873  __IOM uint32_t DAUTHCTRL;
1874  __IOM uint32_t DSCSR;
1875 } DCB_Type;
1876 
1877 /* DHCSR, Debug Halting Control and Status Register Definitions */
1878 #define DCB_DHCSR_DBGKEY_Pos 16U
1879 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1881 #define DCB_DHCSR_S_RESTART_ST_Pos 26U
1882 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1884 #define DCB_DHCSR_S_RESET_ST_Pos 25U
1885 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1887 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1888 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1890 #define DCB_DHCSR_S_SDE_Pos 20U
1891 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1893 #define DCB_DHCSR_S_LOCKUP_Pos 19U
1894 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
1896 #define DCB_DHCSR_S_SLEEP_Pos 18U
1897 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
1899 #define DCB_DHCSR_S_HALT_Pos 17U
1900 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
1902 #define DCB_DHCSR_S_REGRDY_Pos 16U
1903 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
1905 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U
1906 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
1908 #define DCB_DHCSR_C_MASKINTS_Pos 3U
1909 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
1911 #define DCB_DHCSR_C_STEP_Pos 2U
1912 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
1914 #define DCB_DHCSR_C_HALT_Pos 1U
1915 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
1917 #define DCB_DHCSR_C_DEBUGEN_Pos 0U
1918 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
1920 /* DCRSR, Debug Core Register Select Register Definitions */
1921 #define DCB_DCRSR_REGWnR_Pos 16U
1922 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
1924 #define DCB_DCRSR_REGSEL_Pos 0U
1925 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
1927 /* DCRDR, Debug Core Register Data Register Definitions */
1928 #define DCB_DCRDR_DBGTMP_Pos 0U
1929 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
1931 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1932 #define DCB_DEMCR_TRCENA_Pos 24U
1933 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
1935 #define DCB_DEMCR_MONPRKEY_Pos 23U
1936 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
1938 #define DCB_DEMCR_UMON_EN_Pos 21U
1939 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
1941 #define DCB_DEMCR_SDME_Pos 20U
1942 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
1944 #define DCB_DEMCR_MON_REQ_Pos 19U
1945 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
1947 #define DCB_DEMCR_MON_STEP_Pos 18U
1948 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
1950 #define DCB_DEMCR_MON_PEND_Pos 17U
1951 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
1953 #define DCB_DEMCR_MON_EN_Pos 16U
1954 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
1956 #define DCB_DEMCR_VC_SFERR_Pos 11U
1957 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
1959 #define DCB_DEMCR_VC_HARDERR_Pos 10U
1960 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
1962 #define DCB_DEMCR_VC_INTERR_Pos 9U
1963 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
1965 #define DCB_DEMCR_VC_BUSERR_Pos 8U
1966 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
1968 #define DCB_DEMCR_VC_STATERR_Pos 7U
1969 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
1971 #define DCB_DEMCR_VC_CHKERR_Pos 6U
1972 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
1974 #define DCB_DEMCR_VC_NOCPERR_Pos 5U
1975 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
1977 #define DCB_DEMCR_VC_MMERR_Pos 4U
1978 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
1980 #define DCB_DEMCR_VC_CORERESET_Pos 0U
1981 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
1983 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
1984 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
1985 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
1987 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
1988 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
1990 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
1991 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
1993 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
1994 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
1996 /* DSCSR, Debug Security Control and Status Register Definitions */
1997 #define DCB_DSCSR_CDSKEY_Pos 17U
1998 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2000 #define DCB_DSCSR_CDS_Pos 16U
2001 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2003 #define DCB_DSCSR_SBRSEL_Pos 1U
2004 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2006 #define DCB_DSCSR_SBRSELEN_Pos 0U
2007 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2009 
2023 typedef struct
2024 {
2025  __OM uint32_t DLAR;
2026  __IM uint32_t DLSR;
2027  __IM uint32_t DAUTHSTATUS;
2028  __IM uint32_t DDEVARCH;
2029  __IM uint32_t DDEVTYPE;
2030 } DIB_Type;
2031 
2032 /* DLAR, SCS Software Lock Access Register Definitions */
2033 #define DIB_DLAR_KEY_Pos 0U
2034 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
2036 /* DLSR, SCS Software Lock Status Register Definitions */
2037 #define DIB_DLSR_nTT_Pos 2U
2038 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
2040 #define DIB_DLSR_SLK_Pos 1U
2041 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
2043 #define DIB_DLSR_SLI_Pos 0U
2044 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
2046 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2047 #define DIB_DAUTHSTATUS_SNID_Pos 6U
2048 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
2050 #define DIB_DAUTHSTATUS_SID_Pos 4U
2051 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
2053 #define DIB_DAUTHSTATUS_NSNID_Pos 2U
2054 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
2056 #define DIB_DAUTHSTATUS_NSID_Pos 0U
2057 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
2059 /* DDEVARCH, SCS Device Architecture Register Definitions */
2060 #define DIB_DDEVARCH_ARCHITECT_Pos 21U
2061 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
2063 #define DIB_DDEVARCH_PRESENT_Pos 20U
2064 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
2066 #define DIB_DDEVARCH_REVISION_Pos 16U
2067 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
2069 #define DIB_DDEVARCH_ARCHVER_Pos 12U
2070 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
2072 #define DIB_DDEVARCH_ARCHPART_Pos 0U
2073 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
2075 /* DDEVTYPE, SCS Device Type Register Definitions */
2076 #define DIB_DDEVTYPE_SUB_Pos 4U
2077 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
2079 #define DIB_DDEVTYPE_MAJOR_Pos 0U
2080 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
2083 
2099 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2100 
2107 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2108 
2119 /* Memory mapping of Core Hardware */
2120  #define SCS_BASE (0xE000E000UL)
2121  #define ITM_BASE (0xE0000000UL)
2122  #define DWT_BASE (0xE0001000UL)
2123  #define TPI_BASE (0xE0040000UL)
2124  #define CoreDebug_BASE (0xE000EDF0UL)
2125  #define DCB_BASE (0xE000EDF0UL)
2126  #define DIB_BASE (0xE000EFB0UL)
2127  #define SysTick_BASE (SCS_BASE + 0x0010UL)
2128  #define NVIC_BASE (SCS_BASE + 0x0100UL)
2129  #define SCB_BASE (SCS_BASE + 0x0D00UL)
2131  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2132  #define SCB ((SCB_Type *) SCB_BASE )
2133  #define SysTick ((SysTick_Type *) SysTick_BASE )
2134  #define NVIC ((NVIC_Type *) NVIC_BASE )
2135  #define ITM ((ITM_Type *) ITM_BASE )
2136  #define DWT ((DWT_Type *) DWT_BASE )
2137  #define TPI ((TPI_Type *) TPI_BASE )
2138  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
2139  #define DCB ((DCB_Type *) DCB_BASE )
2140  #define DIB ((DIB_Type *) DIB_BASE )
2142  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2143  #define MPU_BASE (SCS_BASE + 0x0D90UL)
2144  #define MPU ((MPU_Type *) MPU_BASE )
2145  #endif
2146 
2147  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2148  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
2149  #define SAU ((SAU_Type *) SAU_BASE )
2150  #endif
2151 
2152  #define FPU_BASE (SCS_BASE + 0x0F30UL)
2153  #define FPU ((FPU_Type *) FPU_BASE )
2155 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2156  #define SCS_BASE_NS (0xE002E000UL)
2157  #define CoreDebug_BASE_NS (0xE002EDF0UL)
2158  #define DCB_BASE_NS (0xE002EDF0UL)
2159  #define DIB_BASE_NS (0xE002EFB0UL)
2160  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2161  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2162  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2164  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2165  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2166  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2167  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2168  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2169  #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
2170  #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
2172  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2173  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2174  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2175  #endif
2176 
2177  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2178  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2180 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2181 
2185 /*******************************************************************************
2186  * Hardware Abstraction Layer
2187  Core Function Interface contains:
2188  - Core NVIC Functions
2189  - Core SysTick Functions
2190  - Core Debug Functions
2191  - Core Register Access Functions
2192  ******************************************************************************/
2199 /* ########################## NVIC functions #################################### */
2207 #ifdef CMSIS_NVIC_VIRTUAL
2208  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2209  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2210  #endif
2211  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2212 #else
2213  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2214  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2215  #define NVIC_EnableIRQ __NVIC_EnableIRQ
2216  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2217  #define NVIC_DisableIRQ __NVIC_DisableIRQ
2218  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2219  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2220  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2221  #define NVIC_GetActive __NVIC_GetActive
2222  #define NVIC_SetPriority __NVIC_SetPriority
2223  #define NVIC_GetPriority __NVIC_GetPriority
2224  #define NVIC_SystemReset __NVIC_SystemReset
2225 #endif /* CMSIS_NVIC_VIRTUAL */
2226 
2227 #ifdef CMSIS_VECTAB_VIRTUAL
2228  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2229  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2230  #endif
2231  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2232 #else
2233  #define NVIC_SetVector __NVIC_SetVector
2234  #define NVIC_GetVector __NVIC_GetVector
2235 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2236 
2237 #define NVIC_USER_IRQ_OFFSET 16
2238 
2239 
2240 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2241 
2242 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2243 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2244 
2245 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2246 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2247 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2248 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2249 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2250 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2251 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2252 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2253 
2254 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2255 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2256 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2257 #else
2258 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2259 #endif
2260 
2261 
2271 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2272 {
2273  uint32_t reg_value;
2274  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2275 
2276  reg_value = SCB->AIRCR; /* read old register configuration */
2277  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2278  reg_value = (reg_value |
2279  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2280  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2281  SCB->AIRCR = reg_value;
2282 }
2283 
2284 
2290 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2291 {
2292  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2293 }
2294 
2295 
2302 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2303 {
2304  if ((int32_t)(IRQn) >= 0)
2305  {
2306  __COMPILER_BARRIER();
2307  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2308  __COMPILER_BARRIER();
2309  }
2310 }
2311 
2312 
2321 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2322 {
2323  if ((int32_t)(IRQn) >= 0)
2324  {
2325  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2326  }
2327  else
2328  {
2329  return(0U);
2330  }
2331 }
2332 
2333 
2340 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2341 {
2342  if ((int32_t)(IRQn) >= 0)
2343  {
2344  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2345  __DSB();
2346  __ISB();
2347  }
2348 }
2349 
2350 
2359 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2360 {
2361  if ((int32_t)(IRQn) >= 0)
2362  {
2363  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2364  }
2365  else
2366  {
2367  return(0U);
2368  }
2369 }
2370 
2371 
2378 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2379 {
2380  if ((int32_t)(IRQn) >= 0)
2381  {
2382  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2383  }
2384 }
2385 
2386 
2393 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2394 {
2395  if ((int32_t)(IRQn) >= 0)
2396  {
2397  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2398  }
2399 }
2400 
2401 
2410 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2411 {
2412  if ((int32_t)(IRQn) >= 0)
2413  {
2414  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2415  }
2416  else
2417  {
2418  return(0U);
2419  }
2420 }
2421 
2422 
2423 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2424 
2432 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2433 {
2434  if ((int32_t)(IRQn) >= 0)
2435  {
2436  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2437  }
2438  else
2439  {
2440  return(0U);
2441  }
2442 }
2443 
2444 
2453 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2454 {
2455  if ((int32_t)(IRQn) >= 0)
2456  {
2457  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2458  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2459  }
2460  else
2461  {
2462  return(0U);
2463  }
2464 }
2465 
2466 
2475 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2476 {
2477  if ((int32_t)(IRQn) >= 0)
2478  {
2479  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2480  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2481  }
2482  else
2483  {
2484  return(0U);
2485  }
2486 }
2487 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2488 
2489 
2499 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2500 {
2501  if ((int32_t)(IRQn) >= 0)
2502  {
2503  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2504  }
2505  else
2506  {
2507  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2508  }
2509 }
2510 
2511 
2521 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2522 {
2523 
2524  if ((int32_t)(IRQn) >= 0)
2525  {
2526  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2527  }
2528  else
2529  {
2530  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2531  }
2532 }
2533 
2534 
2546 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2547 {
2548  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2549  uint32_t PreemptPriorityBits;
2550  uint32_t SubPriorityBits;
2551 
2552  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2553  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2554 
2555  return (
2556  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2557  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2558  );
2559 }
2560 
2561 
2573 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2574 {
2575  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2576  uint32_t PreemptPriorityBits;
2577  uint32_t SubPriorityBits;
2578 
2579  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2580  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2581 
2582  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2583  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2584 }
2585 
2586 
2596 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2597 {
2598  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2599  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2600  __DSB();
2601 }
2602 
2603 
2612 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2613 {
2614  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2615  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2616 }
2617 
2618 
2623 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2624 {
2625  __DSB(); /* Ensure all outstanding memory accesses included
2626  buffered write are completed before reset */
2627  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2628  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2629  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2630  __DSB(); /* Ensure completion of memory access */
2631 
2632  for(;;) /* wait until reset */
2633  {
2634  __NOP();
2635  }
2636 }
2637 
2638 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2639 
2648 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2649 {
2650  uint32_t reg_value;
2651  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2652 
2653  reg_value = SCB_NS->AIRCR; /* read old register configuration */
2654  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2655  reg_value = (reg_value |
2656  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2657  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2658  SCB_NS->AIRCR = reg_value;
2659 }
2660 
2661 
2667 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2668 {
2669  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2670 }
2671 
2672 
2679 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2680 {
2681  if ((int32_t)(IRQn) >= 0)
2682  {
2683  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2684  }
2685 }
2686 
2687 
2696 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2697 {
2698  if ((int32_t)(IRQn) >= 0)
2699  {
2700  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2701  }
2702  else
2703  {
2704  return(0U);
2705  }
2706 }
2707 
2708 
2715 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2716 {
2717  if ((int32_t)(IRQn) >= 0)
2718  {
2719  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2720  }
2721 }
2722 
2723 
2732 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2733 {
2734  if ((int32_t)(IRQn) >= 0)
2735  {
2736  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2737  }
2738  else
2739  {
2740  return(0U);
2741  }
2742 }
2743 
2744 
2751 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2752 {
2753  if ((int32_t)(IRQn) >= 0)
2754  {
2755  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2756  }
2757 }
2758 
2759 
2766 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2767 {
2768  if ((int32_t)(IRQn) >= 0)
2769  {
2770  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2771  }
2772 }
2773 
2774 
2783 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2784 {
2785  if ((int32_t)(IRQn) >= 0)
2786  {
2787  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2788  }
2789  else
2790  {
2791  return(0U);
2792  }
2793 }
2794 
2795 
2805 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2806 {
2807  if ((int32_t)(IRQn) >= 0)
2808  {
2809  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2810  }
2811  else
2812  {
2813  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2814  }
2815 }
2816 
2817 
2826 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2827 {
2828 
2829  if ((int32_t)(IRQn) >= 0)
2830  {
2831  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2832  }
2833  else
2834  {
2835  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2836  }
2837 }
2838 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2839 
2842 /* ########################## MPU functions #################################### */
2843 
2844 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2845 
2846 #include "mpu_armv8.h"
2847 
2848 #endif
2849 
2850 /* ########################## FPU functions #################################### */
2866 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2867 {
2868  uint32_t mvfr0;
2869 
2870  mvfr0 = FPU->MVFR0;
2871  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2872  {
2873  return 2U; /* Double + Single precision FPU */
2874  }
2875  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2876  {
2877  return 1U; /* Single precision FPU */
2878  }
2879  else
2880  {
2881  return 0U; /* No FPU */
2882  }
2883 }
2884 
2885 
2889 /* ########################## Cache functions #################################### */
2890 
2891 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2892  (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2893 #include "cachel1_armv7.h"
2894 #endif
2895 
2896 
2897 /* ########################## SAU functions #################################### */
2905 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2906 
2911 __STATIC_INLINE void TZ_SAU_Enable(void)
2912 {
2913  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2914 }
2915 
2916 
2917 
2922 __STATIC_INLINE void TZ_SAU_Disable(void)
2923 {
2924  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2925 }
2926 
2927 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2928 
2934 /* ################################## Debug Control function ############################################ */
2948 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2949 {
2950  __DSB();
2951  __ISB();
2952  DCB->DAUTHCTRL = value;
2953  __DSB();
2954  __ISB();
2955 }
2956 
2957 
2963 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2964 {
2965  return (DCB->DAUTHCTRL);
2966 }
2967 
2968 
2969 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2970 
2975 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2976 {
2977  __DSB();
2978  __ISB();
2979  DCB_NS->DAUTHCTRL = value;
2980  __DSB();
2981  __ISB();
2982 }
2983 
2984 
2990 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2991 {
2992  return (DCB_NS->DAUTHCTRL);
2993 }
2994 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2995 
3001 /* ################################## Debug Identification function ############################################ */
3015 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3016 {
3017  return (DIB->DAUTHSTATUS);
3018 }
3019 
3020 
3021 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3022 
3027 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3028 {
3029  return (DIB_NS->DAUTHSTATUS);
3030 }
3031 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3032 
3038 /* ################################## SysTick function ############################################ */
3046 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3047 
3059 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3060 {
3061  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3062  {
3063  return (1UL); /* Reload value impossible */
3064  }
3065 
3066  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3067  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3068  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3069  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3070  SysTick_CTRL_TICKINT_Msk |
3071  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3072  return (0UL); /* Function successful */
3073 }
3074 
3075 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3076 
3088 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3089 {
3090  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3091  {
3092  return (1UL); /* Reload value impossible */
3093  }
3094 
3095  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3096  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3097  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3098  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3099  SysTick_CTRL_TICKINT_Msk |
3100  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3101  return (0UL); /* Function successful */
3102 }
3103 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3104 
3105 #endif
3106 
3111 /* ##################################### Debug In/Output function ########################################### */
3119 extern volatile int32_t ITM_RxBuffer;
3120 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
3131 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3132 {
3133  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3134  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3135  {
3136  while (ITM->PORT[0U].u32 == 0UL)
3137  {
3138  __NOP();
3139  }
3140  ITM->PORT[0U].u8 = (uint8_t)ch;
3141  }
3142  return (ch);
3143 }
3144 
3145 
3152 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3153 {
3154  int32_t ch = -1; /* no character available */
3155 
3156  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3157  {
3158  ch = ITM_RxBuffer;
3159  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3160  }
3161 
3162  return (ch);
3163 }
3164 
3165 
3172 __STATIC_INLINE int32_t ITM_CheckChar (void)
3173 {
3174 
3175  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3176  {
3177  return (0); /* no character available */
3178  }
3179  else
3180  {
3181  return (1); /* character available */
3182  }
3183 }
3184 
3190 #ifdef __cplusplus
3191 }
3192 #endif
3193 
3194 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
3195 
3196 #endif /* __CMSIS_GENERIC */
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv81mml.h:2480
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_armv8mml.h:1697
ITM
#define ITM
Definition: core_armv8mml.h:2135
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1176
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_armv81mml.h:2983
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_armv8mml.h:627
mpu_armv8.h
DCB
#define DCB
Definition: core_armv8mml.h:2139
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:3298
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:903
__STATIC_INLINE
#define __STATIC_INLINE
Definition: hw_types.h:57
FPU
#define FPU
Definition: core_armv8mml.h:2153
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_armv8mml.h:612
SysTick
#define SysTick
Definition: core_armv8mml.h:2133
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_armv8mml.h:3120
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:3589
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:3279
IRQn_Type
enum IRQn IRQn_Type
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:3336
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv81mml.h:4173
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_armv81mml.h:3969
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_armv8mml.h:1694
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:3355
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:367
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1362
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv81mml.h:4193
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:3851
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:3550
NVIC
#define NVIC
Definition: core_armv8mml.h:2134
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:944
cmsis_version.h
CMSIS Core(M) Version definitions.
IRQn
IRQn
Definition: cc35xx.h:39
CoreDebug_Type
Definition: core_armv81mml.h:2621
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:511
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_armv8mml.h:1088
SCB
#define SCB
Definition: core_armv8mml.h:2132
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv81mml.h:1075
__IOM
#define __IOM
Definition: core_armv8mml.h:288
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:3573
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv81mml.h:3267
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:3317
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_armv8mml.h:626
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv81mml.h:998
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:475
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1023
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mml.h:611
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:3387
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: cmsis_gcc.h:117
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_armv81mml.h:4036
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv8mml.h:2222
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:3476
DIB
#define DIB
Definition: core_armv8mml.h:2140
SysTick_IRQn
Definition: cc35xx.h:49
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mml.h:633
cmsis_compiler.h
CMSIS compiler generic header file.
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:328
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mml.h:984
__OM
#define __OM
Definition: core_armv8mml.h:287
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:3370
__IM
#define __IM
Definition: core_armv8mml.h:286
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_armv81mml.h:2792
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:436
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: cc35xx.h:114
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mml.h:974
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mml.h:980
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mml.h:2237
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:3523
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:3600
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:385
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_armv81mml.h:3984
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:933
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:3498
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mml.h:977
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv81mml.h:3248
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_gcc.h:53