CC35xxDriverLibrary
core_armv8mbl.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30  #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32 
33 #ifndef __CORE_ARMV8MBL_H_GENERIC
34 #define __CORE_ARMV8MBL_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
57 /*******************************************************************************
58  * CMSIS definitions
59  ******************************************************************************/
65 #include "cmsis_version.h"
66 
67 /* CMSIS definitions */
68 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
71  __ARMv8MBL_CMSIS_VERSION_SUB )
73 #define __CORTEX_M (2U)
78 #define __FPU_USED 0U
79 
80 #if defined ( __CC_ARM )
81  #if defined __TARGET_FPU_VFP
82  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83  #endif
84 
85 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
86  #if defined __ARM_FP
87  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88  #endif
89 
90 #elif defined ( __GNUC__ )
91  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
92  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93  #endif
94 
95 #elif defined ( __ICCARM__ )
96  #if defined __ARMVFP__
97  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #endif
99 
100 #elif defined ( __TI_ARM__ )
101  #if defined __TI_VFP_SUPPORT__
102  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103  #endif
104 
105 #elif defined ( __TASKING__ )
106  #if defined __FPU_VFP__
107  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108  #endif
109 
110 #elif defined ( __CSMC__ )
111  #if ( __CSMC__ & 0x400U)
112  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113  #endif
114 
115 #endif
116 
117 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
118 
119 
120 #ifdef __cplusplus
121 }
122 #endif
123 
124 #endif /* __CORE_ARMV8MBL_H_GENERIC */
125 
126 #ifndef __CMSIS_GENERIC
127 
128 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
129 #define __CORE_ARMV8MBL_H_DEPENDANT
130 
131 #ifdef __cplusplus
132  extern "C" {
133 #endif
134 
135 /* check device defines and use defaults */
136 #if defined __CHECK_DEVICE_DEFINES
137  #ifndef __ARMv8MBL_REV
138  #define __ARMv8MBL_REV 0x0000U
139  #warning "__ARMv8MBL_REV not defined in device header file; using default!"
140  #endif
141 
142  #ifndef __FPU_PRESENT
143  #define __FPU_PRESENT 0U
144  #warning "__FPU_PRESENT not defined in device header file; using default!"
145  #endif
146 
147  #ifndef __MPU_PRESENT
148  #define __MPU_PRESENT 0U
149  #warning "__MPU_PRESENT not defined in device header file; using default!"
150  #endif
151 
152  #ifndef __SAUREGION_PRESENT
153  #define __SAUREGION_PRESENT 0U
154  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
155  #endif
156 
157  #ifndef __VTOR_PRESENT
158  #define __VTOR_PRESENT 0U
159  #warning "__VTOR_PRESENT not defined in device header file; using default!"
160  #endif
161 
162  #ifndef __NVIC_PRIO_BITS
163  #define __NVIC_PRIO_BITS 2U
164  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
165  #endif
166 
167  #ifndef __Vendor_SysTickConfig
168  #define __Vendor_SysTickConfig 0U
169  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
170  #endif
171 
172  #ifndef __ETM_PRESENT
173  #define __ETM_PRESENT 0U
174  #warning "__ETM_PRESENT not defined in device header file; using default!"
175  #endif
176 
177  #ifndef __MTB_PRESENT
178  #define __MTB_PRESENT 0U
179  #warning "__MTB_PRESENT not defined in device header file; using default!"
180  #endif
181 
182 #endif
183 
184 /* IO definitions (access restrictions to peripheral registers) */
192 #ifdef __cplusplus
193  #define __I volatile
194 #else
195  #define __I volatile const
196 #endif
197 #define __O volatile
198 #define __IO volatile
200 /* following defines should be used for structure members */
201 #define __IM volatile const
202 #define __OM volatile
203 #define __IOM volatile
205 
209 /*******************************************************************************
210  * Register Abstraction
211  Core Register contain:
212  - Core Register
213  - Core NVIC Register
214  - Core SCB Register
215  - Core SysTick Register
216  - Core Debug Register
217  - Core MPU Register
218  - Core SAU Register
219  ******************************************************************************/
220 
235 typedef union
236 {
237  struct
238  {
239  uint32_t _reserved0:28;
240  uint32_t V:1;
241  uint32_t C:1;
242  uint32_t Z:1;
243  uint32_t N:1;
244  } b;
245  uint32_t w;
246 } APSR_Type;
247 
248 /* APSR Register Definitions */
249 #define APSR_N_Pos 31U
250 #define APSR_N_Msk (1UL << APSR_N_Pos)
252 #define APSR_Z_Pos 30U
253 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
255 #define APSR_C_Pos 29U
256 #define APSR_C_Msk (1UL << APSR_C_Pos)
258 #define APSR_V_Pos 28U
259 #define APSR_V_Msk (1UL << APSR_V_Pos)
265 typedef union
266 {
267  struct
268  {
269  uint32_t ISR:9;
270  uint32_t _reserved0:23;
271  } b;
272  uint32_t w;
273 } IPSR_Type;
274 
275 /* IPSR Register Definitions */
276 #define IPSR_ISR_Pos 0U
277 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
283 typedef union
284 {
285  struct
286  {
287  uint32_t ISR:9;
288  uint32_t _reserved0:15;
289  uint32_t T:1;
290  uint32_t _reserved1:3;
291  uint32_t V:1;
292  uint32_t C:1;
293  uint32_t Z:1;
294  uint32_t N:1;
295  } b;
296  uint32_t w;
297 } xPSR_Type;
298 
299 /* xPSR Register Definitions */
300 #define xPSR_N_Pos 31U
301 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
303 #define xPSR_Z_Pos 30U
304 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
306 #define xPSR_C_Pos 29U
307 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
309 #define xPSR_V_Pos 28U
310 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
312 #define xPSR_T_Pos 24U
313 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
315 #define xPSR_ISR_Pos 0U
316 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
322 typedef union
323 {
324  struct
325  {
326  uint32_t nPRIV:1;
327  uint32_t SPSEL:1;
328  uint32_t _reserved1:30;
329  } b;
330  uint32_t w;
331 } CONTROL_Type;
332 
333 /* CONTROL Register Definitions */
334 #define CONTROL_SPSEL_Pos 1U
335 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
337 #define CONTROL_nPRIV_Pos 0U
338 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
340 
353 typedef struct
354 {
355  __IOM uint32_t ISER[16U];
356  uint32_t RESERVED0[16U];
357  __IOM uint32_t ICER[16U];
358  uint32_t RSERVED1[16U];
359  __IOM uint32_t ISPR[16U];
360  uint32_t RESERVED2[16U];
361  __IOM uint32_t ICPR[16U];
362  uint32_t RESERVED3[16U];
363  __IOM uint32_t IABR[16U];
364  uint32_t RESERVED4[16U];
365  __IOM uint32_t ITNS[16U];
366  uint32_t RESERVED5[16U];
367  __IOM uint32_t IPR[124U];
368 } NVIC_Type;
369 
383 typedef struct
384 {
385  __IM uint32_t CPUID;
386  __IOM uint32_t ICSR;
387 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
388  __IOM uint32_t VTOR;
389 #else
390  uint32_t RESERVED0;
391 #endif
392  __IOM uint32_t AIRCR;
393  __IOM uint32_t SCR;
394  __IOM uint32_t CCR;
395  uint32_t RESERVED1;
396  __IOM uint32_t SHPR[2U];
397  __IOM uint32_t SHCSR;
398 } SCB_Type;
399 
400 /* SCB CPUID Register Definitions */
401 #define SCB_CPUID_IMPLEMENTER_Pos 24U
402 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
404 #define SCB_CPUID_VARIANT_Pos 20U
405 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
407 #define SCB_CPUID_ARCHITECTURE_Pos 16U
408 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
410 #define SCB_CPUID_PARTNO_Pos 4U
411 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
413 #define SCB_CPUID_REVISION_Pos 0U
414 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
416 /* SCB Interrupt Control State Register Definitions */
417 #define SCB_ICSR_PENDNMISET_Pos 31U
418 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
420 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
421 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
423 #define SCB_ICSR_PENDNMICLR_Pos 30U
424 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
426 #define SCB_ICSR_PENDSVSET_Pos 28U
427 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
429 #define SCB_ICSR_PENDSVCLR_Pos 27U
430 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
432 #define SCB_ICSR_PENDSTSET_Pos 26U
433 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
435 #define SCB_ICSR_PENDSTCLR_Pos 25U
436 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
438 #define SCB_ICSR_STTNS_Pos 24U
439 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
441 #define SCB_ICSR_ISRPREEMPT_Pos 23U
442 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
444 #define SCB_ICSR_ISRPENDING_Pos 22U
445 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
447 #define SCB_ICSR_VECTPENDING_Pos 12U
448 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
450 #define SCB_ICSR_RETTOBASE_Pos 11U
451 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
453 #define SCB_ICSR_VECTACTIVE_Pos 0U
454 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
456 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
457 /* SCB Vector Table Offset Register Definitions */
458 #define SCB_VTOR_TBLOFF_Pos 7U
459 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
460 #endif
461 
462 /* SCB Application Interrupt and Reset Control Register Definitions */
463 #define SCB_AIRCR_VECTKEY_Pos 16U
464 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
466 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
467 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
469 #define SCB_AIRCR_ENDIANESS_Pos 15U
470 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
472 #define SCB_AIRCR_PRIS_Pos 14U
473 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
475 #define SCB_AIRCR_BFHFNMINS_Pos 13U
476 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
478 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
479 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
481 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
487 /* SCB System Control Register Definitions */
488 #define SCB_SCR_SEVONPEND_Pos 4U
489 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
491 #define SCB_SCR_SLEEPDEEPS_Pos 3U
492 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
494 #define SCB_SCR_SLEEPDEEP_Pos 2U
495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
497 #define SCB_SCR_SLEEPONEXIT_Pos 1U
498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
500 /* SCB Configuration Control Register Definitions */
501 #define SCB_CCR_BP_Pos 18U
502 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
504 #define SCB_CCR_IC_Pos 17U
505 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
507 #define SCB_CCR_DC_Pos 16U
508 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
510 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
511 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
513 #define SCB_CCR_BFHFNMIGN_Pos 8U
514 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
516 #define SCB_CCR_DIV_0_TRP_Pos 4U
517 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
519 #define SCB_CCR_UNALIGN_TRP_Pos 3U
520 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
522 #define SCB_CCR_USERSETMPEND_Pos 1U
523 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
525 /* SCB System Handler Control and State Register Definitions */
526 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
527 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
529 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
532 #define SCB_SHCSR_SYSTICKACT_Pos 11U
533 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
535 #define SCB_SHCSR_PENDSVACT_Pos 10U
536 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
538 #define SCB_SHCSR_SVCALLACT_Pos 7U
539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
541 #define SCB_SHCSR_NMIACT_Pos 5U
542 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
544 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
545 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
547 
560 typedef struct
561 {
562  __IOM uint32_t CTRL;
563  __IOM uint32_t LOAD;
564  __IOM uint32_t VAL;
565  __IM uint32_t CALIB;
566 } SysTick_Type;
567 
568 /* SysTick Control / Status Register Definitions */
569 #define SysTick_CTRL_COUNTFLAG_Pos 16U
570 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
572 #define SysTick_CTRL_CLKSOURCE_Pos 2U
573 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
575 #define SysTick_CTRL_TICKINT_Pos 1U
576 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
578 #define SysTick_CTRL_ENABLE_Pos 0U
579 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
581 /* SysTick Reload Register Definitions */
582 #define SysTick_LOAD_RELOAD_Pos 0U
583 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
585 /* SysTick Current Register Definitions */
586 #define SysTick_VAL_CURRENT_Pos 0U
587 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
589 /* SysTick Calibration Register Definitions */
590 #define SysTick_CALIB_NOREF_Pos 31U
591 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
593 #define SysTick_CALIB_SKEW_Pos 30U
594 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
596 #define SysTick_CALIB_TENMS_Pos 0U
597 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
599 
612 typedef struct
613 {
614  __IOM uint32_t CTRL;
615  uint32_t RESERVED0[6U];
616  __IM uint32_t PCSR;
617  __IOM uint32_t COMP0;
618  uint32_t RESERVED1[1U];
619  __IOM uint32_t FUNCTION0;
620  uint32_t RESERVED2[1U];
621  __IOM uint32_t COMP1;
622  uint32_t RESERVED3[1U];
623  __IOM uint32_t FUNCTION1;
624  uint32_t RESERVED4[1U];
625  __IOM uint32_t COMP2;
626  uint32_t RESERVED5[1U];
627  __IOM uint32_t FUNCTION2;
628  uint32_t RESERVED6[1U];
629  __IOM uint32_t COMP3;
630  uint32_t RESERVED7[1U];
631  __IOM uint32_t FUNCTION3;
632  uint32_t RESERVED8[1U];
633  __IOM uint32_t COMP4;
634  uint32_t RESERVED9[1U];
635  __IOM uint32_t FUNCTION4;
636  uint32_t RESERVED10[1U];
637  __IOM uint32_t COMP5;
638  uint32_t RESERVED11[1U];
639  __IOM uint32_t FUNCTION5;
640  uint32_t RESERVED12[1U];
641  __IOM uint32_t COMP6;
642  uint32_t RESERVED13[1U];
643  __IOM uint32_t FUNCTION6;
644  uint32_t RESERVED14[1U];
645  __IOM uint32_t COMP7;
646  uint32_t RESERVED15[1U];
647  __IOM uint32_t FUNCTION7;
648  uint32_t RESERVED16[1U];
649  __IOM uint32_t COMP8;
650  uint32_t RESERVED17[1U];
651  __IOM uint32_t FUNCTION8;
652  uint32_t RESERVED18[1U];
653  __IOM uint32_t COMP9;
654  uint32_t RESERVED19[1U];
655  __IOM uint32_t FUNCTION9;
656  uint32_t RESERVED20[1U];
657  __IOM uint32_t COMP10;
658  uint32_t RESERVED21[1U];
659  __IOM uint32_t FUNCTION10;
660  uint32_t RESERVED22[1U];
661  __IOM uint32_t COMP11;
662  uint32_t RESERVED23[1U];
663  __IOM uint32_t FUNCTION11;
664  uint32_t RESERVED24[1U];
665  __IOM uint32_t COMP12;
666  uint32_t RESERVED25[1U];
667  __IOM uint32_t FUNCTION12;
668  uint32_t RESERVED26[1U];
669  __IOM uint32_t COMP13;
670  uint32_t RESERVED27[1U];
671  __IOM uint32_t FUNCTION13;
672  uint32_t RESERVED28[1U];
673  __IOM uint32_t COMP14;
674  uint32_t RESERVED29[1U];
675  __IOM uint32_t FUNCTION14;
676  uint32_t RESERVED30[1U];
677  __IOM uint32_t COMP15;
678  uint32_t RESERVED31[1U];
679  __IOM uint32_t FUNCTION15;
680 } DWT_Type;
681 
682 /* DWT Control Register Definitions */
683 #define DWT_CTRL_NUMCOMP_Pos 28U
684 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
686 #define DWT_CTRL_NOTRCPKT_Pos 27U
687 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
689 #define DWT_CTRL_NOEXTTRIG_Pos 26U
690 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
692 #define DWT_CTRL_NOCYCCNT_Pos 25U
693 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
695 #define DWT_CTRL_NOPRFCNT_Pos 24U
696 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
698 /* DWT Comparator Function Register Definitions */
699 #define DWT_FUNCTION_ID_Pos 27U
700 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
702 #define DWT_FUNCTION_MATCHED_Pos 24U
703 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
705 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
706 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
708 #define DWT_FUNCTION_ACTION_Pos 4U
709 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)
711 #define DWT_FUNCTION_MATCH_Pos 0U
712 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
714  /* end of group CMSIS_DWT */
715 
716 
727 typedef struct
728 {
729  __IM uint32_t SSPSR;
730  __IOM uint32_t CSPSR;
731  uint32_t RESERVED0[2U];
732  __IOM uint32_t ACPR;
733  uint32_t RESERVED1[55U];
734  __IOM uint32_t SPPR;
735  uint32_t RESERVED2[131U];
736  __IM uint32_t FFSR;
737  __IOM uint32_t FFCR;
738  __IOM uint32_t PSCR;
739  uint32_t RESERVED3[809U];
740  __OM uint32_t LAR;
741  __IM uint32_t LSR;
742  uint32_t RESERVED4[4U];
743  __IM uint32_t TYPE;
744  __IM uint32_t DEVTYPE;
745 } TPI_Type;
746 
747 /* TPI Asynchronous Clock Prescaler Register Definitions */
748 #define TPI_ACPR_SWOSCALER_Pos 0U
749 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
751 /* TPI Selected Pin Protocol Register Definitions */
752 #define TPI_SPPR_TXMODE_Pos 0U
753 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
755 /* TPI Formatter and Flush Status Register Definitions */
756 #define TPI_FFSR_FtNonStop_Pos 3U
757 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
759 #define TPI_FFSR_TCPresent_Pos 2U
760 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
762 #define TPI_FFSR_FtStopped_Pos 1U
763 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
765 #define TPI_FFSR_FlInProg_Pos 0U
766 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
768 /* TPI Formatter and Flush Control Register Definitions */
769 #define TPI_FFCR_TrigIn_Pos 8U
770 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
772 #define TPI_FFCR_FOnMan_Pos 6U
773 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
775 #define TPI_FFCR_EnFCont_Pos 1U
776 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
778 /* TPI Periodic Synchronization Control Register Definitions */
779 #define TPI_PSCR_PSCount_Pos 0U
780 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
782 /* TPI Software Lock Status Register Definitions */
783 #define TPI_LSR_nTT_Pos 1U
784 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
786 #define TPI_LSR_SLK_Pos 1U
787 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
789 #define TPI_LSR_SLI_Pos 0U
790 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
792 /* TPI DEVID Register Definitions */
793 #define TPI_DEVID_NRZVALID_Pos 11U
794 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
796 #define TPI_DEVID_MANCVALID_Pos 10U
797 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
799 #define TPI_DEVID_PTINVALID_Pos 9U
800 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
802 #define TPI_DEVID_FIFOSZ_Pos 6U
803 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
805 /* TPI DEVTYPE Register Definitions */
806 #define TPI_DEVTYPE_SubType_Pos 4U
807 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
809 #define TPI_DEVTYPE_MajorType_Pos 0U
810 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
812  /* end of group CMSIS_TPI */
813 
814 
815 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
816 
826 typedef struct
827 {
828  __IM uint32_t TYPE;
829  __IOM uint32_t CTRL;
830  __IOM uint32_t RNR;
831  __IOM uint32_t RBAR;
832  __IOM uint32_t RLAR;
833  uint32_t RESERVED0[7U];
834  union {
835  __IOM uint32_t MAIR[2];
836  struct {
837  __IOM uint32_t MAIR0;
838  __IOM uint32_t MAIR1;
839  };
840  };
841 } MPU_Type;
842 
843 #define MPU_TYPE_RALIASES 1U
844 
845 /* MPU Type Register Definitions */
846 #define MPU_TYPE_IREGION_Pos 16U
847 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
849 #define MPU_TYPE_DREGION_Pos 8U
850 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
852 #define MPU_TYPE_SEPARATE_Pos 0U
853 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
855 /* MPU Control Register Definitions */
856 #define MPU_CTRL_PRIVDEFENA_Pos 2U
857 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
859 #define MPU_CTRL_HFNMIENA_Pos 1U
860 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
862 #define MPU_CTRL_ENABLE_Pos 0U
863 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
865 /* MPU Region Number Register Definitions */
866 #define MPU_RNR_REGION_Pos 0U
867 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
869 /* MPU Region Base Address Register Definitions */
870 #define MPU_RBAR_BASE_Pos 5U
871 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
873 #define MPU_RBAR_SH_Pos 3U
874 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
876 #define MPU_RBAR_AP_Pos 1U
877 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
879 #define MPU_RBAR_XN_Pos 0U
880 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
882 /* MPU Region Limit Address Register Definitions */
883 #define MPU_RLAR_LIMIT_Pos 5U
884 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
886 #define MPU_RLAR_AttrIndx_Pos 1U
887 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
889 #define MPU_RLAR_EN_Pos 0U
890 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
892 /* MPU Memory Attribute Indirection Register 0 Definitions */
893 #define MPU_MAIR0_Attr3_Pos 24U
894 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
896 #define MPU_MAIR0_Attr2_Pos 16U
897 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
899 #define MPU_MAIR0_Attr1_Pos 8U
900 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
902 #define MPU_MAIR0_Attr0_Pos 0U
903 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
905 /* MPU Memory Attribute Indirection Register 1 Definitions */
906 #define MPU_MAIR1_Attr7_Pos 24U
907 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
909 #define MPU_MAIR1_Attr6_Pos 16U
910 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
912 #define MPU_MAIR1_Attr5_Pos 8U
913 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
915 #define MPU_MAIR1_Attr4_Pos 0U
916 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
918 
919 #endif
920 
921 
922 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
923 
933 typedef struct
934 {
935  __IOM uint32_t CTRL;
936  __IM uint32_t TYPE;
937 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
938  __IOM uint32_t RNR;
939  __IOM uint32_t RBAR;
940  __IOM uint32_t RLAR;
941 #endif
942 } SAU_Type;
943 
944 /* SAU Control Register Definitions */
945 #define SAU_CTRL_ALLNS_Pos 1U
946 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
948 #define SAU_CTRL_ENABLE_Pos 0U
949 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
951 /* SAU Type Register Definitions */
952 #define SAU_TYPE_SREGION_Pos 0U
953 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
955 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
956 /* SAU Region Number Register Definitions */
957 #define SAU_RNR_REGION_Pos 0U
958 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
960 /* SAU Region Base Address Register Definitions */
961 #define SAU_RBAR_BADDR_Pos 5U
962 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
964 /* SAU Region Limit Address Register Definitions */
965 #define SAU_RLAR_LADDR_Pos 5U
966 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
968 #define SAU_RLAR_NSC_Pos 1U
969 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
971 #define SAU_RLAR_ENABLE_Pos 0U
972 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
974 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
975 
977 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
978 
979 
980 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
991 typedef struct
992 {
993  __IOM uint32_t DHCSR;
994  __OM uint32_t DCRSR;
995  __IOM uint32_t DCRDR;
996  __IOM uint32_t DEMCR;
997  uint32_t RESERVED0[1U];
998  __IOM uint32_t DAUTHCTRL;
999  __IOM uint32_t DSCSR;
1000 } CoreDebug_Type;
1001 
1002 /* Debug Halting Control and Status Register Definitions */
1003 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1004 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1006 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1007 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1009 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1010 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1012 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1013 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1015 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1016 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1018 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1019 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1021 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1022 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1024 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1025 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1027 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1028 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1030 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1031 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1033 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1034 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1036 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1037 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1039 /* Debug Core Register Selector Register Definitions */
1040 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1041 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1043 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1044 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1046 /* Debug Exception and Monitor Control Register Definitions */
1047 #define CoreDebug_DEMCR_DWTENA_Pos 24U
1048 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)
1050 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1051 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1053 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1054 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1056 /* Debug Authentication Control Register Definitions */
1057 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1058 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1060 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1061 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1063 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1064 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1066 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1067 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1069 /* Debug Security Control and Status Register Definitions */
1070 #define CoreDebug_DSCSR_CDS_Pos 16U
1071 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1073 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1074 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1076 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1077 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1079 
1092 typedef struct
1093 {
1094  __IOM uint32_t DHCSR;
1095  __OM uint32_t DCRSR;
1096  __IOM uint32_t DCRDR;
1097  __IOM uint32_t DEMCR;
1098  uint32_t RESERVED0[1U];
1099  __IOM uint32_t DAUTHCTRL;
1100  __IOM uint32_t DSCSR;
1101 } DCB_Type;
1102 
1103 /* DHCSR, Debug Halting Control and Status Register Definitions */
1104 #define DCB_DHCSR_DBGKEY_Pos 16U
1105 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1107 #define DCB_DHCSR_S_RESTART_ST_Pos 26U
1108 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1110 #define DCB_DHCSR_S_RESET_ST_Pos 25U
1111 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1113 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1114 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1116 #define DCB_DHCSR_S_SDE_Pos 20U
1117 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1119 #define DCB_DHCSR_S_LOCKUP_Pos 19U
1120 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
1122 #define DCB_DHCSR_S_SLEEP_Pos 18U
1123 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
1125 #define DCB_DHCSR_S_HALT_Pos 17U
1126 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
1128 #define DCB_DHCSR_S_REGRDY_Pos 16U
1129 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
1131 #define DCB_DHCSR_C_MASKINTS_Pos 3U
1132 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
1134 #define DCB_DHCSR_C_STEP_Pos 2U
1135 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
1137 #define DCB_DHCSR_C_HALT_Pos 1U
1138 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
1140 #define DCB_DHCSR_C_DEBUGEN_Pos 0U
1141 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
1143 /* DCRSR, Debug Core Register Select Register Definitions */
1144 #define DCB_DCRSR_REGWnR_Pos 16U
1145 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
1147 #define DCB_DCRSR_REGSEL_Pos 0U
1148 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
1150 /* DCRDR, Debug Core Register Data Register Definitions */
1151 #define DCB_DCRDR_DBGTMP_Pos 0U
1152 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
1154 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1155 #define DCB_DEMCR_TRCENA_Pos 24U
1156 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
1158 #define DCB_DEMCR_VC_HARDERR_Pos 10U
1159 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
1161 #define DCB_DEMCR_VC_CORERESET_Pos 0U
1162 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
1164 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
1165 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
1166 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
1168 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
1169 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
1171 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
1172 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
1174 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
1175 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
1177 /* DSCSR, Debug Security Control and Status Register Definitions */
1178 #define DCB_DSCSR_CDSKEY_Pos 17U
1179 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
1181 #define DCB_DSCSR_CDS_Pos 16U
1182 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
1184 #define DCB_DSCSR_SBRSEL_Pos 1U
1185 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
1187 #define DCB_DSCSR_SBRSELEN_Pos 0U
1188 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
1190 
1204 typedef struct
1205 {
1206  __OM uint32_t DLAR;
1207  __IM uint32_t DLSR;
1208  __IM uint32_t DAUTHSTATUS;
1209  __IM uint32_t DDEVARCH;
1210  __IM uint32_t DDEVTYPE;
1211 } DIB_Type;
1212 
1213 /* DLAR, SCS Software Lock Access Register Definitions */
1214 #define DIB_DLAR_KEY_Pos 0U
1215 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
1217 /* DLSR, SCS Software Lock Status Register Definitions */
1218 #define DIB_DLSR_nTT_Pos 2U
1219 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
1221 #define DIB_DLSR_SLK_Pos 1U
1222 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
1224 #define DIB_DLSR_SLI_Pos 0U
1225 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
1227 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
1228 #define DIB_DAUTHSTATUS_SNID_Pos 6U
1229 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
1231 #define DIB_DAUTHSTATUS_SID_Pos 4U
1232 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
1234 #define DIB_DAUTHSTATUS_NSNID_Pos 2U
1235 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
1237 #define DIB_DAUTHSTATUS_NSID_Pos 0U
1238 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
1240 /* DDEVARCH, SCS Device Architecture Register Definitions */
1241 #define DIB_DDEVARCH_ARCHITECT_Pos 21U
1242 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
1244 #define DIB_DDEVARCH_PRESENT_Pos 20U
1245 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
1247 #define DIB_DDEVARCH_REVISION_Pos 16U
1248 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
1250 #define DIB_DDEVARCH_ARCHVER_Pos 12U
1251 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
1253 #define DIB_DDEVARCH_ARCHPART_Pos 0U
1254 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
1256 /* DDEVTYPE, SCS Device Type Register Definitions */
1257 #define DIB_DDEVTYPE_SUB_Pos 4U
1258 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
1260 #define DIB_DDEVTYPE_MAJOR_Pos 0U
1261 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
1264 
1280 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1281 
1288 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1289 
1300 /* Memory mapping of Core Hardware */
1301  #define SCS_BASE (0xE000E000UL)
1302  #define DWT_BASE (0xE0001000UL)
1303  #define TPI_BASE (0xE0040000UL)
1304  #define CoreDebug_BASE (0xE000EDF0UL)
1305  #define DCB_BASE (0xE000EDF0UL)
1306  #define DIB_BASE (0xE000EFB0UL)
1307  #define SysTick_BASE (SCS_BASE + 0x0010UL)
1308  #define NVIC_BASE (SCS_BASE + 0x0100UL)
1309  #define SCB_BASE (SCS_BASE + 0x0D00UL)
1312  #define SCB ((SCB_Type *) SCB_BASE )
1313  #define SysTick ((SysTick_Type *) SysTick_BASE )
1314  #define NVIC ((NVIC_Type *) NVIC_BASE )
1315  #define DWT ((DWT_Type *) DWT_BASE )
1316  #define TPI ((TPI_Type *) TPI_BASE )
1317  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1318  #define DCB ((DCB_Type *) DCB_BASE )
1319  #define DIB ((DIB_Type *) DIB_BASE )
1321  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1322  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1323  #define MPU ((MPU_Type *) MPU_BASE )
1324  #endif
1325 
1326  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1327  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
1328  #define SAU ((SAU_Type *) SAU_BASE )
1329  #endif
1330 
1331 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1332  #define SCS_BASE_NS (0xE002E000UL)
1333  #define CoreDebug_BASE_NS (0xE002EDF0UL)
1334  #define DCB_BASE_NS (0xE002EDF0UL)
1335  #define DIB_BASE_NS (0xE002EFB0UL)
1336  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
1337  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
1338  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
1340  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
1341  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
1342  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
1343  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
1344  #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
1345  #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
1347  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1348  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
1349  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
1350  #endif
1351 
1352 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1353 
1357 /*******************************************************************************
1358  * Hardware Abstraction Layer
1359  Core Function Interface contains:
1360  - Core NVIC Functions
1361  - Core SysTick Functions
1362  - Core Debug Functions
1363  - Core Register Access Functions
1364  ******************************************************************************/
1371 /* ########################## NVIC functions #################################### */
1379 #ifdef CMSIS_NVIC_VIRTUAL
1380  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1381  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1382  #endif
1383  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1384 #else
1385  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1386  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1387  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1388  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1389  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1390  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1391  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1392  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1393  #define NVIC_GetActive __NVIC_GetActive
1394  #define NVIC_SetPriority __NVIC_SetPriority
1395  #define NVIC_GetPriority __NVIC_GetPriority
1396  #define NVIC_SystemReset __NVIC_SystemReset
1397 #endif /* CMSIS_NVIC_VIRTUAL */
1398 
1399 #ifdef CMSIS_VECTAB_VIRTUAL
1400  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1401  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1402  #endif
1403  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1404 #else
1405  #define NVIC_SetVector __NVIC_SetVector
1406  #define NVIC_GetVector __NVIC_GetVector
1407 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1408 
1409 #define NVIC_USER_IRQ_OFFSET 16
1410 
1411 
1412 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1413 
1414 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1415 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1416 
1417 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1418 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1419 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1420 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1421 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1422 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1423 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1424 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1425 
1426 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1427 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1428 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1429 #else
1430 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1431 #endif
1432 
1433 
1434 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1435 /* The following MACROS handle generation of the register offset and byte masks */
1436 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1437 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1438 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1439 
1440 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1441 #define __NVIC_GetPriorityGrouping() (0U)
1442 
1449 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1450 {
1451  if ((int32_t)(IRQn) >= 0)
1452  {
1453  __COMPILER_BARRIER();
1454  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1455  __COMPILER_BARRIER();
1456  }
1457 }
1458 
1459 
1468 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1469 {
1470  if ((int32_t)(IRQn) >= 0)
1471  {
1472  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1473  }
1474  else
1475  {
1476  return(0U);
1477  }
1478 }
1479 
1480 
1487 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1488 {
1489  if ((int32_t)(IRQn) >= 0)
1490  {
1491  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1492  __DSB();
1493  __ISB();
1494  }
1495 }
1496 
1497 
1506 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1507 {
1508  if ((int32_t)(IRQn) >= 0)
1509  {
1510  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1511  }
1512  else
1513  {
1514  return(0U);
1515  }
1516 }
1517 
1518 
1525 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1526 {
1527  if ((int32_t)(IRQn) >= 0)
1528  {
1529  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1530  }
1531 }
1532 
1533 
1540 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1541 {
1542  if ((int32_t)(IRQn) >= 0)
1543  {
1544  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1545  }
1546 }
1547 
1548 
1557 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1558 {
1559  if ((int32_t)(IRQn) >= 0)
1560  {
1561  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1562  }
1563  else
1564  {
1565  return(0U);
1566  }
1567 }
1568 
1569 
1570 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1571 
1579 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1580 {
1581  if ((int32_t)(IRQn) >= 0)
1582  {
1583  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1584  }
1585  else
1586  {
1587  return(0U);
1588  }
1589 }
1590 
1591 
1600 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1601 {
1602  if ((int32_t)(IRQn) >= 0)
1603  {
1604  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1605  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1606  }
1607  else
1608  {
1609  return(0U);
1610  }
1611 }
1612 
1613 
1622 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1623 {
1624  if ((int32_t)(IRQn) >= 0)
1625  {
1626  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1627  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1628  }
1629  else
1630  {
1631  return(0U);
1632  }
1633 }
1634 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1635 
1636 
1646 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1647 {
1648  if ((int32_t)(IRQn) >= 0)
1649  {
1650  NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1651  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1652  }
1653  else
1654  {
1655  SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1656  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1657  }
1658 }
1659 
1660 
1670 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1671 {
1672 
1673  if ((int32_t)(IRQn) >= 0)
1674  {
1675  return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1676  }
1677  else
1678  {
1679  return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1680  }
1681 }
1682 
1683 
1695 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1696 {
1697  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1698  uint32_t PreemptPriorityBits;
1699  uint32_t SubPriorityBits;
1700 
1701  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1702  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1703 
1704  return (
1705  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1706  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1707  );
1708 }
1709 
1710 
1722 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1723 {
1724  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1725  uint32_t PreemptPriorityBits;
1726  uint32_t SubPriorityBits;
1727 
1728  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1729  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1730 
1731  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1732  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1733 }
1734 
1735 
1746 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1747 {
1748 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1749  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1750 #else
1751  uint32_t *vectors = (uint32_t *)0x0U;
1752 #endif
1753  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1754  __DSB();
1755 }
1756 
1757 
1766 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1767 {
1768 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1769  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1770 #else
1771  uint32_t *vectors = (uint32_t *)0x0U;
1772 #endif
1773  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1774 }
1775 
1776 
1781 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1782 {
1783  __DSB(); /* Ensure all outstanding memory accesses included
1784  buffered write are completed before reset */
1785  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1786  SCB_AIRCR_SYSRESETREQ_Msk);
1787  __DSB(); /* Ensure completion of memory access */
1788 
1789  for(;;) /* wait until reset */
1790  {
1791  __NOP();
1792  }
1793 }
1794 
1795 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1796 
1802 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1803 {
1804  if ((int32_t)(IRQn) >= 0)
1805  {
1806  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1807  }
1808 }
1809 
1810 
1819 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1820 {
1821  if ((int32_t)(IRQn) >= 0)
1822  {
1823  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1824  }
1825  else
1826  {
1827  return(0U);
1828  }
1829 }
1830 
1831 
1838 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1839 {
1840  if ((int32_t)(IRQn) >= 0)
1841  {
1842  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1843  }
1844 }
1845 
1846 
1855 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1856 {
1857  if ((int32_t)(IRQn) >= 0)
1858  {
1859  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1860  }
1861  else
1862  {
1863  return(0U);
1864  }
1865 }
1866 
1867 
1874 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1875 {
1876  if ((int32_t)(IRQn) >= 0)
1877  {
1878  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1879  }
1880 }
1881 
1882 
1889 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1890 {
1891  if ((int32_t)(IRQn) >= 0)
1892  {
1893  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1894  }
1895 }
1896 
1897 
1906 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1907 {
1908  if ((int32_t)(IRQn) >= 0)
1909  {
1910  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1911  }
1912  else
1913  {
1914  return(0U);
1915  }
1916 }
1917 
1918 
1928 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1929 {
1930  if ((int32_t)(IRQn) >= 0)
1931  {
1932  NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1933  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1934  }
1935  else
1936  {
1937  SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1938  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1939  }
1940 }
1941 
1942 
1951 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1952 {
1953 
1954  if ((int32_t)(IRQn) >= 0)
1955  {
1956  return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1957  }
1958  else
1959  {
1960  return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1961  }
1962 }
1963 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1964 
1967 /* ########################## MPU functions #################################### */
1968 
1969 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1970 
1971 #include "mpu_armv8.h"
1972 
1973 #endif
1974 
1975 /* ########################## FPU functions #################################### */
1991 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1992 {
1993  return 0U; /* No FPU */
1994 }
1995 
1996 
2001 /* ########################## SAU functions #################################### */
2009 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2010 
2015 __STATIC_INLINE void TZ_SAU_Enable(void)
2016 {
2017  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2018 }
2019 
2020 
2021 
2026 __STATIC_INLINE void TZ_SAU_Disable(void)
2027 {
2028  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2029 }
2030 
2031 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2032 
2038 /* ################################## Debug Control function ############################################ */
2052 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2053 {
2054  __DSB();
2055  __ISB();
2056  DCB->DAUTHCTRL = value;
2057  __DSB();
2058  __ISB();
2059 }
2060 
2061 
2067 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2068 {
2069  return (DCB->DAUTHCTRL);
2070 }
2071 
2072 
2073 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2074 
2079 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2080 {
2081  __DSB();
2082  __ISB();
2083  DCB_NS->DAUTHCTRL = value;
2084  __DSB();
2085  __ISB();
2086 }
2087 
2088 
2094 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2095 {
2096  return (DCB_NS->DAUTHCTRL);
2097 }
2098 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2099 
2105 /* ################################## Debug Identification function ############################################ */
2119 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
2120 {
2121  return (DIB->DAUTHSTATUS);
2122 }
2123 
2124 
2125 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2126 
2131 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
2132 {
2133  return (DIB_NS->DAUTHSTATUS);
2134 }
2135 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2136 
2142 /* ################################## SysTick function ############################################ */
2150 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2151 
2163 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2164 {
2165  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2166  {
2167  return (1UL); /* Reload value impossible */
2168  }
2169 
2170  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2171  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2172  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2173  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2174  SysTick_CTRL_TICKINT_Msk |
2175  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2176  return (0UL); /* Function successful */
2177 }
2178 
2179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2180 
2192 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2193 {
2194  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2195  {
2196  return (1UL); /* Reload value impossible */
2197  }
2198 
2199  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2200  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2201  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2202  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2203  SysTick_CTRL_TICKINT_Msk |
2204  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2205  return (0UL); /* Function successful */
2206 }
2207 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2208 
2209 #endif
2210 
2216 #ifdef __cplusplus
2217 }
2218 #endif
2219 
2220 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
2221 
2222 #endif /* __CMSIS_GENERIC */
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1176
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_armv81mml.h:2983
mpu_armv8.h
DCB
#define DCB
Definition: core_armv8mbl.h:1318
SCB_Type::RESERVED0
uint32_t RESERVED0
Definition: core_armv8mbl.h:390
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:3298
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:903
__STATIC_INLINE
#define __STATIC_INLINE
Definition: hw_types.h:57
SysTick
#define SysTick
Definition: core_armv8mbl.h:1313
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:3589
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:3279
IRQn_Type
enum IRQn IRQn_Type
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:3336
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_armv81mml.h:3969
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:3355
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:367
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1362
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:3851
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:3550
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_armv8mbl.h:1436
NVIC
#define NVIC
Definition: core_armv8mbl.h:1314
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:944
cmsis_version.h
CMSIS Core(M) Version definitions.
IRQn
IRQn
Definition: cc35xx.h:39
CoreDebug_Type
Definition: core_armv81mml.h:2621
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:511
SCB
#define SCB
Definition: core_armv8mbl.h:1312
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:3573
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:3317
__IOM
#define __IOM
Definition: core_armv8mbl.h:203
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:475
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1023
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mbl.h:463
SCB_Type::RESERVED1
uint32_t RESERVED1
Definition: core_armv8mbl.h:395
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:3387
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: cmsis_gcc.h:117
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_armv8mbl.h:1438
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_armv81mml.h:4036
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv8mbl.h:1394
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:3476
DIB
#define DIB
Definition: core_armv8mbl.h:1319
SysTick_IRQn
Definition: cc35xx.h:49
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mbl.h:482
cmsis_compiler.h
CMSIS compiler generic header file.
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:328
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mbl.h:583
__IM
#define __IM
Definition: core_armv8mbl.h:201
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:3370
__OM
#define __OM
Definition: core_armv8mbl.h:202
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_armv81mml.h:2792
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:436
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: cc35xx.h:114
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mbl.h:573
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mbl.h:579
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mbl.h:1409
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:3523
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:3600
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:385
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_armv81mml.h:3984
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:933
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:3498
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mbl.h:576
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_armv8mbl.h:1437
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_gcc.h:53