CC35xxDriverLibrary
core_armv81mml.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30  #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32 
33 #ifndef __CORE_ARMV81MML_H_GENERIC
34 #define __CORE_ARMV81MML_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
57 /*******************************************************************************
58  * CMSIS definitions
59  ******************************************************************************/
65 #include "cmsis_version.h"
66 
67 /* CMSIS ARMV81MML definitions */
68 #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69 #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70 #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
71  __ARMv81MML_CMSIS_VERSION_SUB )
73 #define __CORTEX_M (81U)
75 #if defined ( __CC_ARM )
76  #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
77 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
78  #if defined __ARM_FP
79  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
80  #define __FPU_USED 1U
81  #else
82  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83  #define __FPU_USED 0U
84  #endif
85  #else
86  #define __FPU_USED 0U
87  #endif
88 
89  #if defined(__ARM_FEATURE_DSP)
90  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
91  #define __DSP_USED 1U
92  #else
93  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
94  #define __DSP_USED 0U
95  #endif
96  #else
97  #define __DSP_USED 0U
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103  #define __FPU_USED 1U
104  #else
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #define __FPU_USED 0U
107  #endif
108  #else
109  #define __FPU_USED 0U
110  #endif
111 
112  #if defined(__ARM_FEATURE_DSP)
113  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
114  #define __DSP_USED 1U
115  #else
116  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
117  #define __DSP_USED 0U
118  #endif
119  #else
120  #define __DSP_USED 0U
121  #endif
122 
123 #elif defined ( __ICCARM__ )
124  #if defined __ARMVFP__
125  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
126  #define __FPU_USED 1U
127  #else
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #define __FPU_USED 0U
130  #endif
131  #else
132  #define __FPU_USED 0U
133  #endif
134 
135  #if defined(__ARM_FEATURE_DSP)
136  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
137  #define __DSP_USED 1U
138  #else
139  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
140  #define __DSP_USED 0U
141  #endif
142  #else
143  #define __DSP_USED 0U
144  #endif
145 
146 #elif defined ( __TI_ARM__ )
147  #if defined __TI_VFP_SUPPORT__
148  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
149  #define __FPU_USED 1U
150  #else
151  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
152  #define __FPU_USED 0U
153  #endif
154  #else
155  #define __FPU_USED 0U
156  #endif
157 
158 #elif defined ( __TASKING__ )
159  #if defined __FPU_VFP__
160  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
161  #define __FPU_USED 1U
162  #else
163  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
164  #define __FPU_USED 0U
165  #endif
166  #else
167  #define __FPU_USED 0U
168  #endif
169 
170 #elif defined ( __CSMC__ )
171  #if ( __CSMC__ & 0x400U)
172  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
173  #define __FPU_USED 1U
174  #else
175  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
176  #define __FPU_USED 0U
177  #endif
178  #else
179  #define __FPU_USED 0U
180  #endif
181 
182 #endif
183 
184 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
185 
186 
187 #ifdef __cplusplus
188 }
189 #endif
190 
191 #endif /* __CORE_ARMV81MML_H_GENERIC */
192 
193 #ifndef __CMSIS_GENERIC
194 
195 #ifndef __CORE_ARMV81MML_H_DEPENDANT
196 #define __CORE_ARMV81MML_H_DEPENDANT
197 
198 #ifdef __cplusplus
199  extern "C" {
200 #endif
201 
202 /* check device defines and use defaults */
203 #if defined __CHECK_DEVICE_DEFINES
204  #ifndef __ARMv81MML_REV
205  #define __ARMv81MML_REV 0x0000U
206  #warning "__ARMv81MML_REV not defined in device header file; using default!"
207  #endif
208 
209  #ifndef __FPU_PRESENT
210  #define __FPU_PRESENT 0U
211  #warning "__FPU_PRESENT not defined in device header file; using default!"
212  #endif
213 
214  #if __FPU_PRESENT != 0U
215  #ifndef __FPU_DP
216  #define __FPU_DP 0U
217  #warning "__FPU_DP not defined in device header file; using default!"
218  #endif
219  #endif
220 
221  #ifndef __MPU_PRESENT
222  #define __MPU_PRESENT 0U
223  #warning "__MPU_PRESENT not defined in device header file; using default!"
224  #endif
225 
226  #ifndef __ICACHE_PRESENT
227  #define __ICACHE_PRESENT 0U
228  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
229  #endif
230 
231  #ifndef __DCACHE_PRESENT
232  #define __DCACHE_PRESENT 0U
233  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __PMU_PRESENT
237  #define __PMU_PRESENT 0U
238  #warning "__PMU_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #if __PMU_PRESENT != 0U
242  #ifndef __PMU_NUM_EVENTCNT
243  #define __PMU_NUM_EVENTCNT 2U
244  #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
245  #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2)
246  #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
247  #endif
248  #endif
249 
250  #ifndef __SAUREGION_PRESENT
251  #define __SAUREGION_PRESENT 0U
252  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
253  #endif
254 
255  #ifndef __DSP_PRESENT
256  #define __DSP_PRESENT 0U
257  #warning "__DSP_PRESENT not defined in device header file; using default!"
258  #endif
259 
260  #ifndef __VTOR_PRESENT
261  #define __VTOR_PRESENT 1U
262  #warning "__VTOR_PRESENT not defined in device header file; using default!"
263  #endif
264 
265  #ifndef __NVIC_PRIO_BITS
266  #define __NVIC_PRIO_BITS 3U
267  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
268  #endif
269 
270  #ifndef __Vendor_SysTickConfig
271  #define __Vendor_SysTickConfig 0U
272  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
273  #endif
274 #endif
275 
276 /* IO definitions (access restrictions to peripheral registers) */
284 #ifdef __cplusplus
285  #define __I volatile
286 #else
287  #define __I volatile const
288 #endif
289 #define __O volatile
290 #define __IO volatile
292 /* following defines should be used for structure members */
293 #define __IM volatile const
294 #define __OM volatile
295 #define __IOM volatile
297 
301 /*******************************************************************************
302  * Register Abstraction
303  Core Register contain:
304  - Core Register
305  - Core NVIC Register
306  - Core SCB Register
307  - Core SysTick Register
308  - Core Debug Register
309  - Core MPU Register
310  - Core SAU Register
311  - Core FPU Register
312  ******************************************************************************/
313 
328 typedef union
329 {
330  struct
331  {
332  uint32_t _reserved0:16;
333  uint32_t GE:4;
334  uint32_t _reserved1:7;
335  uint32_t Q:1;
336  uint32_t V:1;
337  uint32_t C:1;
338  uint32_t Z:1;
339  uint32_t N:1;
340  } b;
341  uint32_t w;
342 } APSR_Type;
343 
344 /* APSR Register Definitions */
345 #define APSR_N_Pos 31U
346 #define APSR_N_Msk (1UL << APSR_N_Pos)
348 #define APSR_Z_Pos 30U
349 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
351 #define APSR_C_Pos 29U
352 #define APSR_C_Msk (1UL << APSR_C_Pos)
354 #define APSR_V_Pos 28U
355 #define APSR_V_Msk (1UL << APSR_V_Pos)
357 #define APSR_Q_Pos 27U
358 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
360 #define APSR_GE_Pos 16U
361 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
367 typedef union
368 {
369  struct
370  {
371  uint32_t ISR:9;
372  uint32_t _reserved0:23;
373  } b;
374  uint32_t w;
375 } IPSR_Type;
376 
377 /* IPSR Register Definitions */
378 #define IPSR_ISR_Pos 0U
379 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
385 typedef union
386 {
387  struct
388  {
389  uint32_t ISR:9;
390  uint32_t _reserved0:7;
391  uint32_t GE:4;
392  uint32_t _reserved1:4;
393  uint32_t T:1;
394  uint32_t IT:2;
395  uint32_t Q:1;
396  uint32_t V:1;
397  uint32_t C:1;
398  uint32_t Z:1;
399  uint32_t N:1;
400  } b;
401  uint32_t w;
402 } xPSR_Type;
403 
404 /* xPSR Register Definitions */
405 #define xPSR_N_Pos 31U
406 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
408 #define xPSR_Z_Pos 30U
409 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
411 #define xPSR_C_Pos 29U
412 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
414 #define xPSR_V_Pos 28U
415 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
417 #define xPSR_Q_Pos 27U
418 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
420 #define xPSR_IT_Pos 25U
421 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
423 #define xPSR_T_Pos 24U
424 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
426 #define xPSR_GE_Pos 16U
427 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
429 #define xPSR_ISR_Pos 0U
430 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
436 typedef union
437 {
438  struct
439  {
440  uint32_t nPRIV:1;
441  uint32_t SPSEL:1;
442  uint32_t FPCA:1;
443  uint32_t SFPA:1;
444  uint32_t _reserved1:28;
445  } b;
446  uint32_t w;
447 } CONTROL_Type;
448 
449 /* CONTROL Register Definitions */
450 #define CONTROL_SFPA_Pos 3U
451 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
453 #define CONTROL_FPCA_Pos 2U
454 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
456 #define CONTROL_SPSEL_Pos 1U
457 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
459 #define CONTROL_nPRIV_Pos 0U
460 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
462 
475 typedef struct
476 {
477  __IOM uint32_t ISER[16U];
478  uint32_t RESERVED0[16U];
479  __IOM uint32_t ICER[16U];
480  uint32_t RSERVED1[16U];
481  __IOM uint32_t ISPR[16U];
482  uint32_t RESERVED2[16U];
483  __IOM uint32_t ICPR[16U];
484  uint32_t RESERVED3[16U];
485  __IOM uint32_t IABR[16U];
486  uint32_t RESERVED4[16U];
487  __IOM uint32_t ITNS[16U];
488  uint32_t RESERVED5[16U];
489  __IOM uint8_t IPR[496U];
490  uint32_t RESERVED6[580U];
491  __OM uint32_t STIR;
492 } NVIC_Type;
493 
494 /* Software Triggered Interrupt Register Definitions */
495 #define NVIC_STIR_INTID_Pos 0U
496 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
498 
511 typedef struct
512 {
513  __IM uint32_t CPUID;
514  __IOM uint32_t ICSR;
515  __IOM uint32_t VTOR;
516  __IOM uint32_t AIRCR;
517  __IOM uint32_t SCR;
518  __IOM uint32_t CCR;
519  __IOM uint8_t SHPR[12U];
520  __IOM uint32_t SHCSR;
521  __IOM uint32_t CFSR;
522  __IOM uint32_t HFSR;
523  __IOM uint32_t DFSR;
524  __IOM uint32_t MMFAR;
525  __IOM uint32_t BFAR;
526  __IOM uint32_t AFSR;
527  __IM uint32_t ID_PFR[2U];
528  __IM uint32_t ID_DFR;
529  __IM uint32_t ID_ADR;
530  __IM uint32_t ID_MMFR[4U];
531  __IM uint32_t ID_ISAR[6U];
532  __IM uint32_t CLIDR;
533  __IM uint32_t CTR;
534  __IM uint32_t CCSIDR;
535  __IOM uint32_t CSSELR;
536  __IOM uint32_t CPACR;
537  __IOM uint32_t NSACR;
538  uint32_t RESERVED3[92U];
539  __OM uint32_t STIR;
540  __IOM uint32_t RFSR;
541  uint32_t RESERVED4[14U];
542  __IM uint32_t MVFR0;
543  __IM uint32_t MVFR1;
544  __IM uint32_t MVFR2;
545  uint32_t RESERVED5[1U];
546  __OM uint32_t ICIALLU;
547  uint32_t RESERVED6[1U];
548  __OM uint32_t ICIMVAU;
549  __OM uint32_t DCIMVAC;
550  __OM uint32_t DCISW;
551  __OM uint32_t DCCMVAU;
552  __OM uint32_t DCCMVAC;
553  __OM uint32_t DCCSW;
554  __OM uint32_t DCCIMVAC;
555  __OM uint32_t DCCISW;
556  __OM uint32_t BPIALL;
557 } SCB_Type;
558 
559 /* SCB CPUID Register Definitions */
560 #define SCB_CPUID_IMPLEMENTER_Pos 24U
561 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
563 #define SCB_CPUID_VARIANT_Pos 20U
564 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
566 #define SCB_CPUID_ARCHITECTURE_Pos 16U
567 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
569 #define SCB_CPUID_PARTNO_Pos 4U
570 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
572 #define SCB_CPUID_REVISION_Pos 0U
573 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
575 /* SCB Interrupt Control State Register Definitions */
576 #define SCB_ICSR_PENDNMISET_Pos 31U
577 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
579 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
580 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
582 #define SCB_ICSR_PENDNMICLR_Pos 30U
583 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
585 #define SCB_ICSR_PENDSVSET_Pos 28U
586 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
588 #define SCB_ICSR_PENDSVCLR_Pos 27U
589 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
591 #define SCB_ICSR_PENDSTSET_Pos 26U
592 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
594 #define SCB_ICSR_PENDSTCLR_Pos 25U
595 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
597 #define SCB_ICSR_STTNS_Pos 24U
598 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
600 #define SCB_ICSR_ISRPREEMPT_Pos 23U
601 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
603 #define SCB_ICSR_ISRPENDING_Pos 22U
604 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
606 #define SCB_ICSR_VECTPENDING_Pos 12U
607 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
609 #define SCB_ICSR_RETTOBASE_Pos 11U
610 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
612 #define SCB_ICSR_VECTACTIVE_Pos 0U
613 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
615 /* SCB Vector Table Offset Register Definitions */
616 #define SCB_VTOR_TBLOFF_Pos 7U
617 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
619 /* SCB Application Interrupt and Reset Control Register Definitions */
620 #define SCB_AIRCR_VECTKEY_Pos 16U
621 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
623 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
624 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
626 #define SCB_AIRCR_ENDIANESS_Pos 15U
627 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
629 #define SCB_AIRCR_PRIS_Pos 14U
630 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
632 #define SCB_AIRCR_BFHFNMINS_Pos 13U
633 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
635 #define SCB_AIRCR_PRIGROUP_Pos 8U
636 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
638 #define SCB_AIRCR_IESB_Pos 5U
639 #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos)
641 #define SCB_AIRCR_DIT_Pos 4U
642 #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos)
644 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
645 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
647 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
648 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
650 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
651 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
653 /* SCB System Control Register Definitions */
654 #define SCB_SCR_SEVONPEND_Pos 4U
655 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
657 #define SCB_SCR_SLEEPDEEPS_Pos 3U
658 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
660 #define SCB_SCR_SLEEPDEEP_Pos 2U
661 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
663 #define SCB_SCR_SLEEPONEXIT_Pos 1U
664 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
666 /* SCB Configuration Control Register Definitions */
667 #define SCB_CCR_TRD_Pos 20U
668 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos)
670 #define SCB_CCR_LOB_Pos 19U
671 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos)
673 #define SCB_CCR_BP_Pos 18U
674 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
676 #define SCB_CCR_IC_Pos 17U
677 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
679 #define SCB_CCR_DC_Pos 16U
680 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
682 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
683 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
685 #define SCB_CCR_BFHFNMIGN_Pos 8U
686 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
688 #define SCB_CCR_DIV_0_TRP_Pos 4U
689 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
691 #define SCB_CCR_UNALIGN_TRP_Pos 3U
692 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
694 #define SCB_CCR_USERSETMPEND_Pos 1U
695 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
697 /* SCB System Handler Control and State Register Definitions */
698 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
699 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
701 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
702 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
704 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
705 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
707 #define SCB_SHCSR_USGFAULTENA_Pos 18U
708 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
710 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
711 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
713 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
714 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
716 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
717 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
719 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
720 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
722 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
723 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
725 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
726 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
728 #define SCB_SHCSR_SYSTICKACT_Pos 11U
729 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
731 #define SCB_SHCSR_PENDSVACT_Pos 10U
732 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
734 #define SCB_SHCSR_MONITORACT_Pos 8U
735 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
737 #define SCB_SHCSR_SVCALLACT_Pos 7U
738 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
740 #define SCB_SHCSR_NMIACT_Pos 5U
741 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
743 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
744 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
746 #define SCB_SHCSR_USGFAULTACT_Pos 3U
747 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
749 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
750 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
752 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
753 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
755 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
756 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
758 /* SCB Configurable Fault Status Register Definitions */
759 #define SCB_CFSR_USGFAULTSR_Pos 16U
760 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
762 #define SCB_CFSR_BUSFAULTSR_Pos 8U
763 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
765 #define SCB_CFSR_MEMFAULTSR_Pos 0U
766 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
768 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
769 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
770 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
772 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
773 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
775 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
776 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
778 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
779 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
781 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
782 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
784 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
785 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
787 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
788 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
789 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
791 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
792 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
794 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
795 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
797 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
798 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
800 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
801 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
803 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
804 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
806 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
807 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
809 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
810 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
811 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
813 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
814 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
816 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
817 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
819 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
820 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
822 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
823 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
825 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
826 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
828 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
829 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
831 /* SCB Hard Fault Status Register Definitions */
832 #define SCB_HFSR_DEBUGEVT_Pos 31U
833 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
835 #define SCB_HFSR_FORCED_Pos 30U
836 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
838 #define SCB_HFSR_VECTTBL_Pos 1U
839 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
841 /* SCB Debug Fault Status Register Definitions */
842 #define SCB_DFSR_PMU_Pos 5U
843 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos)
845 #define SCB_DFSR_EXTERNAL_Pos 4U
846 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
848 #define SCB_DFSR_VCATCH_Pos 3U
849 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
851 #define SCB_DFSR_DWTTRAP_Pos 2U
852 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
854 #define SCB_DFSR_BKPT_Pos 1U
855 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
857 #define SCB_DFSR_HALTED_Pos 0U
858 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
860 /* SCB Non-Secure Access Control Register Definitions */
861 #define SCB_NSACR_CP11_Pos 11U
862 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
864 #define SCB_NSACR_CP10_Pos 10U
865 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
867 #define SCB_NSACR_CP7_Pos 7U
868 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos)
870 #define SCB_NSACR_CP6_Pos 6U
871 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos)
873 #define SCB_NSACR_CP5_Pos 5U
874 #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos)
876 #define SCB_NSACR_CP4_Pos 4U
877 #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos)
879 #define SCB_NSACR_CP3_Pos 3U
880 #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos)
882 #define SCB_NSACR_CP2_Pos 2U
883 #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos)
885 #define SCB_NSACR_CP1_Pos 1U
886 #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos)
888 #define SCB_NSACR_CP0_Pos 0U
889 #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/)
891 /* SCB Debug Feature Register 0 Definitions */
892 #define SCB_ID_DFR_UDE_Pos 28U
893 #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos)
895 #define SCB_ID_DFR_MProfDbg_Pos 20U
896 #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
898 /* SCB Cache Level ID Register Definitions */
899 #define SCB_CLIDR_LOUU_Pos 27U
900 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
902 #define SCB_CLIDR_LOC_Pos 24U
903 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
905 /* SCB Cache Type Register Definitions */
906 #define SCB_CTR_FORMAT_Pos 29U
907 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
909 #define SCB_CTR_CWG_Pos 24U
910 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
912 #define SCB_CTR_ERG_Pos 20U
913 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
915 #define SCB_CTR_DMINLINE_Pos 16U
916 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
918 #define SCB_CTR_IMINLINE_Pos 0U
919 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
921 /* SCB Cache Size ID Register Definitions */
922 #define SCB_CCSIDR_WT_Pos 31U
923 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
925 #define SCB_CCSIDR_WB_Pos 30U
926 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
928 #define SCB_CCSIDR_RA_Pos 29U
929 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
931 #define SCB_CCSIDR_WA_Pos 28U
932 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
934 #define SCB_CCSIDR_NUMSETS_Pos 13U
935 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
937 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
938 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
940 #define SCB_CCSIDR_LINESIZE_Pos 0U
941 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
943 /* SCB Cache Size Selection Register Definitions */
944 #define SCB_CSSELR_LEVEL_Pos 1U
945 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
947 #define SCB_CSSELR_IND_Pos 0U
948 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
950 /* SCB Software Triggered Interrupt Register Definitions */
951 #define SCB_STIR_INTID_Pos 0U
952 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
954 /* SCB RAS Fault Status Register Definitions */
955 #define SCB_RFSR_V_Pos 31U
956 #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos)
958 #define SCB_RFSR_IS_Pos 16U
959 #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos)
961 #define SCB_RFSR_UET_Pos 0U
962 #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/)
964 /* SCB D-Cache Invalidate by Set-way Register Definitions */
965 #define SCB_DCISW_WAY_Pos 30U
966 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
968 #define SCB_DCISW_SET_Pos 5U
969 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
971 /* SCB D-Cache Clean by Set-way Register Definitions */
972 #define SCB_DCCSW_WAY_Pos 30U
973 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
975 #define SCB_DCCSW_SET_Pos 5U
976 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
978 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
979 #define SCB_DCCISW_WAY_Pos 30U
980 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
982 #define SCB_DCCISW_SET_Pos 5U
983 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
985 
998 typedef struct
999 {
1000  uint32_t RESERVED0[1U];
1001  __IM uint32_t ICTR;
1002  __IOM uint32_t ACTLR;
1003  __IOM uint32_t CPPWR;
1004 } SCnSCB_Type;
1005 
1006 /* Interrupt Controller Type Register Definitions */
1007 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
1008 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
1010 
1023 typedef struct
1024 {
1025  __IOM uint32_t CTRL;
1026  __IOM uint32_t LOAD;
1027  __IOM uint32_t VAL;
1028  __IM uint32_t CALIB;
1029 } SysTick_Type;
1030 
1031 /* SysTick Control / Status Register Definitions */
1032 #define SysTick_CTRL_COUNTFLAG_Pos 16U
1033 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1035 #define SysTick_CTRL_CLKSOURCE_Pos 2U
1036 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1038 #define SysTick_CTRL_TICKINT_Pos 1U
1039 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1041 #define SysTick_CTRL_ENABLE_Pos 0U
1042 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1044 /* SysTick Reload Register Definitions */
1045 #define SysTick_LOAD_RELOAD_Pos 0U
1046 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1048 /* SysTick Current Register Definitions */
1049 #define SysTick_VAL_CURRENT_Pos 0U
1050 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1052 /* SysTick Calibration Register Definitions */
1053 #define SysTick_CALIB_NOREF_Pos 31U
1054 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1056 #define SysTick_CALIB_SKEW_Pos 30U
1057 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1059 #define SysTick_CALIB_TENMS_Pos 0U
1060 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1062 
1075 typedef struct
1076 {
1077  __OM union
1078  {
1079  __OM uint8_t u8;
1080  __OM uint16_t u16;
1081  __OM uint32_t u32;
1082  } PORT [32U];
1083  uint32_t RESERVED0[864U];
1084  __IOM uint32_t TER;
1085  uint32_t RESERVED1[15U];
1086  __IOM uint32_t TPR;
1087  uint32_t RESERVED2[15U];
1088  __IOM uint32_t TCR;
1089  uint32_t RESERVED3[32U];
1090  uint32_t RESERVED4[43U];
1091  __OM uint32_t LAR;
1092  __IM uint32_t LSR;
1093  uint32_t RESERVED5[1U];
1094  __IM uint32_t DEVARCH;
1095  uint32_t RESERVED6[3U];
1096  __IM uint32_t DEVTYPE;
1097  __IM uint32_t PID4;
1098  __IM uint32_t PID5;
1099  __IM uint32_t PID6;
1100  __IM uint32_t PID7;
1101  __IM uint32_t PID0;
1102  __IM uint32_t PID1;
1103  __IM uint32_t PID2;
1104  __IM uint32_t PID3;
1105  __IM uint32_t CID0;
1106  __IM uint32_t CID1;
1107  __IM uint32_t CID2;
1108  __IM uint32_t CID3;
1109 } ITM_Type;
1110 
1111 /* ITM Stimulus Port Register Definitions */
1112 #define ITM_STIM_DISABLED_Pos 1U
1113 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1115 #define ITM_STIM_FIFOREADY_Pos 0U
1116 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1118 /* ITM Trace Privilege Register Definitions */
1119 #define ITM_TPR_PRIVMASK_Pos 0U
1120 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1122 /* ITM Trace Control Register Definitions */
1123 #define ITM_TCR_BUSY_Pos 23U
1124 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1126 #define ITM_TCR_TRACEBUSID_Pos 16U
1127 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1129 #define ITM_TCR_GTSFREQ_Pos 10U
1130 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1132 #define ITM_TCR_TSPRESCALE_Pos 8U
1133 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1135 #define ITM_TCR_STALLENA_Pos 5U
1136 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1138 #define ITM_TCR_SWOENA_Pos 4U
1139 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1141 #define ITM_TCR_DWTENA_Pos 3U
1142 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1144 #define ITM_TCR_SYNCENA_Pos 2U
1145 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1147 #define ITM_TCR_TSENA_Pos 1U
1148 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1150 #define ITM_TCR_ITMENA_Pos 0U
1151 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1153 /* ITM Lock Status Register Definitions */
1154 #define ITM_LSR_ByteAcc_Pos 2U
1155 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1157 #define ITM_LSR_Access_Pos 1U
1158 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1160 #define ITM_LSR_Present_Pos 0U
1161 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1163  /* end of group CMSIS_ITM */
1164 
1165 
1176 typedef struct
1177 {
1178  __IOM uint32_t CTRL;
1179  __IOM uint32_t CYCCNT;
1180  __IOM uint32_t CPICNT;
1181  __IOM uint32_t EXCCNT;
1182  __IOM uint32_t SLEEPCNT;
1183  __IOM uint32_t LSUCNT;
1184  __IOM uint32_t FOLDCNT;
1185  __IM uint32_t PCSR;
1186  __IOM uint32_t COMP0;
1187  uint32_t RESERVED1[1U];
1188  __IOM uint32_t FUNCTION0;
1189  uint32_t RESERVED2[1U];
1190  __IOM uint32_t COMP1;
1191  uint32_t RESERVED3[1U];
1192  __IOM uint32_t FUNCTION1;
1193  uint32_t RESERVED4[1U];
1194  __IOM uint32_t COMP2;
1195  uint32_t RESERVED5[1U];
1196  __IOM uint32_t FUNCTION2;
1197  uint32_t RESERVED6[1U];
1198  __IOM uint32_t COMP3;
1199  uint32_t RESERVED7[1U];
1200  __IOM uint32_t FUNCTION3;
1201  uint32_t RESERVED8[1U];
1202  __IOM uint32_t COMP4;
1203  uint32_t RESERVED9[1U];
1204  __IOM uint32_t FUNCTION4;
1205  uint32_t RESERVED10[1U];
1206  __IOM uint32_t COMP5;
1207  uint32_t RESERVED11[1U];
1208  __IOM uint32_t FUNCTION5;
1209  uint32_t RESERVED12[1U];
1210  __IOM uint32_t COMP6;
1211  uint32_t RESERVED13[1U];
1212  __IOM uint32_t FUNCTION6;
1213  uint32_t RESERVED14[1U];
1214  __IOM uint32_t COMP7;
1215  uint32_t RESERVED15[1U];
1216  __IOM uint32_t FUNCTION7;
1217  uint32_t RESERVED16[1U];
1218  __IOM uint32_t COMP8;
1219  uint32_t RESERVED17[1U];
1220  __IOM uint32_t FUNCTION8;
1221  uint32_t RESERVED18[1U];
1222  __IOM uint32_t COMP9;
1223  uint32_t RESERVED19[1U];
1224  __IOM uint32_t FUNCTION9;
1225  uint32_t RESERVED20[1U];
1226  __IOM uint32_t COMP10;
1227  uint32_t RESERVED21[1U];
1228  __IOM uint32_t FUNCTION10;
1229  uint32_t RESERVED22[1U];
1230  __IOM uint32_t COMP11;
1231  uint32_t RESERVED23[1U];
1232  __IOM uint32_t FUNCTION11;
1233  uint32_t RESERVED24[1U];
1234  __IOM uint32_t COMP12;
1235  uint32_t RESERVED25[1U];
1236  __IOM uint32_t FUNCTION12;
1237  uint32_t RESERVED26[1U];
1238  __IOM uint32_t COMP13;
1239  uint32_t RESERVED27[1U];
1240  __IOM uint32_t FUNCTION13;
1241  uint32_t RESERVED28[1U];
1242  __IOM uint32_t COMP14;
1243  uint32_t RESERVED29[1U];
1244  __IOM uint32_t FUNCTION14;
1245  uint32_t RESERVED30[1U];
1246  __IOM uint32_t COMP15;
1247  uint32_t RESERVED31[1U];
1248  __IOM uint32_t FUNCTION15;
1249  uint32_t RESERVED32[934U];
1250  __IM uint32_t LSR;
1251  uint32_t RESERVED33[1U];
1252  __IM uint32_t DEVARCH;
1253 } DWT_Type;
1254 
1255 /* DWT Control Register Definitions */
1256 #define DWT_CTRL_NUMCOMP_Pos 28U
1257 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1259 #define DWT_CTRL_NOTRCPKT_Pos 27U
1260 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1262 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1263 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1265 #define DWT_CTRL_NOCYCCNT_Pos 25U
1266 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1268 #define DWT_CTRL_NOPRFCNT_Pos 24U
1269 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1271 #define DWT_CTRL_CYCDISS_Pos 23U
1272 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1274 #define DWT_CTRL_CYCEVTENA_Pos 22U
1275 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1277 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1278 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1280 #define DWT_CTRL_LSUEVTENA_Pos 20U
1281 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1283 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1284 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1286 #define DWT_CTRL_EXCEVTENA_Pos 18U
1287 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1289 #define DWT_CTRL_CPIEVTENA_Pos 17U
1290 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1292 #define DWT_CTRL_EXCTRCENA_Pos 16U
1293 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1295 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1296 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1298 #define DWT_CTRL_SYNCTAP_Pos 10U
1299 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1301 #define DWT_CTRL_CYCTAP_Pos 9U
1302 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1304 #define DWT_CTRL_POSTINIT_Pos 5U
1305 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1307 #define DWT_CTRL_POSTPRESET_Pos 1U
1308 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1310 #define DWT_CTRL_CYCCNTENA_Pos 0U
1311 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1313 /* DWT CPI Count Register Definitions */
1314 #define DWT_CPICNT_CPICNT_Pos 0U
1315 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1317 /* DWT Exception Overhead Count Register Definitions */
1318 #define DWT_EXCCNT_EXCCNT_Pos 0U
1319 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1321 /* DWT Sleep Count Register Definitions */
1322 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1323 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1325 /* DWT LSU Count Register Definitions */
1326 #define DWT_LSUCNT_LSUCNT_Pos 0U
1327 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1329 /* DWT Folded-instruction Count Register Definitions */
1330 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1331 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1333 /* DWT Comparator Function Register Definitions */
1334 #define DWT_FUNCTION_ID_Pos 27U
1335 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1337 #define DWT_FUNCTION_MATCHED_Pos 24U
1338 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1340 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1341 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1343 #define DWT_FUNCTION_ACTION_Pos 4U
1344 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1346 #define DWT_FUNCTION_MATCH_Pos 0U
1347 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1349  /* end of group CMSIS_DWT */
1350 
1351 
1362 typedef struct
1363 {
1364  __IM uint32_t SSPSR;
1365  __IOM uint32_t CSPSR;
1366  uint32_t RESERVED0[2U];
1367  __IOM uint32_t ACPR;
1368  uint32_t RESERVED1[55U];
1369  __IOM uint32_t SPPR;
1370  uint32_t RESERVED2[131U];
1371  __IM uint32_t FFSR;
1372  __IOM uint32_t FFCR;
1373  __IOM uint32_t PSCR;
1374  uint32_t RESERVED3[809U];
1375  __OM uint32_t LAR;
1376  __IM uint32_t LSR;
1377  uint32_t RESERVED4[4U];
1378  __IM uint32_t TYPE;
1379  __IM uint32_t DEVTYPE;
1380 } TPI_Type;
1381 
1382 /* TPI Asynchronous Clock Prescaler Register Definitions */
1383 #define TPI_ACPR_SWOSCALER_Pos 0U
1384 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
1386 /* TPI Selected Pin Protocol Register Definitions */
1387 #define TPI_SPPR_TXMODE_Pos 0U
1388 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1390 /* TPI Formatter and Flush Status Register Definitions */
1391 #define TPI_FFSR_FtNonStop_Pos 3U
1392 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1394 #define TPI_FFSR_TCPresent_Pos 2U
1395 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1397 #define TPI_FFSR_FtStopped_Pos 1U
1398 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1400 #define TPI_FFSR_FlInProg_Pos 0U
1401 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1403 /* TPI Formatter and Flush Control Register Definitions */
1404 #define TPI_FFCR_TrigIn_Pos 8U
1405 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1407 #define TPI_FFCR_FOnMan_Pos 6U
1408 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1410 #define TPI_FFCR_EnFmt_Pos 0U
1411 #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
1413 /* TPI Periodic Synchronization Control Register Definitions */
1414 #define TPI_PSCR_PSCount_Pos 0U
1415 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
1417 /* TPI Software Lock Status Register Definitions */
1418 #define TPI_LSR_nTT_Pos 1U
1419 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
1421 #define TPI_LSR_SLK_Pos 1U
1422 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
1424 #define TPI_LSR_SLI_Pos 0U
1425 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
1427 /* TPI DEVID Register Definitions */
1428 #define TPI_DEVID_NRZVALID_Pos 11U
1429 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1431 #define TPI_DEVID_MANCVALID_Pos 10U
1432 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1434 #define TPI_DEVID_PTINVALID_Pos 9U
1435 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1437 #define TPI_DEVID_FIFOSZ_Pos 6U
1438 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1440 /* TPI DEVTYPE Register Definitions */
1441 #define TPI_DEVTYPE_SubType_Pos 4U
1442 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1444 #define TPI_DEVTYPE_MajorType_Pos 0U
1445 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1447  /* end of group CMSIS_TPI */
1448 
1449 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
1450 
1460 typedef struct
1461 {
1462  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];
1463 #if __PMU_NUM_EVENTCNT<31
1464  uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
1465 #endif
1466  __IOM uint32_t CCNTR;
1467  uint32_t RESERVED1[224];
1468  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];
1469 #if __PMU_NUM_EVENTCNT<31
1470  uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
1471 #endif
1472  __IOM uint32_t CCFILTR;
1473  uint32_t RESERVED3[480];
1474  __IOM uint32_t CNTENSET;
1475  uint32_t RESERVED4[7];
1476  __IOM uint32_t CNTENCLR;
1477  uint32_t RESERVED5[7];
1478  __IOM uint32_t INTENSET;
1479  uint32_t RESERVED6[7];
1480  __IOM uint32_t INTENCLR;
1481  uint32_t RESERVED7[7];
1482  __IOM uint32_t OVSCLR;
1483  uint32_t RESERVED8[7];
1484  __IOM uint32_t SWINC;
1485  uint32_t RESERVED9[7];
1486  __IOM uint32_t OVSSET;
1487  uint32_t RESERVED10[79];
1488  __IOM uint32_t TYPE;
1489  __IOM uint32_t CTRL;
1490  uint32_t RESERVED11[108];
1491  __IOM uint32_t AUTHSTATUS;
1492  __IOM uint32_t DEVARCH;
1493  uint32_t RESERVED12[4];
1494  __IOM uint32_t DEVTYPE;
1495  __IOM uint32_t PIDR4;
1496  uint32_t RESERVED13[3];
1497  __IOM uint32_t PIDR0;
1498  __IOM uint32_t PIDR1;
1499  __IOM uint32_t PIDR2;
1500  __IOM uint32_t PIDR3;
1501  uint32_t RESERVED14[3];
1502  __IOM uint32_t CIDR0;
1503  __IOM uint32_t CIDR1;
1504  __IOM uint32_t CIDR2;
1505  __IOM uint32_t CIDR3;
1506 } PMU_Type;
1507 
1510 #define PMU_EVCNTR_CNT_Pos 0U
1511 #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/)
1515 #define PMU_EVTYPER_EVENTTOCNT_Pos 0U
1516 #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/)
1520 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U
1521 #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/)
1523 #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U
1524 #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos)
1526 #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U
1527 #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos)
1529 #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U
1530 #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos)
1532 #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U
1533 #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos)
1535 #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U
1536 #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos)
1538 #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U
1539 #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos)
1541 #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U
1542 #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos)
1544 #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U
1545 #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos)
1547 #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U
1548 #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos)
1550 #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U
1551 #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos)
1553 #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U
1554 #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos)
1556 #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U
1557 #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos)
1559 #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U
1560 #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos)
1562 #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U
1563 #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos)
1565 #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U
1566 #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos)
1568 #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U
1569 #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos)
1571 #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U
1572 #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos)
1574 #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U
1575 #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos)
1577 #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U
1578 #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos)
1580 #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U
1581 #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos)
1583 #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U
1584 #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos)
1586 #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U
1587 #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos)
1589 #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U
1590 #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos)
1592 #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U
1593 #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos)
1595 #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U
1596 #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos)
1598 #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U
1599 #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos)
1601 #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U
1602 #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos)
1604 #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U
1605 #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos)
1607 #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U
1608 #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos)
1610 #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U
1611 #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos)
1613 #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U
1614 #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos)
1618 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U
1619 #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/)
1621 #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U
1622 #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos)
1624 #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U
1625 #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos)
1627 #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U
1628 #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos)
1630 #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U
1631 #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos)
1633 #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U
1634 #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos)
1636 #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U
1637 #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos)
1639 #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U
1640 #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos)
1642 #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U
1643 #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos)
1645 #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U
1646 #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos)
1648 #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U
1649 #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos)
1651 #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U
1652 #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos)
1654 #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U
1655 #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos)
1657 #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U
1658 #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos)
1660 #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U
1661 #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos)
1663 #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U
1664 #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos)
1666 #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U
1667 #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos)
1669 #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U
1670 #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos)
1672 #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U
1673 #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos)
1675 #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U
1676 #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos)
1678 #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U
1679 #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos)
1681 #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U
1682 #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos)
1684 #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U
1685 #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos)
1687 #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U
1688 #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos)
1690 #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U
1691 #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos)
1693 #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U
1694 #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos)
1696 #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U
1697 #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos)
1699 #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U
1700 #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos)
1702 #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U
1703 #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos)
1705 #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U
1706 #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos)
1708 #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U
1709 #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos)
1711 #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U
1712 #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos)
1716 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U
1717 #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/)
1719 #define PMU_INTENSET_CNT1_ENABLE_Pos 1U
1720 #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos)
1722 #define PMU_INTENSET_CNT2_ENABLE_Pos 2U
1723 #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos)
1725 #define PMU_INTENSET_CNT3_ENABLE_Pos 3U
1726 #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos)
1728 #define PMU_INTENSET_CNT4_ENABLE_Pos 4U
1729 #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos)
1731 #define PMU_INTENSET_CNT5_ENABLE_Pos 5U
1732 #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos)
1734 #define PMU_INTENSET_CNT6_ENABLE_Pos 6U
1735 #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos)
1737 #define PMU_INTENSET_CNT7_ENABLE_Pos 7U
1738 #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos)
1740 #define PMU_INTENSET_CNT8_ENABLE_Pos 8U
1741 #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos)
1743 #define PMU_INTENSET_CNT9_ENABLE_Pos 9U
1744 #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos)
1746 #define PMU_INTENSET_CNT10_ENABLE_Pos 10U
1747 #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos)
1749 #define PMU_INTENSET_CNT11_ENABLE_Pos 11U
1750 #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos)
1752 #define PMU_INTENSET_CNT12_ENABLE_Pos 12U
1753 #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos)
1755 #define PMU_INTENSET_CNT13_ENABLE_Pos 13U
1756 #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos)
1758 #define PMU_INTENSET_CNT14_ENABLE_Pos 14U
1759 #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos)
1761 #define PMU_INTENSET_CNT15_ENABLE_Pos 15U
1762 #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos)
1764 #define PMU_INTENSET_CNT16_ENABLE_Pos 16U
1765 #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos)
1767 #define PMU_INTENSET_CNT17_ENABLE_Pos 17U
1768 #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos)
1770 #define PMU_INTENSET_CNT18_ENABLE_Pos 18U
1771 #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos)
1773 #define PMU_INTENSET_CNT19_ENABLE_Pos 19U
1774 #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos)
1776 #define PMU_INTENSET_CNT20_ENABLE_Pos 20U
1777 #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos)
1779 #define PMU_INTENSET_CNT21_ENABLE_Pos 21U
1780 #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos)
1782 #define PMU_INTENSET_CNT22_ENABLE_Pos 22U
1783 #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos)
1785 #define PMU_INTENSET_CNT23_ENABLE_Pos 23U
1786 #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos)
1788 #define PMU_INTENSET_CNT24_ENABLE_Pos 24U
1789 #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos)
1791 #define PMU_INTENSET_CNT25_ENABLE_Pos 25U
1792 #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos)
1794 #define PMU_INTENSET_CNT26_ENABLE_Pos 26U
1795 #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos)
1797 #define PMU_INTENSET_CNT27_ENABLE_Pos 27U
1798 #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos)
1800 #define PMU_INTENSET_CNT28_ENABLE_Pos 28U
1801 #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos)
1803 #define PMU_INTENSET_CNT29_ENABLE_Pos 29U
1804 #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos)
1806 #define PMU_INTENSET_CNT30_ENABLE_Pos 30U
1807 #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos)
1809 #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U
1810 #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos)
1814 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U
1815 #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/)
1817 #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U
1818 #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos)
1820 #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U
1821 #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos)
1823 #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U
1824 #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos)
1826 #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U
1827 #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos)
1829 #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U
1830 #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos)
1832 #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U
1833 #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos)
1835 #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U
1836 #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos)
1838 #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U
1839 #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos)
1841 #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U
1842 #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos)
1844 #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U
1845 #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos)
1847 #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U
1848 #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos)
1850 #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U
1851 #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos)
1853 #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U
1854 #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos)
1856 #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U
1857 #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos)
1859 #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U
1860 #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos)
1862 #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U
1863 #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos)
1865 #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U
1866 #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos)
1868 #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U
1869 #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos)
1871 #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U
1872 #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos)
1874 #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U
1875 #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos)
1877 #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U
1878 #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos)
1880 #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U
1881 #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos)
1883 #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U
1884 #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos)
1886 #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U
1887 #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos)
1889 #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U
1890 #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos)
1892 #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U
1893 #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos)
1895 #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U
1896 #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos)
1898 #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U
1899 #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos)
1901 #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U
1902 #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos)
1904 #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U
1905 #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos)
1907 #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U
1908 #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos)
1912 #define PMU_OVSSET_CNT0_STATUS_Pos 0U
1913 #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/)
1915 #define PMU_OVSSET_CNT1_STATUS_Pos 1U
1916 #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos)
1918 #define PMU_OVSSET_CNT2_STATUS_Pos 2U
1919 #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos)
1921 #define PMU_OVSSET_CNT3_STATUS_Pos 3U
1922 #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos)
1924 #define PMU_OVSSET_CNT4_STATUS_Pos 4U
1925 #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos)
1927 #define PMU_OVSSET_CNT5_STATUS_Pos 5U
1928 #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos)
1930 #define PMU_OVSSET_CNT6_STATUS_Pos 6U
1931 #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos)
1933 #define PMU_OVSSET_CNT7_STATUS_Pos 7U
1934 #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos)
1936 #define PMU_OVSSET_CNT8_STATUS_Pos 8U
1937 #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos)
1939 #define PMU_OVSSET_CNT9_STATUS_Pos 9U
1940 #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos)
1942 #define PMU_OVSSET_CNT10_STATUS_Pos 10U
1943 #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos)
1945 #define PMU_OVSSET_CNT11_STATUS_Pos 11U
1946 #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos)
1948 #define PMU_OVSSET_CNT12_STATUS_Pos 12U
1949 #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos)
1951 #define PMU_OVSSET_CNT13_STATUS_Pos 13U
1952 #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos)
1954 #define PMU_OVSSET_CNT14_STATUS_Pos 14U
1955 #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos)
1957 #define PMU_OVSSET_CNT15_STATUS_Pos 15U
1958 #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos)
1960 #define PMU_OVSSET_CNT16_STATUS_Pos 16U
1961 #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos)
1963 #define PMU_OVSSET_CNT17_STATUS_Pos 17U
1964 #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos)
1966 #define PMU_OVSSET_CNT18_STATUS_Pos 18U
1967 #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos)
1969 #define PMU_OVSSET_CNT19_STATUS_Pos 19U
1970 #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos)
1972 #define PMU_OVSSET_CNT20_STATUS_Pos 20U
1973 #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos)
1975 #define PMU_OVSSET_CNT21_STATUS_Pos 21U
1976 #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos)
1978 #define PMU_OVSSET_CNT22_STATUS_Pos 22U
1979 #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos)
1981 #define PMU_OVSSET_CNT23_STATUS_Pos 23U
1982 #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos)
1984 #define PMU_OVSSET_CNT24_STATUS_Pos 24U
1985 #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos)
1987 #define PMU_OVSSET_CNT25_STATUS_Pos 25U
1988 #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos)
1990 #define PMU_OVSSET_CNT26_STATUS_Pos 26U
1991 #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos)
1993 #define PMU_OVSSET_CNT27_STATUS_Pos 27U
1994 #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos)
1996 #define PMU_OVSSET_CNT28_STATUS_Pos 28U
1997 #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos)
1999 #define PMU_OVSSET_CNT29_STATUS_Pos 29U
2000 #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos)
2002 #define PMU_OVSSET_CNT30_STATUS_Pos 30U
2003 #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos)
2005 #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U
2006 #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos)
2010 #define PMU_OVSCLR_CNT0_STATUS_Pos 0U
2011 #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/)
2013 #define PMU_OVSCLR_CNT1_STATUS_Pos 1U
2014 #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos)
2016 #define PMU_OVSCLR_CNT2_STATUS_Pos 2U
2017 #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos)
2019 #define PMU_OVSCLR_CNT3_STATUS_Pos 3U
2020 #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos)
2022 #define PMU_OVSCLR_CNT4_STATUS_Pos 4U
2023 #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos)
2025 #define PMU_OVSCLR_CNT5_STATUS_Pos 5U
2026 #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos)
2028 #define PMU_OVSCLR_CNT6_STATUS_Pos 6U
2029 #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos)
2031 #define PMU_OVSCLR_CNT7_STATUS_Pos 7U
2032 #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos)
2034 #define PMU_OVSCLR_CNT8_STATUS_Pos 8U
2035 #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos)
2037 #define PMU_OVSCLR_CNT9_STATUS_Pos 9U
2038 #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos)
2040 #define PMU_OVSCLR_CNT10_STATUS_Pos 10U
2041 #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos)
2043 #define PMU_OVSCLR_CNT11_STATUS_Pos 11U
2044 #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos)
2046 #define PMU_OVSCLR_CNT12_STATUS_Pos 12U
2047 #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos)
2049 #define PMU_OVSCLR_CNT13_STATUS_Pos 13U
2050 #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos)
2052 #define PMU_OVSCLR_CNT14_STATUS_Pos 14U
2053 #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos)
2055 #define PMU_OVSCLR_CNT15_STATUS_Pos 15U
2056 #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos)
2058 #define PMU_OVSCLR_CNT16_STATUS_Pos 16U
2059 #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos)
2061 #define PMU_OVSCLR_CNT17_STATUS_Pos 17U
2062 #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos)
2064 #define PMU_OVSCLR_CNT18_STATUS_Pos 18U
2065 #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos)
2067 #define PMU_OVSCLR_CNT19_STATUS_Pos 19U
2068 #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos)
2070 #define PMU_OVSCLR_CNT20_STATUS_Pos 20U
2071 #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos)
2073 #define PMU_OVSCLR_CNT21_STATUS_Pos 21U
2074 #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos)
2076 #define PMU_OVSCLR_CNT22_STATUS_Pos 22U
2077 #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos)
2079 #define PMU_OVSCLR_CNT23_STATUS_Pos 23U
2080 #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos)
2082 #define PMU_OVSCLR_CNT24_STATUS_Pos 24U
2083 #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos)
2085 #define PMU_OVSCLR_CNT25_STATUS_Pos 25U
2086 #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos)
2088 #define PMU_OVSCLR_CNT26_STATUS_Pos 26U
2089 #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos)
2091 #define PMU_OVSCLR_CNT27_STATUS_Pos 27U
2092 #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos)
2094 #define PMU_OVSCLR_CNT28_STATUS_Pos 28U
2095 #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos)
2097 #define PMU_OVSCLR_CNT29_STATUS_Pos 29U
2098 #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos)
2100 #define PMU_OVSCLR_CNT30_STATUS_Pos 30U
2101 #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos)
2103 #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U
2104 #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos)
2108 #define PMU_SWINC_CNT0_Pos 0U
2109 #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */)
2111 #define PMU_SWINC_CNT1_Pos 1U
2112 #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos)
2114 #define PMU_SWINC_CNT2_Pos 2U
2115 #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos)
2117 #define PMU_SWINC_CNT3_Pos 3U
2118 #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos)
2120 #define PMU_SWINC_CNT4_Pos 4U
2121 #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos)
2123 #define PMU_SWINC_CNT5_Pos 5U
2124 #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos)
2126 #define PMU_SWINC_CNT6_Pos 6U
2127 #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos)
2129 #define PMU_SWINC_CNT7_Pos 7U
2130 #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos)
2132 #define PMU_SWINC_CNT8_Pos 8U
2133 #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos)
2135 #define PMU_SWINC_CNT9_Pos 9U
2136 #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos)
2138 #define PMU_SWINC_CNT10_Pos 10U
2139 #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos)
2141 #define PMU_SWINC_CNT11_Pos 11U
2142 #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos)
2144 #define PMU_SWINC_CNT12_Pos 12U
2145 #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos)
2147 #define PMU_SWINC_CNT13_Pos 13U
2148 #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos)
2150 #define PMU_SWINC_CNT14_Pos 14U
2151 #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos)
2153 #define PMU_SWINC_CNT15_Pos 15U
2154 #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos)
2156 #define PMU_SWINC_CNT16_Pos 16U
2157 #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos)
2159 #define PMU_SWINC_CNT17_Pos 17U
2160 #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos)
2162 #define PMU_SWINC_CNT18_Pos 18U
2163 #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos)
2165 #define PMU_SWINC_CNT19_Pos 19U
2166 #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos)
2168 #define PMU_SWINC_CNT20_Pos 20U
2169 #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos)
2171 #define PMU_SWINC_CNT21_Pos 21U
2172 #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos)
2174 #define PMU_SWINC_CNT22_Pos 22U
2175 #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos)
2177 #define PMU_SWINC_CNT23_Pos 23U
2178 #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos)
2180 #define PMU_SWINC_CNT24_Pos 24U
2181 #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos)
2183 #define PMU_SWINC_CNT25_Pos 25U
2184 #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos)
2186 #define PMU_SWINC_CNT26_Pos 26U
2187 #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos)
2189 #define PMU_SWINC_CNT27_Pos 27U
2190 #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos)
2192 #define PMU_SWINC_CNT28_Pos 28U
2193 #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos)
2195 #define PMU_SWINC_CNT29_Pos 29U
2196 #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos)
2198 #define PMU_SWINC_CNT30_Pos 30U
2199 #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos)
2203 #define PMU_CTRL_ENABLE_Pos 0U
2204 #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/)
2206 #define PMU_CTRL_EVENTCNT_RESET_Pos 1U
2207 #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos)
2209 #define PMU_CTRL_CYCCNT_RESET_Pos 2U
2210 #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos)
2212 #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U
2213 #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos)
2215 #define PMU_CTRL_FRZ_ON_OV_Pos 9U
2216 #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos)
2218 #define PMU_CTRL_TRACE_ON_OV_Pos 11U
2219 #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos)
2223 #define PMU_TYPE_NUM_CNTS_Pos 0U
2224 #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/)
2226 #define PMU_TYPE_SIZE_CNTS_Pos 8U
2227 #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos)
2229 #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U
2230 #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos)
2232 #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U
2233 #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)
2235 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U
2236 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)
2240 #define PMU_AUTHSTATUS_NSID_Pos 0U
2241 #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/)
2243 #define PMU_AUTHSTATUS_NSNID_Pos 2U
2244 #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos)
2246 #define PMU_AUTHSTATUS_SID_Pos 4U
2247 #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos)
2249 #define PMU_AUTHSTATUS_SNID_Pos 6U
2250 #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos)
2252 #define PMU_AUTHSTATUS_NSUID_Pos 16U
2253 #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos)
2255 #define PMU_AUTHSTATUS_NSUNID_Pos 18U
2256 #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos)
2258 #define PMU_AUTHSTATUS_SUID_Pos 20U
2259 #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos)
2261 #define PMU_AUTHSTATUS_SUNID_Pos 22U
2262 #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos)
2264 
2265 #endif
2266 
2267 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2268 
2278 typedef struct
2279 {
2280  __IM uint32_t TYPE;
2281  __IOM uint32_t CTRL;
2282  __IOM uint32_t RNR;
2283  __IOM uint32_t RBAR;
2284  __IOM uint32_t RLAR;
2285  __IOM uint32_t RBAR_A1;
2286  __IOM uint32_t RLAR_A1;
2287  __IOM uint32_t RBAR_A2;
2288  __IOM uint32_t RLAR_A2;
2289  __IOM uint32_t RBAR_A3;
2290  __IOM uint32_t RLAR_A3;
2291  uint32_t RESERVED0[1];
2292  union {
2293  __IOM uint32_t MAIR[2];
2294  struct {
2295  __IOM uint32_t MAIR0;
2296  __IOM uint32_t MAIR1;
2297  };
2298  };
2299 } MPU_Type;
2300 
2301 #define MPU_TYPE_RALIASES 4U
2302 
2303 /* MPU Type Register Definitions */
2304 #define MPU_TYPE_IREGION_Pos 16U
2305 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
2307 #define MPU_TYPE_DREGION_Pos 8U
2308 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
2310 #define MPU_TYPE_SEPARATE_Pos 0U
2311 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
2313 /* MPU Control Register Definitions */
2314 #define MPU_CTRL_PRIVDEFENA_Pos 2U
2315 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
2317 #define MPU_CTRL_HFNMIENA_Pos 1U
2318 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
2320 #define MPU_CTRL_ENABLE_Pos 0U
2321 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
2323 /* MPU Region Number Register Definitions */
2324 #define MPU_RNR_REGION_Pos 0U
2325 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
2327 /* MPU Region Base Address Register Definitions */
2328 #define MPU_RBAR_BASE_Pos 5U
2329 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
2331 #define MPU_RBAR_SH_Pos 3U
2332 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
2334 #define MPU_RBAR_AP_Pos 1U
2335 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
2337 #define MPU_RBAR_XN_Pos 0U
2338 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
2340 /* MPU Region Limit Address Register Definitions */
2341 #define MPU_RLAR_LIMIT_Pos 5U
2342 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
2344 #define MPU_RLAR_PXN_Pos 4U
2345 #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos)
2347 #define MPU_RLAR_AttrIndx_Pos 1U
2348 #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos)
2350 #define MPU_RLAR_EN_Pos 0U
2351 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
2353 /* MPU Memory Attribute Indirection Register 0 Definitions */
2354 #define MPU_MAIR0_Attr3_Pos 24U
2355 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
2357 #define MPU_MAIR0_Attr2_Pos 16U
2358 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
2360 #define MPU_MAIR0_Attr1_Pos 8U
2361 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
2363 #define MPU_MAIR0_Attr0_Pos 0U
2364 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
2366 /* MPU Memory Attribute Indirection Register 1 Definitions */
2367 #define MPU_MAIR1_Attr7_Pos 24U
2368 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
2370 #define MPU_MAIR1_Attr6_Pos 16U
2371 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
2373 #define MPU_MAIR1_Attr5_Pos 8U
2374 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
2376 #define MPU_MAIR1_Attr4_Pos 0U
2377 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
2379 
2380 #endif
2381 
2382 
2383 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2384 
2394 typedef struct
2395 {
2396  __IOM uint32_t CTRL;
2397  __IM uint32_t TYPE;
2398 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
2399  __IOM uint32_t RNR;
2400  __IOM uint32_t RBAR;
2401  __IOM uint32_t RLAR;
2402 #else
2403  uint32_t RESERVED0[3];
2404 #endif
2405  __IOM uint32_t SFSR;
2406  __IOM uint32_t SFAR;
2407 } SAU_Type;
2408 
2409 /* SAU Control Register Definitions */
2410 #define SAU_CTRL_ALLNS_Pos 1U
2411 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
2413 #define SAU_CTRL_ENABLE_Pos 0U
2414 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
2416 /* SAU Type Register Definitions */
2417 #define SAU_TYPE_SREGION_Pos 0U
2418 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
2420 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
2421 /* SAU Region Number Register Definitions */
2422 #define SAU_RNR_REGION_Pos 0U
2423 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
2425 /* SAU Region Base Address Register Definitions */
2426 #define SAU_RBAR_BADDR_Pos 5U
2427 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
2429 /* SAU Region Limit Address Register Definitions */
2430 #define SAU_RLAR_LADDR_Pos 5U
2431 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
2433 #define SAU_RLAR_NSC_Pos 1U
2434 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
2436 #define SAU_RLAR_ENABLE_Pos 0U
2437 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
2439 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
2440 
2441 /* Secure Fault Status Register Definitions */
2442 #define SAU_SFSR_LSERR_Pos 7U
2443 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
2445 #define SAU_SFSR_SFARVALID_Pos 6U
2446 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
2448 #define SAU_SFSR_LSPERR_Pos 5U
2449 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
2451 #define SAU_SFSR_INVTRAN_Pos 4U
2452 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
2454 #define SAU_SFSR_AUVIOL_Pos 3U
2455 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
2457 #define SAU_SFSR_INVER_Pos 2U
2458 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
2460 #define SAU_SFSR_INVIS_Pos 1U
2461 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
2463 #define SAU_SFSR_INVEP_Pos 0U
2464 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
2466 
2467 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2468 
2469 
2480 typedef struct
2481 {
2482  uint32_t RESERVED0[1U];
2483  __IOM uint32_t FPCCR;
2484  __IOM uint32_t FPCAR;
2485  __IOM uint32_t FPDSCR;
2486  __IM uint32_t MVFR0;
2487  __IM uint32_t MVFR1;
2488  __IM uint32_t MVFR2;
2489 } FPU_Type;
2490 
2491 /* Floating-Point Context Control Register Definitions */
2492 #define FPU_FPCCR_ASPEN_Pos 31U
2493 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
2495 #define FPU_FPCCR_LSPEN_Pos 30U
2496 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
2498 #define FPU_FPCCR_LSPENS_Pos 29U
2499 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
2501 #define FPU_FPCCR_CLRONRET_Pos 28U
2502 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
2504 #define FPU_FPCCR_CLRONRETS_Pos 27U
2505 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
2507 #define FPU_FPCCR_TS_Pos 26U
2508 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
2510 #define FPU_FPCCR_UFRDY_Pos 10U
2511 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
2513 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
2514 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
2516 #define FPU_FPCCR_MONRDY_Pos 8U
2517 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
2519 #define FPU_FPCCR_SFRDY_Pos 7U
2520 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
2522 #define FPU_FPCCR_BFRDY_Pos 6U
2523 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
2525 #define FPU_FPCCR_MMRDY_Pos 5U
2526 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
2528 #define FPU_FPCCR_HFRDY_Pos 4U
2529 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
2531 #define FPU_FPCCR_THREAD_Pos 3U
2532 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
2534 #define FPU_FPCCR_S_Pos 2U
2535 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
2537 #define FPU_FPCCR_USER_Pos 1U
2538 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
2540 #define FPU_FPCCR_LSPACT_Pos 0U
2541 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
2543 /* Floating-Point Context Address Register Definitions */
2544 #define FPU_FPCAR_ADDRESS_Pos 3U
2545 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
2547 /* Floating-Point Default Status Control Register Definitions */
2548 #define FPU_FPDSCR_AHP_Pos 26U
2549 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
2551 #define FPU_FPDSCR_DN_Pos 25U
2552 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
2554 #define FPU_FPDSCR_FZ_Pos 24U
2555 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
2557 #define FPU_FPDSCR_RMode_Pos 22U
2558 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
2560 #define FPU_FPDSCR_FZ16_Pos 19U
2561 #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos)
2563 #define FPU_FPDSCR_LTPSIZE_Pos 16U
2564 #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos)
2566 /* Media and VFP Feature Register 0 Definitions */
2567 #define FPU_MVFR0_FPRound_Pos 28U
2568 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos)
2570 #define FPU_MVFR0_FPSqrt_Pos 20U
2571 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos)
2573 #define FPU_MVFR0_FPDivide_Pos 16U
2574 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos)
2576 #define FPU_MVFR0_FPDP_Pos 8U
2577 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos)
2579 #define FPU_MVFR0_FPSP_Pos 4U
2580 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos)
2582 #define FPU_MVFR0_SIMDReg_Pos 0U
2583 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
2585 /* Media and VFP Feature Register 1 Definitions */
2586 #define FPU_MVFR1_FMAC_Pos 28U
2587 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos)
2589 #define FPU_MVFR1_FPHP_Pos 24U
2590 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos)
2592 #define FPU_MVFR1_FP16_Pos 20U
2593 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos)
2595 #define FPU_MVFR1_MVE_Pos 8U
2596 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos)
2598 #define FPU_MVFR1_FPDNaN_Pos 4U
2599 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos)
2601 #define FPU_MVFR1_FPFtZ_Pos 0U
2602 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
2604 /* Media and VFP Feature Register 2 Definitions */
2605 #define FPU_MVFR2_FPMisc_Pos 4U
2606 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
2608 
2610 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
2611 
2621 typedef struct
2622 {
2623  __IOM uint32_t DHCSR;
2624  __OM uint32_t DCRSR;
2625  __IOM uint32_t DCRDR;
2626  __IOM uint32_t DEMCR;
2627  __OM uint32_t DSCEMCR;
2628  __IOM uint32_t DAUTHCTRL;
2629  __IOM uint32_t DSCSR;
2630 } CoreDebug_Type;
2631 
2632 /* Debug Halting Control and Status Register Definitions */
2633 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
2634 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
2636 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
2637 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
2639 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
2640 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
2642 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
2643 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
2645 #define CoreDebug_DHCSR_S_FPD_Pos 23U
2646 #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos)
2648 #define CoreDebug_DHCSR_S_SUIDE_Pos 22U
2649 #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
2651 #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U
2652 #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
2654 #define CoreDebug_DHCSR_S_SDE_Pos 20U
2655 #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos)
2657 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
2658 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
2660 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
2661 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
2663 #define CoreDebug_DHCSR_S_HALT_Pos 17U
2664 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
2666 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
2667 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
2669 #define CoreDebug_DHCSR_C_PMOV_Pos 6U
2670 #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
2672 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
2673 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
2675 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
2676 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
2678 #define CoreDebug_DHCSR_C_STEP_Pos 2U
2679 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
2681 #define CoreDebug_DHCSR_C_HALT_Pos 1U
2682 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
2684 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
2685 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
2687 /* Debug Core Register Selector Register Definitions */
2688 #define CoreDebug_DCRSR_REGWnR_Pos 16U
2689 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
2691 #define CoreDebug_DCRSR_REGSEL_Pos 0U
2692 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
2694 /* Debug Exception and Monitor Control Register Definitions */
2695 #define CoreDebug_DEMCR_TRCENA_Pos 24U
2696 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
2698 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
2699 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
2701 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
2702 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
2704 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
2705 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
2707 #define CoreDebug_DEMCR_MON_EN_Pos 16U
2708 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
2710 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
2711 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
2713 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
2714 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
2716 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
2717 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
2719 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
2720 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
2722 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
2723 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
2725 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
2726 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
2728 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
2729 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
2731 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
2732 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
2734 /* Debug Set Clear Exception and Monitor Control Register Definitions */
2735 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U
2736 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
2738 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U
2739 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
2741 #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U
2742 #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
2744 #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U
2745 #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
2747 /* Debug Authentication Control Register Definitions */
2748 #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U
2749 #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
2751 #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U
2752 #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
2754 #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U
2755 #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
2757 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
2758 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
2760 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
2761 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
2763 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
2764 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
2766 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
2767 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
2769 /* Debug Security Control and Status Register Definitions */
2770 #define CoreDebug_DSCSR_CDS_Pos 16U
2771 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
2773 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
2774 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
2776 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
2777 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
2779 
2792 typedef struct
2793 {
2794  __IOM uint32_t DHCSR;
2795  __OM uint32_t DCRSR;
2796  __IOM uint32_t DCRDR;
2797  __IOM uint32_t DEMCR;
2798  __OM uint32_t DSCEMCR;
2799  __IOM uint32_t DAUTHCTRL;
2800  __IOM uint32_t DSCSR;
2801 } DCB_Type;
2802 
2803 /* DHCSR, Debug Halting Control and Status Register Definitions */
2804 #define DCB_DHCSR_DBGKEY_Pos 16U
2805 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
2807 #define DCB_DHCSR_S_RESTART_ST_Pos 26U
2808 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
2810 #define DCB_DHCSR_S_RESET_ST_Pos 25U
2811 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
2813 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U
2814 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
2816 #define DCB_DHCSR_S_FPD_Pos 23U
2817 #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)
2819 #define DCB_DHCSR_S_SUIDE_Pos 22U
2820 #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
2822 #define DCB_DHCSR_S_NSUIDE_Pos 21U
2823 #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
2825 #define DCB_DHCSR_S_SDE_Pos 20U
2826 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
2828 #define DCB_DHCSR_S_LOCKUP_Pos 19U
2829 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
2831 #define DCB_DHCSR_S_SLEEP_Pos 18U
2832 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
2834 #define DCB_DHCSR_S_HALT_Pos 17U
2835 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
2837 #define DCB_DHCSR_S_REGRDY_Pos 16U
2838 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
2840 #define DCB_DHCSR_C_PMOV_Pos 6U
2841 #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)
2843 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U
2844 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
2846 #define DCB_DHCSR_C_MASKINTS_Pos 3U
2847 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
2849 #define DCB_DHCSR_C_STEP_Pos 2U
2850 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
2852 #define DCB_DHCSR_C_HALT_Pos 1U
2853 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
2855 #define DCB_DHCSR_C_DEBUGEN_Pos 0U
2856 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
2858 /* DCRSR, Debug Core Register Select Register Definitions */
2859 #define DCB_DCRSR_REGWnR_Pos 16U
2860 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
2862 #define DCB_DCRSR_REGSEL_Pos 0U
2863 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
2865 /* DCRDR, Debug Core Register Data Register Definitions */
2866 #define DCB_DCRDR_DBGTMP_Pos 0U
2867 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
2869 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
2870 #define DCB_DEMCR_TRCENA_Pos 24U
2871 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
2873 #define DCB_DEMCR_MONPRKEY_Pos 23U
2874 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
2876 #define DCB_DEMCR_UMON_EN_Pos 21U
2877 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
2879 #define DCB_DEMCR_SDME_Pos 20U
2880 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
2882 #define DCB_DEMCR_MON_REQ_Pos 19U
2883 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
2885 #define DCB_DEMCR_MON_STEP_Pos 18U
2886 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
2888 #define DCB_DEMCR_MON_PEND_Pos 17U
2889 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
2891 #define DCB_DEMCR_MON_EN_Pos 16U
2892 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
2894 #define DCB_DEMCR_VC_SFERR_Pos 11U
2895 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
2897 #define DCB_DEMCR_VC_HARDERR_Pos 10U
2898 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
2900 #define DCB_DEMCR_VC_INTERR_Pos 9U
2901 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
2903 #define DCB_DEMCR_VC_BUSERR_Pos 8U
2904 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
2906 #define DCB_DEMCR_VC_STATERR_Pos 7U
2907 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
2909 #define DCB_DEMCR_VC_CHKERR_Pos 6U
2910 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
2912 #define DCB_DEMCR_VC_NOCPERR_Pos 5U
2913 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
2915 #define DCB_DEMCR_VC_MMERR_Pos 4U
2916 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
2918 #define DCB_DEMCR_VC_CORERESET_Pos 0U
2919 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
2921 /* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
2922 #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U
2923 #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
2925 #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U
2926 #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
2928 #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U
2929 #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
2931 #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U
2932 #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
2934 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
2935 #define DCB_DAUTHCTRL_UIDEN_Pos 10U
2936 #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
2938 #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U
2939 #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
2941 #define DCB_DAUTHCTRL_FSDMA_Pos 8U
2942 #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
2944 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
2945 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
2947 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
2948 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
2950 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
2951 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
2953 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
2954 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
2956 /* DSCSR, Debug Security Control and Status Register Definitions */
2957 #define DCB_DSCSR_CDSKEY_Pos 17U
2958 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2960 #define DCB_DSCSR_CDS_Pos 16U
2961 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2963 #define DCB_DSCSR_SBRSEL_Pos 1U
2964 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2966 #define DCB_DSCSR_SBRSELEN_Pos 0U
2967 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2969 
2983 typedef struct
2984 {
2985  __OM uint32_t DLAR;
2986  __IM uint32_t DLSR;
2987  __IM uint32_t DAUTHSTATUS;
2988  __IM uint32_t DDEVARCH;
2989  __IM uint32_t DDEVTYPE;
2990 } DIB_Type;
2991 
2992 /* DLAR, SCS Software Lock Access Register Definitions */
2993 #define DIB_DLAR_KEY_Pos 0U
2994 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
2996 /* DLSR, SCS Software Lock Status Register Definitions */
2997 #define DIB_DLSR_nTT_Pos 2U
2998 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
3000 #define DIB_DLSR_SLK_Pos 1U
3001 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
3003 #define DIB_DLSR_SLI_Pos 0U
3004 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
3006 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
3007 #define DIB_DAUTHSTATUS_SUNID_Pos 22U
3008 #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
3010 #define DIB_DAUTHSTATUS_SUID_Pos 20U
3011 #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
3013 #define DIB_DAUTHSTATUS_NSUNID_Pos 18U
3014 #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
3016 #define DIB_DAUTHSTATUS_NSUID_Pos 16U
3017 #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
3019 #define DIB_DAUTHSTATUS_SNID_Pos 6U
3020 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
3022 #define DIB_DAUTHSTATUS_SID_Pos 4U
3023 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
3025 #define DIB_DAUTHSTATUS_NSNID_Pos 2U
3026 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
3028 #define DIB_DAUTHSTATUS_NSID_Pos 0U
3029 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
3031 /* DDEVARCH, SCS Device Architecture Register Definitions */
3032 #define DIB_DDEVARCH_ARCHITECT_Pos 21U
3033 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
3035 #define DIB_DDEVARCH_PRESENT_Pos 20U
3036 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
3038 #define DIB_DDEVARCH_REVISION_Pos 16U
3039 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
3041 #define DIB_DDEVARCH_ARCHVER_Pos 12U
3042 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
3044 #define DIB_DDEVARCH_ARCHPART_Pos 0U
3045 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
3047 /* DDEVTYPE, SCS Device Type Register Definitions */
3048 #define DIB_DDEVTYPE_SUB_Pos 4U
3049 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
3051 #define DIB_DDEVTYPE_MAJOR_Pos 0U
3052 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
3055 
3071 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
3072 
3079 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
3080 
3091 /* Memory mapping of Core Hardware */
3092  #define SCS_BASE (0xE000E000UL)
3093  #define ITM_BASE (0xE0000000UL)
3094  #define DWT_BASE (0xE0001000UL)
3095  #define TPI_BASE (0xE0040000UL)
3096  #define CoreDebug_BASE (0xE000EDF0UL)
3097  #define DCB_BASE (0xE000EDF0UL)
3098  #define DIB_BASE (0xE000EFB0UL)
3099  #define SysTick_BASE (SCS_BASE + 0x0010UL)
3100  #define NVIC_BASE (SCS_BASE + 0x0100UL)
3101  #define SCB_BASE (SCS_BASE + 0x0D00UL)
3103  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
3104  #define SCB ((SCB_Type *) SCB_BASE )
3105  #define SysTick ((SysTick_Type *) SysTick_BASE )
3106  #define NVIC ((NVIC_Type *) NVIC_BASE )
3107  #define ITM ((ITM_Type *) ITM_BASE )
3108  #define DWT ((DWT_Type *) DWT_BASE )
3109  #define TPI ((TPI_Type *) TPI_BASE )
3110  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
3111  #define DCB ((DCB_Type *) DCB_BASE )
3112  #define DIB ((DIB_Type *) DIB_BASE )
3114  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3115  #define MPU_BASE (SCS_BASE + 0x0D90UL)
3116  #define MPU ((MPU_Type *) MPU_BASE )
3117  #endif
3118 
3119  #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
3120  #define PMU_BASE (0xE0003000UL)
3121  #define PMU ((PMU_Type *) PMU_BASE )
3122  #endif
3123 
3124  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3125  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
3126  #define SAU ((SAU_Type *) SAU_BASE )
3127  #endif
3128 
3129  #define FPU_BASE (SCS_BASE + 0x0F30UL)
3130  #define FPU ((FPU_Type *) FPU_BASE )
3132 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3133  #define SCS_BASE_NS (0xE002E000UL)
3134  #define CoreDebug_BASE_NS (0xE002EDF0UL)
3135  #define DCB_BASE_NS (0xE002EDF0UL)
3136  #define DIB_BASE_NS (0xE002EFB0UL)
3137  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
3138  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
3139  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
3141  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
3142  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
3143  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
3144  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
3145  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
3146  #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
3147  #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
3149  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3150  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
3151  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
3152  #endif
3153 
3154  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
3155  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
3157 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3158 
3162 /*******************************************************************************
3163  * Hardware Abstraction Layer
3164  Core Function Interface contains:
3165  - Core NVIC Functions
3166  - Core SysTick Functions
3167  - Core Debug Functions
3168  - Core Register Access Functions
3169  ******************************************************************************/
3176 /* ########################## NVIC functions #################################### */
3184 #ifdef CMSIS_NVIC_VIRTUAL
3185  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
3186  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
3187  #endif
3188  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
3189 #else
3190  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
3191  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
3192  #define NVIC_EnableIRQ __NVIC_EnableIRQ
3193  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
3194  #define NVIC_DisableIRQ __NVIC_DisableIRQ
3195  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
3196  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
3197  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
3198  #define NVIC_GetActive __NVIC_GetActive
3199  #define NVIC_SetPriority __NVIC_SetPriority
3200  #define NVIC_GetPriority __NVIC_GetPriority
3201  #define NVIC_SystemReset __NVIC_SystemReset
3202 #endif /* CMSIS_NVIC_VIRTUAL */
3203 
3204 #ifdef CMSIS_VECTAB_VIRTUAL
3205  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
3206  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
3207  #endif
3208  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
3209 #else
3210  #define NVIC_SetVector __NVIC_SetVector
3211  #define NVIC_GetVector __NVIC_GetVector
3212 #endif /* (CMSIS_VECTAB_VIRTUAL) */
3213 
3214 #define NVIC_USER_IRQ_OFFSET 16
3215 
3216 
3217 /* Special LR values for Secure/Non-Secure call handling and exception handling */
3218 
3219 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
3220 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
3221 
3222 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
3223 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
3224 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
3225 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
3226 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
3227 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
3228 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
3229 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
3230 
3231 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
3232 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
3233 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
3234 #else
3235 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
3236 #endif
3237 
3238 
3248 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
3249 {
3250  uint32_t reg_value;
3251  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3252 
3253  reg_value = SCB->AIRCR; /* read old register configuration */
3254  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
3255  reg_value = (reg_value |
3256  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3257  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
3258  SCB->AIRCR = reg_value;
3259 }
3260 
3261 
3267 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
3268 {
3269  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
3270 }
3271 
3272 
3279 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
3280 {
3281  if ((int32_t)(IRQn) >= 0)
3282  {
3283  __COMPILER_BARRIER();
3284  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3285  __COMPILER_BARRIER();
3286  }
3287 }
3288 
3289 
3298 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
3299 {
3300  if ((int32_t)(IRQn) >= 0)
3301  {
3302  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3303  }
3304  else
3305  {
3306  return(0U);
3307  }
3308 }
3309 
3310 
3317 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
3318 {
3319  if ((int32_t)(IRQn) >= 0)
3320  {
3321  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3322  __DSB();
3323  __ISB();
3324  }
3325 }
3326 
3327 
3336 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
3337 {
3338  if ((int32_t)(IRQn) >= 0)
3339  {
3340  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3341  }
3342  else
3343  {
3344  return(0U);
3345  }
3346 }
3347 
3348 
3355 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
3356 {
3357  if ((int32_t)(IRQn) >= 0)
3358  {
3359  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3360  }
3361 }
3362 
3363 
3370 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
3371 {
3372  if ((int32_t)(IRQn) >= 0)
3373  {
3374  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3375  }
3376 }
3377 
3378 
3387 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
3388 {
3389  if ((int32_t)(IRQn) >= 0)
3390  {
3391  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3392  }
3393  else
3394  {
3395  return(0U);
3396  }
3397 }
3398 
3399 
3400 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3401 
3409 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
3410 {
3411  if ((int32_t)(IRQn) >= 0)
3412  {
3413  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3414  }
3415  else
3416  {
3417  return(0U);
3418  }
3419 }
3420 
3421 
3430 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
3431 {
3432  if ((int32_t)(IRQn) >= 0)
3433  {
3434  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
3435  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3436  }
3437  else
3438  {
3439  return(0U);
3440  }
3441 }
3442 
3443 
3452 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
3453 {
3454  if ((int32_t)(IRQn) >= 0)
3455  {
3456  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
3457  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3458  }
3459  else
3460  {
3461  return(0U);
3462  }
3463 }
3464 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3465 
3466 
3476 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
3477 {
3478  if ((int32_t)(IRQn) >= 0)
3479  {
3480  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3481  }
3482  else
3483  {
3484  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3485  }
3486 }
3487 
3488 
3498 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
3499 {
3500 
3501  if ((int32_t)(IRQn) >= 0)
3502  {
3503  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
3504  }
3505  else
3506  {
3507  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
3508  }
3509 }
3510 
3511 
3523 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
3524 {
3525  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3526  uint32_t PreemptPriorityBits;
3527  uint32_t SubPriorityBits;
3528 
3529  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
3530  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
3531 
3532  return (
3533  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
3534  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
3535  );
3536 }
3537 
3538 
3550 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
3551 {
3552  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3553  uint32_t PreemptPriorityBits;
3554  uint32_t SubPriorityBits;
3555 
3556  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
3557  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
3558 
3559  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
3560  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
3561 }
3562 
3563 
3573 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
3574 {
3575  uint32_t *vectors = (uint32_t *)SCB->VTOR;
3576  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
3577  __DSB();
3578 }
3579 
3580 
3589 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
3590 {
3591  uint32_t *vectors = (uint32_t *)SCB->VTOR;
3592  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
3593 }
3594 
3595 
3600 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
3601 {
3602  __DSB(); /* Ensure all outstanding memory accesses included
3603  buffered write are completed before reset */
3604  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3605  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
3606  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
3607  __DSB(); /* Ensure completion of memory access */
3608 
3609  for(;;) /* wait until reset */
3610  {
3611  __NOP();
3612  }
3613 }
3614 
3615 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3616 
3625 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
3626 {
3627  uint32_t reg_value;
3628  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3629 
3630  reg_value = SCB_NS->AIRCR; /* read old register configuration */
3631  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
3632  reg_value = (reg_value |
3633  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3634  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
3635  SCB_NS->AIRCR = reg_value;
3636 }
3637 
3638 
3644 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
3645 {
3646  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
3647 }
3648 
3649 
3656 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
3657 {
3658  if ((int32_t)(IRQn) >= 0)
3659  {
3660  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3661  }
3662 }
3663 
3664 
3673 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
3674 {
3675  if ((int32_t)(IRQn) >= 0)
3676  {
3677  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3678  }
3679  else
3680  {
3681  return(0U);
3682  }
3683 }
3684 
3685 
3692 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
3693 {
3694  if ((int32_t)(IRQn) >= 0)
3695  {
3696  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3697  }
3698 }
3699 
3700 
3709 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
3710 {
3711  if ((int32_t)(IRQn) >= 0)
3712  {
3713  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3714  }
3715  else
3716  {
3717  return(0U);
3718  }
3719 }
3720 
3721 
3728 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
3729 {
3730  if ((int32_t)(IRQn) >= 0)
3731  {
3732  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3733  }
3734 }
3735 
3736 
3743 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
3744 {
3745  if ((int32_t)(IRQn) >= 0)
3746  {
3747  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3748  }
3749 }
3750 
3751 
3760 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
3761 {
3762  if ((int32_t)(IRQn) >= 0)
3763  {
3764  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3765  }
3766  else
3767  {
3768  return(0U);
3769  }
3770 }
3771 
3772 
3782 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
3783 {
3784  if ((int32_t)(IRQn) >= 0)
3785  {
3786  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3787  }
3788  else
3789  {
3790  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3791  }
3792 }
3793 
3794 
3803 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
3804 {
3805 
3806  if ((int32_t)(IRQn) >= 0)
3807  {
3808  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
3809  }
3810  else
3811  {
3812  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
3813  }
3814 }
3815 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
3816 
3819 /* ########################## MPU functions #################################### */
3820 
3821 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3822 
3823 #include "mpu_armv8.h"
3824 
3825 #endif
3826 
3827 /* ########################## PMU functions and events #################################### */
3828 
3829 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
3830 
3831 #include "pmu_armv8.h"
3832 
3833 #endif
3834 
3835 /* ########################## FPU functions #################################### */
3851 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
3852 {
3853  uint32_t mvfr0;
3854 
3855  mvfr0 = FPU->MVFR0;
3856  if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
3857  {
3858  return 2U; /* Double + Single precision FPU */
3859  }
3860  else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
3861  {
3862  return 1U; /* Single precision FPU */
3863  }
3864  else
3865  {
3866  return 0U; /* No FPU */
3867  }
3868 }
3869 
3870 
3873 /* ########################## MVE functions #################################### */
3889 __STATIC_INLINE uint32_t SCB_GetMVEType(void)
3890 {
3891  const uint32_t mvfr1 = FPU->MVFR1;
3892  if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
3893  {
3894  return 2U;
3895  }
3896  else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
3897  {
3898  return 1U;
3899  }
3900  else
3901  {
3902  return 0U;
3903  }
3904 }
3905 
3906 
3910 /* ########################## Cache functions #################################### */
3911 
3912 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
3913  (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
3914 #include "cachel1_armv7.h"
3915 #endif
3916 
3917 
3918 /* ########################## SAU functions #################################### */
3926 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3927 
3932 __STATIC_INLINE void TZ_SAU_Enable(void)
3933 {
3934  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
3935 }
3936 
3937 
3938 
3943 __STATIC_INLINE void TZ_SAU_Disable(void)
3944 {
3945  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
3946 }
3947 
3948 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3949 
3955 /* ################################## Debug Control function ############################################ */
3969 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
3970 {
3971  __DSB();
3972  __ISB();
3973  DCB->DAUTHCTRL = value;
3974  __DSB();
3975  __ISB();
3976 }
3977 
3978 
3984 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3985 {
3986  return (DCB->DAUTHCTRL);
3987 }
3988 
3989 
3990 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3991 
3996 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3997 {
3998  __DSB();
3999  __ISB();
4000  DCB_NS->DAUTHCTRL = value;
4001  __DSB();
4002  __ISB();
4003 }
4004 
4005 
4011 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
4012 {
4013  return (DCB_NS->DAUTHCTRL);
4014 }
4015 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4016 
4022 /* ################################## Debug Identification function ############################################ */
4036 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
4037 {
4038  return (DIB->DAUTHSTATUS);
4039 }
4040 
4041 
4042 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4043 
4048 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
4049 {
4050  return (DIB_NS->DAUTHSTATUS);
4051 }
4052 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4053 
4059 /* ################################## SysTick function ############################################ */
4067 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
4068 
4080 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
4081 {
4082  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
4083  {
4084  return (1UL); /* Reload value impossible */
4085  }
4086 
4087  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
4088  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
4089  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
4090  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
4091  SysTick_CTRL_TICKINT_Msk |
4092  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
4093  return (0UL); /* Function successful */
4094 }
4095 
4096 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4097 
4109 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
4110 {
4111  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
4112  {
4113  return (1UL); /* Reload value impossible */
4114  }
4115 
4116  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
4117  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
4118  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
4119  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
4120  SysTick_CTRL_TICKINT_Msk |
4121  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
4122  return (0UL); /* Function successful */
4123 }
4124 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4125 
4126 #endif
4127 
4132 /* ##################################### Debug In/Output function ########################################### */
4140 extern volatile int32_t ITM_RxBuffer;
4141 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
4152 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
4153 {
4154  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
4155  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
4156  {
4157  while (ITM->PORT[0U].u32 == 0UL)
4158  {
4159  __NOP();
4160  }
4161  ITM->PORT[0U].u8 = (uint8_t)ch;
4162  }
4163  return (ch);
4164 }
4165 
4166 
4173 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
4174 {
4175  int32_t ch = -1; /* no character available */
4176 
4177  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
4178  {
4179  ch = ITM_RxBuffer;
4180  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
4181  }
4182 
4183  return (ch);
4184 }
4185 
4186 
4193 __STATIC_INLINE int32_t ITM_CheckChar (void)
4194 {
4195 
4196  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
4197  {
4198  return (0); /* no character available */
4199  }
4200  else
4201  {
4202  return (1); /* character available */
4203  }
4204 }
4205 
4211 #ifdef __cplusplus
4212 }
4213 #endif
4214 
4215 #endif /* __CORE_ARMV81MML_H_DEPENDANT */
4216 
4217 #endif /* __CMSIS_GENERIC */
__OM
#define __OM
Definition: core_armv81mml.h:294
DWT_Type::CPICNT
__IOM uint32_t CPICNT
Definition: core_armv81mml.h:1180
DWT_Type::COMP11
__IOM uint32_t COMP11
Definition: core_armv81mml.h:1230
ITM_Type::PID3
__IM uint32_t PID3
Definition: core_armv81mml.h:1104
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv81mml.h:2480
SCB_Type::DCCISW
__OM uint32_t DCCISW
Definition: core_armv81mml.h:555
ITM_Type::LSR
__IM uint32_t LSR
Definition: core_armv81mml.h:1092
ITM
#define ITM
Definition: core_armv81mml.h:3107
SCB_Type::DFSR
__IOM uint32_t DFSR
Definition: core_armv81mml.h:523
ITM_Type::u8
__OM uint8_t u8
Definition: core_armv81mml.h:1079
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1176
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_armv81mml.h:2983
DWT_Type::COMP6
__IOM uint32_t COMP6
Definition: core_armv81mml.h:1210
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_armv81mml.h:636
mpu_armv8.h
SCB_Type::AFSR
__IOM uint32_t AFSR
Definition: core_armv81mml.h:526
DWT_Type::FUNCTION7
__IOM uint32_t FUNCTION7
Definition: core_armv81mml.h:1216
ITM_Type::PID5
__IM uint32_t PID5
Definition: core_armv81mml.h:1098
DCB
#define DCB
Definition: core_armv81mml.h:3111
SCB_Type::DCCSW
__OM uint32_t DCCSW
Definition: core_armv81mml.h:553
SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Definition: core_armv81mml.h:554
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:3298
SysTick_Type::CTRL
__IOM uint32_t CTRL
Definition: core_armv81mml.h:1025
DCB_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_armv81mml.h:2794
DWT_Type::COMP2
__IOM uint32_t COMP2
Definition: core_armv81mml.h:1194
CoreDebug_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_armv81mml.h:2623
DWT_Type::COMP5
__IOM uint32_t COMP5
Definition: core_armv81mml.h:1206
SCB_Type::DCISW
__OM uint32_t DCISW
Definition: core_armv81mml.h:550
TPI_Type::FFSR
__IM uint32_t FFSR
Definition: core_armv81mml.h:1371
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:903
SCB_Type::RFSR
__IOM uint32_t RFSR
Definition: core_armv81mml.h:540
__STATIC_INLINE
#define __STATIC_INLINE
Definition: hw_types.h:57
TPI_Type::LSR
__IM uint32_t LSR
Definition: core_armv81mml.h:1376
TPI_Type::SSPSR
__IM uint32_t SSPSR
Definition: core_armv81mml.h:1364
DCB_Type::DSCEMCR
__OM uint32_t DSCEMCR
Definition: core_armv81mml.h:2798
FPU
#define FPU
Definition: core_armv81mml.h:3130
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_armv81mml.h:621
DWT_Type::CYCCNT
__IOM uint32_t CYCCNT
Definition: core_armv81mml.h:1179
DWT_Type::FUNCTION8
__IOM uint32_t FUNCTION8
Definition: core_armv81mml.h:1220
SysTick_Type::CALIB
__IM uint32_t CALIB
Definition: core_armv81mml.h:1028
SysTick
#define SysTick
Definition: core_armv81mml.h:3105
SysTick_Type::VAL
__IOM uint32_t VAL
Definition: core_armv81mml.h:1027
DWT_Type::FUNCTION12
__IOM uint32_t FUNCTION12
Definition: core_armv81mml.h:1236
SCB_Type::CPUID
__IM uint32_t CPUID
Definition: core_armv81mml.h:513
SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Definition: core_armv81mml.h:546
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_armv81mml.h:4141
DWT_Type::FUNCTION4
__IOM uint32_t FUNCTION4
Definition: core_armv81mml.h:1204
DWT_Type::COMP3
__IOM uint32_t COMP3
Definition: core_armv81mml.h:1198
ITM_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: core_armv81mml.h:1096
FPU_MVFR1_MVE_Pos
#define FPU_MVFR1_MVE_Pos
Definition: core_armv81mml.h:2595
DIB_Type::DAUTHSTATUS
__IM uint32_t DAUTHSTATUS
Definition: core_armv81mml.h:2987
__IOM
#define __IOM
Definition: core_armv81mml.h:295
SCB_Type::CLIDR
__IM uint32_t CLIDR
Definition: core_armv81mml.h:532
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:3589
FPU_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_armv81mml.h:2488
TPI_Type::TYPE
__IM uint32_t TYPE
Definition: core_armv81mml.h:1378
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:3279
IRQn_Type
enum IRQn IRQn_Type
ITM_Type::CID0
__IM uint32_t CID0
Definition: core_armv81mml.h:1105
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:3336
SCB_Type::ID_DFR
__IM uint32_t ID_DFR
Definition: core_armv81mml.h:528
ITM_Type::PID0
__IM uint32_t PID0
Definition: core_armv81mml.h:1101
DWT_Type::FUNCTION1
__IOM uint32_t FUNCTION1
Definition: core_armv81mml.h:1192
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv81mml.h:4173
SCB_Type::ICSR
__IOM uint32_t ICSR
Definition: core_armv81mml.h:514
SCB_Type::CFSR
__IOM uint32_t CFSR
Definition: core_armv81mml.h:521
SysTick_Type::LOAD
__IOM uint32_t LOAD
Definition: core_armv81mml.h:1026
ITM_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: core_armv81mml.h:1094
FPU_MVFR0_FPDP_Msk
#define FPU_MVFR0_FPDP_Msk
Definition: core_armv81mml.h:2577
TPI_Type::CSPSR
__IOM uint32_t CSPSR
Definition: core_armv81mml.h:1365
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_armv81mml.h:3969
DIB_Type::DLSR
__IM uint32_t DLSR
Definition: core_armv81mml.h:2986
SCB_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_armv81mml.h:543
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:3355
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:367
CoreDebug_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_armv81mml.h:2626
CONTROL_Type::w
uint32_t w
Definition: core_armv81mml.h:446
ITM_Type::TPR
__IOM uint32_t TPR
Definition: core_armv81mml.h:1086
CoreDebug_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_armv81mml.h:2625
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1362
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv81mml.h:4193
FPU_Type::FPCCR
__IOM uint32_t FPCCR
Definition: core_armv81mml.h:2483
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:3851
SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Definition: core_armv81mml.h:549
FPU_Type::FPCAR
__IOM uint32_t FPCAR
Definition: core_armv81mml.h:2484
DCB_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_armv81mml.h:2795
SCB_Type::SCR
__IOM uint32_t SCR
Definition: core_armv81mml.h:517
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:3550
SCB_GetMVEType
__STATIC_INLINE uint32_t SCB_GetMVEType(void)
get MVE type
Definition: core_armv81mml.h:3889
SCB_Type::BFAR
__IOM uint32_t BFAR
Definition: core_armv81mml.h:525
DWT_Type::COMP14
__IOM uint32_t COMP14
Definition: core_armv81mml.h:1242
NVIC
#define NVIC
Definition: core_armv81mml.h:3106
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:944
SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Definition: core_armv81mml.h:551
DWT_Type::PCSR
__IM uint32_t PCSR
Definition: core_armv81mml.h:1185
SCnSCB_Type::ICTR
__IM uint32_t ICTR
Definition: core_armv81mml.h:1001
CoreDebug_Type::DSCSR
__IOM uint32_t DSCSR
Definition: core_armv81mml.h:2629
DWT_Type::FUNCTION10
__IOM uint32_t FUNCTION10
Definition: core_armv81mml.h:1228
SCB_Type::ID_ADR
__IM uint32_t ID_ADR
Definition: core_armv81mml.h:529
cmsis_version.h
CMSIS Core(M) Version definitions.
CoreDebug_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_armv81mml.h:2624
xPSR_Type::w
uint32_t w
Definition: core_armv81mml.h:401
ITM_Type::CID2
__IM uint32_t CID2
Definition: core_armv81mml.h:1107
DCB_Type::DAUTHCTRL
__IOM uint32_t DAUTHCTRL
Definition: core_armv81mml.h:2799
TPI_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: core_armv81mml.h:1379
FPU_MVFR0_FPSP_Msk
#define FPU_MVFR0_FPSP_Msk
Definition: core_armv81mml.h:2580
ITM_Type::u16
__OM uint16_t u16
Definition: core_armv81mml.h:1080
IRQn
IRQn
Definition: cc35xx.h:39
SCnSCB_Type::ACTLR
__IOM uint32_t ACTLR
Definition: core_armv81mml.h:1002
SCnSCB_Type::CPPWR
__IOM uint32_t CPPWR
Definition: core_armv81mml.h:1003
DWT_Type::FUNCTION3
__IOM uint32_t FUNCTION3
Definition: core_armv81mml.h:1200
CoreDebug_Type
Definition: core_armv81mml.h:2621
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:511
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_armv81mml.h:1151
DIB_Type::DLAR
__OM uint32_t DLAR
Definition: core_armv81mml.h:2985
ITM_Type::TCR
__IOM uint32_t TCR
Definition: core_armv81mml.h:1088
SCB
#define SCB
Definition: core_armv81mml.h:3104
DWT_Type::COMP7
__IOM uint32_t COMP7
Definition: core_armv81mml.h:1214
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv81mml.h:1075
ITM_Type::PID7
__IM uint32_t PID7
Definition: core_armv81mml.h:1100
IPSR_Type::w
uint32_t w
Definition: core_armv81mml.h:374
DWT_Type::COMP4
__IOM uint32_t COMP4
Definition: core_armv81mml.h:1202
DWT_Type::FUNCTION14
__IOM uint32_t FUNCTION14
Definition: core_armv81mml.h:1244
DWT_Type::COMP13
__IOM uint32_t COMP13
Definition: core_armv81mml.h:1238
CoreDebug_Type::DSCEMCR
__OM uint32_t DSCEMCR
Definition: core_armv81mml.h:2627
SCB_Type::CCR
__IOM uint32_t CCR
Definition: core_armv81mml.h:518
ITM_Type::PID4
__IM uint32_t PID4
Definition: core_armv81mml.h:1097
FPU_Type::FPDSCR
__IOM uint32_t FPDSCR
Definition: core_armv81mml.h:2485
ITM_Type::TER
__IOM uint32_t TER
Definition: core_armv81mml.h:1084
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:3573
SCB_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_armv81mml.h:544
SCB_Type::MMFAR
__IOM uint32_t MMFAR
Definition: core_armv81mml.h:524
SCB_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_armv81mml.h:542
ITM_Type::LAR
__OM uint32_t LAR
Definition: core_armv81mml.h:1091
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv81mml.h:3267
APSR_Type::w
uint32_t w
Definition: core_armv81mml.h:341
DIB_Type::DDEVARCH
__IM uint32_t DDEVARCH
Definition: core_armv81mml.h:2988
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:3317
SCB_Type::CTR
__IM uint32_t CTR
Definition: core_armv81mml.h:533
TPI_Type::LAR
__OM uint32_t LAR
Definition: core_armv81mml.h:1375
SCB_Type::NSACR
__IOM uint32_t NSACR
Definition: core_armv81mml.h:537
DWT_Type::FUNCTION13
__IOM uint32_t FUNCTION13
Definition: core_armv81mml.h:1240
SCB_Type::SHCSR
__IOM uint32_t SHCSR
Definition: core_armv81mml.h:520
SCB_Type::HFSR
__IOM uint32_t HFSR
Definition: core_armv81mml.h:522
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_armv81mml.h:635
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv81mml.h:998
DWT_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: core_armv81mml.h:1252
SCB_Type::CPACR
__IOM uint32_t CPACR
Definition: core_armv81mml.h:536
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:475
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1023
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv81mml.h:620
ITM_Type::PID1
__IM uint32_t PID1
Definition: core_armv81mml.h:1102
DWT_Type::COMP9
__IOM uint32_t COMP9
Definition: core_armv81mml.h:1222
ITM_Type::u32
__OM uint32_t u32
Definition: core_armv81mml.h:1081
DWT_Type::COMP8
__IOM uint32_t COMP8
Definition: core_armv81mml.h:1218
DWT_Type::FOLDCNT
__IOM uint32_t FOLDCNT
Definition: core_armv81mml.h:1184
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:3387
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: cmsis_gcc.h:117
DWT_Type::FUNCTION11
__IOM uint32_t FUNCTION11
Definition: core_armv81mml.h:1232
SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Definition: core_armv81mml.h:534
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_armv81mml.h:4036
ITM_Type::PID6
__IM uint32_t PID6
Definition: core_armv81mml.h:1099
FPU_MVFR1_MVE_Msk
#define FPU_MVFR1_MVE_Msk
Definition: core_armv81mml.h:2596
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv81mml.h:3199
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:3476
DIB
#define DIB
Definition: core_armv81mml.h:3112
SCB_Type::CSSELR
__IOM uint32_t CSSELR
Definition: core_armv81mml.h:535
TPI_Type::PSCR
__IOM uint32_t PSCR
Definition: core_armv81mml.h:1373
SysTick_IRQn
Definition: cc35xx.h:49
DCB_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_armv81mml.h:2796
DWT_Type::COMP0
__IOM uint32_t COMP0
Definition: core_armv81mml.h:1186
ITM_Type::PID2
__IM uint32_t PID2
Definition: core_armv81mml.h:1103
SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Definition: core_armv81mml.h:548
FPU_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_armv81mml.h:2487
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv81mml.h:648
SCB_Type::BPIALL
__OM uint32_t BPIALL
Definition: core_armv81mml.h:556
cmsis_compiler.h
CMSIS compiler generic header file.
DWT_Type::FUNCTION5
__IOM uint32_t FUNCTION5
Definition: core_armv81mml.h:1208
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:328
NVIC_Type::STIR
__OM uint32_t STIR
Definition: core_armv81mml.h:491
CoreDebug_Type::DAUTHCTRL
__IOM uint32_t DAUTHCTRL
Definition: core_armv81mml.h:2628
DWT_Type::FUNCTION15
__IOM uint32_t FUNCTION15
Definition: core_armv81mml.h:1248
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv81mml.h:1046
DWT_Type::CTRL
__IOM uint32_t CTRL
Definition: core_armv81mml.h:1178
SCB_Type::STIR
__OM uint32_t STIR
Definition: core_armv81mml.h:539
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:3370
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_armv81mml.h:2792
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:436
DWT_Type::COMP12
__IOM uint32_t COMP12
Definition: core_armv81mml.h:1234
TPI_Type::SPPR
__IOM uint32_t SPPR
Definition: core_armv81mml.h:1369
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: cc35xx.h:114
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv81mml.h:1036
DIB_Type::DDEVTYPE
__IM uint32_t DDEVTYPE
Definition: core_armv81mml.h:2989
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv81mml.h:1042
DWT_Type::FUNCTION0
__IOM uint32_t FUNCTION0
Definition: core_armv81mml.h:1188
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv81mml.h:3214
FPU_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_armv81mml.h:2486
pmu_armv8.h
DCB_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_armv81mml.h:2797
DWT_Type::LSR
__IM uint32_t LSR
Definition: core_armv81mml.h:1250
DWT_Type::SLEEPCNT
__IOM uint32_t SLEEPCNT
Definition: core_armv81mml.h:1182
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:3523
DWT_Type::COMP1
__IOM uint32_t COMP1
Definition: core_armv81mml.h:1190
DWT_Type::FUNCTION9
__IOM uint32_t FUNCTION9
Definition: core_armv81mml.h:1224
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:3600
DWT_Type::COMP10
__IOM uint32_t COMP10
Definition: core_armv81mml.h:1226
__IM
#define __IM
Definition: core_armv81mml.h:293
ITM_Type::CID3
__IM uint32_t CID3
Definition: core_armv81mml.h:1108
DWT_Type::LSUCNT
__IOM uint32_t LSUCNT
Definition: core_armv81mml.h:1183
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:385
DWT_Type::FUNCTION2
__IOM uint32_t FUNCTION2
Definition: core_armv81mml.h:1196
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_armv81mml.h:3984
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:933
DWT_Type::EXCCNT
__IOM uint32_t EXCCNT
Definition: core_armv81mml.h:1181
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:3498
TPI_Type::FFCR
__IOM uint32_t FFCR
Definition: core_armv81mml.h:1372
SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Definition: core_armv81mml.h:552
TPI_Type::ACPR
__IOM uint32_t ACPR
Definition: core_armv81mml.h:1367
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv81mml.h:1039
DWT_Type::FUNCTION6
__IOM uint32_t FUNCTION6
Definition: core_armv81mml.h:1212
SCB_Type::VTOR
__IOM uint32_t VTOR
Definition: core_armv81mml.h:515
DWT_Type::COMP15
__IOM uint32_t COMP15
Definition: core_armv81mml.h:1246
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv81mml.h:3248
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_gcc.h:53
DCB_Type::DSCSR
__IOM uint32_t DSCSR
Definition: core_armv81mml.h:2800
ITM_Type::CID1
__IM uint32_t CID1
Definition: core_armv81mml.h:1106
SCB_Type::AIRCR
__IOM uint32_t AIRCR
Definition: core_armv81mml.h:516