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Macros
#define	__SAUREGION_PRESENT 0x0001U /* SAU present */

#define	__DSP_PRESENT 0x0001U /* DSP extension present */

#define	__Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */

#define	__CM33_REV 0x0001U /* Core revision */

#define	__MPU_PRESENT 0x0001U /* MPU present or not */

#define	__FPU_PRESENT 0x0001U /* FPU present or not */

#define	__VTOR_PRESENT 0x0001U /* VTOR present */

#define	__NVIC_PRIO_BITS 0x0004U /* 4 NVIC priority bits */

Typedefs
typedef enum IRQn	IRQn_Type

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, INT_SP_UART_0_INT_REQ_IRQn = 0, INT_SP_UART_1_INT_REQ_IRQn = 1, INT_SP_I2C_0_INTREQ_IRQn = 2, INT_SP_I2C_1_INTREQ_IRQn = 3, INT_SP_SPI_0_EVT_REQ_IRQn = 4, INT_SP_SPI_1_EVT_REQ_IRQn = 5, INT_GPTIMER_0_EVT_CPU_IRQn = 6, INT_GPTIMER_1_EVT_CPU_IRQn = 7, INT_SP_UART_2_INT_REQ_IRQn = 8, INT_I2S_IRQ_REQ_IRQn = 9, INT_EVT_PDM_EVENT_REQ_IRQn = 10, INT_EVT_SWINT0_REQ_IRQn = 11, INT_EVT_SWINT1_REQ_IRQn = 12, INT_EVT_SDMMC_PUB_REQ_IRQn = 13, INT_SDIO_CARD_IRQ_REQ_IRQn = 14, INT_ULL_USC_ULPADCHP_PUB_EVT0_REQ_IRQn = 15, INT_NON_SECURED_GPIO_IRQ_EVT_IND_OUT_IRQn = 16, INT_SECURED_GPIO_IRQ_EVT_IND_OUT_IRQn = 17, INT_OSPR_HSM_HOST_0_SEC_IRQn = 18, INT_OSPR_HSM_HOST_0_IRQn = 19, INT_OSPR_HSM_HOST_1_IRQn = 20, INT_SVT_EVT_COMBINED_SYSTIM_OUT_IRQn = 21, INT_SVT_EVT_SYSTIMER_BIT_OUT_IRQn = 22, INT_SVT_EVT_SYSTIMER_OUT_0_IRQn = 23, INT_SVT_EVT_SYSTIMER_OUT_1_IRQn = 24, INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT_IRQn = 25, INT_SECURED_DMA_IRQ_EVT_IND_OUT_IRQn = 26, INT_NON_SECURED_DOORBELL_IRQ_EVT_IND_OUT_IRQn = 27, INT_SECURED_DOORBELL_IRQ_EVT_IND_OUT_IRQn = 28, INT_ICACHE_ERR_IRQn = 29, INT_OSPI_IRQn = 30, INT_OTFDE_IRQn = 31, INT_XIP_ARB_IRQn = 32, INT_XIP_DMA_SEC_IRQn = 33, INT_XIP_DMA_NONSEC_IRQn = 34, INT_SW_INTERRUPT_0_IRQn = 35, INT_SW_INTERRUPT_1_IRQn = 36, INT_SW_INTERRUPT_2_IRQn = 37, INT_SW_INTERRUPT_3_IRQn = 38, INT_SW_INTERRUPT_4_IRQn = 39, INT_SW_INTERRUPT_5_IRQn = 40, INT_SW_INTERRUPT_6_IRQn = 41, INT_SW_INTERRUPT_7_IRQn = 42, INT_PRCM_IRQn = 43, INT_OCLA_IRQn = 44, INT_HIF_FIFO_IRQn = 45, INT_HOST_ELP_TMR_WAKEUP_REQ_IRQn = 46, INT_NAB_HOST_IRQn = 47, INT_BLE_RFC_GPO_8_IRQn = 48, INT_RTC_EVENT_IRQn = 49, INT_DEBUGSS_HOST_CSYSPWRUPREQ_IRQn = 50, INT_DEBUGSS_HOST_FORCEACTIVE_IRQn = 51, INT_SECURED_ERROR_IRQ_EVT_IND_OUT_IRQn = 52 }

Macro Definition Documentation

§ __SAUREGION_PRESENT

#define __SAUREGION_PRESENT 0x0001U /* SAU present */

§ __DSP_PRESENT

#define __DSP_PRESENT 0x0001U /* DSP extension present */

§ __Vendor_SysTickConfig

#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */

§ __CM33_REV

#define __CM33_REV 0x0001U /* Core revision */

§ __MPU_PRESENT

#define __MPU_PRESENT 0x0001U /* MPU present or not */

§ __FPU_PRESENT

#define __FPU_PRESENT 0x0001U /* FPU present or not */

§ __VTOR_PRESENT

#define __VTOR_PRESENT 0x0001U /* VTOR present */

§ __NVIC_PRIO_BITS

#define __NVIC_PRIO_BITS 0x0004U /* 4 NVIC priority bits */

Referenced by __NVIC_GetPriority(), __NVIC_SetPriority(), __NVIC_SystemReset(), DIB_GetAuthStatus(), NVIC_DecodePriority(), and NVIC_EncodePriority().

Typedef Documentation

§ IRQn_Type

typedef enum IRQn IRQn_Type

Enumeration Type Documentation

§ IRQn

enum IRQn

Enumerator
NonMaskableInt_IRQn
HardFault_IRQn
MemoryManagement_IRQn
BusFault_IRQn
UsageFault_IRQn
SVCall_IRQn
DebugMonitor_IRQn
PendSV_IRQn
SysTick_IRQn
INT_SP_UART_0_INT_REQ_IRQn
INT_SP_UART_1_INT_REQ_IRQn
INT_SP_I2C_0_INTREQ_IRQn
INT_SP_I2C_1_INTREQ_IRQn
INT_SP_SPI_0_EVT_REQ_IRQn
INT_SP_SPI_1_EVT_REQ_IRQn
INT_GPTIMER_0_EVT_CPU_IRQn
INT_GPTIMER_1_EVT_CPU_IRQn
INT_SP_UART_2_INT_REQ_IRQn
INT_I2S_IRQ_REQ_IRQn
INT_EVT_PDM_EVENT_REQ_IRQn
INT_EVT_SWINT0_REQ_IRQn
INT_EVT_SWINT1_REQ_IRQn
INT_EVT_SDMMC_PUB_REQ_IRQn
INT_SDIO_CARD_IRQ_REQ_IRQn
INT_ULL_USC_ULPADCHP_PUB_EVT0_REQ_IRQn
INT_NON_SECURED_GPIO_IRQ_EVT_IND_OUT_IRQn
INT_SECURED_GPIO_IRQ_EVT_IND_OUT_IRQn
INT_OSPR_HSM_HOST_0_SEC_IRQn
INT_OSPR_HSM_HOST_0_IRQn
INT_OSPR_HSM_HOST_1_IRQn
INT_SVT_EVT_COMBINED_SYSTIM_OUT_IRQn
INT_SVT_EVT_SYSTIMER_BIT_OUT_IRQn
INT_SVT_EVT_SYSTIMER_OUT_0_IRQn
INT_SVT_EVT_SYSTIMER_OUT_1_IRQn
INT_NON_SECURED_DMA_IRQ_EVT_IND_OUT_IRQn
INT_SECURED_DMA_IRQ_EVT_IND_OUT_IRQn
INT_NON_SECURED_DOORBELL_IRQ_EVT_IND_OUT_IRQn
INT_SECURED_DOORBELL_IRQ_EVT_IND_OUT_IRQn
INT_ICACHE_ERR_IRQn
INT_OSPI_IRQn
INT_OTFDE_IRQn
INT_XIP_ARB_IRQn
INT_XIP_DMA_SEC_IRQn
INT_XIP_DMA_NONSEC_IRQn
INT_SW_INTERRUPT_0_IRQn
INT_SW_INTERRUPT_1_IRQn
INT_SW_INTERRUPT_2_IRQn
INT_SW_INTERRUPT_3_IRQn
INT_SW_INTERRUPT_4_IRQn
INT_SW_INTERRUPT_5_IRQn
INT_SW_INTERRUPT_6_IRQn
INT_SW_INTERRUPT_7_IRQn
INT_PRCM_IRQn
INT_OCLA_IRQn
INT_HIF_FIFO_IRQn
INT_HOST_ELP_TMR_WAKEUP_REQ_IRQn
INT_NAB_HOST_IRQn
INT_BLE_RFC_GPO_8_IRQn
INT_RTC_EVENT_IRQn
INT_DEBUGSS_HOST_CSYSPWRUPREQ_IRQn
INT_DEBUGSS_HOST_FORCEACTIVE_IRQn
INT_SECURED_ERROR_IRQ_EVT_IND_OUT_IRQn

Macros

Typedefs

Enumerations