AM261x MCU+ SDK: ECC : Error Correcting Code

| AM261x MCU+ SDK 26.00.00 |

ECC : Error Correcting Code

To increase functional and system reliability, the memories in many device modules and subsystems are protected by Error Correcting Code (ECC), which performs Single Error Correction (SEC) and Double Error Detection (DED). Detected errors are reported via ESM. Single bit errors are corrected, and double bit errors are detected. The ECC Aggregator is connected to these memory and interconnect components which have the ECC. The ECC aggregator provides access to control and monitor the ECC protected memories in a module or subsystem.

SDL provides support for ECC aggregator configuration. Each ECC aggregator instance can be independently configured through the same SDL API by passing a different instance. The safety manual also defines test-for-diagnostics for the various IPs with ECC/parity support. The SDL also provides the support for executing ECC aggregator self-tests, using the error injection feature of the ECC aggregator. The ECC aggregators should be configured at startup, after running BIST.

# Features Supported

The SDL provides support for the ECC through:

- ECC Configuration API
- ECC self-test API
- ECC error injection API
- ECC static register readback API

- ECC error status APIs

  The SDL ECC module requires a mapping of certain aggregator registers into the address space of the R5F Core. In these cases, the ECC module will use the DPL API SDL_DPL_addrTranslate() to get the address. The application must provide the mapped address through this call. This mapping is required for any ECC aggregator that is used which has an address which is not in the 32-bit address space. The mapping is expected to always be valid because it may be needed at runtime to get information about ECC errors that may be encountered.

    There are over 13 ECC aggregators on the device each supporting multiple memories and interconnects.

# Error Injection for Various RAM ID types

    There are two types of ECC aggregator RAM IDs supported on the device (wrapper and interconnect). The wrapper types are used for memories where local computations are performed for particular processing cores in the device, and the interconnect types are utilized for interconnect bus signals between cores or to/from peripherals.

For wrapper RAM ID types, after injecting an error, the memory associated with that RAM ID needs to be accessed in order to trigger the error interrupt event. It is the application's responsibility to trigger the error event through memory access after injecting the error.

# SysConfig Features

- None

# Features NOT Supported

- None

# Important Usage Guidelines

- None

# Example Usage of R5F ATCM0

The following shows an example of SDL R5F ECC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include <sdl/sdl_exception.h>
#include <sdl/r5/v0/interrupt.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00000510u) // R5F ATCM0 RAM address
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
int32_t retVal = 0;
uint32_t rd_data = 0;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x \r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action \r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
/* Clear DED MSS_CTRL register*/
SDL_REG32_WR(0x50D18094u, 0x01);
rd_data = SDL_REG32_RD(0x50D18094u);
printf("\r\nRead data of DED MSS_CTRL register is 0x%u\r\n",rd_data);
/* Clear DED RAW MSS_CTRL register*/
SDL_REG32_WR(0x50D18098u, 0x01);
rd_data = SDL_REG32_RD(0x50D18098u);
printf("\r\nRead data of DED RAW MSS_CTRL register is 0x%u\r\n",rd_data);
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
/* Clear SEC MSS_CTRL register*/
SDL_REG32_WR(0x50D18088u, 0x01);
rd_data = SDL_REG32_RD(0x50D18088u);
printf("\r\nRead data of SEC MSS_CTRL register is 0x%u\r\n",rd_data);
/* Clear SEC RAW MSS_CTRL register*/
SDL_REG32_WR(0x50D18084u, 0x01);
rd_data = SDL_REG32_RD(0x50D18084u);
printf("\r\nRead data of SEC RAW MSS_CTRL register is 0x%u\r\n",rd_data);
}
esmError = true;
return retVal;
}

This is the list of exception handle and the parameters

const SDL_R5ExptnHandlers ECC_Test_R5ExptnHandlers =
{
.udefExptnHandler = &SDL_EXCEPTION_undefInstructionExptnHandler,
.swiExptnHandler = &SDL_EXCEPTION_swIntrExptnHandler,
.pabtExptnHandler = &SDL_EXCEPTION_prefetchAbortExptnHandler,
.dabtExptnHandler = &SDL_EXCEPTION_dataAbortExptnHandler,
.irqExptnHandler = &SDL_EXCEPTION_irqExptnHandler,
.fiqExptnHandler = &SDL_EXCEPTION_fiqExptnHandler,
.udefExptnHandlerArgs = ((void *)0u),
.swiExptnHandlerArgs = ((void *)0u),
.pabtExptnHandlerArgs = ((void *)0u),
.dabtExptnHandlerArgs = ((void *)0u),
.irqExptnHandlerArgs = ((void *)0u),
};

Below are the functions used to print the which exception is occured

void ECC_Test_undefInstructionExptnCallback(void)
{
printf("\r\nUndefined Instruction exception\r\n");
}
void ECC_Test_swIntrExptnCallback(void)
{
printf("\r\nSoftware interrupt exception\r\n");
}
void ECC_Test_prefetchAbortExptnCallback(void)
{
printf("\r\nPrefetch Abort exception\r\n");
}
void ECC_Test_dataAbortExptnCallback(void)
{
printf("\r\nData Abort exception\r\n");
}
void ECC_Test_irqExptnCallback(void)
{
printf("\r\nIrq exception\r\n");
}
void ECC_Test_fiqExptnCallback(void)
{
printf("\r\nFiq exception\r\n");
}

Initilize Exception handler

void ECC_Test_exceptionInit(void)
{
SDL_EXCEPTION_CallbackFunctions_t exceptionCallbackFunctions =
{
.udefExptnCallback = ECC_Test_undefInstructionExptnCallback,
.swiExptnCallback = ECC_Test_swIntrExptnCallback,
.pabtExptnCallback = ECC_Test_prefetchAbortExptnCallback,
.dabtExptnCallback = ECC_Test_dataAbortExptnCallback,
.irqExptnCallback = ECC_Test_irqExptnCallback,
.fiqExptnCallback = ECC_Test_fiqExptnCallback,
};
/* Initialize SDL exception handler */
SDL_EXCEPTION_init(&exceptionCallbackFunctions);
/* Register SDL exception handler */
Intc_RegisterExptnHandlers(&ECC_Test_R5ExptnHandlers);
return;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_R5FSS0_CORE0_subMemTypeList[SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_R5FSS0_CORE0_ECCInitConfig =
{
.numRams = SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_R5FSS0_CORE0_subMemTypeList[0]),
};
SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00000000u, 0x00018000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00000000u, 0x000010000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00000000u, 0x00018000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Enabling the ECC module

SDL_ECC_UTILS_enableECCATCM();

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_R5FSS0_CORE0_ECCInitConfig);

Execute ECC R5F ATCM0 single bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_ATCM0_BANK0_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for R5FSS0 CORE0 ATCM0 BANK0 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Enabling the ECC module

SDL_ECC_UTILS_enableECCATCM();

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Execute ECC R5F ATCM0 double bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_ATCM0_BANK0_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Double bit error inject: starting \r\n");
/* Run one shot test for R5FSS0 CORE0 ATCM0 BANK0 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x30002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

# Example Usage of R5F BTCM

The following shows an example of SDL R5F ECC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include <sdl/sdl_exception.h>
#include <sdl/r5/v0/interrupt.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#if SDL_B0TCM0_BANK0
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00080010u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID
#endif
#if SDL_B0TCM0_BANK1
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00081510u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID
#endif
#if SDL_B1TCM0_BANK0
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00082510u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID
#endif
#if SDL_B1TCM0_BANK1
#define SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS (1u)
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00083510u) /* R5F BTCM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID
#endif

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
int32_t retVal = 0;
uint32_t rd_data = 0;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x \r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action \r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
/* Clear DED MSS_CTRL register*/
SDL_REG32_WR(0x50D18094u, 0x06);
rd_data = SDL_REG32_RD(0x50D18094u);
printf("\r\nRead data of DED MSS_CTRL register is 0x%u\r\n",rd_data);
/* Clear DED RAW MSS_CTRL register*/
SDL_REG32_WR(0x50D18098u, 0x06);
rd_data = SDL_REG32_RD(0x50D18098u);
printf("\r\nRead data of DED RAW MSS_CTRL register is 0x%u\r\n",rd_data);
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
/* Clear SEC MSS_CTRL register*/
SDL_REG32_WR(0x50D18088u, 0x6);
rd_data = SDL_REG32_RD(0x50D18088u);
printf("\r\nRead data of SEC MSS_CTRL register is 0x%u\r\n",rd_data);
/* Clear SEC RAW MSS_CTRL register*/
SDL_REG32_WR(0x50D18084u, 0x6);
rd_data = SDL_REG32_RD(0x50D18084u);
printf("\r\nRead data of SEC RAW MSS_CTRL register is 0x%u\r\n",rd_data);
}
esmError = true;
return retVal;
}

This is the list of exception handle and the parameters

const SDL_R5ExptnHandlers ECC_Test_R5ExptnHandlers =
{
.udefExptnHandler = &SDL_EXCEPTION_undefInstructionExptnHandler,
.swiExptnHandler = &SDL_EXCEPTION_swIntrExptnHandler,
.pabtExptnHandler = &SDL_EXCEPTION_prefetchAbortExptnHandler,
.dabtExptnHandler = &SDL_EXCEPTION_dataAbortExptnHandler,
.irqExptnHandler = &SDL_EXCEPTION_irqExptnHandler,
.fiqExptnHandler = &SDL_EXCEPTION_fiqExptnHandler,
.udefExptnHandlerArgs = ((void *)0u),
.swiExptnHandlerArgs = ((void *)0u),
.pabtExptnHandlerArgs = ((void *)0u),
.dabtExptnHandlerArgs = ((void *)0u),
.irqExptnHandlerArgs = ((void *)0u),
};

Below are the functions used to print the which exception is occured

void ECC_Test_undefInstructionExptnCallback(void)
{
printf("\r\nUndefined Instruction exception\r\n");
}
void ECC_Test_swIntrExptnCallback(void)
{
printf("\r\nSoftware interrupt exception\r\n");
}
void ECC_Test_prefetchAbortExptnCallback(void)
{
printf("\r\nPrefetch Abort exception\r\n");
}
void ECC_Test_dataAbortExptnCallback(void)
{
printf("\r\nData Abort exception\r\n");
}
void ECC_Test_irqExptnCallback(void)
{
printf("\r\nIrq exception\r\n");
}
void ECC_Test_fiqExptnCallback(void)
{
printf("\r\nFiq exception\r\n");
}

Initilize Exception handler

void ECC_Test_exceptionInit(void)
{
SDL_EXCEPTION_CallbackFunctions_t exceptionCallbackFunctions =
{
.udefExptnCallback = ECC_Test_undefInstructionExptnCallback,
.swiExptnCallback = ECC_Test_swIntrExptnCallback,
.pabtExptnCallback = ECC_Test_prefetchAbortExptnCallback,
.dabtExptnCallback = ECC_Test_dataAbortExptnCallback,
.irqExptnCallback = ECC_Test_irqExptnCallback,
.fiqExptnCallback = ECC_Test_fiqExptnCallback,
};
/* Initialize SDL exception handler */
SDL_EXCEPTION_init(&exceptionCallbackFunctions);
/* Register SDL exception handler */
Intc_RegisterExptnHandlers(&ECC_Test_R5ExptnHandlers);
return;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_R5FSS0_CORE0_subMemTypeList[SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_R5FSS0_CORE0_ECCInitConfig =
{
.numRams = SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_R5FSS0_CORE0_subMemTypeList[0]),
};
SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00000000u, 0x00018000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00000000u, 0x00010000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00000000u, 0x00018000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Enabling the ECC module

#if (SDL_B0TCM0_BANK0) || (SDL_B0TCM0_BANK1)
/*Enabling the B0TCM ECC module*/
SDL_ECC_UTILS_enableECCB0TCM();
#endif
#if (SDL_B1TCM0_BANK0) || (SDL_B1TCM0_BANK1)
/*Enabling the B0TCM ECC module*/
SDL_ECC_UTILS_enableECCB1TCM();
#endif

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_R5FSS0_CORE0_ECCInitConfig);

Execute ECC R5F BTCM single bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_BTCM_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 BTCM Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for R5FSS0 CORE0 BTCM 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 BTCM Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Execute ECC R5F BTCM double bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_BTCM_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 BTCM Double bit error inject: starting \r\n");
/* Run one shot test for R5FSS0 CORE0 BTCM 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 BTCM Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

# Example Usage of MSS L2

The following shows an example of SDL MSS L2 API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x70100008u) /* MSS_L2_SLV2 address */
#define SDL_EXAMPLE_ECC_AGGR SDL_SOC_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID
#define SDL_MSS_L2_MEM_INIT_ADDR (0x50D00240u)
#define SDL_MSS_L2_MEM_INIT_DONE_ADDR (0x50D00244u)
#define SDL_ECC_AGGR_ERROR_STATUS1_ADDR (0x53000020u)
#define SDL_ECC_MSS_L2_BANK_MEM_INIT (0xcu) /* Bank 3 */

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
SDL_ECC_MemType eccmemtype;
SDL_Ecc_AggrIntrSrc eccIntrSrc;
SDL_ECC_ErrorInfo_t eccErrorInfo;
int32_t retVal;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x\r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf(" \r\nTake action \r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
}
retVal = SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);
/* Any additional customer specific actions can be added here */
retVal = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);
printf("\r\nECC Error Call back function called : eccMemType %d, errorSrc 0x%x, " \
"ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\r\n",
eccmemtype, eccIntrSrc, eccErrorInfo.memSubType, (uint32_t)(eccErrorInfo.bitErrorOffset >> 32),
(uint32_t)(eccErrorInfo.bitErrorOffset & 0x00000000FFFFFFFF), eccErrorInfo.bitErrorGroup);
if (eccErrorInfo.injectBitErrCnt != 0)
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, eccErrorInfo.injectBitErrCnt);
}
else
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, eccErrorInfo.bitErrCnt);
}
retVal = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
esmError = true;
return retVal;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MSS_L2_subMemTypeList[SDL_MSS_L2_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MSS_L2_ECCInitConfig =
{
.numRams = SDL_MSS_L2_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MSS_L2_subMemTypeList[0]),
};

Event BitMap for ECC ESM callback for MSS

SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00180000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00180000u, 0x000000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00180000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialization of MSS L2 memory

/* Clear Done memory*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, 0xfu);
/* Initialization of MSS L2 memory*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);
while(SDL_REG32_RD(SDL_MSS_L2_MEM_INIT_DONE_ADDR)!=SDL_ECC_MSS_L2_BANK_MEM_INIT);
/* Clear Done memory after MEM init*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

Clearing any old interrupt presented

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MSS_ECCInitConfig);

Execute ECC MSS L2 single bit inject test

int32_t ECC_Test_run_MSS_L2RAMB_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMSS L2 RAMB Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for MSS L2 RAMB 1 bit error */
injectErrorConfig.flipBitMask = 0x002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nMSS L2 RAMB Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Initialization of MSS L2 memory

SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);
while(SDL_REG32_RD(SDL_MSS_L2_MEM_INIT_DONE_ADDR)!=SDL_ECC_MSS_L2_BANK_MEM_INIT);
/* Clear Done memory after MEM init*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

Clearing any old interrupt presented

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Initialize ECC Memory

SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Execute ECC MSS L2 double bit inject test

int32_t ECC_Test_run_MSS_L2RAMB_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMSS L2 RAMB Double bit error inject: starting \r\n");
/* Run one shot test for MSS L2 RAMB 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x30002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
if (result != SDL_PASS ) {
retVal = -1;
} else {
DebugP_log("\r\nMSS L2 RAMB Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

# Example Usage of MSS TPTC

The following shows an example of SDL MSS TPTC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <drivers/edma.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include <sdl/sdl_ecc.h>
#include "ecc_main.h"

Below are the macros specifies the ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_MSS_MAX_MEM_SECTIONS (1u)
#define SDL_ECC_SEC (1U)
#define SDL_ECC_DED (2U)
#define SDL_EXAMPLE_ECC_AGGR SDL_SOC_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
SDL_ECC_MemType eccmemtype;
SDL_Ecc_AggrIntrSrc eccIntrSrc;
SDL_ECC_ErrorInfo_t eccErrorInfo;
int32_t retVal;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x\r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf(" \r\nTake action \r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
}
retVal = SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);
/* Any additional customer specific actions can be added here */
retVal = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);
printf("\r\nECC Error Call back function called : eccMemType %d, errorSrc 0x%x, " \
"ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\r\n",
eccmemtype, eccIntrSrc, eccErrorInfo.memSubType, (uint32_t)(eccErrorInfo.bitErrorOffset >> 32),
(uint32_t)(eccErrorInfo.bitErrorOffset & 0x00000000FFFFFFFF), eccErrorInfo.bitErrorGroup);
if (eccErrorInfo.injectBitErrCnt != 0)
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, eccErrorInfo.injectBitErrCnt);
}
else
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, eccErrorInfo.bitErrCnt);
}
retVal = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
esmError = true;
return retVal;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MSS_subMemTypeList[SDL_MSS_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MSS_ECCInitConfig =
{
.numRams = SDL_MSS_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MSS_subMemTypeList[0]),
};

Event BitMap for ECC ESM callback for MSS

SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00180000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00180000u, 0x000000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00180000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialization of EDMA and ECC injection

/* EDMA transfer with ECC single bit injection*/
testResult = edma_interrupt_transfer(CONFIG_EDMA0, SDL_ECC_SEC, 0u, EDMA_MSS_TPCC_A_EVT_FREE_0);

Initialize EDMA

EDMA_Init();
DebugP_log("\r\n[EDMA] Interrupt Transfer Test Started...\r\n");
baseAddr = EDMA_getBaseAddr(gEdmaHandle[edmaConfigNum]);
regionId = EDMA_getRegionId(gEdmaHandle[edmaConfigNum]);
dmaCh = channelEvent;
status = EDMA_allocDmaChannel(gEdmaHandle[edmaConfigNum], &dmaCh);
tcc = channelEvent;
status = EDMA_allocTcc(gEdmaHandle[edmaConfigNum], &tcc);
param = channelEvent;
status = EDMA_allocParam(gEdmaHandle[edmaConfigNum], &param);

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MSS_ECCInitConfig);

Execute ECC MSS TPTC single bit inject test

int32_t ECC_Test_run_MSS_TPTC_A0_1Bit_InjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
DebugP_log("\n MSS TPTC_A0 Single bit error inject: test starting");
injectErrorConfig.pErrMem = (uint32_t *)(0x0u);
/* Run one shot test for MSS TPTC_A0 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
DebugP_log("\n MSS TPTC_A0 Single bit error inject at pErrMem 0x%p test failed",
injectErrorConfig.pErrMem);
retVal = -1;
} else {
DebugP_log("\n MSS TPTC_A0 Single bit error inject at pErrMem 0x%p",
injectErrorConfig.pErrMem);
}
return retVal;
}

Execute ECC MSS TPTC double bit inject test

int32_t ECC_Test_run_MSS_TPTC_A0_2Bit_InjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
DebugP_log("\n MSS TPTC_A0 Double bit error inject: starting");
/* Run one shot test for MSS TPTC_A0 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(0x0u);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
DebugP_log("\n MSS TPTC_A0 Double bit error inject: at pErrMem 0x%p: fixed location once test failed",
injectErrorConfig.pErrMem);
retVal = -1;
} else {
DebugP_log("\n MSS TPTC_A0 Double bit error inject at pErrMem 0x%p ",
injectErrorConfig.pErrMem);
}
return retVal;
}

Initialize the source address with a pattern and initialize dst address with zero/another pattern (optional)

srcBuffPtr = (uint8_t *) gEdmaTestSrcBuff;
dstBuffPtr = (uint8_t *) gEdmaTestDstBuff;
for(loopCnt = 0U; loopCnt < EDMA_TEST_BUFFER_SIZE; loopCnt++)
{
srcBuffPtr[loopCnt] = (uint8_t)loopCnt;
dstBuffPtr[loopCnt] = 0;
}
CacheP_wb((void *)srcBuffPtr, EDMA_TEST_BUFFER_SIZE, CacheP_TYPE_ALL);
CacheP_wb((void *)dstBuffPtr, EDMA_TEST_BUFFER_SIZE, CacheP_TYPE_ALL);
/* Request channel */
EDMA_configureChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA,
dmaCh, tcc, param, queueType);
/* Program Param Set */
EDMA_ccPaRAMEntry_init(&edmaParam);
edmaParam.srcAddr = (uint32_t) SOC_virtToPhy(srcBuffPtr);
edmaParam.destAddr = (uint32_t) SOC_virtToPhy(dstBuffPtr);
edmaParam.aCnt = (uint16_t) EDMA_TEST_A_COUNT;
edmaParam.bCnt = (uint16_t) EDMA_TEST_B_COUNT;
edmaParam.cCnt = (uint16_t) EDMA_TEST_C_COUNT;
edmaParam.bCntReload = (uint16_t) EDMA_TEST_B_COUNT;
edmaParam.srcBIdx = (int16_t) EDMA_PARAM_BIDX(EDMA_TEST_A_COUNT);
edmaParam.destBIdx = (int16_t) EDMA_PARAM_BIDX(EDMA_TEST_A_COUNT);
edmaParam.srcCIdx = (int16_t) EDMA_TEST_A_COUNT;
edmaParam.destCIdx = (int16_t) EDMA_TEST_A_COUNT;
edmaParam.linkAddr = 0xFFFFU;
edmaParam.srcBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(EDMA_TEST_A_COUNT);
edmaParam.destBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(EDMA_TEST_A_COUNT);
edmaParam.opt |=
(EDMA_OPT_TCINTEN_MASK | EDMA_OPT_ITCINTEN_MASK |
((((uint32_t)tcc) << EDMA_OPT_TCC_SHIFT) & EDMA_OPT_TCC_MASK));
EDMA_setPaRAM(baseAddr, param, &edmaParam);
status = SemaphoreP_constructBinary(&gEdmaTestDoneSem, 0);
/* Register interrupt */
intrObj.tccNum = tcc;
intrObj.cbFxn = &EDMA_regionIsrFxn;
intrObj.appData = (void *) &gEdmaTestDoneSem;
status = EDMA_registerIntr(gEdmaHandle[edmaConfigNum], &intrObj);
/*
* Transfer is done in A sync mode
* Number of triggers required are B_COUNT * C_COUNT
*/
for(loopCnt = 0; loopCnt < (EDMA_TEST_B_COUNT * EDMA_TEST_C_COUNT); loopCnt++)
{
EDMA_enableTransferRegion(
baseAddr, regionId, dmaCh, EDMA_TRIG_MODE_MANUAL);
SemaphoreP_pend(&gEdmaTestDoneSem, SystemP_WAIT_FOREVER);
}
/* Invalidate destination buffer and compare with src buffer */
CacheP_inv((void *)dstBuffPtr, EDMA_TEST_BUFFER_SIZE, CacheP_TYPE_ALL);
for(loopCnt = 0; loopCnt < EDMA_TEST_BUFFER_SIZE; loopCnt++)
{
if(srcBuffPtr[loopCnt] != dstBuffPtr[loopCnt])
{
DebugP_log("Error matching value at src and dst address %d\r\n", loopCnt);
status = SystemP_FAILURE;
result = SDL_EFAIL;
break;
}
}
status = EDMA_unregisterIntr(gEdmaHandle[edmaConfigNum], &intrObj);
SemaphoreP_destruct(&gEdmaTestDoneSem);
/* Free channel */
EDMA_freeChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA,
dmaCh, EDMA_TRIG_MODE_MANUAL, tcc, EDMA_TEST_EVT_QUEUE_NO);
/* Free the EDMA resources managed by driver. */
status = EDMA_freeDmaChannel(gEdmaHandle[edmaConfigNum], &dmaCh);
status = EDMA_freeTcc(gEdmaHandle[edmaConfigNum], &tcc);
status = EDMA_freeParam(gEdmaHandle[edmaConfigNum], &param);
if(status == SystemP_SUCCESS)
{
DebugP_log("\r\n[EDMA] Interrupt Transfer Test Completed!!\r\n");
if(esmError == TRUE)
{
DebugP_log("\r\nAll tests have passed!!\r\n");
esmError = false;
}
else
{
result = SDL_EFAIL;
DebugP_log("\r\nESM interrupt is not occurred.... Test is failed!!\r\n");
}
}
else
{
result = SDL_EFAIL;
DebugP_log("\r\nSome tests have failed!!\r\n");
}
EDMA_Deinit();

# Example Usage of MCAN

Include the below file to access the APIs

#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x52600000u) /*MCAN0 address*/
#define SDL_EXAMPLE_ECC_AGGR SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MCANA_subMemTypeList[SDL_MCANA_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MCANA_ECCInitConfig =
{
.numRams = SDL_MCANA_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MCANA_subMemTypeList[0]),
};

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
SDL_ECC_MemType eccmemtype;
SDL_Ecc_AggrIntrSrc eccIntrSrc;
SDL_ECC_ErrorInfo_t eccErrorInfo;
int32_t retVal;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x\r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action\r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
}
retVal = SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);
/* Any additional customer specific actions can be added here */
retVal = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);
printf("\r\nECC Error Call back function called : eccMemType %d, errorSrc 0x%x, " \
"ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\r\n",
eccmemtype, eccIntrSrc, eccErrorInfo.memSubType, (uint32_t)(eccErrorInfo.bitErrorOffset >> 32),
(uint32_t)(eccErrorInfo.bitErrorOffset & 0x00000000FFFFFFFF), eccErrorInfo.bitErrorGroup);
if (eccErrorInfo.injectBitErrCnt != 0)
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, eccErrorInfo.injectBitErrCnt);
}
else
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, eccErrorInfo.bitErrCnt);
}
retVal = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
esmError = true;
return retVal;
}

Event BitMap for ECC ESM callback for MCAN

SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x0000000cu, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00000008u, 0x000000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x0000000cu, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MCANA_ECCInitConfig);

Write some data to the RAM memory before injecting

for(i=1;i<=num_of_iterations;i++){
wr_data = (i)<<24 | (i)<<16 | (i)<<8 | i;
SDL_REG32_WR(addr+i*16, wr_data);
}

Execute ECC MCAN single bit inject test

int32_t ECC_Test_run_MCANA_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMCANA Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for MCANA 1 bit error */
injectErrorConfig.flipBitMask = 0x002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nMCANA Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Read data from the RAM memory after injecting

for(i=1;i<=num_of_iterations;i++){
rd_data = SDL_REG32_RD(addr+i*16);
DebugP_log("\r\nRead data = 0x%p\r\n",rd_data);
}

Write some data to the RAM memory before injecting

for(i=1;i<=num_of_iterations;i++){
wr_data = (i)<<24 | (i)<<16 | (i)<<8 | i;
SDL_REG32_WR(addr+i*16, wr_data);
}

Execute ECC MCAN double bit inject test

int32_t ECC_Test_run_MCANA_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMCANA double bit error inject: starting \r\n");
/* Run one shot test for MCANA 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
if (result != SDL_PASS ) {
retVal = -1;
} else {
DebugP_log("\r\nMCANA Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Read data from the RAM memory after injecting

for(i=1;i<=num_of_iterations;i++){
rd_data = SDL_REG32_RD(addr+i*16);
DebugP_log("\r\nRead data = 0x%p\r\n",rd_data);
}

# Example Usage of ICSSM

Include the below file to access the APIs

#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_ICSSM_DRAM0 (1U)
#define SDL_ICSSM_DRAM1 (0U)
#define SDL_ICSSM_PR1_PDSP0_IRAM (0U)
#define SDL_ICSSM_PR1_PDSP1_IRAM (0U)
#define SDL_ICSSM_RAM (0U)
#define SDL_ICSSM_MAX_MEM_SECTIONS (1u)
#if SDL_ICSSM_DRAM0
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x48000000u) /* ICSSM DRAM0 RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID
#endif
#if SDL_ICSSM_DRAM1
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x48002000u) /* ICSSM DRAM1 RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID
#endif
#if SDL_ICSSM_PR1_PDSP0_IRAM
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x48034000u) /* ICSSM PR1 PDSP0 IRAM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID
#endif
#if SDL_ICSSM_PR1_PDSP1_IRAM
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x48038000u) /* ICSSM PR1 PDSP1 IRAM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID
#endif
#if SDL_ICSSM_RAM
#define SDL_EXAMPLE_ECC_RAM_ADDR (0x48010000u) /* ICSSM RAM RAM address */
#define SDL_EXAMPLE_ECC_AGGR SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID
#endif

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_ICSSM_subMemTypeList[SDL_ICSSM_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_ICSSM_ECCInitConfig =
{
.numRams = SDL_ICSSM_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_ICSSM_subMemTypeList[0]),
};

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
SDL_ECC_MemType eccmemtype;
SDL_Ecc_AggrIntrSrc eccIntrSrc;
SDL_ECC_ErrorInfo_t eccErrorInfo;
int32_t retVal;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x\r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action\r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
}
retVal = SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);
/* Any additional customer specific actions can be added here */
retVal = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);
printf("\r\nECC Error Call back function called : eccMemType %d, errorSrc 0x%x, " \
"ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\r\n",
eccmemtype, eccIntrSrc, eccErrorInfo.memSubType, (uint32_t)(eccErrorInfo.bitErrorOffset >> 32),
(uint32_t)(eccErrorInfo.bitErrorOffset & 0x00000000FFFFFFFF), eccErrorInfo.bitErrorGroup);
if (eccErrorInfo.injectBitErrCnt != 0)
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, eccErrorInfo.injectBitErrCnt);
}
else
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, eccErrorInfo.bitErrCnt);
}
retVal = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
esmError = true;
return retVal;
}

Event BitMap for ECC ESM callback for ICSSM

SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00000000u, 0x00000000u, 0x00006000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00000000u, 0x00000000u, 0x00002000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00000000u, 0x00000000u, 0x00006000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_ICSSM_ECCInitConfig);

Execute ECC ICSSM single bit inject test

int32_t ECC_Test_run_ICSSM_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nICSSM Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for ICSSM 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nICSSM Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Execute ECC ICSSM double bit inject test

int32_t ECC_Test_run_ICSSM_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nICSSM Double bit error inject: starting \r\n");
/* Run one shot test for ICSSM 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nICSSM Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

# Example Usage of TCM Parity

Include the below file to access the APIs

#include "parity_main.h"

Below are the macros specifies the values need to set for TCM parity Error forcing

#define SDL_R5F0ATCM0 (0x7U)
#define SDL_R5F0B0TCM0 (0x700U)
#define SDL_R5F0B1TCM0 (0x70000U)
#define SDL_R5F0ATCM1 (0x70U)
#define SDL_R5F0B0TCM1 (0x7000U)
#define SDL_R5F0B1TCM1 (0x700000U)
#define SDL_R5F1ATCM0 (0x7U)
#define SDL_R5F1B0TCM0 (0x700U)
#define SDL_R5F1B1TCM0 (0x70000U)
#define SDL_R5F1ATCM1 (0x70U)
#define SDL_R5F1B0TCM1 (0x7000U)
#define SDL_R5F1B1TCM1 (0x700000U)

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
int32_t retVal = 0;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x \r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action \r\n");
/* Clears all the status registers */
SDL_clearStatusRegs(SetValue);
esmError = true;
return retVal;
}

Event BitMap for ESM callback for TCM Parity

SDL_ESM_config Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x0003C000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
.priorityBitmap = {0x0000C000u, 0x000000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x0003C000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Execute TCM Parity Error injection for B0TCM0 for R5FSS0 core 0

if (retVal == 0)
{
DebugP_log("\r\nTCM PARITY:B0TCM0 Started\r\n");
retValue = SDL_ECC_TCMParity(SDL_R5SS0_CPU0_TCM,\
SDL_R5FSS0_CORE0__B0TCM0,\
SDL_R5F0B0TCM0);
DebugP_log("\r\nTCM Parity Status for B0TCM0 = 0x%x\r\n", retValue);
if (retValue != 0)
{
retVal = 0;
DebugP_log("\r\nB0TCM0 Parity : Completed\r\n");
}
else{
retVal = -1;
DebugP_log("\r\nB0TCM0 Parity : Failed\r\n");
}
}

# Example Usage of DMA Parity

Include the below file to access the APIs

#include "parity_main.h"

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
int32_t retVal = 0;
printf("\r\nESM Call back function called : instType 0x%x, " \
"grpChannel 0x%x, intSrc 0x%x \r\n",
esmInst, grpChannel, intSrc);
printf("\r\nTake action \r\n");
/* Disable parity for TPCC0 */
SDL_REG32_WR(0x50D18180, 0x1000);
esmError = true;
return retVal;
}

Event BitMap for ESM callback for TCM Parity

SDL_ESM_config Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00000000u, 0x80000000u, 0x00000010u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
.priorityBitmap = {0x00000000u, 0x80000000u, 0x00000010u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00000000u, 0x80000000u, 0x00000010u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Execute TPCC Parity Error injection

if (retVal == 0)
{
DebugP_log("\r\nTPCC PARITY : TPCC0 Started\r\n");
retVal = SDL_ECC_TPCCParity(SDL_TPCC0, \
0x11);
DebugP_log("\r\nParam Register = %x\r\n", retVal);
/* wait for delay */
for (i =0 ; i < 200 ; i = i + 1 );
/* Wait until ESM interrupt happens */
while(esmError !=true);
if(esmError == true)
{
DebugP_log("\r\nTPCC PARITY : TPCC0 Completed\r\n");
esmError = false;
}
else{
result = SDL_EFAIL;
}
}

# API

APIs for SDL ECC (ECC_AGGR)

EDMA_registerIntr
int32_t EDMA_registerIntr(EDMA_Handle handle, Edma_IntrObject *intrObj)
Function to register callback function for a TCC.
SDL_ESM_IntType
SDL_ESM_IntType
Definition: esm/v2/sdl_esm.h:90
SDL_ECC_InitConfig_t
Definition: sdl_ecc.h:368
SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL
#define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL
Definition: V1/sdl_ip_ecc.h:160
SDL_ECC_initMemory
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_ECC_ErrorInfo_t::memSubType
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:398
SDL_ECC_InitConfig_t::numRams
uint32_t numRams
Definition: sdl_ecc.h:369
SDL_R5ExptnHandlers
Structure containing the Exception Handlers. If application does not want register an exception handl...
Definition: sdl_interrupt.h:111
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:309
SDL_ECC_injectError
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
EDMA_freeTcc
int32_t EDMA_freeTcc(EDMA_Handle handle, uint32_t *tcc)
Function to free the tcc Channel.
SDL_ECC_ackIntr
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
SDL_ESM_config
ESM init configuration.
Definition: esm/v2/sdl_esm.h:180
SOC_virtToPhy
uint64_t SOC_virtToPhy(void *virtAddr)
SOC Virtual (CPU) to Physical address translation function.
SDL_EXCEPTION_swIntrExptnHandler
void SDL_EXCEPTION_swIntrExptnHandler(void *param)
SW Interrupt Exception Handler.
EDMA_enableTransferRegion
uint32_t EDMA_enableTransferRegion(uint32_t baseAddr, uint32_t regionId, uint32_t chNum, uint32_t trigMode)
Start EDMA transfer on the specified channel.
EDMA_unregisterIntr
int32_t EDMA_unregisterIntr(EDMA_Handle handle, Edma_IntrObject *intrObj)
Function to unregister callback function for a TCC.
SDL_EXCEPTION_undefInstructionExptnHandler
void SDL_EXCEPTION_undefInstructionExptnHandler(void *param)
Undefined Instruction Exception Handler.
EDMA_getRegionId
uint32_t EDMA_getRegionId(EDMA_Handle handle)
Function to get the edma region.
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:66
SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT
#define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT
Definition: V1/sdl_ip_ecc.h:162
SDL_EXCEPTION_prefetchAbortExptnHandler
void SDL_EXCEPTION_prefetchAbortExptnHandler(void *param)
Prefetch Abort Exception Handler.
Intc_RegisterExptnHandlers
void Intc_RegisterExptnHandlers(const SDL_R5ExptnHandlers *handlers)
This function registers handlers for various exceptions.
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
EDMA_PARAM_BIDX_EXT
#define EDMA_PARAM_BIDX_EXT(val)
Definition: edma/v0/edma.h:138
SDL_ECC_UTILS_enableECCB0TCM
void SDL_ECC_UTILS_enableECCB0TCM(void)
EDMA_CHANNEL_TYPE_DMA
#define EDMA_CHANNEL_TYPE_DMA
Values that can be used for parameter chType in API's.
Definition: edma/v0/edma.h:161
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:307
EDMA_freeDmaChannel
int32_t EDMA_freeDmaChannel(EDMA_Handle handle, uint32_t *dmaCh)
Function to free the Dma Channel.
SDL_REG32_WR
#define SDL_REG32_WR(p, v)
This macro writes a 32-bit value to a hardware register.
Definition: sdlr.h:127
SDL_ECC_ErrorInfo_t::bitErrorGroup
uint32_t bitErrorGroup
Definition: sdl_ecc.h:406
EDMA_getBaseAddr
uint32_t EDMA_getBaseAddr(EDMA_Handle handle)
Function to get the edma base address.
edma.h
EDMA_OPT_TCC_MASK
#define EDMA_OPT_TCC_MASK
Definition: edma/v0/edma.h:294
DebugP_log
#define DebugP_log(format,...)
Function to log a string to the enabled console.
Definition: DebugP.h:235
EDMA_allocDmaChannel
int32_t EDMA_allocDmaChannel(EDMA_Handle handle, uint32_t *dmaCh)
Function to allocate the Dma Channel.
SDL_ECC_InjectErrorConfig_t
Definition: sdl_ecc.h:381
SDL_ECC_UTILS_enableECCATCM
void SDL_ECC_UTILS_enableECCATCM(void)
EDMA_OPT_ITCINTEN_MASK
#define EDMA_OPT_ITCINTEN_MASK
Definition: edma/v0/edma.h:292
SDL_ECC_InjectErrorConfig_t::pErrMem
uint32_t * pErrMem
Definition: sdl_ecc.h:382
SemaphoreP_destruct
void SemaphoreP_destruct(SemaphoreP_Object *obj)
Cleanup, delete, destruct a semaphore object.
CacheP_inv
void CacheP_inv(void *addr, uint32_t size, uint32_t type)
Cache invalidate for a specified region.
SDL_EXCEPTION_irqExptnHandler
void SDL_EXCEPTION_irqExptnHandler(void *param)
IRQ Exception Handler.
EDMA_OPT_TCINTEN_MASK
#define EDMA_OPT_TCINTEN_MASK
Definition: edma/v0/edma.h:290
SystemP_SUCCESS
#define SystemP_SUCCESS
Return status when the API execution was successful.
Definition: SystemP.h:56
SDL_ECC_ErrorInfo_t::bitErrorOffset
uint64_t bitErrorOffset
Definition: sdl_ecc.h:408
SDL_ECC_InjectErrorConfig_t::flipBitMask
uint32_t flipBitMask
Definition: sdl_ecc.h:384
sdl_exception.h
Header file contains enumerations, structure definitions and function declarations for SDL EXCEPTION ...
SDL_EXCEPTION_init
void SDL_EXCEPTION_init(const SDL_EXCEPTION_CallbackFunctions_t *callbackFunctions)
Initialise Exception module.
EDMA_freeChannelRegion
uint32_t EDMA_freeChannelRegion(uint32_t baseAddr, uint32_t regionId, uint32_t chType, uint32_t chNum, uint32_t trigMode, uint32_t tccNum, uint32_t evtQNum)
Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set,...
SDL_EXCEPTION_CallbackFunctions_t
Structure of call back functions for various exception events.
Definition: sdl_exception.h:74
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_ESM_Inst
SDL_ESM_Inst
Definition: sdl_esm_soc.h:65
SystemP_FAILURE
#define SystemP_FAILURE
Return status when the API execution was not successful due to a failure.
Definition: SystemP.h:61
EDMA_PARAM_BIDX
#define EDMA_PARAM_BIDX(val)
Definition: edma/v0/edma.h:135
EDMA_OPT_TCC_SHIFT
#define EDMA_OPT_TCC_SHIFT
Definition: edma/v0/edma.h:296
EDMA_TRIG_MODE_MANUAL
#define EDMA_TRIG_MODE_MANUAL
Definition: edma/v0/edma.h:147
CacheP_TYPE_ALL
#define CacheP_TYPE_ALL
Definition: CacheP.h:78
SDL_REG32_RD
#define SDL_REG32_RD(p)
This macro reads a 32-bit value from a hardware register and returns the value.
Definition: sdlr.h:118
SDL_Ecc_AggrIntrSrc
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:181
SDL_ECC_getESMErrorInfo
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
SDL_ESM_config::esmErrorConfig
SDL_ESM_ErrorConfig_t esmErrorConfig
Definition: esm/v2/sdl_esm.h:181
SDL_ESM_init
int32_t SDL_ESM_init(SDL_ESM_Inst instance, const SDL_ESM_config *pConfig, SDL_ESM_applicationCallback applicationCallback, void *appArg)
SDL ESM API to initialize an ESM instance. The API initializes the specified ESM instance with the pr...
EDMA_freeParam
int32_t EDMA_freeParam(EDMA_Handle handle, uint32_t *param)
Function to free the Param.
SDL_UTILS_enable_event_bus
void SDL_UTILS_enable_event_bus(void)
SDL_R5ExptnHandlers::udefExptnHandler
exptnHandlerPtr udefExptnHandler
Definition: sdl_interrupt.h:112
SDL_ECC_ErrorInfo_t
Definition: sdl_ecc.h:395
EDMA_configureChannelRegion
uint32_t EDMA_configureChannelRegion(uint32_t baseAddr, uint32_t regionId, uint32_t chType, uint32_t chNum, uint32_t tccNum, uint32_t paramId, uint32_t evtQNum)
Request a DMA/QDMA/Link channel.
EDMA_allocParam
int32_t EDMA_allocParam(EDMA_Handle handle, uint32_t *param)
Function to allocate Param Set.
SemaphoreP_constructBinary
int32_t SemaphoreP_constructBinary(SemaphoreP_Object *obj, uint32_t initValue)
Create a binary semaphore object.
TRUE
#define TRUE
Definition: os_defs.h:29
SDL_ECC_MemSubType
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:341
CacheP_wb
void CacheP_wb(void *addr, uint32_t size, uint32_t type)
Cache writeback for a specified region.
EDMA_setPaRAM
void EDMA_setPaRAM(uint32_t baseAddr, uint32_t paRAMId, const EDMACCPaRAMEntry *newPaRAM)
Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/Link).
SDL_ECC_UTILS_enableECCB1TCM
void SDL_ECC_UTILS_enableECCB1TCM(void)
SDL_ECC_clearNIntrPending
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
SDL_ECC_ErrorInfo_t::injectBitErrCnt
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:404
SDL_ECC_getErrorInfo
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
SDL_ECC_ErrorInfo_t::bitErrCnt
uint32_t bitErrCnt
Definition: sdl_ecc.h:402
SDL_EXCEPTION_fiqExptnHandler
void SDL_EXCEPTION_fiqExptnHandler(void *param)
FIQ Exception Handler.
SDL_EXCEPTION_dataAbortExptnHandler
void SDL_EXCEPTION_dataAbortExptnHandler(void *param)
Data Abort Exception Handler.
EDMA_ccPaRAMEntry_init
void EDMA_ccPaRAMEntry_init(EDMACCPaRAMEntry *paramEntry)
Clear a PaRAM Set .
SDL_ECC_MemType
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:348
SDL_ECC_init
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SemaphoreP_pend
int32_t SemaphoreP_pend(SemaphoreP_Object *obj, uint32_t timeToWaitInTicks)
Pend on a semaphore object or lock a mutex.
EDMA_allocTcc
int32_t EDMA_allocTcc(EDMA_Handle handle, uint32_t *tcc)
Function to allocate Tcc.
SDL_EXCEPTION_CallbackFunctions_t::udefExptnCallback
SDL_EXCEPTION_Callback_t udefExptnCallback
Definition: sdl_exception.h:75