AM261x MCU+ SDK: sdl_ecc_soc.h Source File

| AM261x MCU+ SDK 26.00.00 |

sdl_ecc_soc.h
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1 /*
2 * SDL ECC
3 *
4 * Software Diagnostics Library module for ECC
5 *
6 * Copyright (c) Texas Instruments Incorporated 2022-2025
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 */
37
52 #ifndef INCLUDE_SDL_ECC_SOC_H_
53 #define INCLUDE_SDL_ECC_SOC_H_
54
55 #include <stdint.h>
56 #include <sdl/sdl_ecc.h>
57 #include <sdl/ecc/sdl_ip_ecc.h>
58 #include <sdl/include/sdl_types.h>
59 #include <sdl/esm/soc/am261x/sdl_esm_core.h>
60 #include <sdl/ecc/sdl_ecc_priv.h>
61 #include <sdl/include/am261x/sdlr_soc_ecc_aggr.h>
62 #include <sdl/include/am261x/soc_config.h>
63 #include <sdl/include/am261x/sdlr_intr_esm0.h>
64 #include <sdl/include/am261x/sdlr_soc_baseaddress.h>
65 #include <sdl/include/am261x/sdlr_intr_r5fss0_core0.h>
66 #include <sdl/include/am261x/sdlr_intr_r5fss0_core1.h>
67 #include <sdl/include/am261x/sdlr_param_regs.h>
68
69 #define SDL_ECC_WIDTH_UNDEFINED 0x1
70
71 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
72 #define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (6U)
73 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
74 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
75 #define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (10U)
76 #define SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
77 #define SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
78 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
79 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
80 #define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
81 #define SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
82 #define SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
83 #define SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
84 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (12U)
85
86 #define SDL_CPSW0_ECC_U_BASE (SDL_CPSW0_U_BASE + 0x3f000u)
87 #define SDL_OSPI_ECC_U_BASE (0x53807000u)
88 #define SDL_FOTA_ECC_U_BASE (0x5380F000u)
89
90 /* define parity control register addresses */
91 /* R5FSS0 */
92 #define SDL_R5FSS0_CORE0_TCM_ERR_STATUS (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS)
93 #define SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)
94 #define SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_TCM_ADDRPARITY_ERRFORCE)
95
96 #define SDL_R5FSS0_CORE1_TCM_ERR_STATUS (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS)
97 #define SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW)
98
99 /* TPCC */
100 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_CTRL)
101 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_PARITY_STATUS)
102
103 #define SDL_TPCC0_ERRAGG_STATUS (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_STATUS)
104 #define SDL_TPCC0_ERRAGG_MASK (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TPCC0_ERRAGG_MASK)
105
106 /* TMU */
107 #define SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL)
108 #define SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL (SDL_MSS_CTRL_U_BASE+SDL_MSS_CTRL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL)
109 #define SDL_TMU0_ROM_PARITY_EN (0x1U)
110 #define SDL_TMU0_ROM_PARITY_FORCE_ERR (0x2U)
111 #define SDL_TMU0_ROM_PARITY_ERR_CLR (0x10000U)
112
113 /*param registers */
114 #define SDL_PARAM_REG_1 (SDL_PARAM_REG_SET0 + 0x20U)
115 #define SDL_PARAM_REG_2 (SDL_PARAM_REG_SET0 + 0x30U)
116
122 static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
123 {
124 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
125 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
126 };
127
133 static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
134 {
135 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
136 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
137 };
138
143 static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
144 {
145 { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID, 0x70000000u,
146 SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_SIZE, 8u,
147 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
148 { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID, 0x70080000u,
149 SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_SIZE, 8u,
150 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
151 { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID, 0x70100000u,
152 SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_SIZE, 8u,
153 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
154 { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID, 0x72000000u,
155 SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_SIZE, 8u,
156 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
157 { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID, 0u,
158 SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_SIZE, 8u,
159 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
160 { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID, 0u,
161 SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_SIZE, 8u,
162 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
163 };
164
169 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
170 {
171 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
172 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
173 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
174 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
175 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
176 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
177 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
178 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
179 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
180 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
181 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
182 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
183 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
184 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
185 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
186 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
187 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
188 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
189 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
190 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
191 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
192 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
193 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
194 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
195 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
196 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
197 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
198 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
199 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
200 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
201 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
202 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
203 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
204 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
205 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
206 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
207 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
208 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
209 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
210 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
211 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
212 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
213 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
214 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
215 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
216 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
217 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
218 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
219 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
220 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
221 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
222 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
223 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
224 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
225 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
226 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
227 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
228 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
229 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
230 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
231 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
232 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
233 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
234 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
235 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
236 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
237 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x0u,
238 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
239 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
240 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
241 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
242 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
243 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
244 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
245 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
246 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
247 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
248 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
249 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
250 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
251 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
252 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
253 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
254 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
255 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_ID, 0,
256 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_SIZE, 4u,
257 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_ROW_WIDTH, ((bool)false) },
258 };
259
264 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
265 {
266 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
267 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
268 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
269 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
270 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
271 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
272 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
273 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
274 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
275 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
276 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
277 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
278 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
279 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
280 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
281 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
282 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
283 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
284 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
285 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
286 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
287 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
288 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
289 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
290 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
291 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
292 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
293 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
294 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
295 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
296 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
297 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
298 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
299 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
300 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
301 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
302 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
303 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
304 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
305 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
306 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
307 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
308 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
309 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
310 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
311 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
312 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
313 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
314 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
315 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
316 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
317 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
318 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
319 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
320 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
321 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
322 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
323 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
324 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
325 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
326 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
327 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
328 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
329 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0u,
330 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
331 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
332 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0u,
333 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
334 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
335 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00080000u,
336 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
337 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
338 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00080000u,
339 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
340 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
341 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00080000u,
342 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
343 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
344 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00080000u,
345 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
346 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
347 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
348 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
349 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
350 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_ID, 0,
351 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_SIZE, 4u,
352 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_ROW_WIDTH, ((bool)false) },
353 };
354
355
360 static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
361 {
362 { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID, 0u,
363 SDL_HSM_ECC_AGGR_RAMB0_RAM_SIZE, 4u,
364 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
365 { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID, 0u,
366 SDL_HSM_ECC_AGGR_RAMB1_RAM_SIZE, 4u,
367 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
368 { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID, 0u,
369 SDL_HSM_ECC_AGGR_RAMB2_RAM_SIZE, 4u,
370 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
371 { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID, 0u,
372 SDL_HSM_ECC_AGGR_RAMB3_RAM_SIZE, 4u,
373 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
374 { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID, 0u,
375 SDL_HSM_ECC_AGGR_SECUREB4_RAM_SIZE, 4u,
376 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
377 { SDL_HSM_ECC_AGGR_MBOX_RAM_ID, 0u,
378 SDL_HSM_ECC_AGGR_MBOX_RAM_SIZE, 4u,
379 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
380 { SDL_HSM_ECC_AGGR_SECURE_RAM_ID, 0u,
381 SDL_HSM_ECC_AGGR_SECURE_RAM_SIZE, 4u,
382 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
383 { SDL_HSM_ECC_AGGR_ROM_RAM_ID, 0u,
384 SDL_HSM_ECC_AGGR_ROM_RAM_SIZE, 4u,
385 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
386 { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID, 0u,
387 SDL_HSM_ECC_AGGR_TPTC_A0_RAM_SIZE, 8u,
388 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
389 { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID, 0u,
390 SDL_HSM_ECC_AGGR_TPTC_A1_RAM_SIZE, 8u,
391 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
392 };
393
398 static const SDL_MemConfig_t SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
399 {
400 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48000000u,
401 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
402 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
403 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48002000u,
404 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
405 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
406 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48034000u,
407 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
408 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
409 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x48038000u,
410 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
411 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
412 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48010000u,
413 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
414 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
415 };
416
421 static const SDL_MemConfig_t SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
422 {
423 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48600000u,
424 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
425 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
426 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48602000u,
427 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
428 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
429 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48634000u,
430 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
431 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
432 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x48638000u,
433 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
434 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
435 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48610000u,
436 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
437 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
438 };
439
444 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
445 {
446 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52600000u,
447 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
448 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
449 };
450
455 static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
456 {
457 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52610000u,
458 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
459 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
460 };
461
466 static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
467 {
468 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x5283E000u,
469 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
470 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
471 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
472 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
473 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
474 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
475 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
476 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
477 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
478 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
479 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
480 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
481 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
482 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
483 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
484 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
485 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
486 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
487 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
488 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
489 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x52832000u,
490 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
491 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
492 };
493
498 static const SDL_MemConfig_t SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries[SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
499 {
500 { SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_ID, 0x53807000u,
501 SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_SIZE, 4u,
502 SDL_FSS_OSPI_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
503 };
504
509 static const SDL_MemConfig_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
510 {
511 { SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_ID, 0x5380f000u,
512 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_SIZE, 4u,
513 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
514 };
515
520 static const SDL_MemConfig_t SDL_OSPI1_RAM_ECC_AGGR_MemEntries[SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
521 {
522 { SDL_OSPI1_RAM_ECC_AGGR_RAM_ID, 0x53807000u,
523 SDL_OSPI1_RAM_ECC_AGGR_RAM_SIZE, 4u,
524 SDL_OSPI1_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
525 };
526
531 static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS] =
532 {
533 { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID,
534 SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_INJECT_TYPE,
535 SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_ECC_TYPE,
536 0u,
537 NULL },
538 { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID,
539 SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_INJECT_TYPE,
540 SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_ECC_TYPE,
541 0u,
542 NULL },
543 { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,
544 SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_INJECT_TYPE,
545 SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_ECC_TYPE,
546 0u,
547 NULL },
548 { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID,
549 SDL_SOC_ECC_AGGR_MAILBOX_ECC_INJECT_TYPE,
550 SDL_SOC_ECC_AGGR_MAILBOX_ECC_ECC_TYPE,
551 0u,
552 NULL },
553 { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID,
554 SDL_SOC_ECC_AGGR_TPTC_A0_ECC_INJECT_TYPE,
555 SDL_SOC_ECC_AGGR_TPTC_A0_ECC_ECC_TYPE,
556 0u,
557 NULL },
558 { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID,
559 SDL_SOC_ECC_AGGR_TPTC_A1_ECC_INJECT_TYPE,
560 SDL_SOC_ECC_AGGR_TPTC_A1_ECC_ECC_TYPE,
561 0u,
562 NULL },
563 };
564
569 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
570 {
571 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
572 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
573 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
574 0u,
575 NULL },
576 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
577 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
578 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
579 0u,
580 NULL },
581 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
582 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
583 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
584 0u,
585 NULL },
586 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
587 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
588 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
589 0u,
590 NULL },
591 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
592 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
593 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
594 0u,
595 NULL },
596 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
597 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
598 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
599 0u,
600 NULL },
601 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
602 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
603 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
604 0u,
605 NULL },
606 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
607 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
608 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
609 0u,
610 NULL },
611 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
612 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
613 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
614 0u,
615 NULL },
616 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
617 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
618 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
619 0u,
620 NULL },
621 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
622 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
623 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
624 0u,
625 NULL },
626 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
627 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
628 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
629 0u,
630 NULL },
631 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
632 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
633 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
634 0u,
635 NULL },
636 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
637 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
638 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
639 0u,
640 NULL },
641 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
642 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
643 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
644 0u,
645 NULL },
646 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
647 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
648 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
649 0u,
650 NULL },
651 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
652 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
653 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
654 0u,
655 NULL },
656 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
657 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
658 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
659 0u,
660 NULL },
661 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
662 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
663 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
664 0u,
665 NULL },
666 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
667 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
668 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
669 0u,
670 NULL },
671 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
672 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
673 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
674 0u,
675 NULL },
676 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
677 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
678 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
679 0u,
680 NULL },
681 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
682 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
683 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
684 0u,
685 NULL },
686 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
687 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
688 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
689 0u,
690 NULL },
691 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
692 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
693 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
694 0u,
695 NULL },
696 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
697 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
698 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
699 0u,
700 NULL },
701 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
702 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
703 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
704 0u,
705 NULL },
706 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
707 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
708 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
709 0u,
710 NULL },
711 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_ID,
712 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_INJECT_TYPE,
713 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_ECC_TYPE,
714 0u,
715 NULL },
716 };
717
722 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
723 {
724 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
725 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
726 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
727 0u,
728 NULL },
729 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
730 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
731 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
732 0u,
733 NULL },
734 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
735 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
736 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
737 0u,
738 NULL },
739 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
740 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
741 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
742 0u,
743 NULL },
744 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
745 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
746 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
747 0u,
748 NULL },
749 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
750 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
751 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
752 0u,
753 NULL },
754 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
755 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
756 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
757 0u,
758 NULL },
759 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
760 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
761 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
762 0u,
763 NULL },
764 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
765 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
766 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
767 0u,
768 NULL },
769 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
770 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
771 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
772 0u,
773 NULL },
774 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
775 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
776 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
777 0u,
778 NULL },
779 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
780 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
781 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
782 0u,
783 NULL },
784 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
785 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
786 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
787 0u,
788 NULL },
789 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
790 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
791 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
792 0u,
793 NULL },
794 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
795 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
796 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
797 0u,
798 NULL },
799 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
800 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
801 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
802 0u,
803 NULL },
804 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
805 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
806 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
807 0u,
808 NULL },
809 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
810 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
811 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
812 0u,
813 NULL },
814 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
815 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
816 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
817 0u,
818 NULL },
819 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
820 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
821 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
822 0u,
823 NULL },
824 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
825 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
826 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
827 0u,
828 NULL },
829 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
830 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
831 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
832 0u,
833 NULL },
834 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
835 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
836 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
837 0u,
838 NULL },
839 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
840 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
841 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
842 0u,
843 NULL },
844 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
845 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
846 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
847 0u,
848 NULL },
849 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
850 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
851 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
852 0u,
853 NULL },
854 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
855 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
856 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
857 0u,
858 NULL },
859 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
860 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
861 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
862 0u,
863 NULL },
864 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_ID,
865 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_INJECT_TYPE,
866 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_ECC_TYPE,
867 0u,
868 NULL },
869 };
870
875 static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS] =
876 {
877 { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID,
878 SDL_HSM_ECC_AGGR_RAMB0_INJECT_TYPE,
879 SDL_HSM_ECC_AGGR_RAMB0_ECC_TYPE,
880 0u,
881 NULL },
882 { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID,
883 SDL_HSM_ECC_AGGR_RAMB1_INJECT_TYPE,
884 SDL_HSM_ECC_AGGR_RAMB1_ECC_TYPE,
885 0u,
886 NULL },
887 { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID,
888 SDL_HSM_ECC_AGGR_RAMB2_INJECT_TYPE,
889 SDL_HSM_ECC_AGGR_RAMB2_ECC_TYPE,
890 0u,
891 NULL },
892 { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID,
893 SDL_HSM_ECC_AGGR_RAMB3_INJECT_TYPE,
894 SDL_HSM_ECC_AGGR_RAMB3_ECC_TYPE,
895 0u,
896 NULL },
897 { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID,
898 SDL_HSM_ECC_AGGR_SECUREB4_INJECT_TYPE,
899 SDL_HSM_ECC_AGGR_SECUREB4_ECC_TYPE,
900 0u,
901 NULL },
902 { SDL_HSM_ECC_AGGR_MBOX_RAM_ID,
903 SDL_HSM_ECC_AGGR_MBOX_INJECT_TYPE,
904 SDL_HSM_ECC_AGGR_MBOX_ECC_TYPE,
905 0u,
906 NULL },
907 { SDL_HSM_ECC_AGGR_SECURE_RAM_ID,
908 SDL_HSM_ECC_AGGR_SECURE_INJECT_TYPE,
909 SDL_HSM_ECC_AGGR_SECURE_ECC_TYPE,
910 0u,
911 NULL },
912 { SDL_HSM_ECC_AGGR_ROM_RAM_ID,
913 SDL_HSM_ECC_AGGR_ROM_INJECT_TYPE,
914 SDL_HSM_ECC_AGGR_ROM_ECC_TYPE,
915 0u,
916 NULL },
917 { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID,
918 SDL_HSM_ECC_AGGR_TPTC_A0_INJECT_TYPE,
919 SDL_HSM_ECC_AGGR_TPTC_A0_ECC_TYPE,
920 0u,
921 NULL },
922 { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID,
923 SDL_HSM_ECC_AGGR_TPTC_A1_INJECT_TYPE,
924 SDL_HSM_ECC_AGGR_TPTC_A1_ECC_TYPE,
925 0u,
926 NULL },
927 };
928
933 static const SDL_RAMIdEntry_t SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
934 {
935 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
936 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
937 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
938 0u,
939 NULL },
940 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
941 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
942 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
943 0u,
944 NULL },
945 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
946 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
947 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
948 0u,
949 NULL },
950 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
951 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
952 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
953 0u,
954 NULL },
955 { SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
956 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
957 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
958 0u,
959 NULL },
960 };
961
966 static const SDL_RAMIdEntry_t SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
967 {
968 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
969 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
970 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
971 0u,
972 NULL },
973 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
974 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
975 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
976 0u,
977 NULL },
978 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
979 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
980 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
981 0u,
982 NULL },
983 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
984 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
985 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
986 0u,
987 NULL },
988 { SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
989 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
990 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
991 0u,
992 NULL },
993 };
994
999 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1000 {
1001 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1002 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1003 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1004 0u,
1005 NULL },
1006 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
1007 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
1008 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
1009 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
1010 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
1011 };
1012
1017 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1018 {
1019 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1020 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1021 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1022 0u,
1023 NULL },
1024 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
1025 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
1026 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
1027 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
1028 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
1029 };
1030
1035 static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS] =
1036 {
1037 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID,
1038 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_INJECT_TYPE,
1039 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ECC_TYPE,
1040 0u,
1041 NULL },
1042 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID,
1043 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_INJECT_TYPE,
1044 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ECC_TYPE,
1045 0u,
1046 NULL },
1047 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID,
1048 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_INJECT_TYPE,
1049 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ECC_TYPE,
1050 0u,
1051 NULL },
1052 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID,
1053 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_INJECT_TYPE,
1054 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ECC_TYPE,
1055 0u,
1056 NULL },
1057 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID,
1058 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_INJECT_TYPE,
1059 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ECC_TYPE,
1060 0u,
1061 NULL },
1062 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID,
1063 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_INJECT_TYPE,
1064 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ECC_TYPE,
1065 0u,
1066 NULL },
1067 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID,
1068 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_INJECT_TYPE,
1069 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ECC_TYPE,
1070 0u,
1071 NULL },
1072 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID,
1073 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_INJECT_TYPE,
1074 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_ECC_TYPE,
1075 0u,
1076 NULL },
1077 };
1078
1083 static const SDL_RAMIdEntry_t SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable[SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS] =
1084 {
1085 { SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_ID,
1086 SDL_FSS_OSPI_RAM_ECC_AGGR_INJECT_TYPE,
1087 SDL_FSS_OSPI_RAM_ECC_AGGR_ECC_TYPE,
1088 0u,
1089 NULL }
1090 };
1091
1096 static const SDL_RAMIdEntry_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS] =
1097 {
1098 { SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_ID,
1099 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_INJECT_TYPE,
1100 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_ECC_TYPE,
1101 0u,
1102 NULL }
1103 };
1104
1109 static const SDL_RAMIdEntry_t SDL_OSPI1_RAM_ECC_AGGR_RamIdTable[SDL_OSPI1_RAM_ECC_AGGR_NUM_RAMS] =
1110 {
1111 { SDL_OSPI1_RAM_ECC_AGGR_RAM_ID,
1112 SDL_OSPI1_RAM_ECC_AGGR_INJECT_TYPE,
1113 SDL_OSPI1_RAM_ECC_AGGR_ECC_TYPE,
1114 0u,
1115 NULL }
1116 };
1117
1118 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
1119 {
1120 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_TOP_U_BASE)),
1121 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE0_U_BASE)),
1122 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE1_U_BASE)),
1123 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_HSM_ECC_AGGR_U_BASE)),
1124 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_U_BASE)),
1125 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM1_ECC_BASE)),
1126 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_U_BASE)),
1127 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_U_BASE)),
1128 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_U_BASE)),
1129 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_OSPI_ECC_U_BASE)),
1130 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FOTA_ECC_U_BASE)),
1131 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS_UL_128_FSS_OF_UL_OSPI0_OSPI_CFG_VBUSP_OSPI_WRAP_ECC_AGG_VBP_U_BASE)),
1132 };
1133
1134 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
1137 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
1138 {
1139
1140 /* Index: SDL_SOC_ECC_AGGR (0) */
1141 {
1142 SDL_SOC_ECC_AGGR_NUM_RAMS,
1143 SDL_SOC_ECC_AGGR_RamIdTable,
1144 SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1145 SDL_SOC_ECC_AGGR_MemEntries,
1146 SDL_ESM_INST_MAIN_ESM0,
1147 SDL_ESM_INTR_LEVEL_SOC_ECCAGG_CORR_LEVEL,
1148 SDL_ESM_INTR_LEVEL_SOC_ECCAGG_UNCORR_LEVEL
1149 },
1150 /* Index: SDL_R5FSS0_CORE0_ECC_AGGR (1) */
1151 {
1152 SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
1153 SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
1154 SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1155 SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1156 SDL_ESM_INST_MAIN_ESM0,
1157 SDL_ESM_INTR_LEVEL_R5SS0_CPU0_ECC_CORRECTED_LEVEL,
1158 SDL_ESM_INTR_LEVEL_R5SS0_CPU0_ECC_UNCORRECTED_LEVEL
1159 },
1160 /* Index: SDL_R5FSS0_CORE1_ECC_AGGR (2) */
1161 {
1162 SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
1163 SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
1164 SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1165 SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
1166 SDL_ESM_INST_MAIN_ESM0,
1167 SDL_ESM_INTR_LEVEL_R5SS0_CPU1_ECC_CORRECTED_LEVEL,
1168 SDL_ESM_INTR_LEVEL_R5SS0_CPU1_ECC_UNCORRECTED_LEVEL
1169 },
1170 /* Index: SDL_HSM_ECC_AGGR (3) */
1171 {
1172 SDL_HSM_ECC_AGGR_NUM_RAMS,
1173 SDL_HSM_ECC_AGGR_RamIdTable,
1174 SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1175 SDL_HSM_ECC_AGGR_MemEntries,
1176 SDL_ESM_INST_MAIN_ESM0,
1177 SDL_ESM_INTR_LEVEL_HSM_ESM_HIGH_INTR,
1178 SDL_ESM_INTR_LEVEL_HSM_ESM_LOW_INTR
1179 },
1180 /* Index: SDL_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR (4) */
1181 {
1182 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
1183 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
1184 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1185 SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
1186 SDL_ESM_INST_MAIN_ESM0,
1187 SDL_ESM_INTR_PULSE_PR0_ECC_SEC_ERR_REQ,
1188 SDL_ESM_INTR_PULSE_PR0_ECC_DED_ERR_REQ
1189 },
1190 /* Index: SDL_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR (4) */
1191 {
1192 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
1193 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
1194 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1195 SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
1196 SDL_ESM_INST_MAIN_ESM0,
1197 SDL_ESM_INTR_PULSE_PR1_ECC_SEC_ERR_REQ,
1198 SDL_ESM_INTR_PULSE_PR1_ECC_DED_ERR_REQ
1199 },
1200 /* Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (5) */
1201 {
1202 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1203 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1204 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1205 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1206 SDL_ESM_INST_MAIN_ESM0,
1207 SDL_ESM_INTR_LEVEL_MCANSS0_ECC_CORR_LVL_INT,
1208 SDL_ESM_INTR_LEVEL_MCANSS0_ECC_UNCORR_LVL_INT
1209 },
1210 /* Index: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (6) */
1211 {
1212 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1213 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1214 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1215 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1216 SDL_ESM_INST_MAIN_ESM0,
1217 SDL_ESM_INTR_LEVEL_MCANSS1_ECC_CORR_LVL_INT,
1218 SDL_ESM_INTR_LEVEL_MCANSS1_ECC_UNCORR_LVL_INT
1219 },
1220 /* Index: SDL_CPSW3GCSS_ECC_AGGR (7) */
1221 {
1222 SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS,
1223 SDL_CPSW3GCSS_ECC_AGGR_RamIdTable,
1224 SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1225 SDL_CPSW3GCSS_ECC_AGGR_MemEntries,
1226 SDL_ESM_INST_MAIN_ESM0,
1227 SDL_ESM_INTR_LEVEL_CPSW_ECC_SEC_PEND_INTR,
1228 SDL_ESM_INTR_LEVEL_CPSW_ECC_DED_PEND_INTR
1229 },
1230 /* Index: SDL_FSS_OSPI_RAM_ECC_AGGR (8) */
1231 {
1232 SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS,
1233 SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable,
1234 SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1235 SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries,
1236 SDL_ESM_INST_MAIN_ESM0,
1237 SDL_ESM_INTR_LEVEL_OSPI_ECC_CORR_LVL_INT,
1238 SDL_ESM_INTR_LEVEL_OSPI_ECC_UNCORR_LVL_INT
1239 },
1240 /* Index: SDL_FSS_FOTA_8051_RAM_ECC_AGGR (9) */
1241 {
1242 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS,
1243 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable,
1244 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1245 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries,
1246 SDL_ESM_INST_MAIN_ESM0,
1247 SDL_ESM_INTR_PULSE_FOTA_ECC_CORR,
1248 SDL_ESM_INTR_PULSE_FOTA_ECC_UNCORR
1249 },
1250 /* Index: SDL_OSPI1_RAM_ECC_AGGR (10) */
1251 {
1252 SDL_OSPI1_RAM_ECC_AGGR_NUM_RAMS,
1253 SDL_OSPI1_RAM_ECC_AGGR_RamIdTable,
1254 SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1255 SDL_OSPI1_RAM_ECC_AGGR_MemEntries,
1256 SDL_ESM_INST_MAIN_ESM0,
1257 SDL_ESM_INTR_LEVEL_OSPI1_ECC_CORR_LVL_INT,
1258 SDL_ESM_INTR_LEVEL_OSPI1_ECC_UNCORR_LVL_INT
1259 },
1260
1261 };
1262
1264 #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_CPSW0_ECC_U_BASE
#define SDL_CPSW0_ECC_U_BASE
Definition: sdl_ecc_soc.h:86
SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:73
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:169
SDL_OSPI1_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_OSPI1_RAM_ECC_AGGR_RamIdTable[SDL_OSPI1_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1109
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:66
SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:933
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:1134
SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:398
SDL_SOC_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:143
SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:421
SDL_ECC_WIDTH_UNDEFINED
#define SDL_ECC_WIDTH_UNDEFINED
Definition: sdl_ecc_soc.h:69
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:264
SDL_SOC_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:531
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_CPSW3GCSS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1035
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1118
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:722
sdl_ip_ecc.h
SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:509
SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries[SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:498
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable[SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1083
SDL_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:875
SDL_GrpChkConfig_t
This structure defines the elements of ECC Group checker for Interconnect.
Definition: sdl_ecc_priv.h:55
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1096
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1017
SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:72
SDL_FOTA_ECC_U_BASE
#define SDL_FOTA_ECC_U_BASE
Definition: sdl_ecc_soc.h:88
SDL_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:360
SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:455
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:1137
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:999
SDL_CPSW3GCSS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:466
SDL_OSPI_ECC_U_BASE
#define SDL_OSPI_ECC_U_BASE
Definition: sdl_ecc_soc.h:87
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133
SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:569
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:444
sdl_ecc_priv.h
SDL_OSPI1_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_OSPI1_RAM_ECC_AGGR_MemEntries[SDL_OSPI1_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:520
SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:966
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84