AM261x MCU+ SDK: sdlr_ecc_ram.h Source File

| AM261x MCU+ SDK 26.00.00 |

sdlr_ecc_ram.h
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1 /********************************************************************
2 * Copyright (C) 2022 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * Name : sdlr_ecc_ram.h
33 */
34 #ifndef SDLR_ECC_RAM_H_
35 #define SDLR_ECC_RAM_H_
36
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <sdl/sdlr.h>
42 #include <stdint.h>
43
44 /**************************************************************************
45 * Hardware Region :
46 **************************************************************************/
47
48 typedef struct {
49 volatile uint8_t Resv_16[16];
50 volatile uint32_t WRAP_REV; /* Revision register */
51 volatile uint32_t CTRL; /* Control register */
52 volatile uint32_t ERR_CTRL1; /* Error inject 1 register */
53 volatile uint32_t ERR_CTRL2; /* Error inject 2 register */
54 volatile uint32_t ERR_STAT1; /* Error status 1 register */
55 volatile uint32_t ERR_STAT2; /* Error status 2 register */
56 volatile uint32_t ERR_STAT3; /* Error status 3 register */
57 } SDL_ecc_ramRegs;
58
59
60 /**************************************************************************
61 * Register Macros
62 **************************************************************************/
63
64 #define SDL_ECC_RAM_WRAP_REV (0x00000010U)
65 #define SDL_ECC_RAM_CTRL (0x00000014U)
66 #define SDL_ECC_RAM_ERR_CTRL1 (0x00000018U)
67 #define SDL_ECC_RAM_ERR_CTRL2 (0x0000001CU)
68 #define SDL_ECC_RAM_ERR_STAT1 (0x00000020U)
69 #define SDL_ECC_RAM_ERR_STAT2 (0x00000024U)
70 #define SDL_ECC_RAM_ERR_STAT3 (0x00000028U)
71
72 /**************************************************************************
73 * Field Definition Macros
74 **************************************************************************/
75
76
77 /* WRAP_REV */
78
79 #define SDL_ECC_RAM_WRAP_REV_SCHEME_MASK (0xC0000000U)
80 #define SDL_ECC_RAM_WRAP_REV_SCHEME_SHIFT (0x0000001EU)
81 #define SDL_ECC_RAM_WRAP_REV_SCHEME_MAX (0x00000003U)
82
83 #define SDL_ECC_RAM_WRAP_REV_BU_MASK (0x30000000U)
84 #define SDL_ECC_RAM_WRAP_REV_BU_SHIFT (0x0000001CU)
85 #define SDL_ECC_RAM_WRAP_REV_BU_MAX (0x00000003U)
86
87 #define SDL_ECC_RAM_WRAP_REV_MODULE_ID_MASK (0x0FFF0000U)
88 #define SDL_ECC_RAM_WRAP_REV_MODULE_ID_SHIFT (0x00000010U)
89 #define SDL_ECC_RAM_WRAP_REV_MODULE_ID_MAX (0x00000FFFU)
90
91 #define SDL_ECC_RAM_WRAP_REV_REVRTL_MASK (0x0000F800U)
92 #define SDL_ECC_RAM_WRAP_REV_REVRTL_SHIFT (0x0000000BU)
93 #define SDL_ECC_RAM_WRAP_REV_REVRTL_MAX (0x0000001FU)
94
95 #define SDL_ECC_RAM_WRAP_REV_REVMAJ_MASK (0x00000700U)
96 #define SDL_ECC_RAM_WRAP_REV_REVMAJ_SHIFT (0x00000008U)
97 #define SDL_ECC_RAM_WRAP_REV_REVMAJ_MAX (0x00000007U)
98
99 #define SDL_ECC_RAM_WRAP_REV_CUSTOM_MASK (0x000000C0U)
100 #define SDL_ECC_RAM_WRAP_REV_CUSTOM_SHIFT (0x00000006U)
101 #define SDL_ECC_RAM_WRAP_REV_CUSTOM_MAX (0x00000003U)
102
103 #define SDL_ECC_RAM_WRAP_REV_REVMIN_MASK (0x0000003FU)
104 #define SDL_ECC_RAM_WRAP_REV_REVMIN_SHIFT (0x00000000U)
105 #define SDL_ECC_RAM_WRAP_REV_REVMIN_MAX (0x0000003FU)
106
107 /* CTRL */
108
109 #define SDL_ECC_RAM_CTRL_ECC_ENABLE_MASK (0x00000001U)
110 #define SDL_ECC_RAM_CTRL_ECC_ENABLE_SHIFT (0x00000000U)
111 #define SDL_ECC_RAM_CTRL_ECC_ENABLE_MAX (0x00000001U)
112
113 #define SDL_ECC_RAM_CTRL_ECC_CHECK_MASK (0x00000002U)
114 #define SDL_ECC_RAM_CTRL_ECC_CHECK_SHIFT (0x00000001U)
115 #define SDL_ECC_RAM_CTRL_ECC_CHECK_MAX (0x00000001U)
116
117 #define SDL_ECC_RAM_CTRL_ENABLE_RMW_MASK (0x00000004U)
118 #define SDL_ECC_RAM_CTRL_ENABLE_RMW_SHIFT (0x00000002U)
119 #define SDL_ECC_RAM_CTRL_ENABLE_RMW_MAX (0x00000001U)
120
121 #define SDL_ECC_RAM_CTRL_FORCE_SEC_MASK (0x00000008U)
122 #define SDL_ECC_RAM_CTRL_FORCE_SEC_SHIFT (0x00000003U)
123 #define SDL_ECC_RAM_CTRL_FORCE_SEC_MAX (0x00000001U)
124
125 #define SDL_ECC_RAM_CTRL_FORCE_DED_MASK (0x00000010U)
126 #define SDL_ECC_RAM_CTRL_FORCE_DED_SHIFT (0x00000004U)
127 #define SDL_ECC_RAM_CTRL_FORCE_DED_MAX (0x00000001U)
128
129 #define SDL_ECC_RAM_CTRL_FORCE_N_ROW_MASK (0x00000020U)
130 #define SDL_ECC_RAM_CTRL_FORCE_N_ROW_SHIFT (0x00000005U)
131 #define SDL_ECC_RAM_CTRL_FORCE_N_ROW_MAX (0x00000001U)
132
133 #define SDL_ECC_RAM_CTRL_ERROR_ONCE_MASK (0x00000040U)
134 #define SDL_ECC_RAM_CTRL_ERROR_ONCE_SHIFT (0x00000006U)
135 #define SDL_ECC_RAM_CTRL_ERROR_ONCE_MAX (0x00000001U)
136
137 #define SDL_ECC_RAM_CTRL_CHECK_PARITY_MASK (0x00000080U)
138 #define SDL_ECC_RAM_CTRL_CHECK_PARITY_SHIFT (0x00000007U)
139 #define SDL_ECC_RAM_CTRL_CHECK_PARITY_MAX (0x00000001U)
140
141 #define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MASK (0x00000100U)
142 #define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_SHIFT (0x00000008U)
143 #define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MAX (0x00000001U)
144
145 /* ERR_CTRL1 */
146
147 #define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MASK (0xFFFFFFFFU)
148 #define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_SHIFT (0x00000000U)
149 #define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MAX (0xFFFFFFFFU)
150
151 /* ERR_CTRL2 */
152
153 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MASK (0x0000FFFFU)
154 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_SHIFT (0x00000000U)
155 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MAX (0x0000FFFFU)
156
157 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MASK (0xFFFF0000U)
158 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_SHIFT (0x00000010U)
159 #define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MAX (0x0000FFFFU)
160
161 /* ERR_STAT1 */
162
163 #define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MASK (0x00000003U)
164 #define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_SHIFT (0x00000000U)
165 #define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MAX (0x00000003U)
166
167 #define SDL_ECC_RAM_ERR_STAT1_ECC_DED_MASK (0x0000000CU)
168 #define SDL_ECC_RAM_ERR_STAT1_ECC_DED_SHIFT (0x00000002U)
169 #define SDL_ECC_RAM_ERR_STAT1_ECC_DED_MAX (0x00000003U)
170
171 #define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MASK (0x00000010U)
172 #define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_SHIFT (0x00000004U)
173 #define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MAX (0x00000001U)
174
175 #define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MASK (0x00000060U)
176 #define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_SHIFT (0x00000005U)
177 #define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MAX (0x00000003U)
178
179 #define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MASK (0x00000080U)
180 #define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_SHIFT (0x00000007U)
181 #define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MAX (0x00000001U)
182
183 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MASK (0x00000300U)
184 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_SHIFT (0x00000008U)
185 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MAX (0x00000003U)
186
187 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MASK (0x00000C00U)
188 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_SHIFT (0x0000000AU)
189 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MAX (0x00000003U)
190
191 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MASK (0x00001000U)
192 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_SHIFT (0x0000000CU)
193 #define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MAX (0x00000001U)
194
195 #define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MASK (0x00006000U)
196 #define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_SHIFT (0x0000000DU)
197 #define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MAX (0x00000003U)
198
199 #define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MASK (0x00008000U)
200 #define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_SHIFT (0x0000000FU)
201 #define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MAX (0x00000001U)
202
203 #define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MASK (0xFFFF0000U)
204 #define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_SHIFT (0x00000010U)
205 #define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MAX (0x0000FFFFU)
206
207 /* ERR_STAT2 */
208
209 #define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MASK (0xFFFFFFFFU)
210 #define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_SHIFT (0x00000000U)
211 #define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MAX (0xFFFFFFFFU)
212
213 /* ERR_STAT3 */
214
215 #define SDL_ECC_RAM_ERR_STAT3_WB_PEND_MASK (0x00000001U)
216 #define SDL_ECC_RAM_ERR_STAT3_WB_PEND_SHIFT (0x00000000U)
217 #define SDL_ECC_RAM_ERR_STAT3_WB_PEND_MAX (0x00000001U)
218
219 #define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MASK (0x00000002U)
220 #define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_SHIFT (0x00000001U)
221 #define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)
222
223 #define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MASK (0x00000200U)
224 #define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_SHIFT (0x00000009U)
225 #define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)
226
227 #ifdef __cplusplus
228 }
229 #endif
230 #endif
SDL_ecc_ramRegs::ERR_STAT1
volatile uint32_t ERR_STAT1
Definition: sdlr_ecc_ram.h:54
SDL_ecc_ramRegs::ERR_STAT2
volatile uint32_t ERR_STAT2
Definition: sdlr_ecc_ram.h:55
SDL_ecc_ramRegs
Definition: sdlr_ecc_ram.h:48
SDL_ecc_ramRegs::WRAP_REV
volatile uint32_t WRAP_REV
Definition: sdlr_ecc_ram.h:50
SDL_ecc_ramRegs::ERR_STAT3
volatile uint32_t ERR_STAT3
Definition: sdlr_ecc_ram.h:56
SDL_ecc_ramRegs::CTRL
volatile uint32_t CTRL
Definition: sdlr_ecc_ram.h:51
SDL_ecc_ramRegs::ERR_CTRL1
volatile uint32_t ERR_CTRL1
Definition: sdlr_ecc_ram.h:52
sdlr.h
This file contains the macro definations for Register layer.
SDL_ecc_ramRegs::ERR_CTRL2
volatile uint32_t ERR_CTRL2
Definition: sdlr_ecc_ram.h:53