AM261x MCU+ SDK: soc_rcm.h Source File

| AM261x MCU+ SDK 26.00.00 |

soc_rcm.h
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1 /*
2 * Copyright (C) 2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef SOC_RCM_AM261X_H_
34 #define SOC_RCM_AM261X_H_
35
36 #include <stdint.h>
37
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif
42
52 #include <kernel/dpl/SystemP.h>
53
54 #define SOC_RCM_FREQ_MHZ2HZ(x) ((x) * 1000 * 1000)
55 #define SOC_RCM_FREQ_HZ2MHZ(x) ((x) / (1000 * 1000))
56
57 #define SOC_RCM_R5_FREQ_400MHZ (0x0U)
58 #define SOC_RCM_R5_FREQ_500MHZ (0x1U)
59
65 typedef enum SOC_WarmResetCause_e
66 {
70 SOC_WarmResetCause_POWER_ON_RESET = 0x41U,
74 SOC_WarmResetCause_MSS_WDT0 = 0x42U,
78 SOC_WarmResetCause_MSS_WDT1 = 0x44U,
82 SOC_WarmResetCause_MSS_WDT2 = 0x48U,
86 SOC_WarmResetCause_MSS_WDT3 = 0x50U,
90 SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ = 0x60U,
94 SOC_WarmResetCause_EXT_PAD_RESET = 0x40U,
98 SOC_WarmResetCause_HSM_WDT = 0xC0U,
102 SOC_WarmResetCause_DBG_RESET = 0x140U,
106 SOC_WarmResetCause_TEMP_SENSOR0_RESET = 0x240U,
110 SOC_WarmResetCause_TEMP_SENSOR1_RESET = 0x440U,
111
112 }SOC_WarmResetCause;
120 typedef enum SOC_WarmResetSource_e
121 {
125 SOC_WarmResetSource_PAD_BYPASS = CSL_TOP_RCM_WARM_RESET_CONFIG_PAD_BYPASS_MASK,
129 SOC_WarmResetSource_DEBUGSS = CSL_TOP_RCM_WARM_RESET_CONFIG_DEBUGSS_RST_EN_MASK,
133 SOC_WarmResetSource_TSENSE0 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE0_RST_EN_MASK,
137 SOC_WarmResetSource_TSENSE1 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE1_RST_EN_MASK,
141 SOC_WarmResetSource_WDOG0 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG0_RST_EN_MASK,
145 SOC_WarmResetSource_WDOG1 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG1_RST_EN_MASK,
146
147 }SOC_WarmResetSource;
156 typedef enum SOC_RcmWarm_ResetTime123_e
157 {
161 SOC_WARM_RESET_PAD_TIME_500NS = 0U,
165 SOC_WARM_RESET_PAD_TIME_1US,
169 SOC_WARM_RESET_PAD_TIME_2US,
173 SOC_WARM_RESET_PAD_TIME_4US,
177 SOC_WARM_RESET_PAD_TIME_8US,
181 SOC_WARM_RESET_PAD_TIME_16US,
185 SOC_WARM_RESET_PAD_TIME_32US,
189 SOC_WARM_RESET_PAD_TIME_64US,
193 SOC_WARM_RESET_PAD_TIME_128US,
197 SOC_WARM_RESET_PAD_TIME_256US,
201 SOC_WARM_RESET_PAD_TIME_512US,
205 SOC_WARM_RESET_PAD_TIME_1024US,
209 SOC_WARM_RESET_PAD_TIME_2048US,
213 SOC_WARM_RESET_PAD_TIME_4096US,
217 SOC_WARM_RESET_PAD_TIME_8192US,
221 SOC_WARM_RESET_PAD_TIME_16384US,
222
223 } SOC_RcmWarm_ResetTime123;
231 typedef enum SOC_RcmResetCause_e
232 {
236 SOC_RcmResetCause_POWER_ON_RESET = 0x0U,
240 SOC_RcmResetCause_WARM_RESET = 0x1U,
244 SOC_RcmResetCause_STC_RESET = 0x2U,
248 SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U,
252 SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U,
256 SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U,
260 SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U,
264 SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U,
268 SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U,
272 SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U,
276 SOC_RcmResetCause_POR_RST_CTRL0 = 0xAU,
280 SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xBU,
281
282 }SOC_RcmResetCause;
290 typedef enum SOC_Rcmr5fssNum_e
291 {
295 r5fss0 = 0x0U,
299 r5fss1 = 0x1U,
300 }SOC_Rcmr5fssNum;
308 typedef enum SOC_RcmPeripheralId_e
309 {
313 SOC_RcmPeripheralId_MCAN0,
317 SOC_RcmPeripheralId_MCAN1,
321 SOC_RcmPeripheralId_OSPI0,
325 SOC_RcmPeripheralId_OSPI1,
329 SOC_RcmPeripheralId_RTI0,
333 SOC_RcmPeripheralId_RTI1,
337 SOC_RcmPeripheralId_RTI2,
341 SOC_RcmPeripheralId_RTI3,
345 SOC_RcmPeripheralId_WDT0,
349 SOC_RcmPeripheralId_WDT1,
353 SOC_RcmPeripheralId_MCSPI0,
357 SOC_RcmPeripheralId_MCSPI1,
361 SOC_RcmPeripheralId_MCSPI2,
365 SOC_RcmPeripheralId_MCSPI3,
369 SOC_RcmPeripheralId_MMC0,
373 SOC_RcmPeripheralId_ICSSM0_CORE,
377 SOC_RcmPeripheralId_ICSSM0_UART0,
381 SOC_RcmPeripheralId_ICSSM1_CORE,
385 SOC_RcmPeripheralId_ICSSM1_UART0,
389 SOC_RcmPeripheralId_CPTS,
393 SOC_RcmPeripheralId_CPSW_5_50_250,
397 SOC_RcmPeripheralId_GPMC,
401 SOC_RcmPeripheralId_CONTROLSS_PLL,
405 SOC_RcmPeripheralId_I2C,
409 SOC_RcmPeripheralId_LIN0_UART0,
413 SOC_RcmPeripheralId_LIN1_UART1,
417 SOC_RcmPeripheralId_LIN2_UART2,
421 SOC_RcmPeripheralId_LIN3_UART3,
422 }SOC_RcmPeripheralId;
430 typedef enum SOC_RcmPeripheralClockSource_e
431 {
435 SOC_RcmPeripheralClockSource_XTALCLK,
439 SOC_RcmPeripheralClockSource_SYS_CLK,
443 SOC_RcmPeripheralClockSource_WUCPUCLK,
447 SOC_RcmPeripheralClockSource_EXT_REFCLK,
451 SOC_RcmPeripheralClockSource_RCCLK10M,
455 SOC_RcmPeripheralClockSource_RCCLK32K,
459 SOC_RcmPeripheralClockSource_CTPS_GENF0,
463 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0,
467 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1,
471 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
475 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT3,
479 SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0,
483 SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0,
487 SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2,
488 } SOC_RcmPeripheralClockSource;
496 typedef enum SOC_RcmPllFoutFreqId_e
497 {
501 RCM_PLL_FOUT_FREQID_CLK_500MHZ,
505 RCM_PLL_FOUT_FREQID_CLK_900MHZ,
509 RCM_PLL_FOUT_FREQID_CLK_960MHZ,
513 RCM_PLL_FOUT_FREQID_CLK_1000MHZ,
517 RCM_PLL_FOUT_FREQID_CLK_2000MHZ,
518 } SOC_RcmPllFoutFreqId;
526 typedef enum SOC_RcmXtalFreqId_e
527 {
531 RCM_XTAL_FREQID_CLK_25MHZ,
532 } SOC_RcmXtalFreqId;
533
534 typedef enum SOC_RcmPllId_e
535 {
536 RCM_PLLID_CORE,
537 RCM_PLLID_ETH,
538 RCM_PLLID_PER,
539 RCM_PLLID_XTALCLK,
540 RCM_PLLID_WUCPUCLK,
541 RCM_PLLID_RCCLK32K,
542 RCM_PLLID_RCCLK10M,
543 RCM_PLLID_EXTREFCLK,
544 } SOC_RcmPllId;
552 typedef enum SOC_RcmPllHSDIVOutId_e
553 {
557 RCM_PLLHSDIV_OUT_0,
561 RCM_PLLHSDIV_OUT_1,
565 RCM_PLLHSDIV_OUT_2,
569 RCM_PLLHSDIV_OUT_3,
573 RCM_PLLHSDIV_OUT_NONE,
574 } SOC_RcmPllHSDIVOutId;
577 typedef struct SOC_RcmClkSrcInfo_s
578 {
579 SOC_RcmPllId pllId;
580 SOC_RcmPllHSDIVOutId hsDivOut;
581 } SOC_RcmClkSrcInfo;
582
583 typedef struct SOC_RcmXTALInfo_s
584 {
585 uint32_t Finp;
586 Bool div2flag;
587 } SOC_RcmXTALInfo;
588
589 typedef struct SOC_RcmADPLLJConfig_s
590 {
591 uint32_t N; /* Input Clock divider/Pre-divider (N) */
592 uint32_t M2; /* Post divider (M2) */
593 uint32_t M; /* Multiplier integer (M) */
594 uint32_t FracM; /* Multiplier fractional (M) */
595 uint32_t Fout; /* Output frequency of PLL */
596 uint32_t Finp; /* Output frequency of PLL */
597 uint32_t SD; /* Sigma delta divider */
598 } SOC_RcmADPLLJConfig_t;
599
600 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)
601 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)
602 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)
603 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)
604 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL (RCM_PLL_HSDIV_OUTPUT_ENABLE_0 | \
605 RCM_PLL_HSDIV_OUTPUT_ENABLE_1 | \
606 RCM_PLL_HSDIV_OUTPUT_ENABLE_2 | \
607 RCM_PLL_HSDIV_OUTPUT_ENABLE_3)
608
609 #define RCM_PLL_HSDIV_OUTPUT_IDX0 (0)
610 #define RCM_PLL_HSDIV_OUTPUT_IDX1 (1)
611 #define RCM_PLL_HSDIV_OUTPUT_IDX2 (2)
612 #define RCM_PLL_HSDIV_OUTPUT_IDX3 (3)
613 #define RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)
614
615 typedef struct SOC_RcmPllHsDivOutConfig_s
616 {
617 uint32_t hsdivOutEnMask;
618 uint32_t hsDivOutFreqHz[RCM_PLL_HSDIV_OUTPUT_COUNT];
619 } SOC_RcmPllHsDivOutConfig;
620
628 extern void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
629
637 extern void SOC_rcmEthApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
638
642 extern uint32_t SOC_rcmCoreApllRelockPreRequisite(void);
643
647 extern void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc);
648
649
657 extern void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
658
666 extern void SOC_rcmPerApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
667
676 extern void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz,
677 uint32_t cpuId);
678
685 extern void SOC_rcmsetTraceClock(uint32_t traceFreqHz);
686
694 extern void SOC_rcmsetClkoutClock(uint32_t clkout0FreqHz, uint32_t clkout1FreqHz);
695
709 extern int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz);
710
721 extern SOC_RcmResetCause SOC_rcmGetResetCause(SOC_Rcmr5fssNum r5fssNum);
722
735 int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enable);
736
746 int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId);
747
754 uint32_t SOC_rcmGetR5Clock(uint32_t cpuId);
755
760 void SOC_rcmR5ConfigLockStep(uint32_t cpuId);
761
766 void SOC_rcmR5ConfigDualCore(uint32_t cpuId);
767
771 extern void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc);
772
776 void SOC_rcmR5SS0TriggerReset(void);
777
782 void SOC_rcmCoreR5FUnhalt(uint32_t cpuId);
783
788 void SOC_rcmStartMemInitTCMA(uint32_t cpuId);
789
794 void SOC_rcmWaitMemInitTCMA(uint32_t cpuId);
795
800 void SOC_rcmStartMemInitTCMB(uint32_t cpuId);
801
806 void SOC_rcmWaitMemInitTCMB(uint32_t cpuId);
807
811 void SOC_rcmMemInitMailboxMemory(void);
815 void SOC_rcmMemInitL2Memory(void);
819 void SOC_rcmR5SS0PowerOnReset(void);
820
824 void SOC_rcmR5SS1TriggerReset(void);
825
829 void SOC_rcmR5SS1PowerOnReset(void);
830
838 uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId);
839
843 void SOC_generateSwWarmReset(void);
844
851 void SOC_configureWarmResetSource(uint32_t source);
852
858 SOC_WarmResetCause SOC_getWarmResetCause(void);
859
863 void SOC_clearWarmResetCause(void);
864
870 void SOC_configureWarmResetOutputDelay(uint16_t opDelayValue);
871
877 void SOC_configureWarmResetInputRiseDelay(uint16_t inpRiseDelayValue);
878
884 void SOC_configureWarmResetInputFallDelay(uint16_t inpFallDelayValue);
885
888 #ifdef __cplusplus
889 }
890 #endif
891
892 #endif
SOC_Rcmr5fssNum
SOC_Rcmr5fssNum
Definition: soc_rcm.h:291
RCM_PLLHSDIV_OUT_NONE
@ RCM_PLLHSDIV_OUT_NONE
Value specifying invalid/no HSDIVIDER ID.
Definition: soc_rcm.h:573
SOC_RcmPeripheralId_LIN0_UART0
@ SOC_RcmPeripheralId_LIN0_UART0
Value specifying LIN0_UART0.
Definition: soc_rcm.h:409
SOC_rcmR5SS1PowerOnReset
void SOC_rcmR5SS1PowerOnReset(void)
Reset R5SS1 Core.
RCM_PLLID_ETH
@ RCM_PLLID_ETH
Definition: soc_rcm.h:537
RCM_PLLHSDIV_OUT_1
@ RCM_PLLHSDIV_OUT_1
Value specifying HSDIVIDER 1.
Definition: soc_rcm.h:561
SOC_RcmPeripheralId_CPSW_5_50_250
@ SOC_RcmPeripheralId_CPSW_5_50_250
Value specifying CPSW_5_50_250.
Definition: soc_rcm.h:393
SOC_RcmResetCause_MMR_CPU0_VIM0_RESET
@ SOC_RcmResetCause_MMR_CPU0_VIM0_RESET
Value specifying R5 Core A Subsytem Reset.
Definition: soc_rcm.h:248
SOC_WARM_RESET_PAD_TIME_1024US
@ SOC_WARM_RESET_PAD_TIME_1024US
Delay Value specifying in time 1024us.
Definition: soc_rcm.h:205
SOC_configureWarmResetInputFallDelay
void SOC_configureWarmResetInputFallDelay(uint16_t inpFallDelayValue)
Program output delay on warm reset Pad 3.
RCM_PLLID_CORE
@ RCM_PLLID_CORE
Definition: soc_rcm.h:536
SOC_RcmPeripheralId_ICSSM0_CORE
@ SOC_RcmPeripheralId_ICSSM0_CORE
Value specifying ICSSM0_CORE.
Definition: soc_rcm.h:373
SOC_RcmResetCause_MMR_CPU0_RESET
@ SOC_RcmResetCause_MMR_CPU0_RESET
Value specifying R5 Core A (core only) Reset.
Definition: soc_rcm.h:256
SOC_rcmCoreApllHSDivConfig
void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure CORE PLL HSDIVIDERS.
RCM_PLLID_PER
@ RCM_PLLID_PER
Definition: soc_rcm.h:538
SOC_rcmEnablePeripheralClock
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enable)
Enable/disable module clock (IP clock configuration)
SOC_rcmCoreR5FUnhalt
void SOC_rcmCoreR5FUnhalt(uint32_t cpuId)
Unhalt R5 cores.
SOC_rcmCoreApllRelockPreRequisite
uint32_t SOC_rcmCoreApllRelockPreRequisite(void)
Pre-requisite sequence to Re-configure CORE PLL.
SOC_WarmResetSource_TSENSE1
@ SOC_WarmResetSource_TSENSE1
Value specifying Temperature Sensor 1.
Definition: soc_rcm.h:137
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2
Value specifying PLL Per Clock Out 2 (160 Mhz)
Definition: soc_rcm.h:487
r5fss1
@ r5fss1
Value specifying Warm Reset.
Definition: soc_rcm.h:299
SOC_RcmPeripheralId_RTI1
@ SOC_RcmPeripheralId_RTI1
Value specifying RTI1.
Definition: soc_rcm.h:333
SOC_RcmADPLLJConfig_t
Definition: soc_rcm.h:590
SOC_RcmPeripheralId_MCSPI2
@ SOC_RcmPeripheralId_MCSPI2
Value specifying MCSPI2.
Definition: soc_rcm.h:361
SystemP.h
SOC_RcmPeripheralClockSource
SOC_RcmPeripheralClockSource
Definition: soc_rcm.h:431
SOC_RcmADPLLJConfig_t::FracM
uint32_t FracM
Definition: soc_rcm.h:594
SOC_WARM_RESET_PAD_TIME_128US
@ SOC_WARM_RESET_PAD_TIME_128US
Delay Value specifying in time 128us.
Definition: soc_rcm.h:193
SOC_rcmsetTraceClock
void SOC_rcmsetTraceClock(uint32_t traceFreqHz)
Set Trace clock frequency.
SOC_RcmPeripheralId_MCSPI0
@ SOC_RcmPeripheralId_MCSPI0
Value specifying MCSPI0.
Definition: soc_rcm.h:353
SOC_rcmStartMemInitTCMA
void SOC_rcmStartMemInitTCMA(uint32_t cpuId)
Start memory initialization for R5 TCMA.
RCM_PLL_FOUT_FREQID_CLK_900MHZ
@ RCM_PLL_FOUT_FREQID_CLK_900MHZ
Value specifying PLL output frequency 900MHz.
Definition: soc_rcm.h:505
RCM_PLLHSDIV_OUT_3
@ RCM_PLLHSDIV_OUT_3
Value specifying HSDIVIDER 3.
Definition: soc_rcm.h:569
SOC_WARM_RESET_PAD_TIME_512US
@ SOC_WARM_RESET_PAD_TIME_512US
Delay Value specifying in time 512us.
Definition: soc_rcm.h:201
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT3
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT3
Value specifying PLL Core Clock Out 3 (166 Mhz)
Definition: soc_rcm.h:475
SOC_RcmADPLLJConfig_t::SD
uint32_t SD
Definition: soc_rcm.h:597
SOC_RcmADPLLJConfig_t::M
uint32_t M
Definition: soc_rcm.h:593
SOC_WARM_RESET_PAD_TIME_4US
@ SOC_WARM_RESET_PAD_TIME_4US
Delay Value specifying in time 4us.
Definition: soc_rcm.h:173
SOC_configureWarmResetInputRiseDelay
void SOC_configureWarmResetInputRiseDelay(uint16_t inpRiseDelayValue)
Program input rise delay on warm reset Pad 2.
SOC_WARM_RESET_PAD_TIME_2048US
@ SOC_WARM_RESET_PAD_TIME_2048US
Delay Value specifying in time 2048us.
Definition: soc_rcm.h:209
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0
Value specifying PLL Core Clock Out 0 (500 Mhz)
Definition: soc_rcm.h:463
SOC_RcmADPLLJConfig_t::Fout
uint32_t Fout
Definition: soc_rcm.h:595
SOC_WARM_RESET_PAD_TIME_2US
@ SOC_WARM_RESET_PAD_TIME_2US
Delay Value specifying in time 2us.
Definition: soc_rcm.h:169
SOC_WarmResetCause_MSS_WDT0
@ SOC_WarmResetCause_MSS_WDT0
Value specifying MSS WDT0.
Definition: soc_rcm.h:74
SOC_rcmSetR5ClockSource
void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc)
Set R5 clock source.
SOC_WarmResetCause_EXT_PAD_RESET
@ SOC_WarmResetCause_EXT_PAD_RESET
Value specifying External Pad Reset.
Definition: soc_rcm.h:94
SOC_WarmResetCause_MSS_WDT3
@ SOC_WarmResetCause_MSS_WDT3
Value specifying MSS WDT3.
Definition: soc_rcm.h:86
SOC_rcmEthApllConfig
void SOC_rcmEthApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure ETH PLL.
SOC_RcmResetCause_POWER_ON_RESET
@ SOC_RcmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:236
SOC_rcmWaitMemInitTCMB
void SOC_rcmWaitMemInitTCMB(uint32_t cpuId)
Wait memory initialization to complete for R5 TCMB.
SOC_RcmPeripheralId
SOC_RcmPeripheralId
Definition: soc_rcm.h:309
SOC_RcmPeripheralClockSource_XTALCLK
@ SOC_RcmPeripheralClockSource_XTALCLK
Value specifying Crystal Clock.
Definition: soc_rcm.h:435
SOC_rcmStartMemInitTCMB
void SOC_rcmStartMemInitTCMB(uint32_t cpuId)
Start memory initialization for R5 TCMB.
SOC_WARM_RESET_PAD_TIME_8US
@ SOC_WARM_RESET_PAD_TIME_8US
Delay Value specifying in time 8us.
Definition: soc_rcm.h:177
SOC_RcmResetCause_RST_CAUSE_UNKNOWN
@ SOC_RcmResetCause_RST_CAUSE_UNKNOWN
Value specifying R5 Reset due to Unknown reason.
Definition: soc_rcm.h:280
SOC_rcmsetClkoutClock
void SOC_rcmsetClkoutClock(uint32_t clkout0FreqHz, uint32_t clkout1FreqHz)
Set CLKOUT clock frequency.
SOC_RcmPeripheralId_WDT1
@ SOC_RcmPeripheralId_WDT1
Value specifying WDT1.
Definition: soc_rcm.h:349
SOC_WARM_RESET_PAD_TIME_32US
@ SOC_WARM_RESET_PAD_TIME_32US
Delay Value specifying in time 32us.
Definition: soc_rcm.h:185
SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ
@ SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ
Value specifying Software Warm Reset.
Definition: soc_rcm.h:90
SOC_RcmPeripheralId_GPMC
@ SOC_RcmPeripheralId_GPMC
Value specifying GPMC.
Definition: soc_rcm.h:397
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0
Value specifying PLL Per Clock Out 0 (240 Mhz)
Definition: soc_rcm.h:483
SOC_configureWarmResetOutputDelay
void SOC_configureWarmResetOutputDelay(uint16_t opDelayValue)
Program output delay on warm reset Pad 1.
SOC_RcmPeripheralClockSource_SYS_CLK
@ SOC_RcmPeripheralClockSource_SYS_CLK
Value specifying System Clock (200Mhz)
Definition: soc_rcm.h:439
SOC_WARM_RESET_PAD_TIME_1US
@ SOC_WARM_RESET_PAD_TIME_1US
Delay Value specifying in time 1us.
Definition: soc_rcm.h:165
SOC_RcmXTALInfo::div2flag
Bool div2flag
Definition: soc_rcm.h:586
SOC_RcmPeripheralId_MCSPI1
@ SOC_RcmPeripheralId_MCSPI1
Value specifying MCSPI1.
Definition: soc_rcm.h:357
SOC_WarmResetSource_TSENSE0
@ SOC_WarmResetSource_TSENSE0
Value specifying Temperature Sensor 0.
Definition: soc_rcm.h:133
SOC_RcmPllHsDivOutConfig
Definition: soc_rcm.h:616
SOC_RcmPeripheralId_MCSPI3
@ SOC_RcmPeripheralId_MCSPI3
Value specifying MCSPI3.
Definition: soc_rcm.h:365
SOC_RcmPllHSDIVOutId
SOC_RcmPllHSDIVOutId
Definition: soc_rcm.h:553
SOC_RcmXtalFreqId
SOC_RcmXtalFreqId
Definition: soc_rcm.h:527
SOC_rcmSetPeripheralClock
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
Set module clock (IP clock configuration)
SOC_RcmXTALInfo
Definition: soc_rcm.h:584
SOC_RcmClkSrcInfo::pllId
SOC_RcmPllId pllId
Definition: soc_rcm.h:579
SOC_rcmGetResetCause
SOC_RcmResetCause SOC_rcmGetResetCause(SOC_Rcmr5fssNum r5fssNum)
Get R5FSS reset cause.
SOC_rcmsetR5SysClock
void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
Set R5FSS and Sysclk frequency (Root clock configuration)
SOC_WARM_RESET_PAD_TIME_8192US
@ SOC_WARM_RESET_PAD_TIME_8192US
Delay Value specifying in time 8192us.
Definition: soc_rcm.h:217
SOC_RcmXTALInfo::Finp
uint32_t Finp
Definition: soc_rcm.h:585
SOC_WARM_RESET_PAD_TIME_16384US
@ SOC_WARM_RESET_PAD_TIME_16384US
Delay Value specifying in time 16384us.
Definition: soc_rcm.h:221
SOC_WARM_RESET_PAD_TIME_500NS
@ SOC_WARM_RESET_PAD_TIME_500NS
Delay Value specifying in time 500ns.
Definition: soc_rcm.h:161
SOC_RcmPeripheralId_I2C
@ SOC_RcmPeripheralId_I2C
Value specifying I2C.
Definition: soc_rcm.h:405
SOC_RcmResetCause_FSM_TRIGGER_RESET
@ SOC_RcmResetCause_FSM_TRIGGER_RESET
Value specifying R5 Reset due to FSM Trigger.
Definition: soc_rcm.h:272
SOC_rcmIsR5FInLockStepMode
uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId)
Return R5SS status operating in lockstep or dual core mode.
SOC_RcmResetCause
SOC_RcmResetCause
Definition: soc_rcm.h:232
RCM_PLLID_WUCPUCLK
@ RCM_PLLID_WUCPUCLK
Definition: soc_rcm.h:540
SOC_clearWarmResetCause
void SOC_clearWarmResetCause(void)
Clear Reset Cause register.
SOC_RcmResetCause_DBG_CPU1_RESET
@ SOC_RcmResetCause_DBG_CPU1_RESET
Value specifying R5 Core B Debug Reset.
Definition: soc_rcm.h:268
SOC_WarmResetCause_TEMP_SENSOR1_RESET
@ SOC_WarmResetCause_TEMP_SENSOR1_RESET
Value specifying Temperature Sensor1 Reset.
Definition: soc_rcm.h:110
SOC_rcmMemInitMailboxMemory
void SOC_rcmMemInitMailboxMemory(void)
Wait memory initialization to complete for Mailbox memory.
SOC_RcmResetCause_DBG_CPU0_RESET
@ SOC_RcmResetCause_DBG_CPU0_RESET
Value specifying R5 Core A Debug Reset.
Definition: soc_rcm.h:264
SOC_RcmPeripheralId_MCAN0
@ SOC_RcmPeripheralId_MCAN0
Value specifying MCAN0.
Definition: soc_rcm.h:313
RCM_PLLID_RCCLK32K
@ RCM_PLLID_RCCLK32K
Definition: soc_rcm.h:541
SOC_WarmResetSource_WDOG0
@ SOC_WarmResetSource_WDOG0
Value specifying Watchdog 0.
Definition: soc_rcm.h:141
RCM_PLLID_RCCLK10M
@ RCM_PLLID_RCCLK10M
Definition: soc_rcm.h:542
SOC_WARM_RESET_PAD_TIME_16US
@ SOC_WARM_RESET_PAD_TIME_16US
Delay Value specifying in time 16us.
Definition: soc_rcm.h:181
RCM_XTAL_FREQID_CLK_25MHZ
@ RCM_XTAL_FREQID_CLK_25MHZ
Value specifying XTAL frequency 25MHZ.
Definition: soc_rcm.h:531
SOC_rcmR5SS1TriggerReset
void SOC_rcmR5SS1TriggerReset(void)
Trigger R5SS1 core reset.
RCM_PLLHSDIV_OUT_0
@ RCM_PLLHSDIV_OUT_0
Value specifying HSDIVIDER 0.
Definition: soc_rcm.h:557
SOC_RcmPllHsDivOutConfig::hsdivOutEnMask
uint32_t hsdivOutEnMask
Definition: soc_rcm.h:617
SOC_WarmResetCause_HSM_WDT
@ SOC_WarmResetCause_HSM_WDT
Value specifying HSM WDT.
Definition: soc_rcm.h:98
SOC_RcmClkSrcInfo
Definition: soc_rcm.h:578
SOC_rcmR5ConfigLockStep
void SOC_rcmR5ConfigLockStep(uint32_t cpuId)
Configure R5 in lock step mode.
SOC_RcmPeripheralId_RTI0
@ SOC_RcmPeripheralId_RTI0
Value specifying RTI0.
Definition: soc_rcm.h:329
SOC_rcmR5SS0TriggerReset
void SOC_rcmR5SS0TriggerReset(void)
Trigger R5 core reset.
SOC_rcmPerApllConfig
void SOC_rcmPerApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure PER PLL.
SOC_rcmWaitMemInitTCMA
void SOC_rcmWaitMemInitTCMA(uint32_t cpuId)
Wait memory initialization to complete for R5 TCMA.
SOC_rcmSetR5Clock
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
Set R5SS0/R5SS1 and SysClk frequency.
SOC_RcmPeripheralClockSource_RCCLK32K
@ SOC_RcmPeripheralClockSource_RCCLK32K
Value specifying RC clock (32KHz)
Definition: soc_rcm.h:455
SOC_WARM_RESET_PAD_TIME_64US
@ SOC_WARM_RESET_PAD_TIME_64US
Delay Value specifying in time 64us.
Definition: soc_rcm.h:189
SOC_WarmResetCause_MSS_WDT2
@ SOC_WarmResetCause_MSS_WDT2
Value specifying MSS WDT2.
Definition: soc_rcm.h:82
SOC_RcmPeripheralClockSource_EXT_REFCLK
@ SOC_RcmPeripheralClockSource_EXT_REFCLK
Value specifying external reference clock.
Definition: soc_rcm.h:447
SOC_RcmPeripheralId_ICSSM0_UART0
@ SOC_RcmPeripheralId_ICSSM0_UART0
Value specifying ICSSM0_UART0.
Definition: soc_rcm.h:377
SOC_WarmResetCause_MSS_WDT1
@ SOC_WarmResetCause_MSS_WDT1
Value specifying MSS WDT1.
Definition: soc_rcm.h:78
SOC_WARM_RESET_PAD_TIME_256US
@ SOC_WARM_RESET_PAD_TIME_256US
Delay Value specifying in time 256us.
Definition: soc_rcm.h:197
SOC_RcmADPLLJConfig_t::Finp
uint32_t Finp
Definition: soc_rcm.h:596
SOC_RcmPllId
SOC_RcmPllId
Definition: soc_rcm.h:535
RCM_PLL_FOUT_FREQID_CLK_2000MHZ
@ RCM_PLL_FOUT_FREQID_CLK_2000MHZ
Value specifying PLL output frequency 2000MHz.
Definition: soc_rcm.h:517
SOC_RcmWarm_ResetTime123
SOC_RcmWarm_ResetTime123
Definition: soc_rcm.h:157
SOC_RcmPeripheralId_LIN3_UART3
@ SOC_RcmPeripheralId_LIN3_UART3
Value specifying LIN3_UART3.
Definition: soc_rcm.h:421
SOC_WarmResetCause_POWER_ON_RESET
@ SOC_WarmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:70
SOC_RcmPeripheralClockSource_WUCPUCLK
@ SOC_RcmPeripheralClockSource_WUCPUCLK
Value specifying wake up clock.
Definition: soc_rcm.h:443
SOC_RcmPeripheralId_RTI3
@ SOC_RcmPeripheralId_RTI3
Value specifying RTI3.
Definition: soc_rcm.h:341
SOC_rcmR5SS0PowerOnReset
void SOC_rcmR5SS0PowerOnReset(void)
Reset R5SS0 Core.
SOC_RcmPeripheralId_LIN1_UART1
@ SOC_RcmPeripheralId_LIN1_UART1
Value specifying LIN1_UART1.
Definition: soc_rcm.h:413
SOC_RcmPeripheralId_MCAN1
@ SOC_RcmPeripheralId_MCAN1
Value specifying MCAN1.
Definition: soc_rcm.h:317
SOC_generateSwWarmReset
void SOC_generateSwWarmReset(void)
Generate SW WARM reset.
SOC_WarmResetSource_WDOG1
@ SOC_WarmResetSource_WDOG1
Value specifying Watchdog 1.
Definition: soc_rcm.h:145
SOC_RcmPeripheralId_RTI2
@ SOC_RcmPeripheralId_RTI2
Value specifying RTI2.
Definition: soc_rcm.h:337
RCM_PLL_FOUT_FREQID_CLK_500MHZ
@ RCM_PLL_FOUT_FREQID_CLK_500MHZ
Value specifying PLL output frequency 500MHz.
Definition: soc_rcm.h:501
SOC_WarmResetCause_TEMP_SENSOR0_RESET
@ SOC_WarmResetCause_TEMP_SENSOR0_RESET
Value specifying Temperature Sensor0 Reset.
Definition: soc_rcm.h:106
SOC_RcmADPLLJConfig_t::N
uint32_t N
Definition: soc_rcm.h:591
SOC_RcmResetCause_STC_RESET
@ SOC_RcmResetCause_STC_RESET
Value specifying STC Reset.
Definition: soc_rcm.h:244
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (500 Mhz)
Definition: soc_rcm.h:467
SOC_RcmResetCause_WARM_RESET
@ SOC_RcmResetCause_WARM_RESET
Value specifying Warm Reset.
Definition: soc_rcm.h:240
SOC_RcmPeripheralId_MMC0
@ SOC_RcmPeripheralId_MMC0
Value specifying MMC0.
Definition: soc_rcm.h:369
SOC_WarmResetSource
SOC_WarmResetSource
Definition: soc_rcm.h:121
SOC_rcmR5ConfigDualCore
void SOC_rcmR5ConfigDualCore(uint32_t cpuId)
Configure R5 in dual core mode.
SOC_rcmMemInitL2Memory
void SOC_rcmMemInitL2Memory(void)
Wait memory initialization to complete for L2 Bank2 and Bank3 memory.
SOC_RcmPeripheralId_OSPI0
@ SOC_RcmPeripheralId_OSPI0
Value specifying OSPI0.
Definition: soc_rcm.h:321
SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0
@ SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0
Value specifying PLL Eth Clock Out 0 (450 Mhz)
Definition: soc_rcm.h:479
SOC_WARM_RESET_PAD_TIME_4096US
@ SOC_WARM_RESET_PAD_TIME_4096US
Delay Value specifying in time 4096us.
Definition: soc_rcm.h:213
SOC_WarmResetCause
SOC_WarmResetCause
Definition: soc_rcm.h:66
SOC_RcmResetCause_MMR_CPU1_VIM1_RESET
@ SOC_RcmResetCause_MMR_CPU1_VIM1_RESET
Value specifying R5 Core B Subsytem Reset.
Definition: soc_rcm.h:252
SOC_WarmResetSource_DEBUGSS
@ SOC_WarmResetSource_DEBUGSS
Value specifying DebugSS.
Definition: soc_rcm.h:129
SOC_RcmClkSrcInfo::hsDivOut
SOC_RcmPllHSDIVOutId hsDivOut
Definition: soc_rcm.h:580
SOC_WarmResetCause_DBG_RESET
@ SOC_WarmResetCause_DBG_RESET
Value specifying Debugger Reset.
Definition: soc_rcm.h:102
RCM_PLLID_EXTREFCLK
@ RCM_PLLID_EXTREFCLK
Definition: soc_rcm.h:543
RCM_PLL_FOUT_FREQID_CLK_960MHZ
@ RCM_PLL_FOUT_FREQID_CLK_960MHZ
Value specifying PLL output frequency 960MHz.
Definition: soc_rcm.h:509
SOC_getWarmResetCause
SOC_WarmResetCause SOC_getWarmResetCause(void)
Returns cause of WARM reset.
SOC_RcmPeripheralId_LIN2_UART2
@ SOC_RcmPeripheralId_LIN2_UART2
Value specifying LIN2_UART2.
Definition: soc_rcm.h:417
SOC_RcmPllFoutFreqId
SOC_RcmPllFoutFreqId
Definition: soc_rcm.h:497
RCM_PLLID_XTALCLK
@ RCM_PLLID_XTALCLK
Definition: soc_rcm.h:539
SOC_RcmPeripheralId_ICSSM1_CORE
@ SOC_RcmPeripheralId_ICSSM1_CORE
Value specifying ICSSM1_CORE.
Definition: soc_rcm.h:381
SOC_RcmADPLLJConfig_t::M2
uint32_t M2
Definition: soc_rcm.h:592
r5fss0
@ r5fss0
Value specifying Power ON Reset.
Definition: soc_rcm.h:295
SOC_RcmResetCause_MMR_CPU1_RESET
@ SOC_RcmResetCause_MMR_CPU1_RESET
Value specifying R5 Core B (core only) Reset.
Definition: soc_rcm.h:260
RCM_PLL_FOUT_FREQID_CLK_1000MHZ
@ RCM_PLL_FOUT_FREQID_CLK_1000MHZ
Value specifying PLL output frequency 1000MHz.
Definition: soc_rcm.h:513
RCM_PLLHSDIV_OUT_2
@ RCM_PLLHSDIV_OUT_2
Value specifying HSDIVIDER 2.
Definition: soc_rcm.h:565
SOC_RcmPeripheralId_WDT0
@ SOC_RcmPeripheralId_WDT0
Value specifying WDT0.
Definition: soc_rcm.h:345
SOC_rcmGetR5Clock
uint32_t SOC_rcmGetR5Clock(uint32_t cpuId)
Get R5SS0/1 frequency.
SOC_RcmPeripheralId_CONTROLSS_PLL
@ SOC_RcmPeripheralId_CONTROLSS_PLL
Value specifying CONTROLSS_PLL.
Definition: soc_rcm.h:401
SOC_WarmResetSource_PAD_BYPASS
@ SOC_WarmResetSource_PAD_BYPASS
Value specifying Pad Warm Reset pin.
Definition: soc_rcm.h:125
SOC_RcmPeripheralId_OSPI1
@ SOC_RcmPeripheralId_OSPI1
Value specifying OSPI0.
Definition: soc_rcm.h:325
SOC_RcmPeripheralId_CPTS
@ SOC_RcmPeripheralId_CPTS
Value specifying CPTS.
Definition: soc_rcm.h:389
SOC_configureWarmResetSource
void SOC_configureWarmResetSource(uint32_t source)
Configure WARM reset source.
SOC_RcmPeripheralClockSource_CTPS_GENF0
@ SOC_RcmPeripheralClockSource_CTPS_GENF0
Value specifying CPTS GENF0 clock.
Definition: soc_rcm.h:459
RCM_PLL_HSDIV_OUTPUT_COUNT
#define RCM_PLL_HSDIV_OUTPUT_COUNT
Definition: soc_rcm.h:613
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2
Value specifying PLL Core Clock Out 2 (500 Mhz)
Definition: soc_rcm.h:471
SOC_rcmCoreApllConfig
void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure CORE PLL.
SOC_RcmResetCause_POR_RST_CTRL0
@ SOC_RcmResetCause_POR_RST_CTRL0
Value specifying R5 Reset due to write to debug POR RST CTRL Reg.
Definition: soc_rcm.h:276
SOC_RcmPeripheralId_ICSSM1_UART0
@ SOC_RcmPeripheralId_ICSSM1_UART0
Value specifying ICSSM1_UART0.
Definition: soc_rcm.h:385
SOC_RcmPeripheralClockSource_RCCLK10M
@ SOC_RcmPeripheralClockSource_RCCLK10M
Value specifying RC clock (10MHz)
Definition: soc_rcm.h:451