AM261x MCU+ SDK: Mdio_Cfg Struct Reference

| AM261x MCU+ SDK 26.00.00 |

Data Fields
Mdio_Cfg Struct Reference
APIs for Networking modules » APIs for Enet LLD » Enet Management Data I/O (MDIO) » CPSW Management Data Input/Output (MDIO)

## Detailed Description

MDIO module configuration.

Configuration parameters for the MDIO module.

## Data Fields
Mdio_OpMode | mode
uint32_t | mdioBusFreqHz
uint32_t | phyStatePollFreqHz
uint32_t | pollEnMask
uint32_t | c45EnMask
bool | isMaster
bool | disableStateMachineOnInit

## Field Documentation

## ◆ mode

Mdio_OpMode Mdio_Cfg::mode

MDIO module operating mode

## ◆ mdioBusFreqHz

uint32_t Mdio_Cfg::mdioBusFreqHz

MDIO bus clock (MDCLK) frequency in Hz

## ◆ phyStatePollFreqHz

uint32_t Mdio_Cfg::phyStatePollFreqHz

Polling inter packet gap frequency in Hz

## ◆ pollEnMask

uint32_t Mdio_Cfg::pollEnMask

Indicates which PHY addresses have polling enabled. The ENET_MDIO_PHY_ADDR_MASK macro should be used to create the mask. Only two PHYs can be monitored in Normal Mode, so only two bits must be set if operating in that mode.

## ◆ c45EnMask

uint32_t Mdio_Cfg::c45EnMask

Indicates which PHY addresses will use Clause-45 frame format. The ENET_MDIO_PHY_ADDR_MASK macro should be used to create the mask

## ◆ isMaster

bool Mdio_Cfg::isMaster

MDIO module can be shared by multiple peripherals, so only one peripheral (master) must perform the MDIO initial configuration and be skipped by the other peripherals (slaves). There must be only one peripheral marked as master among the those that share the MDIO. This condition is not enforced in driver, so it's application's responsibility this requirement is met.

## ◆ disableStateMachineOnInit

bool Mdio_Cfg::disableStateMachineOnInit

Config to disable MDIO state machine on MDIO_open . By default MDIO state machine is enabled on MDIO_open Setting this flag, will cause MDIO to not enable MDIO state machine on open. The MDIO state machine can be enabled at a later point of time via IOCTL. This option allows Synchronizing externally managed PHY with the MDIO whereby external PHY initialization is done and then MDIO state machine can be enabled so that any linkup interrupts are not missed