AM261x MCU+ SDK: SIPC_InterruptConfig Struct Reference

| AM261x MCU+ SDK 26.00.00 |

Data Fields
SIPC_InterruptConfig Struct Reference

## Detailed Description

This structure describes the information related to one interrupt that is setup for receiving mailbox messages One interrupt can be used to handle messages from multiple cores.

## Data Fields
uint32_t | intNum
uint32_t | eventId
HwiP_Object | hwiObj
uint8_t | numCores
uint8_t | coreIdList [MAX_SEC_CORES_WITH_HSM]
uint32_t | clearIntOnInit

## Field Documentation

## ◆ intNum

uint32_t SIPC_InterruptConfig::intNum

interrupt number

## ◆ eventId

uint32_t SIPC_InterruptConfig::eventId

interrupt event ID, not used for ARM cores

## ◆ hwiObj

HwiP_Object SIPC_InterruptConfig::hwiObj

HW interrupt object handle

## ◆ numCores

uint8_t SIPC_InterruptConfig::numCores

Number of remote cores attached to this interrupt.

## ◆ coreIdList

uint8_t SIPC_InterruptConfig::coreIdList[MAX_SEC_CORES_WITH_HSM]

List of secure cores attached to this interrupt

                  See @ref SIPC_SecCoreId for valid values of this field.

## ◆ clearIntOnInit

uint32_t SIPC_InterruptConfig::clearIntOnInit