AM261x MCU+ SDK: sipc_notify_src.h File Reference

| AM261x MCU+ SDK 26.00.00 |

Data Structures | Functions | Variables
sipc_notify_src.h File Reference

Go to the source code of this file.

## Data Structures
struct | SIPC_InterruptConfig
| This structure describes the information related to one interrupt that is setup for receiving mailbox messages One interrupt can be used to handle messages from multiple cores. More...
struct | SIPC_MailboxConfig
| This structure describes the mailbox information to send a message from core A to core B. More...

## Functions
int32_t | SIPC_Register_Isr (HwiP_Params *pHwiParams, SIPC_InterruptConfig *pInterruptConfig, SIPC_Params *params, HwiP_FxnCallback callback)
| Register SIPC interrupts for SOC. More...
void | SIPC_isr (void *args)

## Variables
SIPC_MailboxConfig | gSIPC_SecureHostMboxConfig [CORE_ID_MAX - 1U]
| Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication. More...
SIPC_MailboxConfig | gSIPC_HsmMboxConfig [CORE_ID_MAX - 1U]
| Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication. More...
SIPC_SwQueue * | gSIPC_QueSecureHostToHsm [MAX_SEC_CORES_WITH_HSM - 1U]
| Global structure holding R5 to HSM queues addresses indexed by sec core id. More...
SIPC_SwQueue * | gSIPC_QueHsmToSecureHost [MAX_SEC_CORES_WITH_HSM - 1U]
| Global structure holding HSM -> R5 queues addresses indexed by sec core id. More...

## Function Documentation

## ◆ SIPC_Register_Isr()

int32_t SIPC_Register_Isr | ( | HwiP_Params * | pHwiParams,
|  | SIPC_InterruptConfig * | pInterruptConfig,
|  | SIPC_Params * | params,
|  | HwiP_FxnCallback | callback
| ) |  |

Register SIPC interrupts for SOC.

This API will register SIPC interrupts. This API acts as an abstraction layer to register interrupts for different SOCs having different interrupt controllers

## ◆ SIPC_isr()

void SIPC_isr | ( | void * | args | ) |

## Variable Documentation

## ◆ gSIPC_SecureHostMboxConfig

SIPC_MailboxConfig gSIPC_SecureHostMboxConfig[CORE_ID_MAX - 1U]
| extern

Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.

## ◆ gSIPC_HsmMboxConfig

SIPC_MailboxConfig gSIPC_HsmMboxConfig[CORE_ID_MAX - 1U]
| extern

Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communication.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.

## ◆ gSIPC_QueSecureHostToHsm

SIPC_SwQueue* gSIPC_QueSecureHostToHsm[MAX_SEC_CORES_WITH_HSM - 1U]
| extern

Global structure holding R5 to HSM queues addresses indexed by sec core id.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.

## ◆ gSIPC_QueHsmToSecureHost

SIPC_SwQueue* gSIPC_QueHsmToSecureHost[MAX_SEC_CORES_WITH_HSM - 1U]
| extern

Global structure holding HSM -> R5 queues addresses indexed by sec core id.

This is a pre-defined global since this config typically does not need to change based on end user use-cases for this SOC.