AM261x MCU+ SDK: mcspi_lld.h Source File

| AM261x MCU+ SDK 26.00.00 |

mcspi_lld.h
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1 /*
2 * Copyright (C) 2023-25 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
50 #ifndef MCSPI_LLD_H_
51 #define MCSPI_LLD_H_
52
53 /* ========================================================================== */
54 /* Include Files */
55 /* ========================================================================== */
56 #include <stdint.h>
57 #include <stdbool.h>
58 #include <drivers/hw_include/csl_types.h>
59 #include <drivers/hw_include/cslr_mcspi.h>
60 #include <drivers/hw_include/cslr.h>
61 #include <drivers/mcspi/v0/lld/dma/mcspi_dma.h>
62
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70
71
72 /* function pointer to get clock ticks */
73 typedef uint32_t (*MCSPI_clockGet) (void);
74
75
82 #define MCSPI_STATUS_SUCCESS ((int32_t)0)
83
87 #define MCSPI_STATUS_FAILURE ((int32_t)-1)
88
92 #define MCSPI_TIMEOUT ((int32_t)-2)
93
97 #define MCSPI_INVALID_PARAM ((int32_t)-3)
98
102 #define MCSPI_STATUS_BUSY ((int32_t)-4)
103
107 #define MCSPI_INVALID_STATE ((int32_t)-5)
108
117 #define MCSPI_NO_WAIT ((uint32_t)0)
118
122 #define MCSPI_WAIT_FOREVER ((uint32_t)-1)
123
131 #define MCSPI_STATE_RESET ((uint32_t)0U)
132
136 #define MCSPI_STATE_READY ((uint32_t)1U)
137
141 #define MCSPI_STATE_BUSY ((uint32_t)2U)
142
146 #define MCSPI_STATE_ERROR ((uint32_t)3U)
147
158 #define MCSPI_CHANNEL_0 (0U)
159 #define MCSPI_CHANNEL_1 (1U)
160 #define MCSPI_CHANNEL_2 (2U)
161 #define MCSPI_CHANNEL_3 (3U)
162
172 #define MCSPI_OPER_MODE_POLLED (0U)
173 #define MCSPI_OPER_MODE_INTERRUPT (1U)
174 #define MCSPI_OPER_MODE_DMA (2U)
175
178 #define MCSPI_MAX_NUM_CHANNELS (4U)
179
188 #define MCSPI_TRANSFER_COMPLETED ((int32_t)0U)
189 #define MCSPI_TRANSFER_STARTED ((int32_t)1U)
190 #define MCSPI_TRANSFER_CANCELLED ((int32_t)2U)
191 #define MCSPI_TRANSFER_FAILED ((int32_t)3U)
192 #define MCSPI_TRANSFER_CSN_DEASSERT ((int32_t)4U)
193 #define MCSPI_TRANSFER_TIMEOUT ((int32_t)5U)
194
212 #define MCSPI_MS_MODE_CONTROLLER (CSL_MCSPI_MODULCTRL_MS_MASTER)
213
214 #define MCSPI_MS_MODE_PERIPHERAL (CSL_MCSPI_MODULCTRL_MS_SLAVE)
215
231 #define MCSPI_FF_POL0_PHA0 (0U)
232 #define MCSPI_FF_POL0_PHA1 (1U)
233 #define MCSPI_FF_POL1_PHA0 (2U)
234 #define MCSPI_FF_POL1_PHA1 (3U)
235
246 #define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
247
248 #define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
249
257 #define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)
258 #define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)
259 #define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)
260
269 #define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
270
271 #define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
272
281 #define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
282
283 #define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
284
292 #define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)
293 #define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)
294 #define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)
295 #define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)
296
305 #define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
306
307 #define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
308
319 #define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
320
321 #define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
322
323 #define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
324
325 #define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
326
338 #define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
339
340 #define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
341
353 #define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
354 #define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)
355
366 #define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
367
368 #define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
369
370 #define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
371
372 #define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
373
374 #define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
375
378 #define MCSPI_ERROR_TX_UNDERFLOW (0x00000001U)
379 #define MCSPI_ERROR_RX_OVERFLOW (0x00000002U)
380
382 #define MCSPI_MAX_CLK_DIVIDER_SUPPORTED (4096U)
383
384 /* ========================================================================== */
385 /* Advanced Macros & Typedefs */
386 /* ========================================================================== */
387
389 #define MCSPI_FIFO_LENGTH (64U)
390
393 #define MCSPI_RX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
394 << \
395 CSL_MCSPI_CH0CONF_FFER_SHIFT)
396
400 #define MCSPI_RX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \
401 << CSL_MCSPI_CH0CONF_FFER_SHIFT)
402
406 #define MCSPI_TX_FIFO_ENABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \
407 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
408
412 #define MCSPI_TX_FIFO_DISABLE ((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \
413 << CSL_MCSPI_CH0CONF_FFEW_SHIFT)
414
418 #define MCSPI_REG_OFFSET (0x14U)
419
420 #define MCSPI_CHCONF(x) ((uint32_t) CSL_MCSPI_CH0CONF + \
421 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
422 (uint32_t) (x)))
423
424 #define MCSPI_CHSTAT(x) ((uint32_t) CSL_MCSPI_CH0STAT + \
425 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
426 (uint32_t) (x)))
427
428 #define MCSPI_CHCTRL(x) ((uint32_t) CSL_MCSPI_CH0CTRL + \
429 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
430 (uint32_t) (x)))
431
432 #define MCSPI_CHTX(x) ((uint32_t) CSL_MCSPI_TX0 + \
433 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
434 (uint32_t) (x)))
435
436 #define MCSPI_CHRX(x) ((uint32_t) CSL_MCSPI_RX0 + \
437 (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
438 (uint32_t) (x)))
439
440 #define MCSPI_CLKD_MASK (0x0FU)
441
443 #define MCSPI_IRQSTATUS_CLEAR_ALL (CSL_MCSPI_IRQSTATUS_EOW_MASK | \
444 CSL_MCSPI_IRQSTATUS_WKS_MASK | \
445 CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK | \
446 CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK | \
447 CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK | \
448 CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK | \
449 CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK | \
450 CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK | \
451 CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK | \
452 CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK | \
453 CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK | \
454 CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK | \
455 CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK | \
456 CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK | \
457 CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)
458
459 /* ========================================================================== */
460 /* Structure Declarations */
461 /* ========================================================================== */
462
471 typedef struct
472 {
473 uint32_t channel;
476 uint32_t csDisable;
482 uint32_t dataSize;
493 uint32_t count;
496 void *txBuf;
507 void *rxBuf;
514 void *args;
516 uint32_t timeout;
518 uint32_t status;
520 } MCSPI_Transaction;
521
531 typedef struct MCSPI_ExtendedParams_s
532 {
533 uint32_t channel;
536 uint32_t csDisable;
542 uint32_t dataSize;
553 void *args;
555 } MCSPI_ExtendedParams;
556
568 typedef struct
569 {
570 uint32_t chNum;
572 uint32_t frameFormat;
574 uint32_t bitRate;
576 uint32_t csPolarity;
578 uint32_t trMode;
580 uint32_t inputSelect;
582 uint32_t dpe0;
584 uint32_t dpe1;
586 uint32_t slvCsSelect;
589 uint32_t startBitEnable;
592 uint32_t startBitPolarity;
595 uint32_t turboEnable;
597 uint32_t csIdleTime;
600 uint32_t defaultTxData;
603 uint32_t txFifoTrigLvl;
605 uint32_t rxFifoTrigLvl;
607 } MCSPI_ChConfig;
608
609 /* ========================================================================== */
610 /* Function pointers Declarations */
611 /* ========================================================================== */
612
620 typedef void (*MCSPI_transferCallbackFxn) (void *args, uint32_t transferStatus);
621
629 typedef void (*MCSPI_errorCallbackFxn) (void *args, uint32_t transferStatus);
630
631 /* ========================================================================== */
632 /* Internal/Private Structure Declarations */
633 /* ========================================================================== */
634
638 typedef struct
639 {
640 /*
641 * User parameters
642 */
643 MCSPI_ChConfig *chCfg;
645 uint32_t dmaChConfigNum;
648 /*
649 * State variables
650 */
651 uint32_t isOpen;
653 uint32_t csDisable;
655 uint32_t csEnable;
657 uint8_t *curTxBufPtr;
659 uint8_t *curRxBufPtr;
661 uint32_t curTxWords;
665 uint32_t curRxWords;
668 /*
669 * MCSPI derived variables
670 */
671 uint8_t bufWidthShift;
677 uint32_t dataWidthBitMask;
679 uint32_t effTxFifoDepth;
681 uint32_t effRxFifoDepth;
683 uint32_t intrMask;
685 MCSPI_DmaChConfig dmaChCfg;
687 uint32_t chConfRegVal;
689 uint32_t chCtrlRegVal;
691 uint32_t systRegVal;
692 } MCSPI_ChObject;
693
697 typedef struct
698 {
699 uint32_t inputClkFreq;
701 uint32_t intrNum;
703 uint32_t operMode;
705 uint8_t intrPriority;
707 uint32_t chMode;
709 uint32_t pinMode;
711 uint32_t initDelay;
713 uint32_t multiWordAccess;
715 uint32_t msMode;
717 uint32_t chEnabled[MCSPI_MAX_NUM_CHANNELS];
719 MCSPI_ChObject chObj[MCSPI_MAX_NUM_CHANNELS];
721 MCSPI_DmaHandle mcspiDmaHandle;
723 MCSPI_clockGet clockP_get;
724 /* clock usec to tick */
725 MCSPI_transferCallbackFxn transferCallbackFxn;
727 MCSPI_errorCallbackFxn errorCallbackFxn;
729 } MCSPILLD_InitObject, *MCSPILLD_InitHandle;
730
734 typedef struct
735 {
736 uint32_t baseAddr;
739 /*
740 * User parameters
741 */
742 uint32_t state;
744 void *transferMutex;
746 MCSPILLD_InitHandle hMcspiInit;
748 uint32_t errorFlag;
751 /*
752 * Transfer parameters
753 */
754 uint32_t transferChannel;
756 uint32_t transferCsDisable;
758 uint32_t transferDataSize;
760 MCSPI_Transaction transaction;
762 void* args;
764 } MCSPILLD_Object, *MCSPILLD_Handle;
765
766 /* ========================================================================== */
767 /* Function Declarations */
768 /* ========================================================================== */
769
770 /* Low level HW functions */
771 void MCSPI_reset(uint32_t baseAddr);
772 void MCSPI_clearAllIrqStatus(uint32_t baseAddr);
773 void MCSPI_stop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum);
774 void MCSPI_setChDataSize(uint32_t baseAddr, MCSPI_ChObject *chObj,
775 uint32_t dataSize, uint32_t csDisable);
776
777 static inline void MCSPI_intrStatusClear(const MCSPI_ChObject *chObj,
778 uint32_t baseAddr, uint32_t intFlags)
779 {
780 /* Clear the SSB bit in the MCSPI_SYST register. */
781 CSL_REG32_WR(baseAddr + CSL_MCSPI_SYST, chObj->systRegVal);
782 /* Clear the interrupt status. */
783 CSL_REG32_WR(baseAddr + CSL_MCSPI_IRQSTATUS, intFlags);
784 }
785
786 /* ========================================================================== */
787 /* Function Declarations */
788 /* ========================================================================== */
789
798 int32_t MCSPI_lld_init(MCSPILLD_Handle hMcspi);
799
808 int32_t MCSPI_lld_initDma(MCSPILLD_Handle hMcspi);
817 int32_t MCSPI_lld_deInit(MCSPILLD_Handle hMcspi);
818
827 int32_t MCSPI_lld_deInitDma(MCSPILLD_Handle hMcspi);
828
841 int32_t MCSPI_lld_write(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout,
842 const MCSPI_ExtendedParams *extendedParams);
843
856 int32_t MCSPI_lld_writeIntr(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout,
857 const MCSPI_ExtendedParams *extendedParams);
858
871 int32_t MCSPI_lld_writeDma(MCSPILLD_Handle hMcspi, void * txBuf, uint32_t count,
872 uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
873
886 int32_t MCSPI_lld_read(MCSPILLD_Handle hMcspi, void * rxBuf, uint32_t count, uint32_t timeout,
887 const MCSPI_ExtendedParams *extendedParams);
888
901 int32_t MCSPI_lld_readIntr(MCSPILLD_Handle hMcspi, void * rxBuf, uint32_t count, uint32_t timeout,
902 const MCSPI_ExtendedParams *extendedParams);
903
917 int32_t MCSPI_lld_readDma(MCSPILLD_Handle hMcspi, void * rxBuf, uint32_t count,
918 uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
931 int32_t MCSPI_lld_readWrite(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count,
932 uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
945 int32_t MCSPI_lld_readWriteIntr(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count,
946 uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
959 int32_t MCSPI_lld_readWriteDma(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count,
960 uint32_t timeout, const MCSPI_ExtendedParams *extendedParams);
961
970 int32_t MCSPI_lld_readWriteCancel(MCSPILLD_Handle hMcspi);
971
980 int32_t MCSPI_lld_readWriteDmaCancel(MCSPILLD_Handle hMcspi);
981
991 int32_t MCSPI_lld_transfer(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction);
992
1002 int32_t MCSPI_lld_transferIntr(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction);
1003
1013 int32_t MCSPI_lld_transferDma(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction);
1014
1021 void MCSPI_lld_controllerIsr(void* args);
1022
1029 void MCSPI_lld_peripheralIsr(void* args);
1030
1037 int32_t MCSPI_lld_getState(MCSPILLD_Handle hMcspi);
1038
1047 int32_t MCSPI_lld_transferCancel(MCSPILLD_Handle hMcspi);
1048
1057 int32_t MCSPI_lld_transferDmaCancel(MCSPILLD_Handle hMcspi);
1058
1065 static inline void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig);
1066
1073 static inline void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans);
1074
1083 uint32_t MCSPI_lld_getBaseAddr(MCSPILLD_Handle handle);
1084
1096 int32_t MCSPI_lld_reConfigFifo(MCSPILLD_Handle handle,
1097 uint32_t chNum,
1098 uint32_t numWordsRxTx);
1099
1110 void MCSPI_initiateLastChunkTransfer(MCSPILLD_Handle hMcspi,
1111 MCSPI_ChObject *chObj,
1112 const MCSPI_Transaction *transaction);
1113
1128 static inline uint8_t MCSPI_getBufWidthShift(uint32_t dataSize);
1129
1153 static inline uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum);
1154
1165 static inline uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum);
1166
1176 static inline void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum,
1177 uint32_t regVal);
1178
1189 static inline uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum);
1190
1200 static inline void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum,
1201 uint32_t regVal);
1202
1219 static inline void MCSPI_writeTxDataReg(uint32_t baseAddr,
1220 uint32_t txData,
1221 uint32_t chNum);
1222
1242 static inline void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum,
1243 uint32_t enableFlag);
1244
1264 static inline void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum,
1265 uint32_t enableFlag);
1266
1282 static inline uint32_t MCSPI_readRxDataReg(uint32_t baseAddr,
1283 uint32_t chNum);
1284
1301 static inline void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum,
1302 uint32_t dataWidth);
1303
1322 int32_t MCSPI_lld_dmaInit(MCSPI_DmaHandle mcspiDmaHandle);
1323
1335 int32_t MCSPI_lld_dmaDeInit(MCSPILLD_Handle hMcspi, const MCSPI_ChConfig *chCfg, uint32_t chCnt);
1336
1347 int32_t MCSPI_lld_dmaChInit(MCSPILLD_Handle hMcspi, uint32_t chCnt);
1348
1361 int32_t MCSPI_lld_dmaTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction);
1362
1374 void MCSPI_lld_dmaStop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum);
1375
1378 /* ========================================================================== */
1379 /* Static Function Definitions */
1380 /* ========================================================================== */
1381
1382 static inline void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig)
1383 {
1384 if(chConfig != NULL)
1385 {
1386 chConfig->chNum = MCSPI_CHANNEL_0;
1387 chConfig->frameFormat = MCSPI_FF_POL0_PHA0;
1388 chConfig->bitRate = 1000000U;
1389 chConfig->csPolarity = MCSPI_CS_POL_LOW;
1390 chConfig->trMode = MCSPI_TR_MODE_TX_RX;
1391 chConfig->inputSelect = MCSPI_IS_D1;
1392 chConfig->dpe0 = MCSPI_DPE_ENABLE;
1393 chConfig->dpe1 = MCSPI_DPE_DISABLE;
1394 chConfig->slvCsSelect = MCSPI_SLV_CS_SELECT_0;
1395 chConfig->startBitEnable = FALSE;
1396 chConfig->startBitPolarity = MCSPI_SB_POL_LOW;
1397 chConfig->csIdleTime = MCSPI_TCS0_0_CLK;
1398 chConfig->defaultTxData = 0x00000000U;
1399 }
1400 }
1401
1402 static inline void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans)
1403 {
1404 if(trans != NULL)
1405 {
1406 trans->channel = 0U;
1407 trans->csDisable = TRUE;
1408 trans->dataSize = 8U;
1409 trans->count = 0U;
1410 trans->txBuf = NULL;
1411 trans->rxBuf = NULL;
1412 trans->args = NULL;
1413 trans->timeout = MCSPI_WAIT_FOREVER;
1414 }
1415 }
1416
1417 static inline uint8_t MCSPI_getBufWidthShift(uint32_t dataSize)
1418 {
1419 uint8_t bufWidthShift = 0U;
1420
1421 if(dataSize <= 8U)
1422 {
1423 bufWidthShift = 0U;
1424 }
1425 else if(dataSize <= 16U)
1426 {
1427 bufWidthShift = 1U;
1428 }
1429 else
1430 {
1431 bufWidthShift = 2U;
1432 }
1433
1434 return bufWidthShift;
1435 }
1436
1437 static inline uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
1438 {
1439 /* Return the status from MCSPI_CHSTAT register. */
1440 return (CSL_REG32_RD(baseAddr + MCSPI_CHSTAT(chNum)));
1441 }
1442
1443 static inline uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
1444 {
1445 return CSL_REG32_RD(baseAddr + MCSPI_CHCTRL(chNum));
1446 }
1447
1448 static inline void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum,
1449 uint32_t regVal)
1450 {
1451 CSL_REG32_WR(baseAddr + MCSPI_CHCTRL(chNum), regVal);
1452 }
1453
1454 static inline uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
1455 {
1456 return CSL_REG32_RD(baseAddr + MCSPI_CHCONF(chNum));
1457 }
1458
1459 static inline void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum,
1460 uint32_t regVal)
1461 {
1462 CSL_REG32_WR(baseAddr + MCSPI_CHCONF(chNum), regVal);
1463 }
1464
1465 static inline void MCSPI_writeTxDataReg(uint32_t baseAddr,
1466 uint32_t txData,
1467 uint32_t chNum)
1468 {
1469 /* Load the MCSPI_TX register with the data to be transmitted */
1470 CSL_REG32_WR(baseAddr + MCSPI_CHTX(chNum), txData);
1471 }
1472
1473 static inline void MCSPI_enableTxFIFO(uint32_t baseAddr,
1474 uint32_t chNum,
1475 uint32_t enableFlag)
1476 {
1477 /* Set the FFEW field with user sent value. */
1478 CSL_REG32_FINS(
1479 baseAddr + MCSPI_CHCONF(chNum),
1480 MCSPI_CH0CONF_FFEW,
1481 enableFlag >> CSL_MCSPI_CH0CONF_FFEW_SHIFT);
1482 }
1483
1484 static inline void MCSPI_enableRxFIFO(uint32_t baseAddr,
1485 uint32_t chNum,
1486 uint32_t enableFlag)
1487 {
1488 /* Set the FFER field with the user sent value. */
1489 CSL_REG32_FINS(
1490 baseAddr + MCSPI_CHCONF(chNum),
1491 MCSPI_CH0CONF_FFER,
1492 enableFlag >> CSL_MCSPI_CH0CONF_FFER_SHIFT);
1493 }
1494
1495 static inline uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
1496 {
1497 /* Return the data present in the MCSPI_RX register. */
1498 return (CSL_REG32_RD(baseAddr + MCSPI_CHRX(chNum)));
1499 }
1500
1501 static inline void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum,
1502 uint32_t dataWidth)
1503 {
1504 uint32_t regVal;
1505
1506 regVal = CSL_REG32_RD(baseAddr + MCSPI_CHCONF(chNum));
1507 CSL_FINS(regVal, MCSPI_CH0CONF_WL, (dataWidth - 1U));
1508 CSL_REG32_WR(baseAddr + MCSPI_CHCONF(chNum), regVal);
1509 }
1510
1511 #ifdef __cplusplus
1512 }
1513 #endif
1514
1515 #endif /* #ifndef MCSPI_LLD_H_ */
1516
MCSPI_lld_readWriteDmaCancel
int32_t MCSPI_lld_readWriteDmaCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer in DMA mode.
MCSPILLD_InitObject::pinMode
uint32_t pinMode
Definition: mcspi_lld.h:709
MCSPI_getBufWidthShift
static uint8_t MCSPI_getBufWidthShift(uint32_t dataSize)
This API will return the buffer width in bytes based on dataSize.
Definition: mcspi_lld.h:1417
MCSPI_lld_dmaDeInit
int32_t MCSPI_lld_dmaDeInit(MCSPILLD_Handle hMcspi, const MCSPI_ChConfig *chCfg, uint32_t chCnt)
API to close an MCSPI DMA channel.
EDMA_Config
EDMA Instance Configuration. Pointer to this object is returned as handle by driver open.
Definition: edma/v0/edma.h:675
args
void * args
Definition: hsmclient_msg.h:4
MCSPI_clockGet
uint32_t(* MCSPI_clockGet)(void)
Definition: mcspi_lld.h:73
MCSPI_ChObject::curTxBufPtr
uint8_t * curTxBufPtr
Definition: mcspi_lld.h:657
FALSE
#define FALSE
Definition: os_defs.h:32
MCSPILLD_InitObject
MCSPI driver initialization object.
Definition: mcspi_lld.h:698
MCSPI_ChObject
MCSPI channel object.
Definition: mcspi_lld.h:639
MCSPI_Transaction::count
uint32_t count
Definition: mcspi_lld.h:493
MCSPI_ChConfig::txFifoTrigLvl
uint32_t txFifoTrigLvl
Definition: mcspi_lld.h:603
MCSPI_CHTX
#define MCSPI_CHTX(x)
Base address of McSPI_CHTX(x)
Definition: mcspi_lld.h:432
MCSPI_FF_POL0_PHA0
#define MCSPI_FF_POL0_PHA0
Definition: mcspi_lld.h:231
MCSPI_ChConfig::rxFifoTrigLvl
uint32_t rxFifoTrigLvl
Definition: mcspi_lld.h:605
MCSPILLD_InitObject::intrNum
uint32_t intrNum
Definition: mcspi_lld.h:701
MCSPI_lld_readWriteCancel
int32_t MCSPI_lld_readWriteCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer.
MCSPI_DPE_DISABLE
#define MCSPI_DPE_DISABLE
No transmission on Data Line.
Definition: mcspi_lld.h:283
MCSPI_Transaction::status
uint32_t status
Definition: mcspi_lld.h:518
MCSPI_Transaction
Data structure used with MCSPI_transfer()
Definition: mcspi_lld.h:472
MCSPI_ChObject::effTxFifoDepth
uint32_t effTxFifoDepth
Definition: mcspi_lld.h:679
MCSPI_TCS0_0_CLK
#define MCSPI_TCS0_0_CLK
0.5 clock cycles delay
Definition: mcspi_lld.h:319
MCSPI_writeTxDataReg
static void MCSPI_writeTxDataReg(uint32_t baseAddr, uint32_t txData, uint32_t chNum)
This API will put the data on to the McSPI Channel transmit register.
Definition: mcspi_lld.h:1465
MCSPILLD_Object::transferDataSize
uint32_t transferDataSize
Definition: mcspi_lld.h:758
MCSPI_lld_getBaseAddr
uint32_t MCSPI_lld_getBaseAddr(MCSPILLD_Handle handle)
Function to get base address of MCSPI instance of a particular handle.
MCSPI_ChObject::intrMask
uint32_t intrMask
Definition: mcspi_lld.h:683
MCSPILLD_InitObject::clockP_get
MCSPI_clockGet clockP_get
Definition: mcspi_lld.h:723
MCSPI_WAIT_FOREVER
#define MCSPI_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: mcspi_lld.h:122
MCSPI_ChObject::chConfRegVal
uint32_t chConfRegVal
Definition: mcspi_lld.h:687
MCSPI_enableTxFIFO
static void MCSPI_enableTxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Tx FIFOs of McSPI peripheral.
Definition: mcspi_lld.h:1473
MCSPI_lld_transferCancel
int32_t MCSPI_lld_transferCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer.
MCSPILLD_Object::errorFlag
uint32_t errorFlag
Definition: mcspi_lld.h:748
MCSPI_SLV_CS_SELECT_0
#define MCSPI_SLV_CS_SELECT_0
Definition: mcspi_lld.h:292
MCSPILLD_InitObject::intrPriority
uint8_t intrPriority
Definition: mcspi_lld.h:705
MCSPI_errorCallbackFxn
void(* MCSPI_errorCallbackFxn)(void *args, uint32_t transferStatus)
The definition of a error callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_C...
Definition: mcspi_lld.h:629
MCSPI_ChObject::dmaChConfigNum
uint32_t dmaChConfigNum
Definition: mcspi_lld.h:645
MCSPI_CHCONF
#define MCSPI_CHCONF(x)
Base address of McSPI_CHCONF(x)
Definition: mcspi_lld.h:420
MCSPI_lld_controllerIsr
void MCSPI_lld_controllerIsr(void *args)
This is the McSPI Controller ISR and can be used as IRQ handler in Controller mode.
MCSPI_lld_readWriteIntr
int32_t MCSPI_lld_readWriteIntr(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in Interrupt mode.
MCSPI_ChConfig::bitRate
uint32_t bitRate
Definition: mcspi_lld.h:574
MCSPI_lld_dmaTransfer
int32_t MCSPI_lld_dmaTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction)
API to do a DMA transfer using a specific DMA driver - UDMA, EDMA etc.
MCSPI_ExtendedParams::args
void * args
Definition: mcspi_lld.h:553
MCSPILLD_InitObject::transferCallbackFxn
MCSPI_transferCallbackFxn transferCallbackFxn
Definition: mcspi_lld.h:725
MCSPI_lld_read
int32_t MCSPI_lld_read(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in Polling mode.
MCSPI_lld_Transaction_init
static void MCSPI_lld_Transaction_init(MCSPI_Transaction *trans)
Function to initialize the MCSPI_Transaction struct to its defaults.
Definition: mcspi_lld.h:1402
MCSPILLD_Object
MCSPI driver object.
Definition: mcspi_lld.h:735
MCSPI_SB_POL_LOW
#define MCSPI_SB_POL_LOW
Start-bit polarity is held to 0 during MCSPI transfer.
Definition: mcspi_lld.h:307
MCSPI_Transaction::timeout
uint32_t timeout
Definition: mcspi_lld.h:516
MCSPI_readRxDataReg
static uint32_t MCSPI_readRxDataReg(uint32_t baseAddr, uint32_t chNum)
This API will return the data present in the MCSPI_RX register.
Definition: mcspi_lld.h:1495
MCSPI_DPE_ENABLE
#define MCSPI_DPE_ENABLE
Data line selected for transmission.
Definition: mcspi_lld.h:281
MCSPI_Transaction::csDisable
uint32_t csDisable
Definition: mcspi_lld.h:476
MCSPI_IS_D1
#define MCSPI_IS_D1
Data line 1 (SPIDAT[1]) selected for reception.
Definition: mcspi_lld.h:271
MCSPI_ChObject::chCtrlRegVal
uint32_t chCtrlRegVal
Definition: mcspi_lld.h:689
MCSPILLD_InitHandle
struct MCSPILLD_InitObject * MCSPILLD_InitHandle
MCSPI_lld_peripheralIsr
void MCSPI_lld_peripheralIsr(void *args)
This is the McSPI Peripheral ISR and can be used as IRQ handler in Peripheral mode.
MCSPI_CHRX
#define MCSPI_CHRX(x)
Base address of McSPI_CHRX(x)
Definition: mcspi_lld.h:436
MCSPI_lld_writeDma
int32_t MCSPI_lld_writeDma(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in DMA mode.
MCSPI_ChConfig::trMode
uint32_t trMode
Definition: mcspi_lld.h:578
MCSPI_transferCallbackFxn
void(* MCSPI_transferCallbackFxn)(void *args, uint32_t transferStatus)
The definition of a transfer completion callback function used by the SPI driver when used in MCSPI_T...
Definition: mcspi_lld.h:620
MCSPILLD_Object::hMcspiInit
MCSPILLD_InitHandle hMcspiInit
Definition: mcspi_lld.h:746
MCSPI_TR_MODE_TX_RX
#define MCSPI_TR_MODE_TX_RX
Definition: mcspi_lld.h:257
MCSPI_CHSTAT
#define MCSPI_CHSTAT(x)
Base address of McSPI_CHSTAT(x)
Definition: mcspi_lld.h:424
MCSPI_CHANNEL_0
#define MCSPI_CHANNEL_0
Definition: mcspi_lld.h:158
MCSPILLD_Object::transferChannel
uint32_t transferChannel
Definition: mcspi_lld.h:754
MCSPI_lld_ChConfig_init
static void MCSPI_lld_ChConfig_init(MCSPI_ChConfig *chConfig)
Function to initialize the MCSPI_ChConfig struct to its defaults.
Definition: mcspi_lld.h:1382
MCSPI_ChObject::isOpen
uint32_t isOpen
Definition: mcspi_lld.h:651
MCSPI_readChCtrlReg
static uint32_t MCSPI_readChCtrlReg(uint32_t baseAddr, uint32_t chNum)
This API returns Channel control register value.
Definition: mcspi_lld.h:1443
MCSPILLD_Object::state
uint32_t state
Definition: mcspi_lld.h:742
MCSPI_lld_initDma
int32_t MCSPI_lld_initDma(MCSPILLD_Handle hMcspi)
This API Initializes the McSPI instance in DMA Mode.
MCSPI_lld_deInitDma
int32_t MCSPI_lld_deInitDma(MCSPILLD_Handle hMcspi)
This API De-Initializes the McSPI instance in DMA mode.
MCSPI_lld_dmaChInit
int32_t MCSPI_lld_dmaChInit(MCSPILLD_Handle hMcspi, uint32_t chCnt)
API to init a DMA Channel opened.
MCSPI_lld_transfer
int32_t MCSPI_lld_transfer(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API transfers data from the McSPI instance in Polling mode.
MCSPI_initiateLastChunkTransfer
void MCSPI_initiateLastChunkTransfer(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, const MCSPI_Transaction *transaction)
This API will initiate the last chuncks when FIFO is enabled. The byte thats are non-multiple of FIFO...
MCSPI_ChObject::curRxWords
uint32_t curRxWords
Definition: mcspi_lld.h:665
MCSPI_lld_transferDmaCancel
int32_t MCSPI_lld_transferDmaCancel(MCSPILLD_Handle hMcspi)
This API cancels current McSPI transfer in DMA mode.
MCSPI_lld_init
int32_t MCSPI_lld_init(MCSPILLD_Handle hMcspi)
This API Initializes the McSPI instance.
MCSPI_clearAllIrqStatus
void MCSPI_clearAllIrqStatus(uint32_t baseAddr)
MCSPI_lld_transferDma
int32_t MCSPI_lld_transferDma(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API reads data from the McSPI instance in DMA mode.
MCSPI_enableRxFIFO
static void MCSPI_enableRxFIFO(uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
This API will enable/disable the Rx FIFOs of McSPI peripheral.
Definition: mcspi_lld.h:1484
MCSPI_intrStatusClear
static void MCSPI_intrStatusClear(const MCSPI_ChObject *chObj, uint32_t baseAddr, uint32_t intFlags)
Definition: mcspi_lld.h:777
MCSPI_ChConfig::csPolarity
uint32_t csPolarity
Definition: mcspi_lld.h:576
MCSPI_ChConfig::startBitPolarity
uint32_t startBitPolarity
Definition: mcspi_lld.h:592
MCSPI_ChConfig::turboEnable
uint32_t turboEnable
Definition: mcspi_lld.h:595
MCSPI_ExtendedParams::channel
uint32_t channel
Definition: mcspi_lld.h:533
MCSPILLD_Object::transferMutex
void * transferMutex
Definition: mcspi_lld.h:744
MCSPILLD_InitObject::multiWordAccess
uint32_t multiWordAccess
Definition: mcspi_lld.h:713
MCSPI_lld_dmaInit
int32_t MCSPI_lld_dmaInit(MCSPI_DmaHandle mcspiDmaHandle)
API to open an MCSPI DMA channel.
MCSPI_reset
void MCSPI_reset(uint32_t baseAddr)
MCSPI_lld_dmaStop
void MCSPI_lld_dmaStop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum)
API to Stop DMA using a specific DMA driver - UDMA, EDMA etc.
MCSPI_lld_writeIntr
int32_t MCSPI_lld_writeIntr(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in Interrupt mode.
MCSPI_ChObject::csDisable
uint32_t csDisable
Definition: mcspi_lld.h:653
MCSPI_Transaction::args
void * args
Definition: mcspi_lld.h:514
MCSPI_ChObject::dataWidthBitMask
uint32_t dataWidthBitMask
Definition: mcspi_lld.h:677
MCSPI_ExtendedParams
Data structure used with MCSPI_lld_read(), MCSPI_lld_readIntr(), MCSPI_lld_readDma(),...
Definition: mcspi_lld.h:532
MCSPI_ExtendedParams::dataSize
uint32_t dataSize
Definition: mcspi_lld.h:542
MCSPI_ChConfig::startBitEnable
uint32_t startBitEnable
Definition: mcspi_lld.h:589
MCSPI_Transaction::txBuf
void * txBuf
Definition: mcspi_lld.h:496
MCSPI_CHCTRL
#define MCSPI_CHCTRL(x)
Base address of McSPI_CHCTRL(x)
Definition: mcspi_lld.h:428
MCSPILLD_InitObject::chMode
uint32_t chMode
Definition: mcspi_lld.h:707
MCSPI_lld_reConfigFifo
int32_t MCSPI_lld_reConfigFifo(MCSPILLD_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
Function to re-configure Effective FIFO Words.
MCSPI_Transaction::rxBuf
void * rxBuf
Definition: mcspi_lld.h:507
MCSPI_ChObject::systRegVal
uint32_t systRegVal
Definition: mcspi_lld.h:691
MCSPI_ChObject::effRxFifoDepth
uint32_t effRxFifoDepth
Definition: mcspi_lld.h:681
MCSPI_MAX_NUM_CHANNELS
#define MCSPI_MAX_NUM_CHANNELS
Max number of channels/Chip Select (CS) supported.
Definition: mcspi_lld.h:178
MCSPI_Transaction::dataSize
uint32_t dataSize
Definition: mcspi_lld.h:482
MCSPI_lld_write
int32_t MCSPI_lld_write(MCSPILLD_Handle hMcspi, void *txBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API writes data to the McSPI instance in Polling mode.
MCSPI_ChObject::curTxWords
uint32_t curTxWords
Definition: mcspi_lld.h:661
MCSPILLD_InitObject::mcspiDmaHandle
MCSPI_DmaHandle mcspiDmaHandle
Definition: mcspi_lld.h:721
MCSPI_ChConfig::slvCsSelect
uint32_t slvCsSelect
Definition: mcspi_lld.h:586
MCSPI_lld_deInit
int32_t MCSPI_lld_deInit(MCSPILLD_Handle hMcspi)
This API De-Initializes the McSPI instance.
MCSPI_readChStatusReg
static uint32_t MCSPI_readChStatusReg(uint32_t baseAddr, uint32_t chNum)
This API will return the status of the McSPI channel currently in use.
Definition: mcspi_lld.h:1437
MCSPI_stop
void MCSPI_stop(MCSPILLD_Handle hMcspi, MCSPI_ChObject *chObj, uint32_t chNum)
MCSPI_ChObject::bufWidthShift
uint8_t bufWidthShift
Definition: mcspi_lld.h:671
MCSPILLD_Object::transaction
MCSPI_Transaction transaction
Definition: mcspi_lld.h:760
MCSPILLD_Handle
struct MCSPILLD_Object * MCSPILLD_Handle
MCSPI_lld_readWriteDma
int32_t MCSPI_lld_readWriteDma(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in DMA mode.
MCSPI_ExtendedParams::csDisable
uint32_t csDisable
Definition: mcspi_lld.h:536
MCSPI_ChObject::curRxBufPtr
uint8_t * curRxBufPtr
Definition: mcspi_lld.h:659
MCSPI_lld_readIntr
int32_t MCSPI_lld_readIntr(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in Interrupt mode.
MCSPI_CS_POL_LOW
#define MCSPI_CS_POL_LOW
SPIEN (CS) is held low during the ACTIVE state.
Definition: mcspi_lld.h:248
MCSPILLD_Object::args
void * args
Definition: mcspi_lld.h:762
MCSPI_lld_readWrite
int32_t MCSPI_lld_readWrite(MCSPILLD_Handle hMcspi, void *txBuf, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads writes data from the McSPI instance in polling mode.
MCSPI_ChConfig::defaultTxData
uint32_t defaultTxData
Definition: mcspi_lld.h:600
MCSPI_ChConfig::dpe1
uint32_t dpe1
Definition: mcspi_lld.h:584
MCSPILLD_InitObject::msMode
uint32_t msMode
Definition: mcspi_lld.h:715
MCSPI_ChObject::csEnable
uint32_t csEnable
Definition: mcspi_lld.h:655
MCSPILLD_InitObject::operMode
uint32_t operMode
Definition: mcspi_lld.h:703
MCSPI_writeChCtrlReg
static void MCSPI_writeChCtrlReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel control register value.
Definition: mcspi_lld.h:1448
MCSPI_ChObject::chCfg
MCSPI_ChConfig * chCfg
Definition: mcspi_lld.h:643
TRUE
#define TRUE
Definition: os_defs.h:29
MCSPI_DmaChConfig
struct MCSPI_DmaChConfig_s * MCSPI_DmaChConfig
Definition: mcspi_dma_edma.h:78
MCSPI_readChConf
static uint32_t MCSPI_readChConf(uint32_t baseAddr, uint32_t chNum)
This API returns Channel Config register value.
Definition: mcspi_lld.h:1454
MCSPI_ChObject::dmaChCfg
MCSPI_DmaChConfig dmaChCfg
Definition: mcspi_lld.h:685
MCSPI_Transaction::channel
uint32_t channel
Definition: mcspi_lld.h:473
MCSPI_lld_readDma
int32_t MCSPI_lld_readDma(MCSPILLD_Handle hMcspi, void *rxBuf, uint32_t count, uint32_t timeout, const MCSPI_ExtendedParams *extendedParams)
This API reads data from the McSPI instance in DMA mode.
MCSPI_lld_transferIntr
int32_t MCSPI_lld_transferIntr(MCSPILLD_Handle hMcspi, MCSPI_Transaction *transaction)
This API reads data from the McSPI instance in Interrupt mode.
MCSPI_ChConfig::inputSelect
uint32_t inputSelect
Definition: mcspi_lld.h:580
MCSPILLD_Object::baseAddr
uint32_t baseAddr
Definition: mcspi_lld.h:736
MCSPI_ChConfig::dpe0
uint32_t dpe0
Definition: mcspi_lld.h:582
MCSPI_setChDataSize
void MCSPI_setChDataSize(uint32_t baseAddr, MCSPI_ChObject *chObj, uint32_t dataSize, uint32_t csDisable)
MCSPI_lld_getState
int32_t MCSPI_lld_getState(MCSPILLD_Handle hMcspi)
This API returns the driver state.
MCSPI_ChConfig
MCSPI configuration parameters for the channel.
Definition: mcspi_lld.h:569
MCSPI_writeChConfReg
static void MCSPI_writeChConfReg(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
This API sets Channel Config register value.
Definition: mcspi_lld.h:1459
MCSPILLD_InitObject::errorCallbackFxn
MCSPI_errorCallbackFxn errorCallbackFxn
Definition: mcspi_lld.h:727
MCSPILLD_Object::transferCsDisable
uint32_t transferCsDisable
Definition: mcspi_lld.h:756
MCSPILLD_InitObject::initDelay
uint32_t initDelay
Definition: mcspi_lld.h:711
MCSPI_setDataWidth
static void MCSPI_setDataWidth(uint32_t baseAddr, uint32_t chNum, uint32_t dataWidth)
This API will set the data width in the channel config register.
Definition: mcspi_lld.h:1501
MCSPILLD_InitObject::inputClkFreq
uint32_t inputClkFreq
Definition: mcspi_lld.h:699
MCSPI_ChConfig::frameFormat
uint32_t frameFormat
Definition: mcspi_lld.h:572
MCSPI_ChConfig::csIdleTime
uint32_t csIdleTime
Definition: mcspi_lld.h:597
MCSPI_ChConfig::chNum
uint32_t chNum
Definition: mcspi_lld.h:570