AM261x MCU+ SDK: cslr_soc_defines.h Source File

| AM261x MCU+ SDK 26.00.00 |

cslr_soc_defines.h
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1 /*
2 * Copyright (C) 2020-25 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
36
37 /* ========================================================================== */
38 /* Include Files */
39 /* ========================================================================== */
40
41 /* None */
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /* ========================================================================== */
48 /* Macros & Typedefs */
49 /* ========================================================================== */
51 #define CSL_UART_PER_CNT (4U)
52
54 #define CSL_SPI_PER_CNT (4U)
55
57 #define CSL_LIN_PER_CNT (3U)
58
60 #define CSL_I2C_PER_CNT (2U)
61
63 #define CSL_MCAN_PER_CNT (2U)
64
66 #define CSL_ETPWM_PER_CNT (10U)
67
69 #define CSL_ECAP_PER_CNT (8U)
70
72 #define CSL_EQEP_PER_CNT (2U)
73
75 #define CSL_SDFM_PER_CNT (2U)
76
78 #define CSL_ADC_PER_CNT (3U)
79
81 #define CSL_CMPSSA_PER_CNT (10U)
82
84 #define CSL_CMPSSB_PER_CNT (0U)
85
87 #define SOC_EDMA_NUM_DMACH (64U)
88
89 #define SOC_EDMA_NUM_QDMACH (8U)
90
91 #define SOC_EDMA_NUM_PARAMSETS (256U)
92
93 #define SOC_EDMA_NUM_EVQUE (2U)
94
95 #define SOC_EDMA_CHMAPEXIST (1U)
96
97 #define SOC_EDMA_NUM_REGIONS (8U)
98
99 #define SOC_EDMA_MEMPROTECT (1U)
100
101 #define SOC_EDMA_NUM_TPTC (2U)
102
109 #define EDMA_TPCC_A_ERRINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_ERRINT_MASK)
110 #define EDMA_TPCC_A_MPINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_MPINT_MASK)
111 #define EDMA_TPTC_A0_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_ERR_MASK)
112 #define EDMA_TPTC_A1_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_ERR_MASK)
113 #define EDMA_TPCC_A_PAR_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_PAR_ERR_MASK)
114 #define EDMA_TPCC_A_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_WRITE_ACCESS_ERROR_MASK)
115 #define EDMA_TPTC_A0_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_WRITE_ACCESS_ERROR_MASK)
116 #define EDMA_TPTC_A1_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_WRITE_ACCESS_ERROR_MASK)
117 #define EDMA_TPCC_A_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_READ_ACCESS_ERROR_MASK)
118 #define EDMA_TPTC_A0_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_READ_ACCESS_ERROR_MASK)
119 #define EDMA_TPTC_A1_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_READ_ACCESS_ERROR_MASK)
120
122 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
123
124 #define MCAN_MAX_RX_DMA_BUFFERS (7U)
125
127 #define MCAN_MAX_TX_DMA_BUFFERS (4U)
128
130 #define FSI_MAX_TX_DMA_BUFFERS (2U)
131
133 #define FSI_MAX_RX_DMA_BUFFERS (2U)
134
136 #define MCSPI_DMA_IS_FIFO_SUPPORTED (1U)
137
144 #define CSL_CORE_ID_R5FSS0_0 (0U)
145 #define CSL_CORE_ID_R5FSS0_1 (1U)
146 #define CSL_CORE_ID_MAX (2U)
147
155 #define PRIV_ID_M4FSS0_0 (1U)
156 #define PRIV_ID_R5FSS0_0 (4U)
157 #define PRIV_ID_R5FSS0_1 (5U)
158 #define PRIV_ID_ICSSM0 (9U)
159 #define PRIV_ID_ICSSM1 (11U)
160 #define PRIV_ID_CPSW (10U)
161 #define PRIV_ID_USB (12U)
162
165 /***********************************************************************
166 * MSS - CLOCK setting
167 ***********************************************************************/
168 /* Sys_vclk : 200MHz */
169 #define MSS_SYS_VCLK 200000000U
170 #define R5F_CLOCK_MHZ 400U
171
172 //#define EDMA_MSS_TPCC_A_NUM_PARAM_SETS (128U)
173 //#define EDMA_MSS_TPCC_A_NUM_DMA_CHANS (64U)
174 //#define EDMA_MSS_TPCC_A_NUM_TC (2U)
175 //
176 //#define EDMA_HSM_TPCC_A_NUM_PARAM_SETS (128U)
177 //#define EDMA_HSM_TPCC_A_NUM_TC (2U)
178
186 #define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
187
196 #define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
197
198 #define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
199
202 #define CSL_CORE_R5F_INTR_MAX (256U)
203
204 /***********************************************************************
205 * Cache line size definitions
206 ***********************************************************************/
207 /* Cache line size definitions */
208 #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
209 #define CSL_CACHE_L1P_LINESIZE (32U)
210 #define CSL_CACHE_L1D_LINESIZE (32U)
211 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') /* M4F */
212 /* No cache support */
213 #endif
214
215 /* ========================================================================== */
216 /* Structures and Enums */
217 /* ========================================================================== */
218
219 /* None */
220
221 /* ========================================================================== */
222 /* Global Variables */
223 /* ========================================================================== */
224
225 /* None */
226
227 /* ========================================================================== */
228 /* Function Declarations */
229 /* ========================================================================== */
230
231 /* None */
232
233 #ifdef __cplusplus
234 }
235 #endif
236
237 #endif /* CSLR_SOC_DEFINES_H_ */