AM261x MCU+ SDK: enet_osal.h File Reference

| AM261x MCU+ SDK 26.00.00 |

Data Structures | Typedefs | Enumerations | Functions
enet_osal.h File Reference

## Introduction

This file contains the OSAL API of the Enet driver.

Go to the source code of this file.

## Data Structures
struct | SemaphoreP_enetOsal
| Semaphore structure. More...
struct | HwiP_enetOsal
| Hwi structure. More...

## Typedefs
typedef void(* | EnetOsal_Isr) (uintptr_t arg)
| Enet OSAL ISR callback function prototype. More...

## Enumerations
enum | EnetOSAL_armGicTrigType_t { ENETOSAL_ARM_GIC_TRIG_TYPE_LEVEL = 1, ENETOSAL_ARM_GIC_TRIG_TYPE_EDGE = 2, ENETOSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL = 3, ENETOSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL = 4, ENETOSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE = 5, ENETOSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE = 6 }
| Enumerates the types different trigger types. Please refer to Section 4.3.13 Interrupt Configuration Registers, GICD_ICFGRn of ARM Generic Interrupt Controller Architecture version 2.0 Architecture Specification document for details. More...

## Functions
uintptr_t | EnetOsal_disableAllIntr (void)
| Enet OSAL intr disable function prototype. More...
void | EnetOsal_restoreAllIntr (uintptr_t cookie)
| Enet OSAL intr restore function prototype. More...
HwiP_enetOsal * | EnetOsal_registerIntr (EnetOsal_Isr isrFxn, uint32_t coreIntrNum, uint32_t intrPriority, uint32_t intrTrigType, void *arg)
| Register an ISR for an interrupt. More...
void | EnetOsal_unregisterIntr (HwiP_enetOsal *hHwi)
| Unregister an interrupt. More...
void | EnetOsal_enableIntr (uint32_t coreIntrNum)
| Enable interrupt. More...
void | EnetOsal_disableIntr (uint32_t coreIntrNum)
| Disable interrupt. More...
SemaphoreP_enetOsal * | EnetOsal_createMutex (void)
| Create a mutex. More...
void | EnetOsal_deleteMutex (SemaphoreP_enetOsal *hMutex)
| Delete a mutex. More...
void | EnetOsal_lockMutex (SemaphoreP_enetOsal *hMutex)
| Lock a mutex. More...
void | EnetOsal_unlockMutex (SemaphoreP_enetOsal *hMutex)
| Unlock a mutex. More...
void | EnetOsal_cacheInv (void *addr, int32_t size)
| Invalidate cache. More...
void | EnetOsal_cacheWb (void *addr, int32_t size)
| Write-back cache. More...
void | EnetOsal_cacheWbInv (void *addr, int32_t size)
| Write-back and invalidate cache. More...
bool | EnetOsal_isCacheCoherent (void)
uint32_t | EnetOsal_timerGetDiff (uint32_t startTime)
| Get the time difference with respect to timestamp. More...
uint32_t | EnetOsal_timerRead (void)
| Read current timer value. More...

## Typedef Documentation

## ◆ EnetOsal_Isr

typedef void(* EnetOsal_Isr) (uintptr_t arg)

Enet OSAL ISR callback function prototype.

Parameters

  arg | App data

## Enumeration Type Documentation

## ◆ EnetOSAL_armGicTrigType_t

enum EnetOSAL_armGicTrigType_t

Enumerates the types different trigger types. Please refer to Section 4.3.13 Interrupt Configuration Registers, GICD_ICFGRn of ARM Generic Interrupt Controller Architecture version 2.0 Architecture Specification document for details.

Enumerator
ENETOSAL_ARM_GIC_TRIG_TYPE_LEVEL | Corresponding interrupt is level sensitive
ENETOSAL_ARM_GIC_TRIG_TYPE_EDGE | Corresponding interrupt is edge sensitive
ENETOSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL | Coressponding interrupt is high level sensitive
ENETOSAL_ARM_GIC_TRIG_TYPE_LOW_LEVEL | Coressponding interrupt is low level sensitive
ENETOSAL_ARM_GIC_TRIG_TYPE_RISING_EDGE | Coressponding interrupt is rising edge sensitive
ENETOSAL_ARM_GIC_TRIG_TYPE_FALLING_EDGE | Coressponding interrupt is falling edge sensitive

## Function Documentation

## ◆ EnetOsal_disableAllIntr()

uintptr_t EnetOsal_disableAllIntr | ( | void |  | ) |

Enet OSAL intr disable function prototype.

Returns
  Cookie to be passed back to enable interrupt function

## ◆ EnetOsal_restoreAllIntr()

void EnetOsal_restoreAllIntr | ( | uintptr_t | cookie | ) |

Enet OSAL intr restore function prototype.

Parameters

  cookie | This is returned in disable interrupt function

## ◆ EnetOsal_registerIntr()

HwiP_enetOsal* EnetOsal_registerIntr | ( | EnetOsal_Isr | isrFxn,
|  | uint32_t | coreIntrNum,
|  | uint32_t | intrPriority,
|  | uint32_t | intrTrigType,
|  | void * | arg
| ) |  |

Register an ISR for an interrupt.

Parameters

  isrFxn | Interrupt service routine
  coreIntrNum | Interrupt number
  intrPriority | Interrupt priority
  intrTrigType | Interrupt trigger type
  arg | Argument to ISR function

Returns
  Interrupt handle pointer

## ◆ EnetOsal_unregisterIntr()

void EnetOsal_unregisterIntr | ( | HwiP_enetOsal * | hHwi | ) |

Unregister an interrupt.

Parameters

  hHwi | Interrupt handle pointer

## ◆ EnetOsal_enableIntr()

void EnetOsal_enableIntr | ( | uint32_t | coreIntrNum | ) |

Enable interrupt.

Parameters

  coreIntrNum | Interrupt number

## ◆ EnetOsal_disableIntr()

void EnetOsal_disableIntr | ( | uint32_t | coreIntrNum | ) |

Disable interrupt.

Parameters

  coreIntrNum | Interrupt number

## ◆ EnetOsal_createMutex()

SemaphoreP_enetOsal* EnetOsal_createMutex | ( | void |  | ) |

Create a mutex.

Returns
  Mutex handle pointer

## ◆ EnetOsal_deleteMutex()

void EnetOsal_deleteMutex | ( | SemaphoreP_enetOsal * | hMutex | ) |

Delete a mutex.

Parameters

  hMutex | Mutex handle pointer

## ◆ EnetOsal_lockMutex()

void EnetOsal_lockMutex | ( | SemaphoreP_enetOsal * | hMutex | ) |

Lock a mutex.

Parameters

  hMutex | Mutex handle pointer

## ◆ EnetOsal_unlockMutex()

void EnetOsal_unlockMutex | ( | SemaphoreP_enetOsal * | hMutex | ) |

Unlock a mutex.

Parameters

  hMutex | Mutex handle pointer

## ◆ EnetOsal_cacheInv()

void EnetOsal_cacheInv | ( | void * | addr,
|  | int32_t | size
| ) |  |

Invalidate cache.

Invalidates cache in a range of memory.

Parameters

  addr | Start address of the cache line(s)
  size | Size (in bytes) of the memory to invalidate

## ◆ EnetOsal_cacheWb()

void EnetOsal_cacheWb | ( | void * | addr,
|  | int32_t | size
| ) |  |

Write-back cache.

Writes back cache a range of memory from cache.

Parameters

  addr | Start address of the cache line(s)
  size | Size (in bytes) of the memory to be written back

## ◆ EnetOsal_cacheWbInv()

void EnetOsal_cacheWbInv | ( | void * | addr,
|  | int32_t | size
| ) |  |

Write-back and invalidate cache.

Writes back and invalidates a range of memory.

Parameters

  addr | Start address of the cache line/s
  size | Size (in bytes) of the memory to be written back

## ◆ EnetOsal_isCacheCoherent()

bool EnetOsal_isCacheCoherent | ( | void |  | ) |

## ◆ EnetOsal_timerGetDiff()

uint32_t EnetOsal_timerGetDiff | ( | uint32_t | startTime | ) |

Get the time difference with respect to timestamp.

Gets the difference between time value passed to this function and current time from timer.

Returns
  Time difference

## ◆ EnetOsal_timerRead()

uint32_t EnetOsal_timerRead | ( | void |  | ) |

Read current timer value.

Returns
  Timer's read value