AM261x MCU+ SDK: sdlr_esm.h File Reference

| AM261x MCU+ SDK 26.00.00 |

Data Structures | Macros
v0/v0_0/sdlr_esm.h File Reference

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## Data Structures
struct | SDL_esmRegs_ERR_GRP
struct | SDL_esmRegs

## Macros
#define | SDL_ESM_REGS_BASE (0x00000000U)
#define | SDL_ESM_PID (0x00000000U)
#define | SDL_ESM_INFO (0x00000004U)
#define | SDL_ESM_EN (0x00000008U)
#define | SDL_ESM_SFT_RST (0x0000000CU)
#define | SDL_ESM_ERR_RAW (0x00000010U)
#define | SDL_ESM_ERR_STS (0x00000014U)
#define | SDL_ESM_ERR_EN_SET (0x00000018U)
#define | SDL_ESM_ERR_EN_CLR (0x0000001CU)
#define | SDL_ESM_LOW_PRI (0x00000020U)
#define | SDL_ESM_HI_PRI (0x00000024U)
#define | SDL_ESM_LOW (0x00000028U)
#define | SDL_ESM_HI (0x0000002CU)
#define | SDL_ESM_EOI (0x00000030U)
#define | SDL_ESM_PIN_CTRL (0x00000040U)
#define | SDL_ESM_PIN_STS (0x00000044U)
#define | SDL_ESM_PIN_CNTR (0x00000048U)
#define | SDL_ESM_PIN_CNTR_PRE (0x0000004CU)
#define | SDL_ESM_PWMH_PIN_CNTR (0x00000050U)
#define | SDL_ESM_PWMH_PIN_CNTR_PRE (0x00000054U)
#define | SDL_ESM_PWML_PIN_CNTR (0x00000058U)
#define | SDL_ESM_PWML_PIN_CNTR_PRE (0x0000005CU)
#define | SDL_ESM_ERR_GRP_RAW(ERR_GRP) (0x00000400U+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_STS(ERR_GRP) (0x00000404U+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_INTR_EN_SET(ERR_GRP) (0x00000408U+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_INTR_EN_CLR(ERR_GRP) (0x0000040CU+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_INT_PRIO(ERR_GRP) (0x00000410U+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_PIN_EN_SET(ERR_GRP) (0x00000414U+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_PIN_EN_CLR(ERR_GRP) (0x00000418U+((ERR_GRP)*0x20U))
#define | SDL_ESM_ERR_GRP_RAW_STS_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_RAW_STS_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_RAW_STS_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_STS_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_STS_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_STS_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_PID_MINOR_MASK (0x0000003FU)
#define | SDL_ESM_PID_MINOR_SHIFT (0x00000000U)
#define | SDL_ESM_PID_MINOR_MAX (0x0000003FU)
#define | SDL_ESM_PID_CUSTOM_MASK (0x000000C0U)
#define | SDL_ESM_PID_CUSTOM_SHIFT (0x00000006U)
#define | SDL_ESM_PID_CUSTOM_MAX (0x00000003U)
#define | SDL_ESM_PID_MAJOR_MASK (0x00000700U)
#define | SDL_ESM_PID_MAJOR_SHIFT (0x00000008U)
#define | SDL_ESM_PID_MAJOR_MAX (0x00000007U)
#define | SDL_ESM_PID_RTL_MASK (0x0000F800U)
#define | SDL_ESM_PID_RTL_SHIFT (0x0000000BU)
#define | SDL_ESM_PID_RTL_MAX (0x0000001FU)
#define | SDL_ESM_PID_FUNC_MASK (0x0FFF0000U)
#define | SDL_ESM_PID_FUNC_SHIFT (0x00000010U)
#define | SDL_ESM_PID_FUNC_MAX (0x00000FFFU)
#define | SDL_ESM_PID_BU_MASK (0x30000000U)
#define | SDL_ESM_PID_BU_SHIFT (0x0000001CU)
#define | SDL_ESM_PID_BU_MAX (0x00000003U)
#define | SDL_ESM_PID_SCHEME_MASK (0xC0000000U)
#define | SDL_ESM_PID_SCHEME_SHIFT (0x0000001EU)
#define | SDL_ESM_PID_SCHEME_MAX (0x00000003U)
#define | SDL_ESM_INFO_GROUPS_MASK (0x000000FFU)
#define | SDL_ESM_INFO_GROUPS_SHIFT (0x00000000U)
#define | SDL_ESM_INFO_GROUPS_MAX (0x000000FFU)
#define | SDL_ESM_INFO_PULSE_GROUPS_MASK (0x0000FF00U)
#define | SDL_ESM_INFO_PULSE_GROUPS_SHIFT (0x00000008U)
#define | SDL_ESM_INFO_PULSE_GROUPS_MAX (0x000000FFU)
#define | SDL_ESM_INFO_LAST_RESET_MASK (0x80000000U)
#define | SDL_ESM_INFO_LAST_RESET_SHIFT (0x0000001FU)
#define | SDL_ESM_INFO_LAST_RESET_MAX (0x00000001U)
#define | SDL_ESM_EN_KEY_MASK (0x0000000FU)
#define | SDL_ESM_EN_KEY_SHIFT (0x00000000U)
#define | SDL_ESM_EN_KEY_MAX (0x0000000FU)
#define | SDL_ESM_SFT_RST_KEY_MASK (0x0000000FU)
#define | SDL_ESM_SFT_RST_KEY_SHIFT (0x00000000U)
#define | SDL_ESM_SFT_RST_KEY_MAX (0x0000000FU)
#define | SDL_ESM_ERR_RAW_STS_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_RAW_STS_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_RAW_STS_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_STS_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_STS_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_STS_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_EN_SET_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_EN_SET_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_EN_SET_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_ERR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
#define | SDL_ESM_ERR_EN_CLR_MSK_SHIFT (0x00000000U)
#define | SDL_ESM_ERR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
#define | SDL_ESM_LOW_PRI_PLS_MASK (0xFFFF0000U)
#define | SDL_ESM_LOW_PRI_PLS_SHIFT (0x00000010U)
#define | SDL_ESM_LOW_PRI_PLS_MAX (0x0000FFFFU)
#define | SDL_ESM_LOW_PRI_LVL_MASK (0x0000FFFFU)
#define | SDL_ESM_LOW_PRI_LVL_SHIFT (0x00000000U)
#define | SDL_ESM_LOW_PRI_LVL_MAX (0x0000FFFFU)
#define | SDL_ESM_HI_PRI_PLS_MASK (0xFFFF0000U)
#define | SDL_ESM_HI_PRI_PLS_SHIFT (0x00000010U)
#define | SDL_ESM_HI_PRI_PLS_MAX (0x0000FFFFU)
#define | SDL_ESM_HI_PRI_LVL_MASK (0x0000FFFFU)
#define | SDL_ESM_HI_PRI_LVL_SHIFT (0x00000000U)
#define | SDL_ESM_HI_PRI_LVL_MAX (0x0000FFFFU)
#define | SDL_ESM_LOW_STS_MASK (0xFFFFFFFFU)
#define | SDL_ESM_LOW_STS_SHIFT (0x00000000U)
#define | SDL_ESM_LOW_STS_MAX (0xFFFFFFFFU)
#define | SDL_ESM_HI_STS_MASK (0xFFFFFFFFU)
#define | SDL_ESM_HI_STS_SHIFT (0x00000000U)
#define | SDL_ESM_HI_STS_MAX (0xFFFFFFFFU)
#define | SDL_ESM_EOI_KEY_MASK (0x000007FFU)
#define | SDL_ESM_EOI_KEY_SHIFT (0x00000000U)
#define | SDL_ESM_EOI_KEY_MAX (0x000007FFU)
#define | SDL_ESM_PIN_CTRL_KEY_MASK (0x0000000FU)
#define | SDL_ESM_PIN_CTRL_KEY_SHIFT (0x00000000U)
#define | SDL_ESM_PIN_CTRL_KEY_MAX (0x0000000FU)
#define | SDL_ESM_PIN_CTRL_PWM_EN_MASK (0x000000F0U)
#define | SDL_ESM_PIN_CTRL_PWM_EN_SHIFT (0x00000004U)
#define | SDL_ESM_PIN_CTRL_PWM_EN_MAX (0x0000000FU)
#define | SDL_ESM_PIN_STS_VAL_MASK (0x00000001U)
#define | SDL_ESM_PIN_STS_VAL_SHIFT (0x00000000U)
#define | SDL_ESM_PIN_STS_VAL_MAX (0x00000001U)
#define | SDL_ESM_PIN_CNTR_COUNT_MASK (0x00FFFFFFU)
#define | SDL_ESM_PIN_CNTR_COUNT_SHIFT (0x00000000U)
#define | SDL_ESM_PIN_CNTR_COUNT_MAX (0x00FFFFFFU)
#define | SDL_ESM_PIN_CNTR_PRE_COUNT_MASK (0x00FFFFFFU)
#define | SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT (0x00000000U)
#define | SDL_ESM_PIN_CNTR_PRE_COUNT_MAX (0x00FFFFFFU)

## Macro Definition Documentation

## ◆ SDL_ESM_REGS_BASE

#define SDL_ESM_REGS_BASE (0x00000000U)

## ◆ SDL_ESM_PID

#define SDL_ESM_PID (0x00000000U)

## ◆ SDL_ESM_INFO

#define SDL_ESM_INFO (0x00000004U)

## ◆ SDL_ESM_EN

#define SDL_ESM_EN (0x00000008U)

## ◆ SDL_ESM_SFT_RST

#define SDL_ESM_SFT_RST (0x0000000CU)

## ◆ SDL_ESM_ERR_RAW

#define SDL_ESM_ERR_RAW (0x00000010U)

## ◆ SDL_ESM_ERR_STS

#define SDL_ESM_ERR_STS (0x00000014U)

## ◆ SDL_ESM_ERR_EN_SET

#define SDL_ESM_ERR_EN_SET (0x00000018U)

## ◆ SDL_ESM_ERR_EN_CLR

#define SDL_ESM_ERR_EN_CLR (0x0000001CU)

## ◆ SDL_ESM_LOW_PRI

#define SDL_ESM_LOW_PRI (0x00000020U)

## ◆ SDL_ESM_HI_PRI

#define SDL_ESM_HI_PRI (0x00000024U)

## ◆ SDL_ESM_LOW

#define SDL_ESM_LOW (0x00000028U)

## ◆ SDL_ESM_HI

#define SDL_ESM_HI (0x0000002CU)

## ◆ SDL_ESM_EOI

#define SDL_ESM_EOI (0x00000030U)

## ◆ SDL_ESM_PIN_CTRL

#define SDL_ESM_PIN_CTRL (0x00000040U)

## ◆ SDL_ESM_PIN_STS

#define SDL_ESM_PIN_STS (0x00000044U)

## ◆ SDL_ESM_PIN_CNTR

#define SDL_ESM_PIN_CNTR (0x00000048U)

## ◆ SDL_ESM_PIN_CNTR_PRE

#define SDL_ESM_PIN_CNTR_PRE (0x0000004CU)

## ◆ SDL_ESM_PWMH_PIN_CNTR

#define SDL_ESM_PWMH_PIN_CNTR (0x00000050U)

## ◆ SDL_ESM_PWMH_PIN_CNTR_PRE

#define SDL_ESM_PWMH_PIN_CNTR_PRE (0x00000054U)

## ◆ SDL_ESM_PWML_PIN_CNTR

#define SDL_ESM_PWML_PIN_CNTR (0x00000058U)

## ◆ SDL_ESM_PWML_PIN_CNTR_PRE

#define SDL_ESM_PWML_PIN_CNTR_PRE (0x0000005CU)

## ◆ SDL_ESM_ERR_GRP_RAW

#define SDL_ESM_ERR_GRP_RAW | ( |  | ERR_GRP | ) | (0x00000400U+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_STS

#define SDL_ESM_ERR_GRP_STS | ( |  | ERR_GRP | ) | (0x00000404U+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_INTR_EN_SET

#define SDL_ESM_ERR_GRP_INTR_EN_SET | ( |  | ERR_GRP | ) | (0x00000408U+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_INTR_EN_CLR

#define SDL_ESM_ERR_GRP_INTR_EN_CLR | ( |  | ERR_GRP | ) | (0x0000040CU+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_INT_PRIO

#define SDL_ESM_ERR_GRP_INT_PRIO | ( |  | ERR_GRP | ) | (0x00000410U+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_PIN_EN_SET

#define SDL_ESM_ERR_GRP_PIN_EN_SET | ( |  | ERR_GRP | ) | (0x00000414U+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_PIN_EN_CLR

#define SDL_ESM_ERR_GRP_PIN_EN_CLR | ( |  | ERR_GRP | ) | (0x00000418U+((ERR_GRP)*0x20U))

## ◆ SDL_ESM_ERR_GRP_RAW_STS_MASK

#define SDL_ESM_ERR_GRP_RAW_STS_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_RAW_STS_SHIFT

#define SDL_ESM_ERR_GRP_RAW_STS_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_RAW_STS_MAX

#define SDL_ESM_ERR_GRP_RAW_STS_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_STS_MSK_MASK

#define SDL_ESM_ERR_GRP_STS_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_STS_MSK_SHIFT

#define SDL_ESM_ERR_GRP_STS_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_STS_MSK_MAX

#define SDL_ESM_ERR_GRP_STS_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK

#define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT

#define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX

#define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK

#define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT

#define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX

#define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK

#define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT

#define SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX

#define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK

#define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT

#define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX

#define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK

#define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT

#define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX

#define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_PID_MINOR_MASK

#define SDL_ESM_PID_MINOR_MASK (0x0000003FU)

## ◆ SDL_ESM_PID_MINOR_SHIFT

#define SDL_ESM_PID_MINOR_SHIFT (0x00000000U)

## ◆ SDL_ESM_PID_MINOR_MAX

#define SDL_ESM_PID_MINOR_MAX (0x0000003FU)

## ◆ SDL_ESM_PID_CUSTOM_MASK

#define SDL_ESM_PID_CUSTOM_MASK (0x000000C0U)

## ◆ SDL_ESM_PID_CUSTOM_SHIFT

#define SDL_ESM_PID_CUSTOM_SHIFT (0x00000006U)

## ◆ SDL_ESM_PID_CUSTOM_MAX

#define SDL_ESM_PID_CUSTOM_MAX (0x00000003U)

## ◆ SDL_ESM_PID_MAJOR_MASK

#define SDL_ESM_PID_MAJOR_MASK (0x00000700U)

## ◆ SDL_ESM_PID_MAJOR_SHIFT

#define SDL_ESM_PID_MAJOR_SHIFT (0x00000008U)

## ◆ SDL_ESM_PID_MAJOR_MAX

#define SDL_ESM_PID_MAJOR_MAX (0x00000007U)

## ◆ SDL_ESM_PID_RTL_MASK

#define SDL_ESM_PID_RTL_MASK (0x0000F800U)

## ◆ SDL_ESM_PID_RTL_SHIFT

#define SDL_ESM_PID_RTL_SHIFT (0x0000000BU)

## ◆ SDL_ESM_PID_RTL_MAX

#define SDL_ESM_PID_RTL_MAX (0x0000001FU)

## ◆ SDL_ESM_PID_FUNC_MASK

#define SDL_ESM_PID_FUNC_MASK (0x0FFF0000U)

## ◆ SDL_ESM_PID_FUNC_SHIFT

#define SDL_ESM_PID_FUNC_SHIFT (0x00000010U)

## ◆ SDL_ESM_PID_FUNC_MAX

#define SDL_ESM_PID_FUNC_MAX (0x00000FFFU)

## ◆ SDL_ESM_PID_BU_MASK

#define SDL_ESM_PID_BU_MASK (0x30000000U)

## ◆ SDL_ESM_PID_BU_SHIFT

#define SDL_ESM_PID_BU_SHIFT (0x0000001CU)

## ◆ SDL_ESM_PID_BU_MAX

#define SDL_ESM_PID_BU_MAX (0x00000003U)

## ◆ SDL_ESM_PID_SCHEME_MASK

#define SDL_ESM_PID_SCHEME_MASK (0xC0000000U)

## ◆ SDL_ESM_PID_SCHEME_SHIFT

#define SDL_ESM_PID_SCHEME_SHIFT (0x0000001EU)

## ◆ SDL_ESM_PID_SCHEME_MAX

#define SDL_ESM_PID_SCHEME_MAX (0x00000003U)

## ◆ SDL_ESM_INFO_GROUPS_MASK

#define SDL_ESM_INFO_GROUPS_MASK (0x000000FFU)

## ◆ SDL_ESM_INFO_GROUPS_SHIFT

#define SDL_ESM_INFO_GROUPS_SHIFT (0x00000000U)

## ◆ SDL_ESM_INFO_GROUPS_MAX

#define SDL_ESM_INFO_GROUPS_MAX (0x000000FFU)

## ◆ SDL_ESM_INFO_PULSE_GROUPS_MASK

#define SDL_ESM_INFO_PULSE_GROUPS_MASK (0x0000FF00U)

## ◆ SDL_ESM_INFO_PULSE_GROUPS_SHIFT

#define SDL_ESM_INFO_PULSE_GROUPS_SHIFT (0x00000008U)

## ◆ SDL_ESM_INFO_PULSE_GROUPS_MAX

#define SDL_ESM_INFO_PULSE_GROUPS_MAX (0x000000FFU)

## ◆ SDL_ESM_INFO_LAST_RESET_MASK

#define SDL_ESM_INFO_LAST_RESET_MASK (0x80000000U)

## ◆ SDL_ESM_INFO_LAST_RESET_SHIFT

#define SDL_ESM_INFO_LAST_RESET_SHIFT (0x0000001FU)

## ◆ SDL_ESM_INFO_LAST_RESET_MAX

#define SDL_ESM_INFO_LAST_RESET_MAX (0x00000001U)

## ◆ SDL_ESM_EN_KEY_MASK

#define SDL_ESM_EN_KEY_MASK (0x0000000FU)

## ◆ SDL_ESM_EN_KEY_SHIFT

#define SDL_ESM_EN_KEY_SHIFT (0x00000000U)

## ◆ SDL_ESM_EN_KEY_MAX

#define SDL_ESM_EN_KEY_MAX (0x0000000FU)

## ◆ SDL_ESM_SFT_RST_KEY_MASK

#define SDL_ESM_SFT_RST_KEY_MASK (0x0000000FU)

## ◆ SDL_ESM_SFT_RST_KEY_SHIFT

#define SDL_ESM_SFT_RST_KEY_SHIFT (0x00000000U)

## ◆ SDL_ESM_SFT_RST_KEY_MAX

#define SDL_ESM_SFT_RST_KEY_MAX (0x0000000FU)

## ◆ SDL_ESM_ERR_RAW_STS_MASK

#define SDL_ESM_ERR_RAW_STS_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_RAW_STS_SHIFT

#define SDL_ESM_ERR_RAW_STS_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_RAW_STS_MAX

#define SDL_ESM_ERR_RAW_STS_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_STS_MSK_MASK

#define SDL_ESM_ERR_STS_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_STS_MSK_SHIFT

#define SDL_ESM_ERR_STS_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_STS_MSK_MAX

#define SDL_ESM_ERR_STS_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_EN_SET_MSK_MASK

#define SDL_ESM_ERR_EN_SET_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_EN_SET_MSK_SHIFT

#define SDL_ESM_ERR_EN_SET_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_EN_SET_MSK_MAX

#define SDL_ESM_ERR_EN_SET_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_EN_CLR_MSK_MASK

#define SDL_ESM_ERR_EN_CLR_MSK_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_ERR_EN_CLR_MSK_SHIFT

#define SDL_ESM_ERR_EN_CLR_MSK_SHIFT (0x00000000U)

## ◆ SDL_ESM_ERR_EN_CLR_MSK_MAX

#define SDL_ESM_ERR_EN_CLR_MSK_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_LOW_PRI_PLS_MASK

#define SDL_ESM_LOW_PRI_PLS_MASK (0xFFFF0000U)

## ◆ SDL_ESM_LOW_PRI_PLS_SHIFT

#define SDL_ESM_LOW_PRI_PLS_SHIFT (0x00000010U)

## ◆ SDL_ESM_LOW_PRI_PLS_MAX

#define SDL_ESM_LOW_PRI_PLS_MAX (0x0000FFFFU)

## ◆ SDL_ESM_LOW_PRI_LVL_MASK

#define SDL_ESM_LOW_PRI_LVL_MASK (0x0000FFFFU)

## ◆ SDL_ESM_LOW_PRI_LVL_SHIFT

#define SDL_ESM_LOW_PRI_LVL_SHIFT (0x00000000U)

## ◆ SDL_ESM_LOW_PRI_LVL_MAX

#define SDL_ESM_LOW_PRI_LVL_MAX (0x0000FFFFU)

## ◆ SDL_ESM_HI_PRI_PLS_MASK

#define SDL_ESM_HI_PRI_PLS_MASK (0xFFFF0000U)

## ◆ SDL_ESM_HI_PRI_PLS_SHIFT

#define SDL_ESM_HI_PRI_PLS_SHIFT (0x00000010U)

## ◆ SDL_ESM_HI_PRI_PLS_MAX

#define SDL_ESM_HI_PRI_PLS_MAX (0x0000FFFFU)

## ◆ SDL_ESM_HI_PRI_LVL_MASK

#define SDL_ESM_HI_PRI_LVL_MASK (0x0000FFFFU)

## ◆ SDL_ESM_HI_PRI_LVL_SHIFT

#define SDL_ESM_HI_PRI_LVL_SHIFT (0x00000000U)

## ◆ SDL_ESM_HI_PRI_LVL_MAX

#define SDL_ESM_HI_PRI_LVL_MAX (0x0000FFFFU)

## ◆ SDL_ESM_LOW_STS_MASK

#define SDL_ESM_LOW_STS_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_LOW_STS_SHIFT

#define SDL_ESM_LOW_STS_SHIFT (0x00000000U)

## ◆ SDL_ESM_LOW_STS_MAX

#define SDL_ESM_LOW_STS_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_HI_STS_MASK

#define SDL_ESM_HI_STS_MASK (0xFFFFFFFFU)

## ◆ SDL_ESM_HI_STS_SHIFT

#define SDL_ESM_HI_STS_SHIFT (0x00000000U)

## ◆ SDL_ESM_HI_STS_MAX

#define SDL_ESM_HI_STS_MAX (0xFFFFFFFFU)

## ◆ SDL_ESM_EOI_KEY_MASK

#define SDL_ESM_EOI_KEY_MASK (0x000007FFU)

## ◆ SDL_ESM_EOI_KEY_SHIFT

#define SDL_ESM_EOI_KEY_SHIFT (0x00000000U)

## ◆ SDL_ESM_EOI_KEY_MAX

#define SDL_ESM_EOI_KEY_MAX (0x000007FFU)

## ◆ SDL_ESM_PIN_CTRL_KEY_MASK

#define SDL_ESM_PIN_CTRL_KEY_MASK (0x0000000FU)

## ◆ SDL_ESM_PIN_CTRL_KEY_SHIFT

#define SDL_ESM_PIN_CTRL_KEY_SHIFT (0x00000000U)

## ◆ SDL_ESM_PIN_CTRL_KEY_MAX

#define SDL_ESM_PIN_CTRL_KEY_MAX (0x0000000FU)

## ◆ SDL_ESM_PIN_CTRL_PWM_EN_MASK

#define SDL_ESM_PIN_CTRL_PWM_EN_MASK (0x000000F0U)

## ◆ SDL_ESM_PIN_CTRL_PWM_EN_SHIFT

#define SDL_ESM_PIN_CTRL_PWM_EN_SHIFT (0x00000004U)

## ◆ SDL_ESM_PIN_CTRL_PWM_EN_MAX

#define SDL_ESM_PIN_CTRL_PWM_EN_MAX (0x0000000FU)

## ◆ SDL_ESM_PIN_STS_VAL_MASK

#define SDL_ESM_PIN_STS_VAL_MASK (0x00000001U)

## ◆ SDL_ESM_PIN_STS_VAL_SHIFT

#define SDL_ESM_PIN_STS_VAL_SHIFT (0x00000000U)

## ◆ SDL_ESM_PIN_STS_VAL_MAX

#define SDL_ESM_PIN_STS_VAL_MAX (0x00000001U)

## ◆ SDL_ESM_PIN_CNTR_COUNT_MASK

#define SDL_ESM_PIN_CNTR_COUNT_MASK (0x00FFFFFFU)

## ◆ SDL_ESM_PIN_CNTR_COUNT_SHIFT

#define SDL_ESM_PIN_CNTR_COUNT_SHIFT (0x00000000U)

## ◆ SDL_ESM_PIN_CNTR_COUNT_MAX

#define SDL_ESM_PIN_CNTR_COUNT_MAX (0x00FFFFFFU)

## ◆ SDL_ESM_PIN_CNTR_PRE_COUNT_MASK

#define SDL_ESM_PIN_CNTR_PRE_COUNT_MASK (0x00FFFFFFU)

## ◆ SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT

#define SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT (0x00000000U)

## ◆ SDL_ESM_PIN_CNTR_PRE_COUNT_MAX

#define SDL_ESM_PIN_CNTR_PRE_COUNT_MAX (0x00FFFFFFU)