AM261x MCU+ SDK: sdl_ip_ecc.h Source File

| AM261x MCU+ SDK 26.00.00 |

V1/sdl_ip_ecc.h
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1
40 #ifndef SDL_ECC_AGGR_H
41 #define SDL_ECC_AGGR_H
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #include <stdint.h>
48 #include <stdbool.h>
49 #include <sdl/ecc/sdlr_ecc.h>
50
100 #define SDL_ECC_AGGR_INTR_SRC_NONE ((uint32_t) 0U)
101
102 #define SDL_ECC_AGGR_INTR_SRC_SINGLE_BIT ((uint32_t) 1U)
103
104 #define SDL_ECC_AGGR_INTR_SRC_DOUBLE_BIT ((uint32_t) 2U)
105
106 #define SDL_ECC_ADDR_ERROR_TYPE_SUCCESSIVE_SINGLE_BITS ((uint32_t) 3U)
107
108 #define SDL_ECC_AGGR_INTR_SRC_INVALID ((uint32_t) 4U)
109
116 #define SDL_ECC_AGGR_SELECT_ERR_CTRL1 (0U)
117
118 #define SDL_ECC_AGGR_SELECT_ERR_CTRL2 (1U)
119
120 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_CTRL (2U)
121
128 #define SDL_ECC_AGGR_SELECT_ERR_STAT1 (0U)
129
130 #define SDL_ECC_AGGR_SELECT_ERR_STAT2 (1U)
131
132 #define SDL_ECC_AGGR_SELECT_ERR_STAT3 (2U)
133
134 #define SDL_ECC_AGGR_MAX_NUM_RAM_ERR_STAT (3U)
135
136
142 #define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS (8U)
143
144 #define SDL_ECC_AGGR_VALID_TIMEOUT_ERR (1U)
145
146 #define SDL_ECC_AGGR_VALID_PARITY_ERR (2U)
147
149 #define SDL_ECC_AGGR_INJECT_PATTERN_ZERO ((uint32_t) 0U)
150
151 #define SDL_ECC_AGGR_INJECT_PATTERN_F ((uint32_t) 1U)
152
153 #define SDL_ECC_AGGR_INJECT_PATTERN_A ((uint32_t) 2U)
154
155 #define SDL_ECC_AGGR_INJECT_PATTERN_5 ((uint32_t) 3U)
156 /* Max Inject pattern */
157 #define SDL_ECC_EGGR_INJECT_PATTERN_MAX (SDL_ECC_AGGR_INJECT_PATTERN_A)
158
160 #define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL ((uint32_t) 0U)
161
162 #define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT ((uint32_t) 1U)
163
181 typedef uint32_t SDL_Ecc_AggrIntrSrc;
182
183
190 typedef uint32_t SDL_Ecc_AggrEDCErrorSubType;
191
192
198 typedef uint8_t SDL_ecc_aggrValid;
199
206 typedef uint32_t SDL_Ecc_injectPattern;
222 typedef struct
223 {
225 SDL_Ecc_AggrIntrSrc intrSrc;
227 uint32_t eccRow;
229 uint32_t eccBit1;
231 uint32_t eccBit2;
233 bool bOneShotMode;
235 bool bNextRow;
236 } SDL_Ecc_AggrErrorInfo;
237
245 typedef struct
246 {
248 bool controlRegErr;
250 bool successiveSingleBitErr;
252 bool sVBUSTimeoutErr;
254 bool writebackPend;
256 uint32_t parityErrorCount;
258 uint32_t eccRow;
260 uint32_t eccBit1;
262 uint32_t singleBitErrorCount;
264 uint32_t doubleBitErrorCount;
265 } SDL_Ecc_AggrEccRamErrorStatusInfo;
266
273 typedef struct {
275 bool intrEnableTimeoutErr;
277 bool intrEnableParityErr;
279 SDL_ecc_aggrValid validCfg;
280 } SDL_ecc_aggrEnableCtrl;
281
288 typedef struct {
290 bool intrStatusSetTimeoutErr;
292 bool intrStatusSetParityErr;
294 uint32_t timeOutCnt;
296 uint32_t parityCnt;
298 SDL_ecc_aggrValid validCfg;
299 } SDL_ecc_aggrStatusCtrl;
300
301
302
310 typedef struct {
312 uint32_t REV;
314 uint32_t ECC_CTRL;
316 uint32_t ECC_ERR_CTRL1;
318 uint32_t ECC_ERR_CTRL2;
320 uint32_t ECC_SEC_ENABLE_SET_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
322 uint32_t ECC_SEC_ENABLE_CLR_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
324 uint32_t ECC_DED_ENABLE_SET_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
326 uint32_t ECC_DED_ENABLE_CLR_REG[SDL_ECC_AGGR_NUM_ENABLE_REGISTERS];
327 } SDL_ECC_staticRegs;
328
363 int32_t SDL_ecc_aggrGetRevision(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pRev);
364
388 int32_t SDL_ecc_aggrGetNumRams(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pNumRams);
389
417 int32_t SDL_ecc_aggrReadEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t *pRegVal);
418
444 int32_t SDL_ecc_aggrReadEccRamWrapRevReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal);
445
472 int32_t SDL_ecc_aggrReadEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal);
473
494 int32_t SDL_ecc_aggrReadEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal);
495
516 int32_t SDL_ecc_aggrReadEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal);
517
543 int32_t SDL_ecc_aggrWriteEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t val);
544
568 int32_t SDL_ecc_aggrWriteEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t val);
569
595 int32_t SDL_ecc_aggrWriteEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val);
596
621 int32_t SDL_ecc_aggrWriteEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val);
622
648 int32_t SDL_ecc_aggrConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW);
649
676 int32_t SDL_ecc_aggrVerifyConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW);
677
702 int32_t SDL_ecc_aggrGetEccRamErrorStatus(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrEccRamErrorStatusInfo *pEccErrorStatus);
703
728 int32_t SDL_ecc_aggrForceEccRamError(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, const SDL_Ecc_AggrErrorInfo *pEccForceError);
729
754 int32_t SDL_ecc_aggrAckIntr(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc);
755
786 int32_t SDL_ecc_aggrIsEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend);
787
813 int32_t SDL_ecc_aggrSetEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);
814
842 int32_t SDL_ecc_aggrSetEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents);
843
869 int32_t SDL_ecc_aggrClrEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);
870
897 int32_t SDL_ecc_aggrClrEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents);
898
930 int32_t SDL_ecc_aggrIsIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend);
931
955 int32_t SDL_ecc_aggrIsAnyIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool *pIsPend);
956
982 int32_t SDL_ecc_aggrEnableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);
983
1009 int32_t SDL_ecc_aggrDisableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc);
1010
1034 int32_t SDL_ecc_aggrEnableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId);
1035
1059 int32_t SDL_ecc_aggrDisableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId);
1060
1085 int32_t SDL_ecc_aggrEnableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc);
1086
1111 int32_t SDL_ecc_aggrDisableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc);
1112
1135 int32_t SDL_ecc_aggrEnableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs);
1136
1159 int32_t SDL_ecc_aggrDisableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs);
1160
1184 int32_t SDL_ecc_aggrReadStaticRegs(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ECC_staticRegs *pEccAggrStaticRegs);
1185
1209 int32_t SDL_ecc_aggrIntrEnableCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrEnableCtrl *pEnableCtrl);
1210
1211
1236 int32_t SDL_ecc_aggrIntrStatusCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrStatusCtrl *pStatusCtrl);
1237
1263 int32_t SDL_ecc_aggrIntrGetStatus(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ecc_aggrStatusCtrl *pStatusCtrl);
1264
1265
1268 #ifdef __cplusplus
1269 }
1270 #endif
1271
1272 #endif
SDL_ecc_aggrWriteEccRamErrStatReg
int32_t SDL_ecc_aggrWriteEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val)
SDL_ecc_aggrAckIntr
int32_t SDL_ecc_aggrAckIntr(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrDisableIntr
int32_t SDL_ecc_aggrDisableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrWriteEccRamReg
int32_t SDL_ecc_aggrWriteEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t val)
SDL_ecc_aggrStatusCtrl::timeOutCnt
uint32_t timeOutCnt
Definition: V1/sdl_ip_ecc.h:294
SDL_ecc_aggrSetEccRamNIntrPending
int32_t SDL_ecc_aggrSetEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents)
SDL_Ecc_AggrEccRamErrorStatusInfo::singleBitErrorCount
uint32_t singleBitErrorCount
Definition: V1/sdl_ip_ecc.h:262
SDL_ECC_staticRegs::REV
uint32_t REV
Definition: V1/sdl_ip_ecc.h:312
SDL_Ecc_AggrEccRamErrorStatusInfo
This structure contains error status information returned by the SDL_ecc_aggrGetEccRamGetErrorStatus ...
Definition: V1/sdl_ip_ecc.h:246
SDL_Ecc_AggrEDCErrorSubType
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: V1/sdl_ip_ecc.h:190
SDL_ecc_aggrIsIntrPending
int32_t SDL_ecc_aggrIsIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend)
SDL_ECC_staticRegs::ECC_CTRL
uint32_t ECC_CTRL
Definition: V1/sdl_ip_ecc.h:314
SDL_ecc_aggrClrEccRamNIntrPending
int32_t SDL_ecc_aggrClrEccRamNIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, uint32_t numEvents)
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_Ecc_AggrErrorInfo::intrSrc
SDL_Ecc_AggrIntrSrc intrSrc
Definition: V1/sdl_ip_ecc.h:225
SDL_Ecc_AggrErrorInfo::bNextRow
bool bNextRow
Definition: V1/sdl_ip_ecc.h:235
SDL_ecc_aggrEnableCtrl::intrEnableTimeoutErr
bool intrEnableTimeoutErr
Definition: V1/sdl_ip_ecc.h:275
sdlr_ecc.h
SDL_ecc_aggrDisableIntrs
int32_t SDL_ecc_aggrDisableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrForceEccRamError
int32_t SDL_ecc_aggrForceEccRamError(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, const SDL_Ecc_AggrErrorInfo *pEccForceError)
SDL_ecc_aggrReadStaticRegs
int32_t SDL_ecc_aggrReadStaticRegs(SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ECC_staticRegs *pEccAggrStaticRegs)
SDL_ecc_aggrClrEccRamIntrPending
int32_t SDL_ecc_aggrClrEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_Ecc_AggrErrorInfo::eccBit1
uint32_t eccBit1
Definition: V1/sdl_ip_ecc.h:229
SDL_ecc_aggrIntrEnableCtrl
int32_t SDL_ecc_aggrIntrEnableCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrEnableCtrl *pEnableCtrl)
SDL_ecc_aggrStatusCtrl::intrStatusSetTimeoutErr
bool intrStatusSetTimeoutErr
Definition: V1/sdl_ip_ecc.h:290
SDL_ecc_aggrReadEccRamErrStatReg
int32_t SDL_ecc_aggrReadEccRamErrStatReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal)
SDL_ecc_aggrEnableAllIntrs
int32_t SDL_ecc_aggrEnableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs)
SDL_Ecc_AggrErrorInfo
This structure contains error forcing information used by the SDL_ecc_aggrForceEccRamError function.
Definition: V1/sdl_ip_ecc.h:223
SDL_ecc_aggrWriteEccRamErrCtrlReg
int32_t SDL_ecc_aggrWriteEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t val)
SDL_ecc_aggrStatusCtrl::parityCnt
uint32_t parityCnt
Definition: V1/sdl_ip_ecc.h:296
SDL_ECC_staticRegs::ECC_ERR_CTRL1
uint32_t ECC_ERR_CTRL1
Definition: V1/sdl_ip_ecc.h:316
SDL_ECC_staticRegs::ECC_ERR_CTRL2
uint32_t ECC_ERR_CTRL2
Definition: V1/sdl_ip_ecc.h:318
SDL_ecc_aggrValid
uint8_t SDL_ecc_aggrValid
This defines the valid ecc aggr error configuration.
Definition: V1/sdl_ip_ecc.h:198
SDL_ecc_aggrReadEccRamErrCtrlReg
int32_t SDL_ecc_aggrReadEccRamErrCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t instSelect, uint32_t *pRegVal)
SDL_Ecc_AggrEccRamErrorStatusInfo::controlRegErr
bool controlRegErr
Definition: V1/sdl_ip_ecc.h:248
SDL_ecc_aggrStatusCtrl::intrStatusSetParityErr
bool intrStatusSetParityErr
Definition: V1/sdl_ip_ecc.h:292
SDL_ECC_staticRegs
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: V1/sdl_ip_ecc.h:310
SDL_ecc_aggrReadEccRamCtrlReg
int32_t SDL_ecc_aggrReadEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal)
SDL_ecc_aggrIntrStatusCtrl
int32_t SDL_ecc_aggrIntrStatusCtrl(SDL_ecc_aggrRegs *pEccAggrRegs, const SDL_ecc_aggrStatusCtrl *pStatusCtrl)
SDL_ECC_AGGR_NUM_ENABLE_REGISTERS
#define SDL_ECC_AGGR_NUM_ENABLE_REGISTERS
This defines the number of enable registers.
Definition: V1/sdl_ip_ecc.h:142
SDL_Ecc_AggrEccRamErrorStatusInfo::eccBit1
uint32_t eccBit1
Definition: V1/sdl_ip_ecc.h:260
SDL_ecc_aggrReadEccRamReg
int32_t SDL_ecc_aggrReadEccRamReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t regOffset, uint32_t *pRegVal)
SDL_Ecc_AggrErrorInfo::eccBit2
uint32_t eccBit2
Definition: V1/sdl_ip_ecc.h:231
SDL_ecc_aggrEnableCtrl::intrEnableParityErr
bool intrEnableParityErr
Definition: V1/sdl_ip_ecc.h:277
SDL_Ecc_AggrEccRamErrorStatusInfo::eccRow
uint32_t eccRow
Definition: V1/sdl_ip_ecc.h:258
SDL_ecc_aggrEnableIntrs
int32_t SDL_ecc_aggrEnableIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_Ecc_AggrErrorInfo::bOneShotMode
bool bOneShotMode
Definition: V1/sdl_ip_ecc.h:233
SDL_Ecc_AggrEccRamErrorStatusInfo::parityErrorCount
uint32_t parityErrorCount
Definition: V1/sdl_ip_ecc.h:256
SDL_Ecc_AggrEccRamErrorStatusInfo::writebackPend
bool writebackPend
Definition: V1/sdl_ip_ecc.h:254
SDL_ecc_aggrDisableAllIntrs
int32_t SDL_ecc_aggrDisableAllIntrs(const SDL_ecc_aggrRegs *pEccAggrRegs)
SDL_ecc_aggrEnableCtrl::validCfg
SDL_ecc_aggrValid validCfg
Definition: V1/sdl_ip_ecc.h:279
SDL_Ecc_AggrIntrSrc
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:181
SDL_Ecc_injectPattern
uint32_t SDL_Ecc_injectPattern
This enumerator defines the types of ECC patterns.
Definition: V1/sdl_ip_ecc.h:206
SDL_Ecc_AggrEccRamErrorStatusInfo::sVBUSTimeoutErr
bool sVBUSTimeoutErr
Definition: V1/sdl_ip_ecc.h:252
SDL_ecc_aggrVerifyConfigEccRam
int32_t SDL_ecc_aggrVerifyConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW)
SDL_ecc_aggrGetNumRams
int32_t SDL_ecc_aggrGetNumRams(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pNumRams)
SDL_ecc_aggrWriteEccRamCtrlReg
int32_t SDL_ecc_aggrWriteEccRamCtrlReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t val)
SDL_Ecc_AggrEccRamErrorStatusInfo::doubleBitErrorCount
uint32_t doubleBitErrorCount
Definition: V1/sdl_ip_ecc.h:264
SDL_ecc_aggrStatusCtrl
This structure contains the ECC aggr status config.
Definition: V1/sdl_ip_ecc.h:288
SDL_Ecc_AggrEccRamErrorStatusInfo::successiveSingleBitErr
bool successiveSingleBitErr
Definition: V1/sdl_ip_ecc.h:250
SDL_ecc_aggrEnableCtrl
This structure contains the ECC aggr enable error config.
Definition: V1/sdl_ip_ecc.h:273
SDL_ecc_aggrEnableAllIntr
int32_t SDL_ecc_aggrEnableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId)
SDL_ecc_aggrGetEccRamErrorStatus
int32_t SDL_ecc_aggrGetEccRamErrorStatus(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrEccRamErrorStatusInfo *pEccErrorStatus)
SDL_ecc_aggrIsAnyIntrPending
int32_t SDL_ecc_aggrIsAnyIntrPending(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool *pIsPend)
SDL_ecc_aggrEnableIntr
int32_t SDL_ecc_aggrEnableIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrIntrGetStatus
int32_t SDL_ecc_aggrIntrGetStatus(const SDL_ecc_aggrRegs *pEccAggrRegs, SDL_ecc_aggrStatusCtrl *pStatusCtrl)
SDL_ecc_aggrGetRevision
int32_t SDL_ecc_aggrGetRevision(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t *pRev)
SDL_ecc_aggrDisableAllIntr
int32_t SDL_ecc_aggrDisableAllIntr(const SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId)
SDL_ecc_aggrIsEccRamIntrPending
int32_t SDL_ecc_aggrIsEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc, bool *pIsPend)
SDL_ecc_aggrSetEccRamIntrPending
int32_t SDL_ecc_aggrSetEccRamIntrPending(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, SDL_Ecc_AggrIntrSrc intrSrc)
SDL_ecc_aggrStatusCtrl::validCfg
SDL_ecc_aggrValid validCfg
Definition: V1/sdl_ip_ecc.h:298
SDL_Ecc_AggrErrorInfo::eccRow
uint32_t eccRow
Definition: V1/sdl_ip_ecc.h:227
SDL_ecc_aggrConfigEccRam
int32_t SDL_ecc_aggrConfigEccRam(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, bool bEnable, bool bEccCheck, bool bEnableRMW)
SDL_ecc_aggrReadEccRamWrapRevReg
int32_t SDL_ecc_aggrReadEccRamWrapRevReg(SDL_ecc_aggrRegs *pEccAggrRegs, uint32_t ramId, uint32_t *pRegVal)