AM261x MCU+ SDK: GPMC

| AM261x MCU+ SDK 26.00.00 |

GPMC

The General-Purpose Memory Controller (GPMC) is an unified memory controller dedicated to interfacing external memory devices like

- Asynchronous SRAM like memories and application specific integrated circuit devices
- Asynchronous, synchronous, and page mode burst NOR flash devices
- NAND flash
- Pseudo-SRAM devices

# Features Supported

- Supports up to 4 chip select regions of programmable size and programmable base addresses in a total address space of 1GB
- Fully pipelined operation for optimal memory bandwidth usage
- The clock to the external memory is provided from GPMC_FCLK divided by 1, 2, 3, or 4
- Supports programmable autoclock gating when no access is detected
- Independent and programmable control signal timing parameters for setup and hold time on a per-chip basis. Parameters are set according to the memory device timing parameters with a timing granularity of one GPMC_FCLK clock cycle.
- Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin monitoring
- Support bus keeping
- Support bus turnaround
- 32-bit interconnect target interface which supports non-wrapping and wrapping burst of up to 16x32 bits

# SysConfig Features

Note
  It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

- Set input clock frequency and clock divider
- Set interrupt trigger type
- Configuring pinmux based on selected pin

# Features NOT Supported

# GPMC Overview

The GPMC basic programming model offers maximum flexibility to support various access protocols for each of the four configurable chip-selects. Use optimal chip-select settings, based on the characteristics of the external device:

- Different protocols can be selected to support generic asynchronous or synchronous random-access devices (NOR flash, SRAM) or to support specific NAND devices.
- The address and data bus can be multiplexed on the same external bus.
- Read and write access can be independently defined as asynchronous or synchronous.
- System requests (byte, 16-bit word, burst) are performed through single or multiple accesses. External access profiles (single, multiple with optimized burst length, native- or emulated-wrap) are based on external device characteristics (supported protocol, bus width, data buffer size, native-wrap support).
- System burst read or write requests are synchronous-burst (multiple-read or multiple-write). When neither burst nor page mode is supported by external memory or ASIC devices, system burst read or write requests are translated to successive single synchronous or asynchronous accesses (single reads or single writes). 8-bit wide devices are supported only in single synchronous or single asynchronous read or write mode.
- To simulate a programmable internal-wait-state, an external WAIT pin can be monitored to dynamically control external access at the beginning (initial access time) of and during a burst access. Each control signal is controlled independently for each chip-select. The internal functional clock of the GPMC (GPMC_FCLK) is used as a time reference to specify the following:
  1. Read- and write-access duration
  2. Most GPMC external interface control-signal assertion and deassertion times
  3. Data-capture time during read access
  4. External wait-pin monitoring time
  5. Duration of idle time between accesses, when required

Below figure shows the GPMC functional block diagram. The GPMC consists of six blocks:

- Interconnect port interface
- Address decoder, GPMC configuration, and chip-select configuration register file
- Access engine
- Prefetch and write-posting engine
- Error correction code engine (ECC)
- External device/memory port interface
  GPMC FUNCTIONAL BLOCK DIAGRAM

The GPMC can access various external devices. The flexible programming model allows a wide range of attached device types and access schemes. Based on the programmed configuration bit fields stored in the GPMC registers, the GPMC can generate the timing of all control signals depending on the attached device and access type. Given the chip-select decoding and its associated configuration registers, the GPMC selects the appropriate control signal timing for the device type

# Example Usage

Include the below file to access the APIs

#include <stdio.h>
#include <drivers/gpmc.h>

GPMC Instance Open

GPMC_Params gpmcParams;
GPMC_Params_init(&gpmcParams);
gGpmcHandle = GPMC_open(0, &gpmcParams);
DebugP_assert(gGpmcHandle != NULL);

GPMC Instance Close

GPMC_close(gGpmcHandle);

# API

APIs for GPMC

GPMC_Params_init
static void GPMC_Params_init(GPMC_Params *params)
Function to initialize the GPMC_Params struct to its defaults.
Definition: gpmc.h:1199
GPMC_close
void GPMC_close(GPMC_Handle handle)
Function to close a GPMC peripheral specified by the GPMC handle.
GPMC_open
GPMC_Handle GPMC_open(uint32_t index, const GPMC_Params *prms)
This function opens a given GPMC peripheral.
GPMC_Params
GPMC driver instance parameters.
Definition: gpmc.h:615
DebugP_assert
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:187