AM261x MCU+ SDK: etpwm.h Source File

| AM261x MCU+ SDK 26.00.00 |

etpwm.h
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1 /*
2 * Copyright (C) 2021-2023 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
42 #ifndef EPWM_V1_H_
43 #define EPWM_V1_H_
44
45 //*****************************************************************************
46 //
47 // If building with a C++ compiler, make all of the definitions in this header
48 // have a C binding.
49 //
50 //*****************************************************************************
51 #ifdef __cplusplus
52 extern "C"
53 {
54 #endif
55
56 //*****************************************************************************
57 //
58 // Header Files
59 //
60 //*****************************************************************************
61 #include <stdbool.h>
62 #include <stdint.h>
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
65 #include <kernel/dpl/DebugP.h>
66 #include <drivers/hw_include/cslr_epwm.h>
67
68 //*****************************************************************************
69 //
70 // Defines for the API.
71 //
72 //*****************************************************************************
73 //*****************************************************************************
74 //
75 // Define to specify mask for source parameter for
76 // EPWM_enableSyncOutPulseSource() & EPWM_disableSyncOutPulseSource()
77 //
78 //*****************************************************************************
79 #define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK |\
80 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK |\
81 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK |\
82 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK |\
83 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK |\
84 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
85 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
86
87 //*****************************************************************************
88 //
89 // Values that can be passed to EPWM_enableSyncOutPulseSource() &
90 // EPWM_disableSyncOutPulseSource() as the \e mode parameter.
91 //
92 //*****************************************************************************
94 #define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
95 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
97 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
99 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
101 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
103 #define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
105 #define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
107 #define EPWM_SYNC_OUT_PULSE_ON_ALL EPWM_SYNC_OUT_SOURCE_M
109
110 //
111 // Time Base Module
112 //
113 //*****************************************************************************
114 //
117 //
118 //*****************************************************************************
119 typedef enum
120 {
122 EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0,
124 EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1,
126 EPWM_EMULATION_FREE_RUN = 2
127 } EPWM_EmulationMode;
128
129 //*****************************************************************************
130 //
133 //
134 //*****************************************************************************
135 typedef enum
136 {
137 EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0,
138 EPWM_COUNT_MODE_UP_AFTER_SYNC = 1
139 } EPWM_SyncCountMode;
140
141 //*****************************************************************************
142 //
145 //
146 //*****************************************************************************
147 typedef enum
148 {
149 EPWM_CLOCK_DIVIDER_1 = 0,
150 EPWM_CLOCK_DIVIDER_2 = 1,
151 EPWM_CLOCK_DIVIDER_4 = 2,
152 EPWM_CLOCK_DIVIDER_8 = 3,
153 EPWM_CLOCK_DIVIDER_16 = 4,
154 EPWM_CLOCK_DIVIDER_32 = 5,
155 EPWM_CLOCK_DIVIDER_64 = 6,
156 EPWM_CLOCK_DIVIDER_128 = 7
157 } EPWM_ClockDivider;
158
159 //*****************************************************************************
160 //
163 //
164 //*****************************************************************************
165 typedef enum
166 {
167 EPWM_HSCLOCK_DIVIDER_1 = 0,
168 EPWM_HSCLOCK_DIVIDER_2 = 1,
169 EPWM_HSCLOCK_DIVIDER_4 = 2,
170 EPWM_HSCLOCK_DIVIDER_6 = 3,
171 EPWM_HSCLOCK_DIVIDER_8 = 4,
172 EPWM_HSCLOCK_DIVIDER_10 = 5,
173 EPWM_HSCLOCK_DIVIDER_12 = 6,
174 EPWM_HSCLOCK_DIVIDER_14 = 7
175 } EPWM_HSClockDivider;
176
177 //*****************************************************************************
178 //
182 //
183 //*****************************************************************************
184 typedef enum
185 {
187 EPWM_SYNC_IN_PULSE_SRC_DISABLE = 0x0,
189 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0 = 0x1,
191 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1 = 0x2,
193 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2 = 0x3,
195 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3 = 0x4,
197 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4 = 0x5,
199 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5 = 0x6,
201 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6 = 0x7,
203 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7 = 0x8,
205 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8 = 0x9,
207 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9 = 0xA,
209 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10 = 0xB,
211 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11 = 0xC,
213 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12 = 0xD,
215 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13 = 0xE,
217 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14 = 0xF,
219 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15 = 0x10,
221 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16 = 0x11,
223 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17 = 0x12,
225 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18 = 0x13,
227 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19 = 0x14,
229 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20 = 0x15,
231 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21 = 0x16,
233 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22 = 0x17,
235 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23 = 0x18,
237 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24 = 0x19,
239 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25 = 0x1A,
241 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26 = 0x1B,
243 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27 = 0x1C,
245 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28 = 0x1D,
247 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29 = 0x1E,
249 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30 = 0x1F,
251 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31 = 0x20,
253 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0 = 0x40,
255 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1 = 0x41,
257 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2 = 0x42,
259 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3 = 0x43,
261 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4 = 0x44,
263 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5 = 0x45,
265 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6 = 0x46,
267 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7 = 0x47,
269 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8 = 0x48,
271 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9 = 0x49,
273 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP10 = 0x4A,
275 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP11 = 0x4B,
277 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP12 = 0x4C,
279 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP13 = 0x4D,
281 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP14 = 0x4E,
283 EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP15 = 0x4F,
285 EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4 = 0x50,
287 EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20 = 0x51,
289 EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0 = 0x58,
291 EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1 = 0x59,
293 EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0 = 0x60,
295 EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1 = 0x61,
297 EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2 = 0x62,
299 EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3 = 0x63,
301 EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0 = 0x64,
303 EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1 = 0x65,
305 EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2 = 0x66,
307 EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3 = 0x67,
309 EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0 = 0x68,
311 EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1 = 0x69,
313 EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2 = 0x6A,
315 EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3 = 0x6B,
317 EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0 = 0x6C,
319 EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1 = 0x6D,
321 EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2 = 0x6E,
323 EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3 = 0x6F
324 } EPWM_SyncInPulseSource;
325
326 //*****************************************************************************
327 //
330 //
331 //*****************************************************************************
332 typedef enum
333 {
334 EPWM_OSHT_SYNC_OUT_TRIG_SYNC = 0x0,
335 EPWM_OSHT_SYNC_OUT_TRIG_RELOAD = 0x1
336 } EPWM_OneShotSyncOutTrigger;
337
338 //*****************************************************************************
339 //
342 //
343 //*****************************************************************************
344 typedef enum
345 {
347 EPWM_PERIOD_SHADOW_LOAD = 0,
349 EPWM_PERIOD_DIRECT_LOAD = 1
350 } EPWM_PeriodLoadMode;
351
352 //*****************************************************************************
353 //
356 //
357 //*****************************************************************************
358 typedef enum
359 {
360 EPWM_COUNTER_MODE_UP = 0,
361 EPWM_COUNTER_MODE_DOWN = 1,
362 EPWM_COUNTER_MODE_UP_DOWN = 2,
363 EPWM_COUNTER_MODE_STOP_FREEZE = 3
364 } EPWM_TimeBaseCountMode;
365
366 //*****************************************************************************
367 //
370 //
371 //*****************************************************************************
372 typedef enum
373 {
375 EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0,
378 EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1,
380 EPWM_SHADOW_LOAD_MODE_SYNC = 2
381 } EPWM_PeriodShadowLoadMode;
382
383 //*****************************************************************************
384 //
385 // Values that can be returned by the EPWM_getTimeBaseCounterDirection()
386 //
387 //*****************************************************************************
389 #define EPWM_TIME_BASE_STATUS_COUNT_DOWN (0U)
390 #define EPWM_TIME_BASE_STATUS_COUNT_UP (1U)
392
393 //*****************************************************************************
394 //
397 //
398 //*****************************************************************************
399 typedef enum
400 {
401 EPWM_LINK_WITH_EPWM_0 = 0,
402 EPWM_LINK_WITH_EPWM_1 = 1,
403 EPWM_LINK_WITH_EPWM_2 = 2,
404 EPWM_LINK_WITH_EPWM_3 = 3,
405 EPWM_LINK_WITH_EPWM_4 = 4,
406 EPWM_LINK_WITH_EPWM_5 = 5,
407 EPWM_LINK_WITH_EPWM_6 = 6,
408 EPWM_LINK_WITH_EPWM_7 = 7,
409 EPWM_LINK_WITH_EPWM_8 = 8,
410 EPWM_LINK_WITH_EPWM_9 = 9,
411 EPWM_LINK_WITH_EPWM_10 = 10,
412 EPWM_LINK_WITH_EPWM_11 = 11,
413 EPWM_LINK_WITH_EPWM_12 = 12,
414 EPWM_LINK_WITH_EPWM_13 = 13,
415 EPWM_LINK_WITH_EPWM_14 = 14,
416 EPWM_LINK_WITH_EPWM_15 = 15,
417 EPWM_LINK_WITH_EPWM_16 = 16,
418 EPWM_LINK_WITH_EPWM_17 = 17,
419 EPWM_LINK_WITH_EPWM_18 = 18,
420 EPWM_LINK_WITH_EPWM_19 = 19,
421 EPWM_LINK_WITH_EPWM_20 = 20,
422 EPWM_LINK_WITH_EPWM_21 = 21,
423 EPWM_LINK_WITH_EPWM_22 = 22,
424 EPWM_LINK_WITH_EPWM_23 = 23,
425 EPWM_LINK_WITH_EPWM_24 = 24,
426 EPWM_LINK_WITH_EPWM_25 = 25,
427 EPWM_LINK_WITH_EPWM_26 = 26,
428 EPWM_LINK_WITH_EPWM_27 = 27,
429 EPWM_LINK_WITH_EPWM_28 = 28,
430 EPWM_LINK_WITH_EPWM_29 = 29,
431 EPWM_LINK_WITH_EPWM_30 = 30,
432 EPWM_LINK_WITH_EPWM_31 = 31,
433 } EPWM_CurrentLink;
434
435 //*****************************************************************************
436 //
439 //
440 //*****************************************************************************
441 typedef enum
442 {
443 EPWM_LINK_TBPRD = 0,
444 EPWM_LINK_COMP_A = 5,
445 EPWM_LINK_COMP_B = 10,
446 EPWM_LINK_COMP_C = 16,
447 EPWM_LINK_COMP_D = 21,
448 EPWM_LINK_GLDCTL2 = 26,
449 EPWM_LINK_DBRED = 1,
450 EPWM_LINK_DBFED = 6,
451 EPWM_LINK_XLOAD = 2
452 } EPWM_LinkComponent;
453
454 //
455 // Counter Compare Module
456 //
457 //*****************************************************************************
458 //
463 //
464 //*****************************************************************************
465 typedef enum
466 {
467 EPWM_COUNTER_COMPARE_A = 0,
468 EPWM_COUNTER_COMPARE_B = 4,
469 EPWM_COUNTER_COMPARE_C = 10,
470 EPWM_COUNTER_COMPARE_D = 14
471 } EPWM_CounterCompareModule;
472
473 //*****************************************************************************
474 //
477 //
478 //*****************************************************************************
479 typedef enum
480 {
482 EPWM_COMP_LOAD_ON_CNTR_ZERO = 0,
484 EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1,
486 EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2,
488 EPWM_COMP_LOAD_FREEZE = 3,
490 EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4,
492 EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5,
494 EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6,
496 EPWM_COMP_LOAD_ON_SYNC_ONLY = 8
497 } EPWM_CounterCompareLoadMode;
498
499 //
500 // Action Qualifier Module
501 //
502 //*****************************************************************************
503 //
506 //
507 //*****************************************************************************
508 typedef enum
509 {
510 EPWM_ACTION_QUALIFIER_A = 0,
511 EPWM_ACTION_QUALIFIER_B = 2
512 } EPWM_ActionQualifierModule;
513
514 //*****************************************************************************
515 //
518 //
519 //*****************************************************************************
520 typedef enum
521 {
523 EPWM_AQ_LOAD_ON_CNTR_ZERO = 0,
525 EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1,
527 EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2,
529 EPWM_AQ_LOAD_FREEZE = 3,
531 EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4,
533 EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5,
535 EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6,
537 EPWM_AQ_LOAD_ON_SYNC_ONLY = 8
538 } EPWM_ActionQualifierLoadMode;
539
540 //*****************************************************************************
541 //
544 //
545 //*****************************************************************************
546 typedef enum
547 {
548 EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0,
549 EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1,
550 EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2,
551 EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3,
552 EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4,
553 EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5,
554 EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6,
555 EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7,
556 EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT = 8
557 } EPWM_ActionQualifierTriggerSource;
558
559 //*****************************************************************************
560 //
563 //
564 //*****************************************************************************
565 typedef enum
566 {
568 EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0,
570 EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2,
572 EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4,
574 EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6,
576 EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8,
578 EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10,
580 EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1,
582 EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3,
584 EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5,
586 EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7
587 } EPWM_ActionQualifierOutputEvent;
588
589 //*****************************************************************************
590 //
593 //
594 //*****************************************************************************
595 typedef enum
596 {
597 EPWM_AQ_OUTPUT_NO_CHANGE = 0,
598 EPWM_AQ_OUTPUT_LOW = 1,
599 EPWM_AQ_OUTPUT_HIGH = 2,
600 EPWM_AQ_OUTPUT_TOGGLE = 3
601 } EPWM_ActionQualifierOutput;
602
603 //*****************************************************************************
604 //
607 //
608 //*****************************************************************************
609 typedef enum
610 {
611 EPWM_AQ_SW_DISABLED = 0,
612 EPWM_AQ_SW_OUTPUT_LOW = 1,
613 EPWM_AQ_SW_OUTPUT_HIGH = 2
614 } EPWM_ActionQualifierSWOutput;
615
616 //*****************************************************************************
617 //
620 //
621 //*****************************************************************************
622 typedef enum
623 {
625 EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0,
627 EPWM_AQ_OUTPUT_LOW_ZERO = 0x1,
629 EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2,
631 EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3,
633 EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0,
635 EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4,
637 EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8,
639 EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC,
641 EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00,
643 EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10,
645 EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20,
647 EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30,
649 EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00,
651 EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40,
653 EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80,
655 EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0,
657 EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000,
659 EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100,
661 EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200,
663 EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300,
665 EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000,
667 EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400,
669 EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800,
671 EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00
672 } EPWM_ActionQualifierEventAction;
673
674 //*****************************************************************************
675 //
679 //
680 //*****************************************************************************
681 typedef enum
682 {
684 EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0,
686 EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1,
688 EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2,
690 EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3,
692 EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0,
694 EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4,
696 EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8,
698 EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC,
700 EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00,
702 EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10,
704 EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20,
706 EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30,
708 EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00,
710 EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40,
712 EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80,
714 EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0
715 } EPWM_AdditionalActionQualifierEventAction;
716
717 //*****************************************************************************
718 //
724 //
725 //*****************************************************************************
726 typedef enum
727 {
728 EPWM_AQ_OUTPUT_A = 0,
729 EPWM_AQ_OUTPUT_B = 4
730 } EPWM_ActionQualifierOutputModule;
731
732 //*****************************************************************************
733 //
736 //
737 //*****************************************************************************
738 typedef enum
739 {
741 EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0,
743 EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1,
745 EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2,
747 EPWM_AQ_SW_IMMEDIATE_LOAD = 3
748 } EPWM_ActionQualifierContForce;
749
750 //*****************************************************************************
751 //
754 //
755 //*****************************************************************************
756 typedef enum
757 {
758 EPWM_DB_OUTPUT_A = 1,
759 EPWM_DB_OUTPUT_B = 0
760 } EPWM_DeadBandOutput;
761
762 //*****************************************************************************
763 //
766 //
767 //*****************************************************************************
768 typedef enum
769 {
770 EPWM_DB_RED = 1,
771 EPWM_DB_FED = 0
772 } EPWM_DeadBandDelayMode;
773
774 //*****************************************************************************
775 //
778 //
779 //*****************************************************************************
780 typedef enum
781 {
782 EPWM_DB_POLARITY_ACTIVE_HIGH = 0,
783 EPWM_DB_POLARITY_ACTIVE_LOW = 1
784 } EPWM_DeadBandPolarity;
785
786 //*****************************************************************************
787 //
788 // Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(),
789 // EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter.
790 //
791 //*****************************************************************************
793 #define EPWM_DB_INPUT_EPWMA (0U)
794 #define EPWM_DB_INPUT_EPWMB (1U)
796 #define EPWM_DB_INPUT_DB_RED (2U)
798
799 //*****************************************************************************
800 //
803 //
804 //*****************************************************************************
805 typedef enum
806 {
808 EPWM_DB_LOAD_ON_CNTR_ZERO = 0,
810 EPWM_DB_LOAD_ON_CNTR_PERIOD = 1,
812 EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2,
814 EPWM_DB_LOAD_FREEZE = 3
815 } EPWM_DeadBandControlLoadMode;
816
817 //*****************************************************************************
818 //
821 //
822 //*****************************************************************************
823 typedef enum
824 {
826 EPWM_RED_LOAD_ON_CNTR_ZERO = 0,
828 EPWM_RED_LOAD_ON_CNTR_PERIOD = 1,
830 EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2,
832 EPWM_RED_LOAD_FREEZE = 3
833 } EPWM_RisingEdgeDelayLoadMode;
834
835 //*****************************************************************************
836 //
839 //
840 //*****************************************************************************
841 typedef enum
842 {
844 EPWM_FED_LOAD_ON_CNTR_ZERO = 0,
846 EPWM_FED_LOAD_ON_CNTR_PERIOD = 1,
848 EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2,
850 EPWM_FED_LOAD_FREEZE = 3
851 } EPWM_FallingEdgeDelayLoadMode;
852
853 //*****************************************************************************
854 //
857 //
858 //*****************************************************************************
859 typedef enum
860 {
862 EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0,
864 EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1
865 } EPWM_DeadBandClockMode;
866
867 //
868 // Trip Zone
869 //
870 //*****************************************************************************
871 //
872 // Values that can be passed to EPWM_enableTripZoneSignals() and
873 // EPWM_disableTripZoneSignals() as the tzSignal parameter.
874 //
875 //*****************************************************************************
877 #define EPWM_TZ_SIGNAL_CBC1 (0x1U)
878 #define EPWM_TZ_SIGNAL_CBC2 (0x2U)
880 #define EPWM_TZ_SIGNAL_CBC3 (0x4U)
882 #define EPWM_TZ_SIGNAL_CBC4 (0x8U)
884 #define EPWM_TZ_SIGNAL_CBC5 (0x10U)
886 #define EPWM_TZ_SIGNAL_CBC6 (0x20U)
888 #define EPWM_TZ_SIGNAL_DCAEVT2 (0x40U)
890 #define EPWM_TZ_SIGNAL_DCBEVT2 (0x80U)
892 #define EPWM_TZ_SIGNAL_OSHT1 (0x100U)
894 #define EPWM_TZ_SIGNAL_OSHT2 (0x200U)
896 #define EPWM_TZ_SIGNAL_OSHT3 (0x400U)
898 #define EPWM_TZ_SIGNAL_OSHT4 (0x800U)
900 #define EPWM_TZ_SIGNAL_OSHT5 (0x1000U)
902 #define EPWM_TZ_SIGNAL_OSHT6 (0x2000U)
904 #define EPWM_TZ_SIGNAL_DCAEVT1 (0x4000U)
906 #define EPWM_TZ_SIGNAL_DCBEVT1 (0x8000U)
908 // //! One-shot Capture event
909 // #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x10000U)
910 // //! Cycle by cycle capture event
911 // #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1000000U)
912
913 //*****************************************************************************
914 //
915 // Values that can be passed to EPWM_enableTripZone2Signals() and
916 // EPWM_disableTripZone2Signals() as the tzSignal parameter.
917 //
918 //*****************************************************************************
920 #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1U)
921 #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x100U)
923
924 //*****************************************************************************
925 //
928 //
929 //*****************************************************************************
930 typedef enum
931 {
932 EPWM_TZ_DC_OUTPUT_A1 = 0,
933 EPWM_TZ_DC_OUTPUT_A2 = 3,
934 EPWM_TZ_DC_OUTPUT_B1 = 6,
935 EPWM_TZ_DC_OUTPUT_B2 = 9
936 } EPWM_TripZoneDigitalCompareOutput;
937
938 //*****************************************************************************
939 //
942 //
943 //*****************************************************************************
944 typedef enum
945 {
946 EPWM_TZ_EVENT_DC_DISABLED = 0,
947 EPWM_TZ_EVENT_DCXH_LOW = 1,
948 EPWM_TZ_EVENT_DCXH_HIGH = 2,
949 EPWM_TZ_EVENT_DCXL_LOW = 3,
950 EPWM_TZ_EVENT_DCXL_HIGH = 4,
951 EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5
952 } EPWM_TripZoneDigitalCompareOutputEvent;
953
954 //*****************************************************************************
955 //
958 //
959 //*****************************************************************************
960 typedef enum
961 {
962 EPWM_TZ_ACTION_EVENT_TZA = 0,
963 EPWM_TZ_ACTION_EVENT_TZB = 2,
964 EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4,
965 EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6,
966 EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8,
967 EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10
968 } EPWM_TripZoneEvent;
969
970 //*****************************************************************************
971 //
974 //
975 //*****************************************************************************
976 typedef enum
977 {
978 EPWM_TZ_ACTION_HIGH_Z = 0,
979 EPWM_TZ_ACTION_HIGH = 1,
980 EPWM_TZ_ACTION_LOW = 2,
981 EPWM_TZ_ACTION_DISABLE = 3
982 } EPWM_TripZoneAction;
983
984 //*****************************************************************************
985 //
988 //
989 //*****************************************************************************
990 typedef enum
991 {
993 EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9,
995 EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6,
997 EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3,
999 EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0
1000 } EPWM_TripZoneAdvancedEvent;
1001
1002 //*****************************************************************************
1003 //
1007 //
1008 //*****************************************************************************
1009 typedef enum
1010 {
1011 EPWM_TZ_ADV_ACTION_HIGH_Z = 0,
1012 EPWM_TZ_ADV_ACTION_HIGH = 1,
1013 EPWM_TZ_ADV_ACTION_LOW = 2,
1014 EPWM_TZ_ADV_ACTION_TOGGLE = 3,
1015 EPWM_TZ_ADV_ACTION_DISABLE = 7
1016 } EPWM_TripZoneAdvancedAction;
1017
1018 //*****************************************************************************
1019 //
1023 //
1024 //*****************************************************************************
1025 typedef enum
1026 {
1028 EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0,
1030 EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3,
1032 EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6,
1034 EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9
1035 } EPWM_TripZoneAdvDigitalCompareEvent;
1036
1037 //*****************************************************************************
1038 //
1039 // Values that can be passed to EPWM_enableTripZoneInterrupt()and
1040 // EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter .
1041 //
1042 //*****************************************************************************
1044 #define EPWM_TZ_INTERRUPT_CBC (0x2U)
1045 #define EPWM_TZ_INTERRUPT_OST (0x4U)
1047 #define EPWM_TZ_INTERRUPT_DCAEVT1 (0x8U)
1049 #define EPWM_TZ_INTERRUPT_DCAEVT2 (0x10U)
1051 #define EPWM_TZ_INTERRUPT_DCBEVT1 (0x20U)
1053 #define EPWM_TZ_INTERRUPT_DCBEVT2 (0x40U)
1055 #define EPWM_TZ_INTERRUPT_CAPEVT (0x80U)
1057
1058 //*****************************************************************************
1059 //
1060 // Values that can be returned by EPWM_getTripZoneFlagStatus() .
1061 //
1062 //*****************************************************************************
1064 #define EPWM_TZ_FLAG_CBC (0x2U)
1065 #define EPWM_TZ_FLAG_OST (0x4U)
1067 #define EPWM_TZ_FLAG_DCAEVT1 (0x8U)
1069 #define EPWM_TZ_FLAG_DCAEVT2 (0x10U)
1071 #define EPWM_TZ_FLAG_DCBEVT1 (0x20U)
1073 #define EPWM_TZ_FLAG_DCBEVT2 (0x40U)
1075 #define EPWM_TZ_FLAG_CAPEVT (0x80U)
1077
1078 //*****************************************************************************
1079 //
1080 // Value can be passed to EPWM_clearTripZoneFlag() as the
1081 // tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus().
1082 //
1083 //*****************************************************************************
1085 #define EPWM_TZ_INTERRUPT (0x1U)
1086
1087 //*****************************************************************************
1088 //
1089 // Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag()
1090 // as the tzCbcFlag parameter and returned by
1091 // EPWM_getCycleByCycleTripZoneFlagStatus().
1092 //
1093 //*****************************************************************************
1095 #define EPWM_TZ_CBC_FLAG_1 (0x1U)
1096 #define EPWM_TZ_CBC_FLAG_2 (0x2U)
1098 #define EPWM_TZ_CBC_FLAG_3 (0x4U)
1100 #define EPWM_TZ_CBC_FLAG_4 (0x8U)
1102 #define EPWM_TZ_CBC_FLAG_5 (0x10U)
1104 #define EPWM_TZ_CBC_FLAG_6 (0x20U)
1106 #define EPWM_TZ_CBC_FLAG_DCAEVT2 (0x40U)
1108 #define EPWM_TZ_CBC_FLAG_DCBEVT2 (0x80U)
1110 #define EPWM_TZ_CBC_FLAG_CAPEVT (0x100U)
1112
1113 //*****************************************************************************
1114 //
1115 // Values that can be passed to EPWM_clearOneShotTripZoneFlag() as
1116 // the tzCbcFlag parameter and returned by the
1117 // EPWM_getOneShotTripZoneFlagStatus() .
1118 //
1119 //*****************************************************************************
1121 #define EPWM_TZ_OST_FLAG_OST1 (0x1U)
1122 #define EPWM_TZ_OST_FLAG_OST2 (0x2U)
1124 #define EPWM_TZ_OST_FLAG_OST3 (0x4U)
1126 #define EPWM_TZ_OST_FLAG_OST4 (0x8U)
1128 #define EPWM_TZ_OST_FLAG_OST5 (0x10U)
1130 #define EPWM_TZ_OST_FLAG_OST6 (0x20U)
1132 #define EPWM_TZ_OST_FLAG_DCAEVT1 (0x40U)
1134 #define EPWM_TZ_OST_FLAG_DCBEVT1 (0x80U)
1136 #define EPWM_TZ_OST_FLAG_CAPEVT (0x100U)
1138
1139 //*****************************************************************************
1140 //
1143 //
1144 //*****************************************************************************
1145 typedef enum
1146 {
1148 EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0,
1150 EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1,
1152 EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2
1153 } EPWM_CycleByCycleTripZoneClearMode;
1154
1155 //*****************************************************************************
1156 //
1157 // Values that can be passed to EPWM_forceTripZoneEvent() as the
1158 // tzForceEvent parameter.
1159 //
1160 //*****************************************************************************
1162 #define EPWM_TZ_FORCE_EVENT_CBC (0x2U)
1163 #define EPWM_TZ_FORCE_EVENT_OST (0x4U)
1165 #define EPWM_TZ_FORCE_EVENT_DCAEVT1 (0x8U)
1167 #define EPWM_TZ_FORCE_EVENT_DCAEVT2 (0x10U)
1169 #define EPWM_TZ_FORCE_EVENT_DCBEVT1 (0x20U)
1171 #define EPWM_TZ_FORCE_EVENT_DCBEVT2 (0x40U)
1173 #define EPWM_TZ_FORCE_EVENT_CAPEVT (0x80U)
1175
1176 //*****************************************************************************
1177 //
1178 // Values that can be passed to EPWM_enableTripZoneOutput() and
1179 // EPWM_disableTripZoneOutput as the tzOutput parameter.
1180 //
1181 //*****************************************************************************
1183 #define EPWM_TZ_SELECT_TRIPOUT_OST (0x1)
1184 #define EPWM_TZ_SELECT_TRIPOUT_CBC (0x2)
1186 #define EPWM_TZ_SELECT_TRIPOUT_TZ1 (0x4)
1188 #define EPWM_TZ_SELECT_TRIPOUT_TZ2 (0x8)
1190 #define EPWM_TZ_SELECT_TRIPOUT_TZ3 (0x10)
1192 #define EPWM_TZ_SELECT_TRIPOUT_TZ4 (0x20)
1194 #define EPWM_TZ_SELECT_TRIPOUT_TZ5 (0x40)
1196 #define EPWM_TZ_SELECT_TRIPOUT_TZ6 (0x80)
1198 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1 (0x100)
1200 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2 (0x200)
1202 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1 (0x400)
1204 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2 (0x800)
1206 #define EPWM_TZ_SELECT_TRIPOUT_CAPEVT (0x1000)
1208
1209 //*****************************************************************************
1210 //
1211 // Values that can be passed to EPWM_setInterruptSource() as the
1212 // interruptSource parameter.
1213 //
1214 //*****************************************************************************
1216 #define EPWM_INT_TBCTR_ZERO (1U)
1217 #define EPWM_INT_TBCTR_PERIOD (2U)
1219 #define EPWM_INT_TBCTR_ETINTMIX (3U)
1221 #define EPWM_INT_TBCTR_U_CMPA (4U)
1223 #define EPWM_INT_TBCTR_U_CMPC (8U)
1225 #define EPWM_INT_TBCTR_D_CMPA (5U)
1227 #define EPWM_INT_TBCTR_D_CMPC (10U)
1229 #define EPWM_INT_TBCTR_U_CMPB (6U)
1231 #define EPWM_INT_TBCTR_U_CMPD (12U)
1233 #define EPWM_INT_TBCTR_D_CMPB (7U)
1235 #define EPWM_INT_TBCTR_D_CMPD (14U)
1237
1238 //*****************************************************************************
1239 //
1240 // Values that can be passed to EPWM_setInterruptSource() and
1241 // EPWM_setADCTriggerSource() as the mixedSource parameter.
1242 //
1243 //*****************************************************************************
1245 #define EPWM_INT_MIX_TBCTR_ZERO (0x1)
1246 #define EPWM_INT_MIX_TBCTR_PERIOD (0x2)
1248 #define EPWM_INT_MIX_TBCTR_U_CMPA (0x4)
1250 #define EPWM_INT_MIX_TBCTR_D_CMPA (0x8)
1252 #define EPWM_INT_MIX_TBCTR_U_CMPB (0x10)
1254 #define EPWM_INT_MIX_TBCTR_D_CMPB (0x20)
1256 #define EPWM_INT_MIX_TBCTR_U_CMPC (0x40)
1258 #define EPWM_INT_MIX_TBCTR_D_CMPC (0x80)
1260 #define EPWM_INT_MIX_TBCTR_U_CMPD (0x100)
1262 #define EPWM_INT_MIX_TBCTR_D_CMPD (0x200)
1264 #define EPWM_INT_MIX_DCAEVT1 (0x400)
1266
1267
1268 //*****************************************************************************
1269 //
1277 //
1278 //*****************************************************************************
1279 typedef enum
1280 {
1281 EPWM_SOC_A = 0,
1282 EPWM_SOC_B = 1
1283 } EPWM_ADCStartOfConversionType;
1284
1285 //*****************************************************************************
1286 //
1289 //
1290 //*****************************************************************************
1291 typedef enum
1292 {
1294 EPWM_SOC_DCxEVT1 = 0,
1296 EPWM_SOC_TBCTR_ZERO = 1,
1298 EPWM_SOC_TBCTR_PERIOD = 2,
1300 EPWM_SOC_TBCTR_MIXED_EVENT = 3,
1302 EPWM_SOC_TBCTR_U_CMPA = 4,
1304 EPWM_SOC_TBCTR_U_CMPC = 8,
1306 EPWM_SOC_TBCTR_D_CMPA = 5,
1308 EPWM_SOC_TBCTR_D_CMPC = 10,
1310 EPWM_SOC_TBCTR_U_CMPB = 6,
1312 EPWM_SOC_TBCTR_U_CMPD = 12,
1314 EPWM_SOC_TBCTR_D_CMPB = 7,
1316 EPWM_SOC_TBCTR_D_CMPD = 14
1317 } EPWM_ADCStartOfConversionSource;
1318
1319 //
1320 // Digital Compare Module
1321 //
1322 //*****************************************************************************
1323 //
1328 //
1329 //*****************************************************************************
1330 typedef enum
1331 {
1332 EPWM_DC_TYPE_DCAH = 0,
1333 EPWM_DC_TYPE_DCAL = 1,
1334 EPWM_DC_TYPE_DCBH = 2,
1335 EPWM_DC_TYPE_DCBL = 3
1336 } EPWM_DigitalCompareType;
1337
1338 //*****************************************************************************
1339 //
1343 //
1344 //*****************************************************************************
1345 typedef enum
1346 {
1347 EPWM_DC_TRIP_TRIPIN1 = 0,
1348 EPWM_DC_TRIP_TRIPIN2 = 1,
1349 EPWM_DC_TRIP_TRIPIN3 = 2,
1350 EPWM_DC_TRIP_TRIPIN4 = 3,
1351 EPWM_DC_TRIP_TRIPIN5 = 4,
1352 EPWM_DC_TRIP_TRIPIN6 = 5,
1353 EPWM_DC_TRIP_TRIPIN7 = 6,
1354 EPWM_DC_TRIP_TRIPIN8 = 7,
1355 EPWM_DC_TRIP_TRIPIN9 = 8,
1356 EPWM_DC_TRIP_TRIPIN10 = 9,
1357 EPWM_DC_TRIP_TRIPIN11 = 10,
1358 EPWM_DC_TRIP_TRIPIN12 = 11,
1359 EPWM_DC_TRIP_TRIPIN13 = 12,
1360 EPWM_DC_TRIP_TRIPIN14 = 13,
1361 EPWM_DC_TRIP_TRIPIN15 = 14,
1362 EPWM_DC_TRIP_COMBINATION = 15
1363 } EPWM_DigitalCompareTripInput;
1364
1365 //*****************************************************************************
1366 //
1367 // Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput()
1368 // EPWM_enableCaptureTripCombinationInput(),
1369 // EPWM_disableCaptureTripCombinationInput(),
1370 // EPWM_disableDigitalCompareTripCombinationInput() as the tripInput
1371 // parameter.
1372 //
1373 //*****************************************************************************
1375 #define EPWM_DC_COMBINATIONAL_TRIPIN1 (0x1U)
1376 #define EPWM_DC_COMBINATIONAL_TRIPIN2 (0x2U)
1378 #define EPWM_DC_COMBINATIONAL_TRIPIN3 (0x4U)
1380 #define EPWM_DC_COMBINATIONAL_TRIPIN4 (0x8U)
1382 #define EPWM_DC_COMBINATIONAL_TRIPIN5 (0x10U)
1384 #define EPWM_DC_COMBINATIONAL_TRIPIN6 (0x20U)
1386 #define EPWM_DC_COMBINATIONAL_TRIPIN7 (0x40U)
1388 #define EPWM_DC_COMBINATIONAL_TRIPIN8 (0x80U)
1390 #define EPWM_DC_COMBINATIONAL_TRIPIN9 (0x100U)
1392 #define EPWM_DC_COMBINATIONAL_TRIPIN10 (0x200U)
1394 #define EPWM_DC_COMBINATIONAL_TRIPIN11 (0x400U)
1396 #define EPWM_DC_COMBINATIONAL_TRIPIN12 (0x800U)
1398 #define EPWM_DC_COMBINATIONAL_TRIPIN13 (0x1000U)
1400 #define EPWM_DC_COMBINATIONAL_TRIPIN14 (0x2000U)
1402 #define EPWM_DC_COMBINATIONAL_TRIPIN15 (0x4000U)
1404
1405 //*****************************************************************************
1406 //
1409 //
1410 //*****************************************************************************
1411 typedef enum
1412 {
1414 EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0,
1416 EPWM_DC_WINDOW_START_TBCTR_ZERO = 1,
1418 EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2,
1420 EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX = 3
1421 } EPWM_DigitalCompareBlankingPulse;
1422
1423 //*****************************************************************************
1424 //
1425 // Values that can be passed to EPWM_setDigitalCompareBlankingEvent()
1426 // as the mixedSource parameter.
1427 //
1428 //*****************************************************************************
1430 #define EPWM_DC_TBCTR_ZERO (0x1)
1431 #define EPWM_DC_TBCTR_PERIOD (0x2)
1433 #define EPWM_DC_TBCTR_U_CMPA (0x4)
1435 #define EPWM_DC_TBCTR_D_CMPA (0x8)
1437 #define EPWM_DC_TBCTR_U_CMPB (0x10)
1439 #define EPWM_DC_TBCTR_D_CMPB (0x20)
1441 #define EPWM_DC_TBCTR_U_CMPC (0x40)
1443 #define EPWM_DC_TBCTR_D_CMPC (0x80)
1445 #define EPWM_DC_TBCTR_U_CMPD (0x100)
1447 #define EPWM_DC_TBCTR_D_CMPD (0x200)
1449
1450 //*****************************************************************************
1451 //
1454 //
1455 //*****************************************************************************
1456 typedef enum
1457 {
1458 EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0,
1459 EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1,
1460 EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2,
1461 EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3
1462 } EPWM_DigitalCompareFilterInput;
1463
1464 //*****************************************************************************
1465 //
1472 //
1473 //*****************************************************************************
1474 typedef enum
1475 {
1476 EPWM_DC_MODULE_A = 0,
1477 EPWM_DC_MODULE_B = 1
1478 } EPWM_DigitalCompareModule;
1479
1480 //*****************************************************************************
1481 //
1487 //
1488 //*****************************************************************************
1489 typedef enum
1490 {
1491 EPWM_DC_EVENT_1 = 0,
1492 EPWM_DC_EVENT_2 = 1
1493 } EPWM_DigitalCompareEvent;
1494
1495 //*****************************************************************************
1496 //
1499 //
1500 //*****************************************************************************
1501 typedef enum
1502 {
1504 EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0,
1506 EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1
1507 } EPWM_DigitalCompareEventSource;
1508
1509 //*****************************************************************************
1510 //
1513 //
1514 //*****************************************************************************
1515 typedef enum
1516 {
1518 EPWM_DC_EVENT_INPUT_SYNCED = 0,
1520 EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1
1521 } EPWM_DigitalCompareSyncMode;
1522
1523 //*****************************************************************************
1524 //
1527 //
1528 //*****************************************************************************
1529 typedef enum
1530 {
1532 EPWM_DC_CBC_LATCH_DISABLED = 0x0,
1534 EPWM_DC_CBC_LATCH_ENABLED = 0x1
1535 } EPWM_DigitalCompareCBCLatchMode;
1536
1537 //*****************************************************************************
1538 //
1541 //
1542 //*****************************************************************************
1543 typedef enum
1544 {
1546 EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO = 0x0,
1548 EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD = 0x1,
1550 EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD = 0x2
1551 } EPWM_DigitalCompareCBCLatchClearEvent;
1552
1553 //*****************************************************************************
1554 //
1557 //
1558 //*****************************************************************************
1559 typedef enum
1560 {
1562 EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0,
1564 EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1,
1566 EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2,
1568 EPWM_GL_LOAD_PULSE_SYNC = 0x3,
1570 EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4,
1572 EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5,
1574 EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6,
1576 EPWM_GL_LOAD_PULSE_CNTR_CMPC_U = 0x8,
1578 EPWM_GL_LOAD_PULSE_CNTR_CMPC_D = 0x9,
1580 EPWM_GL_LOAD_PULSE_CNTR_CMPD_U = 0xA,
1582 EPWM_GL_LOAD_PULSE_CNTR_CMPD_D = 0xB,
1584 EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF
1585 } EPWM_GlobalLoadTrigger;
1586
1587 //*****************************************************************************
1588 //
1589 // Values that can be passed to EPWM_enableGlobalLoadRegisters(),
1590 // EPWM_disableGlobalLoadRegisters() as theloadRegister parameter.
1591 //
1592 //*****************************************************************************
1594 #define EPWM_GL_REGISTER_TBPRD_TBPRDHR (0x1U)
1595 #define EPWM_GL_REGISTER_CMPA_CMPAHR (0x2U)
1597 #define EPWM_GL_REGISTER_CMPB_CMPBHR (0x4U)
1599 #define EPWM_GL_REGISTER_CMPC (0x8U)
1601 #define EPWM_GL_REGISTER_CMPD (0x10U)
1603 #define EPWM_GL_REGISTER_DBRED_DBREDHR (0x20U)
1605 #define EPWM_GL_REGISTER_DBFED_DBFEDHR (0x40U)
1607 #define EPWM_GL_REGISTER_DBCTL (0x80U)
1609 #define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 (0x100U)
1611 #define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 (0x200U)
1613 #define EPWM_GL_REGISTER_AQCSFRC (0x400U)
1615
1616 //*****************************************************************************
1617 //
1620 //
1621 //*****************************************************************************
1622 typedef enum
1623 {
1625 EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U,
1627 EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U,
1629 EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U,
1631 EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U,
1633 EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U,
1635 EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U,
1637 EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U,
1639 EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U
1640 } EPWM_ValleyTriggerSource;
1641
1642 //*****************************************************************************
1643 //
1646 //
1647 //*****************************************************************************
1648 typedef enum
1649 {
1650 EPWM_VALLEY_COUNT_START_EDGE = 0,
1651 EPWM_VALLEY_COUNT_STOP_EDGE = 1
1652 } EPWM_ValleyCounterEdge;
1653
1654 //*****************************************************************************
1655 //
1658 //
1659 //*****************************************************************************
1660 typedef enum
1661 {
1663 EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U,
1666 EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U,
1669 EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U,
1672 EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U,
1675 EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U
1676 } EPWM_ValleyDelayMode;
1677
1678 //
1679 // DC Edge Filter
1680 //
1681 //*****************************************************************************
1682 //
1685 //
1686 //*****************************************************************************
1687 typedef enum
1688 {
1690 EPWM_DC_EDGEFILT_MODE_RISING = 0,
1692 EPWM_DC_EDGEFILT_MODE_FALLING = 1,
1694 EPWM_DC_EDGEFILT_MODE_BOTH = 2
1695 } EPWM_DigitalCompareEdgeFilterMode;
1696
1697 //*****************************************************************************
1698 //
1701 //
1702 //*****************************************************************************
1703 typedef enum
1704 {
1706 EPWM_DC_EDGEFILT_EDGECNT_0 = 0,
1708 EPWM_DC_EDGEFILT_EDGECNT_1 = 1,
1710 EPWM_DC_EDGEFILT_EDGECNT_2 = 2,
1712 EPWM_DC_EDGEFILT_EDGECNT_3 = 3,
1714 EPWM_DC_EDGEFILT_EDGECNT_4 = 4,
1716 EPWM_DC_EDGEFILT_EDGECNT_5 = 5,
1718 EPWM_DC_EDGEFILT_EDGECNT_6 = 6,
1720 EPWM_DC_EDGEFILT_EDGECNT_7 = 7
1721 } EPWM_DigitalCompareEdgeFilterEdgeCount;
1722
1723 //*****************************************************************************
1724 //
1727 //
1728 //*****************************************************************************
1729 typedef enum
1730 {
1731 EPWM_REGISTER_GROUP_HR = 0x1,
1732 EPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2,
1733 EPWM_REGISTER_GROUP_TRIP_ZONE = 0x4,
1734 EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8,
1735 EPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10
1736 } EPWM_LockRegisterGroup;
1737
1738 //
1739 // Minimum Dead Band
1740 //
1741 //*****************************************************************************
1742 //
1744 //
1745 //*****************************************************************************
1747 #define EPWM_MINDB_BLOCK_A (0x0U)
1748 #define EPWM_MINDB_BLOCK_B (0x1U)
1750
1751 //*****************************************************************************
1752 //
1754 //
1755 //*****************************************************************************
1757 #define EPWM_MINDB_NO_INVERT (0x0)
1758 #define EPWM_MINDB_INVERT (0x1)
1760
1761 //*****************************************************************************
1762 //
1764 //
1765 //*****************************************************************************
1767 #define EPWM_MINDB_INVERT_LOGICAL_AND (0x0)
1768 #define EPWM_MINDB_LOGICAL_OR (0x1)
1770
1771 //*****************************************************************************
1772 //
1774 //
1775 //*****************************************************************************
1777 #define EPWM_MINDB_PWMB (0x0)
1778 #define EPWM_MINDB_PWM_OUTXBAR_OUT1 (0x1)
1780 #define EPWM_MINDB_PWM_OUTXBAR_OUT2 (0x2)
1782 #define EPWM_MINDB_PWM_OUTXBAR_OUT3 (0x3)
1784 #define EPWM_MINDB_PWM_OUTXBAR_OUT4 (0x4)
1786 #define EPWM_MINDB_PWM_OUTXBAR_OUT5 (0x5)
1788 #define EPWM_MINDB_PWM_OUTXBAR_OUT6 (0x6)
1790 #define EPWM_MINDB_PWM_OUTXBAR_OUT7 (0x7)
1792 #define EPWM_MINDB_PWM_OUTXBAR_OUT8 (0x8)
1794 #define EPWM_MINDB_PWM_OUTXBAR_OUT9 (0x9)
1796 #define EPWM_MINDB_PWM_OUTXBAR_OUT10 (0xA)
1798 #define EPWM_MINDB_PWM_OUTXBAR_OUT11 (0xB)
1800 #define EPWM_MINDB_PWM_OUTXBAR_OUT12 (0xC)
1802 #define EPWM_MINDB_PWM_OUTXBAR_OUT13 (0xD)
1804 #define EPWM_MINDB_PWM_OUTXBAR_OUT14 (0xE)
1806 #define EPWM_MINDB_PWM_OUTXBAR_OUT15 (0xF)
1808
1809 //*****************************************************************************
1810 //
1812 //
1813 //*****************************************************************************
1815 #define EPWM_MINDB_BLOCKING_SIGNAL_SAME (0x0)
1816 #define EPWM_MINDB_BLOCKING_SIGNAL_DIFF (0x1)
1818
1819 //*****************************************************************************
1820 //
1822 //
1823 //*****************************************************************************
1825 #define EPWM_MINDB_ICSS_XBAR_OUT0 (0x0)
1826 #define EPWM_MINDB_ICSS_XBAR_OUT1 (0x1)
1828 #define EPWM_MINDB_ICSS_XBAR_OUT2 (0x2)
1830 #define EPWM_MINDB_ICSS_XBAR_OUT3 (0x3)
1832 #define EPWM_MINDB_ICSS_XBAR_OUT4 (0x4)
1834 #define EPWM_MINDB_ICSS_XBAR_OUT5 (0x5)
1836 #define EPWM_MINDB_ICSS_XBAR_OUT6 (0x6)
1838 #define EPWM_MINDB_ICSS_XBAR_OUT7 (0x7)
1840 #define EPWM_MINDB_ICSS_XBAR_OUT8 (0x8)
1842 #define EPWM_MINDB_ICSS_XBAR_OUT9 (0x9)
1844 #define EPWM_MINDB_ICSS_XBAR_OUT10 (0xA)
1846 #define EPWM_MINDB_ICSS_XBAR_OUT11 (0xB)
1848 #define EPWM_MINDB_ICSS_XBAR_OUT12 (0xC)
1850 #define EPWM_MINDB_ICSS_XBAR_OUT13 (0xD)
1852 #define EPWM_MINDB_ICSS_XBAR_OUT14 (0xE)
1854 #define EPWM_MINDB_ICSS_XBAR_OUT15 (0xF)
1856
1857 //*****************************************************************************
1858 //
1862 //
1863 //*****************************************************************************
1864 typedef enum
1865 {
1866 HRPWM_CHANNEL_A = 0,
1867 HRPWM_CHANNEL_B = 8
1868 } HRPWM_Channel;
1869
1870 //*****************************************************************************
1871 //
1874 //
1875 //*****************************************************************************
1876 typedef enum
1877 {
1879 HRPWM_MEP_CTRL_DISABLE = 0,
1881 HRPWM_MEP_CTRL_RISING_EDGE = 1,
1883 HRPWM_MEP_CTRL_FALLING_EDGE = 2,
1885 HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3
1886 } HRPWM_MEPEdgeMode;
1887
1888 //*****************************************************************************
1889 //
1892 //
1893 //*****************************************************************************
1894 typedef enum
1895 {
1897 HRPWM_MEP_DUTY_PERIOD_CTRL = 0,
1899 HRPWM_MEP_PHASE_CTRL = 1
1900 } HRPWM_MEPCtrlMode;
1901
1902 //*****************************************************************************
1903 //
1907 //
1908 //*****************************************************************************
1909 typedef enum
1910 {
1912 HRPWM_LOAD_ON_CNTR_ZERO = 0,
1914 HRPWM_LOAD_ON_CNTR_PERIOD = 1,
1916 HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2,
1918 HRPWM_LOAD_ON_CMPB_EQ = 3
1919 } HRPWM_LoadMode;
1920
1921 //*****************************************************************************
1922 //
1925 //
1926 //*****************************************************************************
1927 typedef enum
1928 {
1930 HRPWM_OUTPUT_ON_B_NORMAL = 0,
1932 HRPWM_OUTPUT_ON_B_INV_A = 1
1933 } HRPWM_ChannelBOutput;
1934
1935 //*****************************************************************************
1936 //
1939 //
1940 //*****************************************************************************
1941 typedef enum
1942 {
1944 HRPWM_PWMSYNC_SOURCE_PERIOD = 0,
1946 HRPWM_PWMSYNC_SOURCE_ZERO = 1,
1948 HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4,
1950 HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5,
1952 HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6,
1954 HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7
1955 } HRPWM_SyncPulseSource;
1956
1957 //*****************************************************************************
1958 //
1961 //
1962 //*****************************************************************************
1963 typedef enum
1964 {
1965 HRPWM_COUNTER_COMPARE_A = 0,
1966 HRPWM_COUNTER_COMPARE_B = 4
1967 } HRPWM_CounterCompareModule;
1968
1969 //*****************************************************************************
1970 //
1973 //
1974 //*****************************************************************************
1975 typedef enum
1976 {
1978 HRPWM_DB_MEP_CTRL_DISABLE = 0,
1980 HRPWM_DB_MEP_CTRL_RED = 1,
1982 HRPWM_DB_MEP_CTRL_FED = 2,
1984 HRPWM_DB_MEP_CTRL_RED_FED = 3
1985 } HRPWM_MEPDeadBandEdgeMode;
1986 //*****************************************************************************
1987 //
1990 //
1991 //*****************************************************************************
1992 typedef enum
1993 {
1995 HRPWM_XCMP1_ACTIVE = 0,
1997 HRPWM_XCMP2_ACTIVE = 4,
1999 HRPWM_XCMP3_ACTIVE = 8,
2001 HRPWM_XCMP4_ACTIVE = 12,
2003 HRPWM_XCMP5_ACTIVE = 16,
2005 HRPWM_XCMP6_ACTIVE = 20,
2007 HRPWM_XCMP7_ACTIVE = 24,
2009 HRPWM_XCMP8_ACTIVE = 28,
2011 HRPWM_XTBPRD_ACTIVE = 32,
2012
2014 HRPWM_XCMP1_SHADOW1 = 128,
2016 HRPWM_XCMP2_SHADOW1 = 132,
2018 HRPWM_XCMP3_SHADOW1 = 136,
2020 HRPWM_XCMP4_SHADOW1 = 140,
2022 HRPWM_XCMP5_SHADOW1 = 144,
2024 HRPWM_XCMP6_SHADOW1 = 148,
2026 HRPWM_XCMP7_SHADOW1 = 152,
2028 HRPWM_XCMP8_SHADOW1 = 156,
2030 HRPWM_XTBPRD_SHADOW1 = 160,
2031
2033 HRPWM_XCMP1_SHADOW2 = 256,
2035 HRPWM_XCMP2_SHADOW2 = 260,
2037 HRPWM_XCMP3_SHADOW2 = 264,
2039 HRPWM_XCMP4_SHADOW2 = 268,
2041 HRPWM_XCMP5_SHADOW2 = 272,
2043 HRPWM_XCMP6_SHADOW2 = 276,
2045 HRPWM_XCMP7_SHADOW2 = 280,
2047 HRPWM_XCMP8_SHADOW2 = 284,
2049 HRPWM_XTBPRD_SHADOW2 = 288,
2050
2052 HRPWM_XCMP1_SHADOW3 = 384,
2054 HRPWM_XCMP2_SHADOW3 = 388,
2056 HRPWM_XCMP3_SHADOW3 = 392,
2058 HRPWM_XCMP4_SHADOW3 = 396,
2060 HRPWM_XCMP5_SHADOW3 = 400,
2062 HRPWM_XCMP6_SHADOW3 = 404,
2064 HRPWM_XCMP7_SHADOW3 = 408,
2066 HRPWM_XCMP8_SHADOW3 = 412,
2068 HRPWM_XTBPRD_SHADOW3 = 416,
2069 }HRPWM_XCMPReg;
2070 //
2073 //
2074 //*****************************************************************************
2076 #define EPWM_XCMP_ACTIVE (0x0U)
2077 #define EPWM_XCMP_SHADOW1 (0x1U)
2079 #define EPWM_XCMP_SHADOW2 (0x2U)
2081 #define EPWM_XCMP_SHADOW3 (0x3U)
2083
2084 //*****************************************************************************
2085 //
2088 //
2089 //*****************************************************************************
2090 typedef enum
2091 {
2093 EPWM_XCMP1_ACTIVE = 0,
2095 EPWM_XCMP2_ACTIVE = 4,
2097 EPWM_XCMP3_ACTIVE = 8,
2099 EPWM_XCMP4_ACTIVE = 12,
2101 EPWM_XCMP5_ACTIVE = 16,
2103 EPWM_XCMP6_ACTIVE = 20,
2105 EPWM_XCMP7_ACTIVE = 24,
2107 EPWM_XCMP8_ACTIVE = 28,
2109 EPWM_XTBPRD_ACTIVE = 32,
2110
2112 EPWM_XCMP1_SHADOW1 = 128,
2114 EPWM_XCMP2_SHADOW1 = 132,
2116 EPWM_XCMP3_SHADOW1 = 136,
2118 EPWM_XCMP4_SHADOW1 = 140,
2120 EPWM_XCMP5_SHADOW1 = 144,
2122 EPWM_XCMP6_SHADOW1 = 148,
2124 EPWM_XCMP7_SHADOW1 = 152,
2126 EPWM_XCMP8_SHADOW1 = 156,
2128 EPWM_XTBPRD_SHADOW1 = 160,
2129
2131 EPWM_XCMP1_SHADOW2 = 256,
2133 EPWM_XCMP2_SHADOW2 = 260,
2135 EPWM_XCMP3_SHADOW2 = 264,
2137 EPWM_XCMP4_SHADOW2 = 268,
2139 EPWM_XCMP5_SHADOW2 = 272,
2141 EPWM_XCMP6_SHADOW2 = 276,
2143 EPWM_XCMP7_SHADOW2 = 280,
2145 EPWM_XCMP8_SHADOW2 = 284,
2147 EPWM_XTBPRD_SHADOW2 = 288,
2148
2150 EPWM_XCMP1_SHADOW3 = 384,
2152 EPWM_XCMP2_SHADOW3 = 388,
2154 EPWM_XCMP3_SHADOW3 = 392,
2156 EPWM_XCMP4_SHADOW3 = 396,
2158 EPWM_XCMP5_SHADOW3 = 400,
2160 EPWM_XCMP6_SHADOW3 = 404,
2162 EPWM_XCMP7_SHADOW3 = 408,
2164 EPWM_XCMP8_SHADOW3 = 412,
2166 EPWM_XTBPRD_SHADOW3 = 416,
2167
2168 }EPWM_XCMPReg;
2169
2170 //*****************************************************************************
2171 //
2174 //
2175 //*****************************************************************************
2176 typedef enum
2177 {
2179 EPWM_CMPC_SHADOW1 = 0x0U,
2181 EPWM_CMPD_SHADOW1 = 0x4U,
2183 EPWM_CMPC_SHADOW2 = 0x80U,
2185 EPWM_CMPD_SHADOW2 = 0x84U,
2187 EPWM_CMPC_SHADOW3 = 0x100U,
2189 EPWM_CMPD_SHADOW3 = 0x104U
2190
2191 }EPWM_XCompareReg;
2192
2193 //*****************************************************************************
2194 //
2197 //
2198 //*****************************************************************************
2199 typedef enum
2200 {
2202 EPWM_XMAX_ACTIVE = 0x0U,
2204 EPWM_XMIN_ACTIVE = 0x2U,
2206 EPWM_XMAX_SHADOW1 = 0x80U,
2208 EPWM_XMIN_SHADOW1 = 0x82U,
2210 EPWM_XMAX_SHADOW2 = 0x100U,
2212 EPWM_XMIN_SHADOW2 = 0x102U,
2214 EPWM_XMAX_SHADOW3 = 0x180U,
2216 EPWM_XMIN_SHADOW3 = 0x182U,
2217
2218 }EPWM_XMinMaxReg;
2219
2220 //*****************************************************************************
2221 //
2223 //
2224 //*****************************************************************************
2225 typedef enum
2226 {
2228 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1 = 0,
2230 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2 = 2,
2232 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3 = 4,
2234 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4 = 6,
2236 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5 = 8,
2238 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6 = 10,
2240 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7 = 12,
2242 EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8 = 14
2243 } EPWM_XCMPActionQualifierOutputEvent;
2244
2245 //*****************************************************************************
2246 //
2248 //
2249 //*****************************************************************************
2250
2251 typedef enum
2252 {
2254 EPWM_XCMP_NONE_CMPA = 0,
2256 EPWM_XCMP_1_CMPA = 1,
2258 EPWM_XCMP_2_CMPA = 2,
2260 EPWM_XCMP_3_CMPA = 3,
2262 EPWM_XCMP_4_CMPA = 4,
2264 EPWM_XCMP_5_CMPA = 5,
2266 EPWM_XCMP_6_CMPA = 6,
2268 EPWM_XCMP_7_CMPA = 7,
2270 EPWM_XCMP_8_CMPA = 8
2271 }EPWM_XCMP_ALLOC_CMPA;
2272
2273 //*****************************************************************************
2274 //
2276 //
2277 //*****************************************************************************
2278
2279 typedef enum
2280 {
2282 EPWM_XCMP_1_CMPB = 5,
2284 EPWM_XCMP_2_CMPB = 6,
2286 EPWM_XCMP_3_CMPB = 7,
2288 EPWM_XCMP_4_CMPB = 8
2289 }EPWM_XCMP_ALLOC_CMPB;
2290
2291 //*****************************************************************************
2292 //
2295 //
2296 //*****************************************************************************
2297 typedef enum
2298 {
2300 EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE = 0,
2302 EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE = 1
2303 }EPWM_XCMPXloadCtlLoadMode;
2304
2305 //*****************************************************************************
2306 //
2309 //
2310 //*****************************************************************************
2311
2312 typedef enum
2313 {
2315 EPWM_XCMP_XLOADCTL_SHDWLEVEL_0 = 0,
2317 EPWM_XCMP_XLOADCTL_SHDWLEVEL_1 = 1,
2319 EPWM_XCMP_XLOADCTL_SHDWLEVEL_2 = 2,
2321 EPWM_XCMP_XLOADCTL_SHDWLEVEL_3 = 3
2322 }EPWM_XCMP_XLOADCTL_SHDWLEVEL;
2323
2324 //*****************************************************************************
2325 //
2328 //
2329 //*****************************************************************************
2330
2331 typedef enum
2332 {
2334 EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL = 0,
2336 EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE = 1,
2338 EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO = 2,
2340 EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE =3
2341 }EPWM_XCMP_XLOADCTL_SHDWBUFPTR;
2342
2343 //
2344 // Diode Emulation Logic
2345 //
2346 //*****************************************************************************
2347 //
2350 //
2351 //*****************************************************************************
2352 typedef enum{
2354 EPWM_DIODE_EMULATION_CBC = 0,
2356 EPWM_DIODE_EMULATION_OST = 1
2357 }EPWM_DiodeEmulationMode;
2358
2359
2360 //*****************************************************************************
2361 //
2364 //
2365 //*****************************************************************************
2366 typedef enum{
2368 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0 = 0x01,
2370 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1 = 0x02,
2372 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2 = 0x03,
2374 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3 = 0x04,
2376 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4 = 0x05,
2378 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5 = 0x06,
2380 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6 = 0x07,
2382 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7 = 0x08,
2384 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8 = 0x09,
2386 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9 = 0x0A,
2388 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10 = 0x0B,
2390 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11 = 0x0C,
2392 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12 = 0x0D,
2394 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13 = 0x0E,
2396 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14 = 0x0F,
2398 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15 = 0x10,
2400 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16 = 0x11,
2402 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17 = 0x12,
2404 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18 = 0x13,
2406 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19 = 0x14,
2408 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20 = 0x15,
2410 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21 = 0x16,
2412 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22 = 0x17,
2414 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23 = 0x18,
2416 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24 = 0x19,
2418 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25 = 0x1A,
2420 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26 = 0x1B,
2422 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27 = 0x1C,
2424 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28 = 0x1D,
2426 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29 = 0x1E,
2428 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30 = 0x1F,
2430 EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31 = 0x20,
2432 EPWM_DE_TRIP_SRC_CMPSSA0 = 0x21,
2434 EPWM_DE_TRIP_SRC_CMPSSA1 = 0x22,
2436 EPWM_DE_TRIP_SRC_CMPSSA2 = 0x23,
2438 EPWM_DE_TRIP_SRC_CMPSSA3 = 0x24,
2440 EPWM_DE_TRIP_SRC_CMPSSA4 = 0x25,
2442 EPWM_DE_TRIP_SRC_CMPSSA5 = 0x26,
2444 EPWM_DE_TRIP_SRC_CMPSSA6 = 0x27,
2446 EPWM_DE_TRIP_SRC_CMPSSA7 = 0x28,
2448 EPWM_DE_TRIP_SRC_CMPSSA8 = 0x29,
2450 EPWM_DE_TRIP_SRC_CMPSSA9 = 0x2A,
2452 EPWM_DE_TRIP_SRC_CMPSSB0 = 0x31,
2454 EPWM_DE_TRIP_SRC_CMPSSB1 = 0x32,
2456 EPWM_DE_TRIP_SRC_CMPSSB2 = 0x33,
2458 EPWM_DE_TRIP_SRC_CMPSSB3 = 0x34,
2460 EPWM_DE_TRIP_SRC_CMPSSB4 = 0x35,
2462 EPWM_DE_TRIP_SRC_CMPSSB5 = 0x36,
2464 EPWM_DE_TRIP_SRC_CMPSSB6 = 0x37,
2466 EPWM_DE_TRIP_SRC_CMPSSB7 = 0x38,
2468 EPWM_DE_TRIP_SRC_CMPSSB8 = 0x39,
2470 EPWM_DE_TRIP_SRC_CMPSSB9 = 0x3A
2471 }EPWM_DiodeEmulationTripSource;
2472
2473
2474 typedef enum{
2475
2477 EPWM_DE_SYNC_TRIPHorL = 0x00,
2479 EPWM_DE_SYNC_INV_TRIPHorL = 0x01,
2481 EPWM_DE_LOW = 0x10,
2483 EPWM_DE_HIGH = 0x11
2484 }EPWM_DiodeEmulationSignal;
2485 //*****************************************************************************
2486 //
2489 //
2490 //*****************************************************************************
2492 #define EPWM_DE_CHANNEL_A (0x0U)
2493 #define EPWM_DE_CHANNEL_B (0x1U)
2495
2496 //*****************************************************************************
2497 //
2499 //
2500 //*****************************************************************************
2501
2503 #define EPWM_DE_COUNT_UP (0x0U)
2504 #define EPWM_DE_COUNT_DOWN (0x1U)
2506
2507 //*****************************************************************************
2508 //
2510 //
2511 //*****************************************************************************
2512
2514 #define EPWM_DE_TRIPL (0x1U)
2515 #define EPWM_DE_TRIPH (0x0U)
2517
2518 //*****************************************************************************
2519 //
2522 //
2523 //*****************************************************************************
2525 #define EPWM_CAPGATE_INPUT_ALWAYS_ON (0U)
2526 #define EPWM_CAPGATE_INPUT_ALWAYS_OFF (1U)
2528 #define EPWM_CAPGATE_INPUT_SYNC (2U)
2530 #define EPWM_CAPGATE_INPUT_SYNC_INVERT (3U)
2532
2533 //*****************************************************************************
2534 //
2537 //
2538 //*****************************************************************************
2540 #define EPWM_CAPTURE_INPUT_CAPIN_SYNC (0U)
2541 #define EPWM_CAPTURE_INPUT_CAPIN_SYNC_INVERT (1U)
2543
2544 //*****************************************************************************
2545 //
2550 //
2551 //*****************************************************************************
2553 #define EPWM_CAPTURE_GATE (1U)
2554 #define EPWM_CAPTURE_INPUT (0U)
2556
2557 //*****************************************************************************
2558 //
2561 //
2562 //*****************************************************************************
2564 #define EPWM_AQ_A_SW_DISABLED_B_SW_DISABLED (0x0U)
2565 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_DISABLED (0x1U)
2567 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_DISABLED (0x2U)
2569 #define EPWM_AQ_A_SW_DISABLED_B_SW_OUTPUT_LOW (0x4U)
2571 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_OUTPUT_LOW (0x5U)
2573 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_OUTPUT_LOW (0x6U)
2575 #define EPWM_AQ_A_SW_DISABLED_B_SW_OUTPUT_HIGH (0x8U)
2577 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_OUTPUT_HIGH (0x9U)
2579 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_OUTPUT_HIGH (0xAU)
2581
2582
2583 //*****************************************************************************
2584 //
2586 //
2587 //*****************************************************************************
2588 #define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
2589 #define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
2590 #define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
2591 #define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
2592 #define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
2593 #define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
2594 #define EPWM_LOCK_KEY (0xA5A50000U)
2595
2596 //*****************************************************************************
2597 //
2600 //
2601 //*****************************************************************************
2602 typedef struct
2603 {
2604 Float32 freqInHz;
2605 Float32 dutyValA;
2606 Float32 dutyValB;
2607 bool invertSignalB;
2608 Float32 sysClkInHz;
2609 EPWM_TimeBaseCountMode tbCtrMode;
2610 EPWM_ClockDivider tbClkDiv;
2611 EPWM_HSClockDivider tbHSClkDiv;
2612 } EPWM_SignalParams;
2613
2614 //
2615 // Time Base Sub Module related APIs
2616 //
2617 //*****************************************************************************
2618 //
2627 //
2628 //*****************************************************************************
2629 static inline void
2630 EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
2631 {
2632 //
2633 // Write to TBCTR register
2634 //
2635 HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
2636 }
2637
2638 //*****************************************************************************
2639 //
2652 //
2653 //*****************************************************************************
2654 static inline void
2655 EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
2656 {
2657 if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC)
2658 {
2659 //
2660 // Set PHSDIR bit
2661 //
2662 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2663 (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
2664 CSL_EPWM_TBCTL_PHSDIR_MASK));
2665 }
2666 else
2667 {
2668 //
2669 // Clear PHSDIR bit
2670 //
2671 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2672 (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2673 ~CSL_EPWM_TBCTL_PHSDIR_MASK));
2674 }
2675 }
2676
2677 //*****************************************************************************
2678 //
2698 //
2699 //*****************************************************************************
2700 static inline void
2701 EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler,
2702 EPWM_HSClockDivider highSpeedPrescaler)
2703 {
2704 //
2705 // Write to CLKDIV and HSPCLKDIV bit
2706 //
2707 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2708 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2709 ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
2710 (uint16_t)(((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
2711 (uint16_t)((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
2712 }
2713
2714 //*****************************************************************************
2715 //
2725 //
2726 //*****************************************************************************
2727 static inline void
2728 EPWM_forceSyncPulse(uint32_t base)
2729 {
2730 //
2731 // Set SWFSYNC bit
2732 //
2733 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2734 HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
2735 }
2736
2737 //*****************************************************************************
2738 //
2765 //
2766 //*****************************************************************************
2767 static inline void
2768 EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
2769 {
2770 //
2771 // Set EPWM Sync-In Source Mode.
2772 //
2773 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
2774 ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
2775 (~(uint16_t)CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
2776 (uint16_t)((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
2777 }
2778
2779 //*****************************************************************************
2780 //
2812 //
2813 //*****************************************************************************
2814 static inline void
2815 EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
2816 {
2817 //
2818 // Check the arguments
2819 //
2820 DebugP_assert(source <= EPWM_SYNC_OUT_SOURCE_M);
2821
2822 //
2823 // Enable selected EPWM Sync-Out Sources.
2824 //
2825 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2826 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
2827 (uint16_t)source));
2828 }
2829
2830 //*****************************************************************************
2831 //
2857 //
2858 //*****************************************************************************
2859 static inline void
2860 EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
2861 {
2862 //
2863 // Check the arguments
2864 //
2865 DebugP_assert(source <= EPWM_SYNC_OUT_SOURCE_M);
2866
2867 //
2868 // Disable EPWM Sync-Out Sources.
2869 //
2870 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2871 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
2872 ~((uint16_t)source)));
2873 }
2874
2875 //*****************************************************************************
2876 //
2890 //
2891 //*****************************************************************************
2892 static inline void
2893 EPWM_setOneShotSyncOutTrigger(uint32_t base,
2894 EPWM_OneShotSyncOutTrigger trigger)
2895 {
2896 //
2897 // Set source for One-Shot Sync-Out Pulse.
2898 //
2899 HW_WR_REG16(base + CSL_EPWM_TBCTL3,
2900 ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
2901 ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
2902 (uint16_t)trigger));
2903 }
2904
2905 //*****************************************************************************
2906 //
2919 //
2920 //*****************************************************************************
2921 static inline void
2922 EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
2923 {
2924 if(loadMode == EPWM_PERIOD_SHADOW_LOAD)
2925 {
2926 //
2927 // Clear PRDLD
2928 //
2929 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2930 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
2931 }
2932 else
2933 {
2934 //
2935 // Set PRDLD
2936 //
2937 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2938 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
2939 }
2940 }
2941
2942 //*****************************************************************************
2943 //
2952 //
2953 //*****************************************************************************
2954 static inline void
2955 EPWM_enablePhaseShiftLoad(uint32_t base)
2956 {
2957 //
2958 // Set PHSEN bit
2959 //
2960 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2961 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
2962 }
2963
2964 //*****************************************************************************
2965 //
2973 //
2974 //*****************************************************************************
2975 static inline void
2976 EPWM_disablePhaseShiftLoad(uint32_t base)
2977 {
2978 //
2979 // Clear PHSEN bit
2980 //
2981 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2982 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
2983 }
2984
2985 //*****************************************************************************
2986 //
3000 //
3001 //*****************************************************************************
3002 static inline void
3003 EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
3004 {
3005 //
3006 // Write to CTRMODE bit
3007 //
3008 HW_WR_REG16(base + CSL_EPWM_TBCTL,
3009 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
3010 ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
3011 }
3012
3013 //*****************************************************************************
3014 //
3031 //
3032 //*****************************************************************************
3033 static inline void
3034 EPWM_selectPeriodLoadEvent(uint32_t base,
3035 EPWM_PeriodShadowLoadMode shadowLoadMode)
3036 {
3037 //
3038 // Write to PRDLDSYNC bit
3039 //
3040 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3041 ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
3042 ~(uint16_t)(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
3043 (uint16_t)((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
3044 }
3045 //*****************************************************************************
3046 //
3054 //
3055 //*****************************************************************************
3056 static inline void
3057 EPWM_enableOneShotSync(uint32_t base)
3058 {
3059 //
3060 // Set OSHTSYNCMODE bit
3061 //
3062 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3063 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
3064 CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
3065 }
3066
3067 //*****************************************************************************
3068 //
3076 //
3077 //*****************************************************************************
3078 static inline void
3079 EPWM_disableOneShotSync(uint32_t base)
3080 {
3081 //
3082 // Clear OSHTSYNCMODE bit
3083 //
3084 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3085 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
3086 ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
3087 }
3088
3089 //*****************************************************************************
3090 //
3098 //
3099 //*****************************************************************************
3100 static inline void
3101 EPWM_startOneShotSync(uint32_t base)
3102 {
3103 //
3104 // Set OSHTSYNC bit
3105 //
3106 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3107 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
3108 }
3109
3110 //*****************************************************************************
3111 //
3119 //
3120 //*****************************************************************************
3121 static inline uint16_t
3122 EPWM_getTimeBaseCounterValue(uint32_t base)
3123 {
3124 //
3125 // Returns TBCTR value
3126 //
3127 return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
3128 }
3129
3130 //*****************************************************************************
3131 //
3140 //
3141 //*****************************************************************************
3142 static inline bool
3143 EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
3144 {
3145 //
3146 // Return true if CTRMAX bit is set, false otherwise
3147 //
3148 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
3149 CSL_EPWM_TBSTS_CTRMAX_MASK) ==
3150 CSL_EPWM_TBSTS_CTRMAX_MASK) ? true : false);
3151 }
3152
3153 //*****************************************************************************
3154 //
3163 //
3164 //*****************************************************************************
3165 static inline void
3166 EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
3167 {
3168 //
3169 // Set CTRMAX bit
3170 //
3171 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3172 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
3173 }
3174
3175 //*****************************************************************************
3176 //
3185 //
3186 //*****************************************************************************
3187 static inline bool
3188 EPWM_getSyncStatus(uint32_t base)
3189 {
3190 //
3191 // Return true if SYNCI bit is set, false otherwise
3192 //
3193 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
3194 CSL_EPWM_TBSTS_SYNCI_MASK) ? true : false);
3195 }
3196
3197 //*****************************************************************************
3198 //
3206 //
3207 //*****************************************************************************
3208 static inline void
3209 EPWM_clearSyncEvent(uint32_t base)
3210 {
3211 //
3212 // Set SYNCI bit
3213 //
3214 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3215 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
3216 }
3217
3218 //*****************************************************************************
3219 //
3229 //
3230 //*****************************************************************************
3231 static inline uint16_t
3232 EPWM_getTimeBaseCounterDirection(uint32_t base)
3233 {
3234 //
3235 // Return CTRDIR bit
3236 //
3237 return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
3238 }
3239
3240 //*****************************************************************************
3241 //
3253 //
3254 //*****************************************************************************
3255 static inline void
3256 EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
3257 {
3258 //
3259 // Write to TBPHS bit
3260 //
3261 HW_WR_REG32(base + CSL_EPWM_TBPHS,
3262 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
3263 ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
3264 ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
3265 }
3266
3267 //*****************************************************************************
3268 //
3282 //
3283 //*****************************************************************************
3284 static inline void
3285 EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
3286 {
3287 //
3288 // Write to TBPRD bit
3289 //
3290 HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
3291 }
3292
3293 //*****************************************************************************
3294 //
3302 //
3303 //*****************************************************************************
3304 static inline uint16_t
3305 EPWM_getTimeBasePeriod(uint32_t base)
3306 {
3307 //
3308 // Read from TBPRD bit
3309 //
3310 return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
3311 }
3312
3313 //*****************************************************************************
3314 //
3375 //
3376 //*****************************************************************************
3377 static inline void
3378 EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink,
3379 EPWM_LinkComponent linkComp)
3380 {
3381 uint32_t registerOffset;
3382 uint32_t linkComponent = (uint32_t)linkComp;
3383
3384 if((linkComponent == (uint32_t)EPWM_LINK_DBRED) || (linkComponent == (uint32_t)EPWM_LINK_DBFED))
3385 {
3386 registerOffset = base + CSL_EPWM_EPWMXLINK2;
3387 linkComponent = (uint32_t)linkComponent - 1U;
3388 }
3389 else if (linkComponent == (uint32_t)EPWM_LINK_XLOAD)
3390 {
3391 registerOffset = base + CSL_EPWM_EPWMXLINKXLOAD;
3392 linkComponent = (uint32_t)linkComponent - 2U;
3393 }
3394 else
3395 {
3396 registerOffset = base + CSL_EPWM_EPWMXLINK;
3397 }
3398
3399 //
3400 // Configure EPWM links
3401 //
3402 HW_WR_REG32(registerOffset,
3403 ((uint32_t)(HW_RD_REG32(registerOffset) &
3404 ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComponent)) |
3405 ((uint32_t)epwmLink << linkComponent)));
3406 }
3407
3408 //*****************************************************************************
3409 //
3436 //
3437 //*****************************************************************************
3438 static inline void
3439 EPWM_setCounterCompareShadowLoadMode(uint32_t base,
3440 EPWM_CounterCompareModule compModule,
3441 EPWM_CounterCompareLoadMode loadMode)
3442 {
3443 uint16_t syncModeOffset;
3444 uint16_t loadModeOffset;
3445 uint16_t shadowModeOffset;
3446 uint32_t registerOffset;
3447
3448 if((compModule == EPWM_COUNTER_COMPARE_A) ||
3449 (compModule == EPWM_COUNTER_COMPARE_C))
3450 {
3451 syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
3452 loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
3453 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3454 }
3455 else
3456 {
3457 syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
3458 loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
3459 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3460 }
3461
3462 //
3463 // Get the register offset. CSL_EPWM_CMPCTL for A&B or
3464 // CSL_EPWM_CMPCTL2 for C&D
3465 //
3466 if((compModule == EPWM_COUNTER_COMPARE_A) ||
3467 (compModule == EPWM_COUNTER_COMPARE_B))
3468 {
3469 registerOffset = base + CSL_EPWM_CMPCTL;
3470 }
3471 else
3472 {
3473 registerOffset = base + CSL_EPWM_CMPCTL2;
3474 }
3475
3476 //
3477 // Set the appropriate sync and load mode bits and also enable shadow
3478 // load mode. Shadow to active load can also be frozen.
3479 //
3480 HW_WR_REG16(registerOffset,
3481 ((HW_RD_REG16(registerOffset) &
3482 ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
3483 (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
3484 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
3485 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3486 (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
3487 loadModeOffset))));
3488 }
3489
3490 //*****************************************************************************
3491 //
3506 //
3507 //*****************************************************************************
3508 static inline void
3509 EPWM_disableCounterCompareShadowLoadMode(uint32_t base,
3510 EPWM_CounterCompareModule compModule)
3511 {
3512 uint16_t shadowModeOffset;
3513 uint32_t registerOffset;
3514
3515 if((compModule == EPWM_COUNTER_COMPARE_A) ||
3516 (compModule == EPWM_COUNTER_COMPARE_C))
3517 {
3518 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3519 }
3520 else
3521 {
3522 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3523 }
3524
3525 //
3526 // Get the register offset. CSL_EPWM_CMPCTL for A&B or
3527 // CSL_EPWM_CMPCTL2 for C&D
3528 //
3529 if((compModule == EPWM_COUNTER_COMPARE_A) ||
3530 (compModule == EPWM_COUNTER_COMPARE_B))
3531 {
3532 registerOffset = base + CSL_EPWM_CMPCTL;
3533 }
3534 else
3535 {
3536 registerOffset = base + CSL_EPWM_CMPCTL2;
3537 }
3538
3539 //
3540 // Disable shadow load mode.
3541 //
3542 HW_WR_REG16(registerOffset,
3543 (HW_RD_REG16(registerOffset) |
3544 ((uint32_t)CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
3545 }
3546
3547 //*****************************************************************************
3548 //
3564 //
3565 //*****************************************************************************
3566 static inline void
3567 EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule,
3568 uint16_t compCount)
3569 {
3570 uint32_t registerOffset;
3571
3572 //
3573 // Get the register offset for the Counter compare
3574 //
3575 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3576
3577 //
3578 // Write to the counter compare registers.
3579 //
3580 if((compModule == EPWM_COUNTER_COMPARE_A) ||
3581 (compModule == EPWM_COUNTER_COMPARE_B))
3582 {
3583 //
3584 // Write to COMPA or COMPB bits
3585 //
3586 HW_WR_REG16(registerOffset + 0x2U, compCount);
3587 }
3588 else
3589 {
3590 //
3591 // Write to COMPC or COMPD bits
3592 //
3593 HW_WR_REG16(registerOffset, compCount);
3594 }
3595 }
3596 //*****************************************************************************
3597 //
3607 //
3608 //*****************************************************************************
3609 static inline void
3610 EPWM_setCounterCompareValue_opt_cmpA(uint32_t base, uint16_t compCount)
3611 {
3612 HW_WR_REG16(base + CSL_EPWM_CMPA + 0x2U, compCount);
3613 }
3614
3615 //*****************************************************************************
3616 //
3626 //
3627 //*****************************************************************************
3628 static inline void
3629 EPWM_setCounterCompareValue_opt_cmpB(uint32_t base, uint16_t compCount)
3630 {
3631 HW_WR_REG16(base + CSL_EPWM_CMPB + 0x2U, compCount);
3632 }
3633
3634 //*****************************************************************************
3635 //
3645 //
3646 //*****************************************************************************
3647 static inline void
3648 EPWM_setCounterCompareValue_opt_cmpC(uint32_t base, uint16_t compCount)
3649 {
3650 HW_WR_REG16(base + CSL_EPWM_CMPC, compCount);
3651 }
3652
3653 //*****************************************************************************
3654 //
3664 //
3665 //*****************************************************************************
3666 static inline void
3667 EPWM_setCounterCompareValue_opt_cmpD(uint32_t base, uint16_t compCount)
3668 {
3669 HW_WR_REG16(base + CSL_EPWM_CMPD, compCount);
3670 }
3671
3672 //*****************************************************************************
3673 //
3687 //
3688 //*****************************************************************************
3689 static inline uint16_t
3690 EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
3691 {
3692 uint32_t registerOffset;
3693 uint16_t compCount;
3694
3695 //
3696 // Get the register offset for the Counter compare
3697 //
3698 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3699
3700 //
3701 // Read from the counter compare registers.
3702 //
3703 if((compModule == EPWM_COUNTER_COMPARE_A) ||
3704 (compModule == EPWM_COUNTER_COMPARE_B))
3705 {
3706 //
3707 // Read COMPA or COMPB bits
3708 //
3709 compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
3710 (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
3711 CSL_EPWM_CMPA_CMPA_SHIFT);
3712 }
3713 else
3714 {
3715 //
3716 // Read COMPC or COMPD bits
3717 //
3718 compCount = HW_RD_REG16(registerOffset);
3719 }
3720 return(compCount);
3721 }
3722
3723 //*****************************************************************************
3724 //
3737 //
3738 //*****************************************************************************
3739 static inline bool
3740 EPWM_getCounterCompareShadowStatus(uint32_t base,
3741 EPWM_CounterCompareModule compModule)
3742 {
3743 //
3744 // Check the arguments
3745 //
3746 DebugP_assert((compModule == EPWM_COUNTER_COMPARE_A) ||
3747 (compModule == EPWM_COUNTER_COMPARE_B));
3748
3749 //
3750 // Read the value of SHDWAFULL or SHDWBFULL bit
3751 //
3752 return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
3753 ((((uint16_t)compModule >> 1U) & 0x2U) +
3754 CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
3755 0x1U) == 0x1U) ? true:false);
3756 }
3757
3758 //
3759 // Action Qualifier module related APIs
3760 //
3761 //*****************************************************************************
3762 //
3789 //
3790 //*****************************************************************************
3791 static inline void
3792 EPWM_setActionQualifierShadowLoadMode(uint32_t base,
3793 EPWM_ActionQualifierModule aqModule,
3794 EPWM_ActionQualifierLoadMode loadMode)
3795 {
3796 uint16_t syncModeOffset;
3797 uint16_t shadowModeOffset;
3798
3799 syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
3800 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3801
3802 //
3803 // Set the appropriate sync and load mode bits and also enable shadow
3804 // load mode. Shadow to active load can also be frozen.
3805 //
3806
3807 HW_WR_REG16((base + CSL_EPWM_AQCTL),
3808 ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3809 (~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
3810 (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
3811 (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)) |
3812 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3813 (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
3814 (uint16_t)aqModule))));
3815 }
3816
3817 //*****************************************************************************
3818 //
3831 //
3832 //*****************************************************************************
3833 static inline void
3834 EPWM_disableActionQualifierShadowLoadMode(uint32_t base,
3835 EPWM_ActionQualifierModule aqModule)
3836 {
3837 uint16_t shadowModeOffset;
3838
3839 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3840
3841 //
3842 // Disable shadow load mode. Action qualifier is loaded on
3843 // immediate mode only.
3844 //
3845 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3846 (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3847 ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
3848 }
3849
3850 //*****************************************************************************
3851 //
3870 //
3871 //*****************************************************************************
3872 static inline void
3873 EPWM_setActionQualifierT1TriggerSource(uint32_t base,
3874 EPWM_ActionQualifierTriggerSource trigger)
3875 {
3876 //
3877 // Set T1 trigger source
3878 //
3879 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3880 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3881 (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
3882 ((uint16_t)trigger)));
3883 }
3884
3885 //*****************************************************************************
3886 //
3905 //
3906 //*****************************************************************************
3907 static inline void
3908 EPWM_setActionQualifierT2TriggerSource(uint32_t base,
3909 EPWM_ActionQualifierTriggerSource trigger)
3910 {
3911 //
3912 // Set T2 trigger source
3913 //
3914 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3915 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3916 (~(uint16_t)CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
3917 (uint16_t)((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
3918 }
3919
3920 //*****************************************************************************
3921 //
3960 //
3961 //*****************************************************************************
3962 static inline void
3963 EPWM_setActionQualifierAction(uint32_t base,
3964 EPWM_ActionQualifierOutputModule epwmOutput,
3965 EPWM_ActionQualifierOutput output,
3966 EPWM_ActionQualifierOutputEvent event)
3967 {
3968 uint32_t registerOffset;
3969 uint32_t registerTOffset;
3970
3971 //
3972 // Get the register offset
3973 //
3974 registerOffset = (uint32_t)CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3975 registerTOffset = (uint32_t)CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3976
3977 //
3978 // If the event occurs on T1 or T2 events
3979 //
3980 if(((uint16_t)event & 0x1U) == 1U)
3981 {
3982 //
3983 // Write to T1U,T1D,T2U or T2D of AQCTLA2 register
3984 //
3985 HW_WR_REG16(base + registerTOffset,
3986 ((HW_RD_REG16(base + registerTOffset) &
3987 ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
3988 ((uint16_t)output << ((uint16_t)event - 1U))));
3989 }
3990 else
3991 {
3992 //
3993 // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register
3994 //
3995 HW_WR_REG16(base + registerOffset,
3996 ((HW_RD_REG16(base + registerOffset) &
3997 ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
3998 ((uint16_t)output << (uint16_t)event)));
3999 }
4000 }
4001
4002 //*****************************************************************************
4003 //
4084 //
4085 //*****************************************************************************
4086 static inline void
4087 EPWM_setActionQualifierActionComplete(uint32_t base,
4088 EPWM_ActionQualifierOutputModule epwmOutput,
4089 EPWM_ActionQualifierEventAction action)
4090 {
4091 uint32_t registerOffset;
4092
4093 //
4094 // Get the register offset
4095 //
4096 registerOffset = (uint32_t)CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
4097
4098 //
4099 // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register
4100 //
4101 HW_WR_REG16(base + registerOffset, action);
4102 }
4103
4104 //*****************************************************************************
4105 //
4163 //
4164 //*****************************************************************************
4165 static inline void
4166 EPWM_setAdditionalActionQualifierActionComplete(uint32_t base,
4167 EPWM_ActionQualifierOutputModule epwmOutput,
4168 EPWM_AdditionalActionQualifierEventAction action)
4169 {
4170 uint32_t registerTOffset;
4171
4172 //
4173 // Get the register offset
4174 //
4175 registerTOffset = (uint32_t)CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
4176
4177 //
4178 // Write to T1U, T1D, T2U or T2D of AQCTLA2 register
4179 //
4180 HW_WR_REG16(base + registerTOffset, action);
4181 }
4182
4183 //*****************************************************************************
4184 //
4203 //
4204 //*****************************************************************************
4205 static inline void
4206 EPWM_setActionQualifierContSWForceShadowMode(uint32_t base,
4207 EPWM_ActionQualifierContForce mode)
4208 {
4209 //
4210 // Set the Action qualifier software action reload mode.
4211 // Write to RLDCSF bit
4212 //
4213 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4214 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4215 ~(uint16_t)CSL_EPWM_AQSFRC_RLDCSF_MASK) |
4216 (uint16_t)((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
4217 }
4218
4219 //*****************************************************************************
4220 //
4239 //
4240 //*****************************************************************************
4241 static inline void
4242 EPWM_setActionQualifierContSWForceAction(uint32_t base,
4243 EPWM_ActionQualifierOutputModule epwmOutput,
4244 EPWM_ActionQualifierSWOutput output)
4245 {
4246 //
4247 // Initiate a continuous software forced output
4248 //
4249 if(epwmOutput == EPWM_AQ_OUTPUT_A)
4250 {
4251 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4252 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4253 ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
4254 ((uint16_t)output)));
4255 }
4256 else
4257 {
4258 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4259 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4260 ~(uint16_t)CSL_EPWM_AQCSFRC_CSFB_MASK) |
4261 (uint16_t)((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
4262 }
4263 }
4264
4265 //*****************************************************************************
4266 //
4296 //*****************************************************************************
4297 static inline void
4298 EPWM_setActionQualifierContSWForceAction_opt_outputs(uint32_t base, uint8_t outputAB)
4299 {
4300 HW_WR_REG16(base + CSL_EPWM_AQCSFRC, outputAB);
4301 }
4302
4303 //*****************************************************************************
4304 //
4325 //
4326 //*****************************************************************************
4327 static inline void
4328 EPWM_setActionQualifierSWAction(uint32_t base,
4329 EPWM_ActionQualifierOutputModule epwmOutput,
4330 EPWM_ActionQualifierOutput output)
4331 {
4332 //
4333 // Set the one time software forced action
4334 //
4335 if(epwmOutput == EPWM_AQ_OUTPUT_A)
4336 {
4337 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4338 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4339 ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
4340 ((uint16_t)output)));
4341 }
4342 else
4343 {
4344 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4345 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4346 ~(uint16_t)CSL_EPWM_AQSFRC_ACTSFB_MASK) |
4347 (uint16_t)((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
4348 }
4349 }
4350
4351 //*****************************************************************************
4352 //
4365 //
4366 //*****************************************************************************
4367 static inline void
4368 EPWM_forceActionQualifierSWAction(uint32_t base,
4369 EPWM_ActionQualifierOutputModule epwmOutput)
4370 {
4371 //
4372 // Initiate a software forced event
4373 //
4374 if(epwmOutput == EPWM_AQ_OUTPUT_A)
4375 {
4376 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4377 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4378 CSL_EPWM_AQSFRC_OTSFA_MASK));
4379 }
4380 else
4381 {
4382 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4383 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4384 CSL_EPWM_AQSFRC_OTSFB_MASK));
4385 }
4386 }
4387
4388 //
4389 // Dead Band Module related APIs
4390 //
4391 //*****************************************************************************
4392 //
4411 //
4412 //*****************************************************************************
4413 static inline void
4414 EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output,
4415 bool enableSwapMode)
4416 {
4417 uint16_t mask;
4418
4419 mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
4420
4421 if(enableSwapMode)
4422 {
4423 //
4424 // Set the appropriate outswap bit to swap output
4425 //
4426 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4427 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4428 }
4429 else
4430 {
4431 //
4432 // Clear the appropriate outswap bit to disable output swap
4433 //
4434 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4435 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4436 }
4437 }
4438
4439 //*****************************************************************************
4440 //
4459 //
4460 //*****************************************************************************
4461 static inline void
4462 EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode,
4463 bool enableDelayMode)
4464 {
4465 uint16_t mask;
4466
4467 mask = (uint16_t)1U << ((uint16_t)((uint16_t)delayMode + (uint16_t)CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
4468
4469 if(enableDelayMode)
4470 {
4471 //
4472 // Set the appropriate outmode bit to enable Dead Band delay
4473 //
4474 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4475 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4476 }
4477 else
4478 {
4479 //
4480 // Clear the appropriate outswap bit to disable output swap
4481 //
4482 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4483 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4484 }
4485 }
4486
4487 //*****************************************************************************
4488 //
4506 //
4507 //*****************************************************************************
4508 static inline void
4509 EPWM_setDeadBandDelayPolarity(uint32_t base,
4510 EPWM_DeadBandDelayMode delayMode,
4511 EPWM_DeadBandPolarity polarity)
4512 {
4513 uint16_t shift;
4514
4515 shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
4516
4517 //
4518 // Set the appropriate polsel bits for dead band polarity
4519 //
4520 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4521 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
4522 ((uint16_t)polarity << shift)));
4523 }
4524
4525 //*****************************************************************************
4526 //
4540 //
4541 //*****************************************************************************
4542 static inline void
4543 EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
4544 {
4545 //
4546 // Check the arguments
4547 //
4548 DebugP_assert((input == EPWM_DB_INPUT_EPWMA) ||
4549 (input == EPWM_DB_INPUT_EPWMB));
4550
4551 //
4552 // Set the Rising Edge Delay input
4553 //
4554 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4555 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4556 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
4557 ((uint32_t)input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
4558 }
4559
4560 //*****************************************************************************
4561 //
4578 //
4579 //*****************************************************************************
4580 static inline void
4581 EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
4582 {
4583 //
4584 // Check the arguments
4585 //
4586 DebugP_assert((input == EPWM_DB_INPUT_EPWMA) ||
4587 (input == EPWM_DB_INPUT_EPWMB) ||
4588 (input == EPWM_DB_INPUT_DB_RED));
4589
4590 if(input == EPWM_DB_INPUT_DB_RED)
4591 {
4592 //
4593 // Set the Falling Edge Delay input
4594 //
4595 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4596 (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
4597 CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4598 }
4599 else
4600 {
4601 //
4602 // Set the Falling Edge Delay input
4603 //
4604 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4605 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4606 ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4607
4608 //
4609 // Set the Rising Edge Delay input
4610 //
4611 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4612 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4613 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
4614 ((uint32_t)input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
4615 }
4616 }
4617
4618 //*****************************************************************************
4619 //
4635 //
4636 //*****************************************************************************
4637 static inline void
4638 EPWM_setDeadBandControlShadowLoadMode(uint32_t base,
4639 EPWM_DeadBandControlLoadMode loadMode)
4640 {
4641 //
4642 // Enable the shadow mode and setup the load event
4643 //
4644 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4645 ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4646 ~(uint16_t)CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
4647 (uint16_t)(CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
4648 }
4649
4650 //*****************************************************************************
4651 //
4660 //
4661 //*****************************************************************************
4662 static inline void
4663 EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
4664 {
4665 //
4666 // Disable the shadow load mode. Only immediate load mode only.
4667 //
4668 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4669 (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4670 ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
4671 }
4672
4673 //*****************************************************************************
4674 //
4689 //
4690 //*****************************************************************************
4691 static inline void
4692 EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base,
4693 EPWM_RisingEdgeDelayLoadMode loadMode)
4694 {
4695 //
4696 // Enable the shadow mode. Set-up the load mode
4697 //
4698 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4699 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4700 ~(uint16_t)CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
4701 (uint16_t)(CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
4702 (uint16_t)((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
4703
4704 }
4705
4706 //*****************************************************************************
4707 //
4715 //
4716 //*****************************************************************************
4717 static inline void
4718 EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
4719 {
4720 //
4721 // Disable the shadow mode.
4722 //
4723 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4724 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4725 ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
4726 }
4727
4728 //*****************************************************************************
4729 //
4744 //
4745 //*****************************************************************************
4746 static inline void
4747 EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base,
4748 EPWM_FallingEdgeDelayLoadMode loadMode)
4749 {
4750 //
4751 // Enable the shadow mode. Setup the load mode.
4752 //
4753 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4754 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4755 ~(uint16_t)CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
4756 (uint16_t)(CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
4757 (uint16_t)((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
4758 }
4759
4760 //*****************************************************************************
4761 //
4770 //
4771 //*****************************************************************************
4772 static inline void
4773 EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
4774 {
4775 //
4776 // Disable the shadow mode.
4777 //
4778 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4779 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4780 ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
4781 }
4782
4783 //*****************************************************************************
4784 //
4799 //
4800 //*****************************************************************************
4801 static inline void
4802 EPWM_setDeadBandCounterClock(uint32_t base,
4803 EPWM_DeadBandClockMode clockMode)
4804 {
4805 //
4806 // Set the DB clock mode
4807 //
4808 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4809 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4810 ~(uint16_t)CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
4811 (uint16_t)((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
4812 }
4813
4814 //*****************************************************************************
4815 //
4825 //
4826 //*****************************************************************************
4827 static inline void
4828 EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
4829 {
4830 //
4831 // Check the arguments
4832 //
4833 DebugP_assert(redCount <= CSL_EPWM_DBRED_DBRED_MAX);
4834
4835 //
4836 // Set the RED (Rising Edge Delay) count
4837 //
4838 HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
4839 }
4840
4841 //*****************************************************************************
4842 //
4852 //
4853 //*****************************************************************************
4854 static inline void
4855 EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
4856 {
4857 //
4858 // Check the arguments
4859 //
4860 DebugP_assert(fedCount <= CSL_EPWM_DBFED_DBFED_MAX);
4861
4862 //
4863 // Set the FED (Falling Edge Delay) count
4864 //
4865 HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
4866 }
4867
4868 //
4869 // Chopper module related APIs
4870 //
4871 //*****************************************************************************
4872 //
4880 //
4881 //*****************************************************************************
4882 static inline void
4883 EPWM_enableChopper(uint32_t base)
4884 {
4885 //
4886 // Set CHPEN bit. Enable Chopper
4887 //
4888 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4889 (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
4890 }
4891
4892 //*****************************************************************************
4893 //
4901 //
4902 //*****************************************************************************
4903 static inline void
4904 EPWM_disableChopper(uint32_t base)
4905 {
4906 //
4907 // Clear CHPEN bit. Disable Chopper
4908 //
4909 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4910 (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
4911 }
4912
4913 //*****************************************************************************
4914 //
4926 //
4927 //*****************************************************************************
4928 static inline void
4929 EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
4930 {
4931 //
4932 // Check the arguments
4933 //
4934 DebugP_assert(dutyCycleCount < CSL_EPWM_PCCTL_CHPDUTY_MAX);
4935
4936 //
4937 // Set the chopper duty cycle
4938 //
4939 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4940 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
4941 ((uint32_t)dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
4942
4943 }
4944
4945 //*****************************************************************************
4946 //
4958 //
4959 //*****************************************************************************
4960 static inline void
4961 EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
4962 {
4963 //
4964 // Check the arguments
4965 //
4966 DebugP_assert(freqDiv <= CSL_EPWM_PCCTL_CHPFREQ_MAX);
4967
4968 //
4969 // Set the chopper clock
4970 //
4971 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4972 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4973 ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
4974 ((uint32_t)freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
4975 }
4976
4977 //*****************************************************************************
4978 //
4990 //
4991 //*****************************************************************************
4992 static inline void
4993 EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
4994 {
4995 //
4996 // Check the arguments
4997 //
4998 DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
4999
5000 //
5001 // Set the chopper clock
5002 //
5003 HW_WR_REG16(base + CSL_EPWM_PCCTL,
5004 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
5005 ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
5006 ((uint32_t)firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
5007 }
5008
5009 //
5010 // Trip Zone module related APIs
5011 //
5012 //*****************************************************************************
5013 //
5043 //
5044 //*****************************************************************************
5045 static inline void
5046 EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
5047 {
5048 //
5049 // Set the trip zone bits
5050 //
5051 HW_WR_REG32(base + CSL_EPWM_TZSEL,
5052 (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
5053 }
5054
5055 //*****************************************************************************
5056 //
5086 //
5087 //*****************************************************************************
5088 static inline void
5089 EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
5090 {
5091 //
5092 // Clear the trip zone bits
5093 //
5094 HW_WR_REG32(base + CSL_EPWM_TZSEL,
5095 (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
5096 }
5097
5098 //*****************************************************************************
5099 //
5115 //
5116 //*****************************************************************************
5117 static inline void
5118 EPWM_enableTripZone2Signals(uint32_t base, uint16_t tzSignal)
5119 {
5120 //
5121 // Set the trip zone bits
5122 //
5123 HW_WR_REG16(base + CSL_EPWM_TZSEL2,
5124 (HW_RD_REG16(base + CSL_EPWM_TZSEL2) | tzSignal));
5125 }
5126
5127 //*****************************************************************************
5128 //
5144 //
5145 //*****************************************************************************
5146 static inline void
5147 EPWM_disableTripZone2Signals(uint32_t base, uint16_t tzSignal)
5148 {
5149 //
5150 // Clear the trip zone bits
5151 //
5152 HW_WR_REG16(base + CSL_EPWM_TZSEL2,
5153 (HW_RD_REG16(base + CSL_EPWM_TZSEL2) & ~tzSignal));
5154 }
5155
5156 //*****************************************************************************
5157 //
5186 //
5187 //*****************************************************************************
5188 static inline void
5189 EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base,
5190 EPWM_TripZoneDigitalCompareOutput dcType,
5191 EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
5192 {
5193 //
5194 // Set Digital Compare Events conditions that cause a Digital Compare trip
5195 //
5196 HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
5197 ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
5198 ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
5199 ((uint16_t)dcEvent << (uint16_t)dcType)));
5200 }
5201
5202 //*****************************************************************************
5203 //
5213 //
5214 //*****************************************************************************
5215 static inline void
5216 EPWM_enableTripZoneAdvAction(uint32_t base)
5217 {
5218 //
5219 // Enable Advanced feature. Set ETZE bit
5220 //
5221 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5222 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5223 }
5224
5225 //*****************************************************************************
5226 //
5234 //
5235 //*****************************************************************************
5236 static inline void
5237 EPWM_disableTripZoneAdvAction(uint32_t base)
5238 {
5239 //
5240 // Disable Advanced feature. clear ETZE bit
5241 //
5242 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5243 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
5244 }
5245
5246 //*****************************************************************************
5247 //
5276 //
5277 //*****************************************************************************
5278 static inline void
5279 EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent,
5280 EPWM_TripZoneAction tzAction)
5281 {
5282 //
5283 // Set the Action for Trip Zone events
5284 //
5285 HW_WR_REG16(base + CSL_EPWM_TZCTL,
5286 ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
5287 ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
5288 ((uint16_t)tzAction << (uint16_t)tzEvent)));
5289 }
5290
5291 //*****************************************************************************
5292 //
5327 //
5328 //*****************************************************************************
5329 static inline void
5330 EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent,
5331 EPWM_TripZoneAdvancedAction tzAdvAction)
5332 {
5333 //
5334 // Set the Advanced Action for Trip Zone events
5335 //
5336 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5337 ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
5338 ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
5339 ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
5340
5341 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5342 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5343 }
5344
5345 //*****************************************************************************
5346 //
5378 //
5379 //*****************************************************************************
5380 static inline void
5381 EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base,
5382 EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
5383 EPWM_TripZoneAdvancedAction tzAdvDCAction)
5384 {
5385 //
5386 // Set the Advanced Action for Trip Zone events
5387 //
5388 HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
5389 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
5390 ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5391 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5392
5393 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5394 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5395 }
5396
5397 //*****************************************************************************
5398 //
5430 //
5431 //*****************************************************************************
5432 static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base,
5433 EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
5434 EPWM_TripZoneAdvancedAction tzAdvDCAction)
5435 {
5436 //
5437 // Set the Advanced Action for Trip Zone events
5438 //
5439 HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
5440 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
5441 ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5442 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5443
5444 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5445 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5446 }
5447
5448 //*****************************************************************************
5449 //
5469 //
5470 //*****************************************************************************
5471 static inline void
5472 EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
5473 {
5474 //
5475 // Check the arguments
5476 //
5477 DebugP_assert((tzInterrupt <= 0x80U));
5478
5479 //
5480 // Enable Trip zone interrupts
5481 //
5482 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5483 (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
5484 }
5485
5486 //*****************************************************************************
5487 //
5507 //
5508 //***************************************************************************
5509 static inline void
5510 EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
5511 {
5512 //
5513 // Check the arguments
5514 //
5515 DebugP_assert((tzInterrupt > 0U) && (tzInterrupt <= 0x80U));
5516
5517 //
5518 // Disable Trip zone interrupts
5519 //
5520 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5521 (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
5522 }
5523
5524 //*****************************************************************************
5525 //
5543 //
5544 //***************************************************************************
5545 static inline uint16_t
5546 EPWM_getTripZoneFlagStatus(uint32_t base)
5547 {
5548 //
5549 // Return the Trip zone flag status
5550 //
5551 return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
5552 }
5553
5554 //*****************************************************************************
5555 //
5575 //
5576 //***************************************************************************
5577 static inline uint16_t
5578 EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
5579 {
5580 //
5581 // Return the Cycle By Cycle Trip zone flag status
5582 //
5583 return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
5584 }
5585
5586 //*****************************************************************************
5587 //
5605 //
5606 //***************************************************************************
5607 static inline uint16_t
5608 EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
5609 {
5610 //
5611 // Return the One Shot Trip zone flag status
5612 //
5613 return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
5614 }
5615
5616 //*****************************************************************************
5617 //
5634 //
5635 //**************************************************************************
5636 static inline void
5637 EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base,
5638 EPWM_CycleByCycleTripZoneClearMode clearEvent)
5639 {
5640 //
5641 // Set the Cycle by Cycle Trip Latch mode
5642 //
5643 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5644 ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
5645 ~(uint16_t)CSL_EPWM_TZCLR_CBCPULSE_MASK) |
5646 (uint16_t)((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
5647 }
5648
5649 //*****************************************************************************
5650 //
5671 //
5672 //***************************************************************************
5673 static inline void
5674 EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
5675 {
5676 //
5677 // Check the arguments
5678 //
5679 DebugP_assert((tzFlags <= 0x80U) && (tzFlags >= 0x1U));
5680
5681 //
5682 // Clear Trip zone event flag
5683 //
5684 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5685 (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
5686 }
5687
5688 //*****************************************************************************
5689 //
5709 //
5710 //***************************************************************************
5711 static inline void
5712 EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
5713 {
5714 //
5715 // Check the arguments
5716 //
5717 DebugP_assert(tzCBCFlags < 0x200U);
5718
5719 //
5720 // Clear the Cycle By Cycle Trip zone flag
5721 //
5722 HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
5723 (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
5724 }
5725
5726 //*****************************************************************************
5727 //
5746 //
5747 //***************************************************************************
5748 static inline void
5749 EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
5750 {
5751 //
5752 // Check the arguments
5753 //
5754 DebugP_assert(tzOSTFlags < 0x200U);
5755
5756 //
5757 // Clear the One Shot Trip zone flag
5758 //
5759 HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
5760 (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
5761 }
5762
5763 //*****************************************************************************
5764 //
5781 //
5782 //***************************************************************************
5783 static inline void
5784 EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
5785 {
5786 //
5787 // Check the arguments
5788 //
5789 DebugP_assert((tzForceEvent & 0xFF01U)== 0U);
5790
5791 //
5792 // Force a Trip Zone event
5793 //
5794 HW_WR_REG16(base + CSL_EPWM_TZFRC,
5795 (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
5796 }
5797
5798 //*****************************************************************************
5799 //
5813 //
5814 //***************************************************************************
5815 static inline void
5816 EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
5817 {
5818 //
5819 // Enable the Trip Zone signals as output
5820 //
5821 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5822 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
5823 }
5824
5825 //*****************************************************************************
5826 //
5840 //
5841 //***************************************************************************
5842 static inline void
5843 EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
5844 {
5845 //
5846 // Disable the Trip Zone signals as output
5847 //
5848 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5849 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
5850 }
5851
5852 //
5853 // Event Trigger related APIs
5854 //
5855 //*****************************************************************************
5856 //
5864 //
5865 //*****************************************************************************
5866 static inline void
5867 EPWM_enableInterrupt(uint32_t base)
5868 {
5869 //
5870 // Enable ePWM interrupt
5871 //
5872 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5873 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
5874 }
5875
5876 //*****************************************************************************
5877 //
5885 //
5886 //*****************************************************************************
5887 static inline void
5888 EPWM_disableInterrupt(uint32_t base)
5889 {
5890 //
5891 // Disable ePWM interrupt
5892 //
5893 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5894 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
5895 }
5896
5897 //*****************************************************************************
5898 //
5921 //
5922 //*****************************************************************************
5923 static inline void
5924 EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource,
5925 uint16_t mixedSource)
5926 {
5927 uint16_t intSource;
5928
5929 //
5930 // Check the arguments
5931 //
5932 DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
5933 (interruptSource == 10U) || (interruptSource == 12U) ||
5934 (interruptSource == 14U));
5935
5936 if((interruptSource == EPWM_INT_TBCTR_U_CMPC) ||
5937 (interruptSource == EPWM_INT_TBCTR_U_CMPD) ||
5938 (interruptSource == EPWM_INT_TBCTR_D_CMPC) ||
5939 (interruptSource == EPWM_INT_TBCTR_D_CMPD))
5940 {
5941 //
5942 // Shift the interrupt source by 1
5943 //
5944 intSource = interruptSource >> 1U;
5945
5946 //
5947 // Enable events based on comp C or comp D
5948 //
5949 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5950 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5951 CSL_EPWM_ETSEL_INTSELCMP_MASK));
5952 }
5953 else if((interruptSource == EPWM_INT_TBCTR_U_CMPA) ||
5954 (interruptSource == EPWM_INT_TBCTR_U_CMPB) ||
5955 (interruptSource == EPWM_INT_TBCTR_D_CMPA) ||
5956 (interruptSource == EPWM_INT_TBCTR_D_CMPB))
5957 {
5958 intSource = interruptSource;
5959
5960 //
5961 // Enable events based on comp A or comp B
5962 //
5963 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5964 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5965 ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
5966 }
5967 else if(interruptSource == EPWM_INT_TBCTR_ETINTMIX)
5968 {
5969 intSource = interruptSource;
5970
5971 //
5972 // Enable mixed events
5973 //
5974 HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
5975 }
5976 else
5977 {
5978 intSource = interruptSource;
5979 }
5980
5981 //
5982 // Set the interrupt source
5983 //
5984 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5985 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5986 ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
5987 }
5988
5989 //*****************************************************************************
5990 //
6001 //
6002 //*****************************************************************************
6003 static inline void
6004 EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
6005 {
6006 //
6007 // Check the arguments
6008 //
6009 DebugP_assert(eventCount <= CSL_EPWM_ETINTPS_INTPRD2_MAX);
6010
6011 //
6012 // Enable advanced feature of interrupt every up to 15 events
6013 //
6014 HW_WR_REG16(base + CSL_EPWM_ETPS,
6015 (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
6016
6017 HW_WR_REG16(base + CSL_EPWM_ETINTPS,
6018 ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
6019 ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
6020 }
6021
6022 //*****************************************************************************
6023 //
6033 //
6034 //*****************************************************************************
6035 static inline bool
6036 EPWM_getEventTriggerInterruptStatus(uint32_t base)
6037 {
6038 //
6039 // Return INT bit of ETFLG register
6040 //
6041 return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
6042 0x1U) ? true : false);
6043 }
6044
6045 //*****************************************************************************
6046 //
6054 //
6055 //*****************************************************************************
6056 static inline void
6057 EPWM_clearEventTriggerInterruptFlag(uint32_t base)
6058 {
6059 //
6060 // Clear INT bit of ETCLR register
6061 //
6062 HW_WR_REG16(base + CSL_EPWM_ETCLR, (CSL_EPWM_ETCLR_INT_MASK));
6063 }
6064
6065 //*****************************************************************************
6066 //
6077 //
6078 //*****************************************************************************
6079 static inline void
6080 EPWM_enableInterruptEventCountInit(uint32_t base)
6081 {
6082 //
6083 // Enable interrupt event count initializing/loading
6084 //
6085 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6086 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6087 CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
6088 }
6089
6090 //*****************************************************************************
6091 //
6100 //
6101 //*****************************************************************************
6102 static inline void
6103 EPWM_disableInterruptEventCountInit(uint32_t base)
6104 {
6105 //
6106 // Disable interrupt event count initializing/loading
6107 //
6108 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6109 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6110 ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
6111 }
6112
6113 //*****************************************************************************
6114 //
6126 //
6127 //*****************************************************************************
6128 static inline void
6129 EPWM_forceInterruptEventCountInit(uint32_t base)
6130 {
6131 //
6132 // Load the Interrupt Event counter value
6133 //
6134 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6135 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6136 CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
6137 }
6138
6139 //*****************************************************************************
6140 //
6151 //
6152 //*****************************************************************************
6153 static inline void
6154 EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
6155 {
6156 //
6157 // Check the arguments
6158 //
6159 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
6160
6161 //
6162 // Set the Pre-interrupt event count
6163 //
6164 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6165 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6166 ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
6167 (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
6168 }
6169
6170 //*****************************************************************************
6171 //
6179 //
6180 //*****************************************************************************
6181 static inline uint16_t
6182 EPWM_getInterruptEventCount(uint32_t base)
6183 {
6184 //
6185 // Return the interrupt event count
6186 //
6187 return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
6188 CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
6189 CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
6190 }
6191
6192 //*****************************************************************************
6193 //
6201 //
6202 //*****************************************************************************
6203 static inline void
6204 EPWM_forceEventTriggerInterrupt(uint32_t base)
6205 {
6206 //
6207 // Set INT bit of ETFRC register
6208 //
6209 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6210 (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
6211 }
6212
6213 //
6214 // ADC SOC configuration related APIs
6215 //
6216 //*****************************************************************************
6217 //
6229 //
6230 //*****************************************************************************
6231 static inline void
6232 EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
6233 {
6234 //
6235 // Enable an SOC
6236 //
6237 if(adcSOCType == EPWM_SOC_A)
6238 {
6239 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6240 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
6241 }
6242 else
6243 {
6244 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6245 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
6246 }
6247 }
6248
6249 //*****************************************************************************
6250 //
6262 //
6263 //*****************************************************************************
6264 static inline void
6265 EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
6266 {
6267 //
6268 // Disable an SOC
6269 //
6270 if(adcSOCType == EPWM_SOC_A)
6271 {
6272 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6273 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
6274 }
6275 else
6276 {
6277 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6278 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
6279 }
6280 }
6281
6282 //*****************************************************************************
6283 //
6312 //
6313 //*****************************************************************************
6314 static inline void
6315 EPWM_setADCTriggerSource(uint32_t base,
6316 EPWM_ADCStartOfConversionType adcSOCType,
6317 EPWM_ADCStartOfConversionSource socSource,
6318 uint16_t mixedSource)
6319 {
6320 uint16_t source;
6321
6322 if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
6323 (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
6324 (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
6325 (socSource == EPWM_SOC_TBCTR_D_CMPD))
6326 {
6327 source = (uint16_t)socSource >> 1U;
6328 }
6329 else
6330 {
6331 source = (uint16_t)socSource;
6332 }
6333
6334 if(adcSOCType == EPWM_SOC_A)
6335 {
6336 //
6337 // Set the SOC source
6338 //
6339 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6340 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6341 ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
6342 ((uint32_t)source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
6343
6344 //
6345 // Enable the comparator selection
6346 //
6347 if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
6348 (socSource == EPWM_SOC_TBCTR_U_CMPB) ||
6349 (socSource == EPWM_SOC_TBCTR_D_CMPA) ||
6350 (socSource == EPWM_SOC_TBCTR_D_CMPB))
6351 {
6352 //
6353 // Enable events based on comp A or comp B
6354 //
6355 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6356 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6357 ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6358 }
6359 else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
6360 (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
6361 (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
6362 (socSource == EPWM_SOC_TBCTR_D_CMPD))
6363 {
6364 //
6365 // Enable events based on comp C or comp D
6366 //
6367 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6368 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6369 CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6370 }
6371 else if(socSource == EPWM_SOC_TBCTR_MIXED_EVENT)
6372 {
6373 //
6374 // Enable mixed events
6375 //
6376 HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
6377 }
6378 else
6379 {
6380 //
6381 // No action required for the other socSource options
6382 //
6383 }
6384 }
6385 else
6386 {
6387 //
6388 // Enable the comparator selection
6389 //
6390 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6391 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6392 ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
6393 ((uint32_t)source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
6394
6395 //
6396 // Enable the comparator selection
6397 //
6398 if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
6399 (socSource == EPWM_SOC_TBCTR_U_CMPB) ||
6400 (socSource == EPWM_SOC_TBCTR_D_CMPA) ||
6401 (socSource == EPWM_SOC_TBCTR_D_CMPB))
6402 {
6403 //
6404 // Enable events based on comp A or comp B
6405 //
6406 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6407 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6408 ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6409 }
6410 else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
6411 (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
6412 (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
6413 (socSource == EPWM_SOC_TBCTR_D_CMPD))
6414 {
6415 //
6416 // Enable events based on comp C or comp D
6417 //
6418 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6419 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6420 CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6421 }
6422 else if(socSource == EPWM_SOC_TBCTR_MIXED_EVENT)
6423 {
6424 //
6425 // Enable mixed events
6426 //
6427 HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
6428 }
6429 else
6430 {
6431 //
6432 // No action required for the other socSource options
6433 //
6434 }
6435 }
6436 }
6437
6438 //*****************************************************************************
6439 //
6459 //
6460 //*****************************************************************************
6461 static inline void
6462 EPWM_setADCTriggerEventPrescale(uint32_t base,
6463 EPWM_ADCStartOfConversionType adcSOCType,
6464 uint16_t preScaleCount)
6465 {
6466 //
6467 // Check the arguments
6468 //
6469 DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
6470
6471 //
6472 // Enable advanced feature of SOC every up to 15 events
6473 //
6474 HW_WR_REG16(base + CSL_EPWM_ETPS,
6475 (HW_RD_REG16(base + CSL_EPWM_ETPS) |
6476 CSL_EPWM_ETPS_SOCPSSEL_MASK));
6477
6478 if(adcSOCType == EPWM_SOC_A)
6479 {
6480 //
6481 // Set the count for SOC A
6482 //
6483 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6484 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6485 ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
6486 preScaleCount));
6487 }
6488 else
6489 {
6490 //
6491 // Set the count for SOC B
6492 //
6493 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6494 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6495 ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
6496 ((uint32_t)preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
6497 }
6498 }
6499
6500 //*****************************************************************************
6501 //
6514 //
6515 //*****************************************************************************
6516 static inline bool
6517 EPWM_getADCTriggerFlagStatus(uint32_t base,
6518 EPWM_ADCStartOfConversionType adcSOCType)
6519 {
6520 //
6521 // Return the SOC A/ B status
6522 //
6523 return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
6524 ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
6525 0x1U) == 0x1U) ? true : false);
6526 }
6527
6528 //*****************************************************************************
6529 //
6541 //
6542 //*****************************************************************************
6543 static inline void
6544 EPWM_clearADCTriggerFlag(uint32_t base,
6545 EPWM_ADCStartOfConversionType adcSOCType)
6546 {
6547 //
6548 // Clear SOC A/B bit of ETCLR register
6549 //
6550 HW_WR_REG16(base + CSL_EPWM_ETCLR,
6551 (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
6552 ((uint16_t)1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT))));
6553 }
6554
6555 //*****************************************************************************
6556 //
6572 //
6573 //*****************************************************************************
6574 static inline void
6575 EPWM_enableADCTriggerEventCountInit(uint32_t base,
6576 EPWM_ADCStartOfConversionType adcSOCType)
6577 {
6578 //
6579 // Enable SOC event count initializing/loading
6580 //
6581 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6582 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | ((uint16_t)1U <<
6583 ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6584 }
6585
6586 //*****************************************************************************
6587 //
6602 //
6603 //*****************************************************************************
6604 static inline void
6605 EPWM_disableADCTriggerEventCountInit(uint32_t base,
6606 EPWM_ADCStartOfConversionType adcSOCType)
6607 {
6608 //
6609 // Disable SOC event count initializing/loading
6610 //
6611 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6612 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6613 ~(1U << ((uint16_t)adcSOCType +
6614 CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6615 }
6616
6617 //*****************************************************************************
6618 //
6631 //
6632 //*****************************************************************************
6633 static inline void
6634 EPWM_forceADCTriggerEventCountInit(uint32_t base,
6635 EPWM_ADCStartOfConversionType adcSOCType)
6636 {
6637 //
6638 // Load the Interrupt Event counter value
6639 //
6640 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6641 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6642 ((uint16_t)1U << ((uint16_t)adcSOCType +
6643 CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT))));
6644 }
6645
6646 //*****************************************************************************
6647 //
6661 //
6662 //*****************************************************************************
6663 static inline void
6664 EPWM_setADCTriggerEventCountInitValue(uint32_t base,
6665 EPWM_ADCStartOfConversionType adcSOCType,
6666 uint16_t eventCount)
6667 {
6668 //
6669 // Check the arguments
6670 //
6671 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
6672
6673 //
6674 // Set the ADC Trigger event count
6675 //
6676 if(adcSOCType == EPWM_SOC_A)
6677 {
6678 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6679 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6680 ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
6681 (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
6682 }
6683 else
6684 {
6685 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6686 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6687 ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
6688 ((uint32_t)eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
6689 }
6690 }
6691
6692 //*****************************************************************************
6693 //
6705 //
6706 //*****************************************************************************
6707 static inline uint16_t
6708 EPWM_getADCTriggerEventCount(uint32_t base,
6709 EPWM_ADCStartOfConversionType adcSOCType)
6710 {
6711 uint16_t eventCount;
6712
6713 //
6714 // Return the SOC event count
6715 //
6716 if(adcSOCType == EPWM_SOC_A)
6717 {
6718 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6719 CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
6720 CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
6721 }
6722 else
6723 {
6724 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6725 CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
6726 CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
6727 }
6728
6729 return(eventCount);
6730 }
6731
6732 //*****************************************************************************
6733 //
6745 //
6746 //*****************************************************************************
6747 static inline void
6748 EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
6749 {
6750 //
6751 // Set SOC A/B bit of ETFRC register
6752 //
6753 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6754 (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
6755 ((uint16_t)1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT))));
6756 }
6757
6758 //
6759 // Digital Compare module related APIs
6760 //
6761 //*****************************************************************************
6762 //
6784 //
6785 //*****************************************************************************
6786 static inline void
6787 EPWM_selectDigitalCompareTripInput(uint32_t base,
6788 EPWM_DigitalCompareTripInput tripSource,
6789 EPWM_DigitalCompareType dcType)
6790 {
6791 //
6792 // Set the DC trip input
6793 //
6794 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
6795 ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
6796 ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
6797 ((uint16_t)dcType << 2U))) |
6798 ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
6799 }
6800
6801 //
6802 // DCFILT
6803 //
6804 //*****************************************************************************
6805 //
6813 //
6814 //*****************************************************************************
6815 static inline void
6816 EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
6817 {
6818 //
6819 // Enable DC filter blanking window
6820 //
6821 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6822 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
6823 }
6824
6825 //*****************************************************************************
6826 //
6834 //
6835 //*****************************************************************************
6836 static inline void
6837 EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
6838 {
6839 //
6840 // Disable DC filter blanking window
6841 //
6842 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6843 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
6844 }
6845
6846 //*****************************************************************************
6847 //
6856 //
6857 //*****************************************************************************
6858 static inline void
6859 EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
6860 {
6861 //
6862 // Enable DC window inverse mode.
6863 //
6864 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6865 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
6866 }
6867
6868 //*****************************************************************************
6869 //
6877 //
6878 //*****************************************************************************
6879 static inline void
6880 EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
6881 {
6882 //
6883 // Disable DC window inverse mode.
6884 //
6885 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6886 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6887 ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
6888 }
6889
6890 //*****************************************************************************
6891 //
6907 //
6908 //*****************************************************************************
6909 static inline void
6910 EPWM_setDigitalCompareBlankingEvent(uint32_t base,
6911 EPWM_DigitalCompareBlankingPulse blankingPulse,
6912 uint16_t mixedSource)
6913 {
6914 if(blankingPulse == EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX)
6915 {
6916 //
6917 // Enable mixed events
6918 //
6919 HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
6920 }
6921
6922 //
6923 // Set DC blanking event
6924 //
6925 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6926 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6927 ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
6928 ((uint16_t)((uint32_t)blankingPulse <<
6929 CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
6930 }
6931
6932 //*****************************************************************************
6933 //
6948 //
6949 //*****************************************************************************
6950 static inline void
6951 EPWM_setDigitalCompareFilterInput(uint32_t base,
6952 EPWM_DigitalCompareFilterInput filterInput)
6953 {
6954 //
6955 // Set the signal source that will be filtered
6956 //
6957 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6958 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
6959 ((uint16_t)filterInput)));
6960 }
6961
6962 //
6963 // DC Edge Filter
6964 //
6965 //*****************************************************************************
6966 //
6975 //
6976 //*****************************************************************************
6977 static inline void
6978 EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
6979 {
6980 //
6981 // Enable DC Edge Filter
6982 //
6983 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6984 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
6985 CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6986 }
6987
6988 //*****************************************************************************
6989 //
6997 //
6998 //*****************************************************************************
6999 static inline void
7000 EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
7001 {
7002 //
7003 // Disable DC Edge Filter
7004 //
7005 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
7006 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7007 ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
7008 }
7009
7010 //*****************************************************************************
7011 //
7024 //
7025 //*****************************************************************************
7026 static inline void
7027 EPWM_setDigitalCompareEdgeFilterMode(uint32_t base,
7028 EPWM_DigitalCompareEdgeFilterMode edgeMode)
7029 {
7030 //
7031 // Set DC Edge filter mode
7032 //
7033 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
7034 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7035 ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
7036 ((uint32_t)edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
7037 }
7038
7039 //*****************************************************************************
7040 //
7058 //
7059 //*****************************************************************************
7060 static inline void
7061 EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base,
7062 EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
7063 {
7064 //
7065 // Set DC Edge filter edge count
7066 //
7067 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
7068 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7069 ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
7070 ((uint32_t)edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
7071 }
7072
7073 //*****************************************************************************
7074 //
7083 //
7084 //*****************************************************************************
7085 static inline uint16_t
7086 EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
7087 {
7088 //
7089 // Return configured DC edge filter edge count
7090 //
7091 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7092 CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
7093 CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
7094 }
7095
7096 //*****************************************************************************
7097 //
7106 //
7107 //*****************************************************************************
7108 static inline uint16_t
7109 EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
7110 {
7111 //
7112 // Return captured edge count by DC Edge filter
7113 //
7114 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7115 CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
7116 CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
7117 }
7118
7119 //*****************************************************************************
7120 //
7131 //
7132 //*****************************************************************************
7133 static inline void
7134 EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
7135 {
7136 //
7137 // Set the blanking window offset in TBCLK counts
7138 //
7139 HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
7140 }
7141
7142 //*****************************************************************************
7143 //
7153 //
7154 //*****************************************************************************
7155 static inline void
7156 EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
7157 {
7158 //
7159 // Set the blanking window length in TBCLK counts
7160 //
7161 HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
7162 }
7163
7164 //*****************************************************************************
7165 //
7173 //
7174 //*****************************************************************************
7175 static inline uint16_t
7176 EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
7177 {
7178 //
7179 // Return the Blanking Window Offset count
7180 //
7181 return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
7182 }
7183
7184 //*****************************************************************************
7185 //
7193 //
7194 //*****************************************************************************
7195 static inline uint16_t
7196 EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
7197 {
7198 //
7199 // Return the Blanking Window Length count
7200 //
7201 return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
7202 }
7203
7204 //*****************************************************************************
7205 //
7231 //
7232 //*****************************************************************************
7233 static inline void
7234 EPWM_setDigitalCompareEventSource(uint32_t base,
7235 EPWM_DigitalCompareModule dcModule,
7236 EPWM_DigitalCompareEvent dcEvent,
7237 EPWM_DigitalCompareEventSource dcEventSource)
7238 {
7239 uint32_t registerOffset;
7240
7241 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7242
7243 //
7244 // Set the DC event 1 source source
7245 //
7246 if(dcEvent == EPWM_DC_EVENT_1)
7247 {
7248 HW_WR_REG16(base + registerOffset,
7249 ((HW_RD_REG16(base + registerOffset) &
7250 ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
7251 (uint16_t)dcEventSource));
7252 }
7253 else
7254 {
7255 HW_WR_REG16(base + registerOffset,
7256 ((HW_RD_REG16(base + registerOffset) &
7257 ~(uint16_t)CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
7258 (uint16_t)((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
7259 }
7260 }
7261
7262 //*****************************************************************************
7263 //
7286 //
7287 //*****************************************************************************
7288 static inline void
7289 EPWM_setDigitalCompareEventSyncMode(uint32_t base,
7290 EPWM_DigitalCompareModule dcModule,
7291 EPWM_DigitalCompareEvent dcEvent,
7292 EPWM_DigitalCompareSyncMode syncMode)
7293 {
7294 uint32_t registerOffset;
7295
7296 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7297
7298 //
7299 // Set the DC event sync mode
7300 //
7301 if(dcEvent == EPWM_DC_EVENT_1)
7302 {
7303 HW_WR_REG16(base + registerOffset,
7304 ((HW_RD_REG16(base + registerOffset) &
7305 ~(uint16_t)CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
7306 (uint16_t)((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
7307 }
7308 else
7309 {
7310 HW_WR_REG16(base + registerOffset,
7311 ((HW_RD_REG16(base + registerOffset) &
7312 ~(uint16_t)CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
7313 (uint16_t)((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
7314 }
7315 }
7316
7317 //*****************************************************************************
7318 //
7331 //
7332 //*****************************************************************************
7333 static inline void
7334 EPWM_enableDigitalCompareADCTrigger(uint32_t base,
7335 EPWM_DigitalCompareModule dcModule)
7336 {
7337 uint32_t registerOffset;
7338
7339 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7340
7341 //
7342 // Enable Digital Compare start of conversion generation
7343 //
7344 HW_WR_REG16(base + registerOffset,
7345 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7346 }
7347
7348 //*****************************************************************************
7349 //
7362 //
7363 //*****************************************************************************
7364 static inline void
7365 EPWM_disableDigitalCompareADCTrigger(uint32_t base,
7366 EPWM_DigitalCompareModule dcModule)
7367 {
7368 uint32_t registerOffset;
7369
7370 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7371
7372 //
7373 // Disable Digital Compare start of conversion generation
7374 //
7375 HW_WR_REG16(base + registerOffset,
7376 (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7377 }
7378
7379 //*****************************************************************************
7380 //
7393 //
7394 //*****************************************************************************
7395 static inline void
7396 EPWM_enableDigitalCompareSyncEvent(uint32_t base,
7397 EPWM_DigitalCompareModule dcModule)
7398 {
7399 uint32_t registerOffset;
7400
7401 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7402
7403 //
7404 // Enable Digital Compare sync out pulse generation
7405 //
7406 HW_WR_REG16(base + registerOffset,
7407 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7408 }
7409
7410 //*****************************************************************************
7411 //
7424 //
7425 //*****************************************************************************
7426 static inline void
7427 EPWM_disableDigitalCompareSyncEvent(uint32_t base,
7428 EPWM_DigitalCompareModule dcModule)
7429 {
7430 uint32_t registerOffset;
7431
7432 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7433
7434 //
7435 // Disable Digital Compare sync out pulse generation
7436 //
7437 HW_WR_REG16(base + registerOffset,
7438 (HW_RD_REG16(base + registerOffset) &
7439 ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7440 }
7441
7442 //*****************************************************************************
7443 //
7464 //
7465 //*****************************************************************************
7466 static inline void
7467 EPWM_setDigitalCompareCBCLatchMode(uint32_t base,
7468 EPWM_DigitalCompareModule dcModule,
7469 EPWM_DigitalCompareEvent dcEvent,
7470 EPWM_DigitalCompareCBCLatchMode latchMode)
7471 {
7472 uint32_t registerOffset;
7473
7474 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7475
7476 //
7477 // Set the DC CBC Latch Mode
7478 //
7479 if(dcEvent == EPWM_DC_EVENT_1)
7480 {
7481 HW_WR_REG16(base + registerOffset,
7482 ((HW_RD_REG16(base + registerOffset) &
7483 ~(uint16_t)CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
7484 (uint16_t)((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
7485 }
7486 else
7487 {
7488 HW_WR_REG16(base + registerOffset,
7489 ((HW_RD_REG16(base + registerOffset) &
7490 ~(uint16_t)CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
7491 (uint16_t)((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
7492 }
7493 }
7494
7495 //*****************************************************************************
7496 //
7522 //
7523 //*****************************************************************************
7524 static inline void
7525 EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base,
7526 EPWM_DigitalCompareModule dcModule,
7527 EPWM_DigitalCompareEvent dcEvent,
7528 EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
7529 {
7530 uint32_t registerOffset;
7531
7532 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7533
7534 //
7535 // Set the DC CBC Latch Clear Event
7536 //
7537 if(dcEvent == EPWM_DC_EVENT_1)
7538 {
7539 HW_WR_REG16(base + registerOffset,
7540 ((HW_RD_REG16(base + registerOffset) &
7541 ~(uint16_t)CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
7542 (uint16_t)((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
7543 }
7544 else
7545 {
7546 HW_WR_REG16(base + registerOffset,
7547 ((HW_RD_REG16(base + registerOffset) &
7548 ~(uint16_t)CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
7549 (uint16_t)((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
7550 }
7551 }
7552
7553 //*****************************************************************************
7554 //
7574 //
7575 //*****************************************************************************
7576 static inline bool
7577 EPWM_getDigitalCompareCBCLatchStatus(uint32_t base,
7578 EPWM_DigitalCompareModule dcModule,
7579 EPWM_DigitalCompareEvent dcEvent)
7580 {
7581 uint32_t registerOffset;
7582 uint16_t status;
7583
7584 registerOffset = CSL_EPWM_DCACTL + (uint32_t)((uint16_t)dcModule * (uint32_t)EPWM_DCxCTL_STEP);
7585
7586 //
7587 // Get DC CBC Latch Clear Event
7588 //
7589 if(dcEvent == EPWM_DC_EVENT_1)
7590 {
7591 status = HW_RD_REG16(base + registerOffset) &
7592 CSL_EPWM_DCACTL_EVT1LAT_MASK;
7593 }
7594 else
7595 {
7596 status = HW_RD_REG16(base + registerOffset) &
7597 CSL_EPWM_DCACTL_EVT2LAT_MASK;
7598 }
7599
7600 return(status != 0U);
7601 }
7602
7603 //
7604 // DC capture mode
7605 //
7606 //*****************************************************************************
7607 //
7615 //
7616 //*****************************************************************************
7617 static inline void
7618 EPWM_enableDigitalCompareCounterCapture(uint32_t base)
7619 {
7620 //
7621 // Enable Time base counter capture
7622 //
7623 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7624 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
7625 }
7626
7627 //*****************************************************************************
7628 //
7636 //
7637 //*****************************************************************************
7638 static inline void
7639 EPWM_disableDigitalCompareCounterCapture(uint32_t base)
7640 {
7641 //
7642 // Disable Time base counter capture
7643 //
7644 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7645 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7646 ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
7647 }
7648
7649 //*****************************************************************************
7650 //
7662 //
7663 //*****************************************************************************
7664 static inline void
7665 EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
7666 {
7667 if(enableShadowMode)
7668 {
7669 //
7670 // Enable DC counter shadow mode
7671 //
7672 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7673 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7674 ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7675 }
7676 else
7677 {
7678 //
7679 // Disable DC counter shadow mode
7680 //
7681 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7682 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
7683 CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7684 }
7685 }
7686
7687 //*****************************************************************************
7688 //
7699 //
7700 //*****************************************************************************
7701 static inline bool
7702 EPWM_getDigitalCompareCaptureStatus(uint32_t base)
7703 {
7704 //
7705 // Return the DC compare status
7706 //
7707 return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7708 CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
7709 }
7710
7711 //*****************************************************************************
7712 //
7722 //
7723 //*****************************************************************************
7724 static inline uint16_t
7725 EPWM_getDigitalCompareCaptureCount(uint32_t base)
7726 {
7727 //
7728 // Return the DC Time Base Counter Capture count value
7729 //
7730 return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
7731 }
7732
7733 //*****************************************************************************
7734 //
7752 //
7753 //*****************************************************************************
7754 static inline void
7755 EPWM_enableDigitalCompareTripCombinationInput(uint32_t base,
7756 uint16_t tripInput,
7757 EPWM_DigitalCompareType dcType)
7758 {
7759 uint32_t registerOffset;
7760
7761 //
7762 // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
7763 // offset with respect to DCAHTRIPSEL
7764 //
7765 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7766 (uint32_t)((uint16_t)dcType * (uint32_t)EPWM_DCxxTRIPSEL);
7767
7768 //
7769 // Set the DC trip input
7770 //
7771 HW_WR_REG16(base + registerOffset,
7772 (HW_RD_REG16(base + registerOffset) | tripInput));
7773
7774 //
7775 // Enable the combination input
7776 //
7777 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
7778 (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
7779 ((uint16_t)CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
7780 }
7781
7782 //*****************************************************************************
7783 //
7801 //
7802 //*****************************************************************************
7803 static inline void
7804 EPWM_disableDigitalCompareTripCombinationInput(uint32_t base,
7805 uint16_t tripInput,
7806 EPWM_DigitalCompareType dcType)
7807 {
7808 uint32_t registerOffset;
7809
7810 //
7811 // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
7812 // offset with respect to DCAHTRIPSEL
7813 //
7814 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7815 (uint32_t)((uint16_t)dcType * (uint32_t)EPWM_DCxxTRIPSEL);
7816
7817 //
7818 // Set the DC trip input
7819 //
7820 HW_WR_REG16(base + registerOffset,
7821 (HW_RD_REG16(base + registerOffset) & ~tripInput));
7822 }
7823
7824 //
7825 // Event capture mode
7826 //
7827 //*****************************************************************************
7828 //
7837 //
7838 //*****************************************************************************
7839 static inline void
7840 EPWM_enableCaptureInEvent(uint32_t base)
7841 {
7842
7843 //
7844 // Enables CAPIN.sync signal
7845 //
7846 HW_WR_REG16(
7847 base + CSL_EPWM_CAPCTL,
7848 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) | CSL_EPWM_CAPCTL_SRCSEL_MASK)
7849 );
7850 }
7851
7852 //*****************************************************************************
7853 //
7862 //
7863 //*****************************************************************************
7864 static inline void
7865 EPWM_disableCaptureInEvent(uint32_t base)
7866 {
7867 //
7868 // Disables CAPIN.sync signal
7869 //
7870 HW_WR_REG16(
7871 base + CSL_EPWM_CAPCTL,
7872 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_SRCSEL_MASK))
7873 );
7874 }
7875
7876 //*****************************************************************************
7877 //
7891 //
7892 //*****************************************************************************
7893 static inline void
7894 EPWM_configCaptureGateInputPolarity(uint32_t base,
7895 uint8_t polSel)
7896 {
7897 //
7898 // Configures polarity for CAPGATE
7899 //
7900 HW_WR_REG16(
7901 base + CSL_EPWM_CAPCTL,
7902 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_CAPGATEPOL_MASK)) |
7903 ((uint16_t)polSel << CSL_EPWM_CAPCTL_CAPGATEPOL_SHIFT));
7904 }
7905
7906 //*****************************************************************************
7907 //
7919 //
7920 //*****************************************************************************
7921 static inline void
7922 EPWM_invertCaptureInputPolarity(uint32_t base,
7923 uint8_t polSel)
7924 {
7925 //
7926 // Configures polarity for Capture Input
7927 //
7928 HW_WR_REG16(
7929 base + CSL_EPWM_CAPCTL,
7930 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_CAPINPOL_MASK)) |
7931 ((uint16_t)polSel << CSL_EPWM_CAPCTL_CAPINPOL_SHIFT));
7932 }
7933
7934 //*****************************************************************************
7935 //
7943 //
7944 //*****************************************************************************
7945 static inline void
7946 EPWM_enableIndependentPulseLogic(uint32_t base)
7947 {
7948 //
7949 // Configures polarity for Capture Input
7950 //
7951 HW_WR_REG16(
7952 base + CSL_EPWM_CAPCTL,
7953 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_PULSECTL_MASK)) |
7954 (((uint16_t)1U) << CSL_EPWM_CAPCTL_PULSECTL_SHIFT));
7955 }
7956
7957 //*****************************************************************************
7958 //
7967 //
7968 //*****************************************************************************
7969 static inline void
7970 EPWM_disableIndependentPulseLogic(uint32_t base)
7971 {
7972 //
7973 // Configures polarity for Capture Input
7974 //
7975 HW_WR_REG16(
7976 base + CSL_EPWM_CAPCTL,
7977 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) | (CSL_EPWM_CAPCTL_PULSECTL_MASK)) &
7978 (~(((uint16_t)1U) << CSL_EPWM_CAPCTL_PULSECTL_SHIFT)));
7979 }
7980
7981 //*****************************************************************************
7982 //
7990 //
7991 //*****************************************************************************
7992 static inline void
7993 EPWM_forceCaptureEventLoad(uint32_t base)
7994 {
7995 //
7996 // Force a Capture Event Load
7997 //
7998 HW_WR_REG16(
7999 base + CSL_EPWM_CAPCTL,
8000 HW_RD_REG16(base + CSL_EPWM_CAPCTL) | (CSL_EPWM_CAPCTL_FRCLOAD_MASK));
8001 }
8002
8003 //*****************************************************************************
8004 //
8024 //
8025 //*****************************************************************************
8026 static inline void
8027 EPWM_selectCaptureTripInput(uint32_t base,
8028 EPWM_DigitalCompareTripInput tripSource,
8029 uint8_t dcType)
8030 {
8031 //
8032 // Set the Capture trip input
8033 //
8034 if(dcType == EPWM_CAPTURE_GATE)
8035 {
8036 HW_WR_REG16(
8037 base + CSL_EPWM_CAPTRIPSEL,
8038 (HW_RD_REG16(base + CSL_EPWM_CAPTRIPSEL) & (~CSL_EPWM_CAPTRIPSEL_CAPGATECOMPSEL_MASK)) |
8039 (((uint16_t)tripSource) << CSL_EPWM_CAPTRIPSEL_CAPGATECOMPSEL_SHIFT));
8040 }
8041 else
8042 {
8043 HW_WR_REG16(
8044 base + CSL_EPWM_CAPTRIPSEL,
8045 (HW_RD_REG16(base + CSL_EPWM_CAPTRIPSEL) & (~CSL_EPWM_CAPTRIPSEL_CAPINCOMPSEL_MASK)) |
8046 (((uint16_t)tripSource) << CSL_EPWM_CAPTRIPSEL_CAPINCOMPSEL_SHIFT));
8047 }
8048 }
8049
8050
8051 //*****************************************************************************
8052 //
8068 //
8069 //*****************************************************************************
8070 static inline void
8071 EPWM_enableCaptureTripCombinationInput(uint32_t base,
8072 uint16_t tripInput,
8073 uint8_t dcType)
8074 {
8075
8076 if(dcType == EPWM_CAPTURE_GATE)
8077 {
8078 //
8079 // Set the capture trip input
8080 //
8081 HW_WR_REG16(
8082 base + CSL_EPWM_CAPGATETRIPSEL, tripInput);
8083
8084 }
8085 else
8086 {
8087 //
8088 // Set the capture trip input
8089 //
8090 HW_WR_REG16(
8091 base + CSL_EPWM_CAPINTRIPSEL, tripInput);
8092 }
8093 //
8094 // Enable the combination input
8095 //
8096 EPWM_DigitalCompareTripInput combinational_input = EPWM_DC_TRIP_COMBINATION;
8097 if(tripInput != 0U)
8098 {
8099 EPWM_selectCaptureTripInput(base, combinational_input, dcType);
8100 }
8101 }
8102
8103 //*****************************************************************************
8104 //
8120 //
8121 //*****************************************************************************
8122 static inline void
8123 EPWM_disableCaptureTripCombinationInput(uint32_t base,
8124 uint16_t tripInput,
8125 uint8_t dcType)
8126 {
8127 if(dcType == EPWM_CAPTURE_GATE)
8128 {
8129 //
8130 // Set the capture trip input
8131 //
8132 HW_WR_REG16(
8133 base + CSL_EPWM_CAPGATETRIPSEL,
8134 HW_RD_REG16(base + CSL_EPWM_CAPGATETRIPSEL) & (~tripInput));
8135
8136 }
8137 else
8138 {
8139 //
8140 // Set the capture trip input
8141 //
8142 HW_WR_REG16(
8143 base + CSL_EPWM_CAPINTRIPSEL,
8144 HW_RD_REG16(base + CSL_EPWM_CAPGATETRIPSEL) & (~tripInput));
8145 }
8146 }
8147
8148 //
8149 // Valley switching
8150 //
8151 //*****************************************************************************
8152 //
8160 //
8161 //*****************************************************************************
8162 static inline void
8163 EPWM_enableValleyCapture(uint32_t base)
8164 {
8165 //
8166 // Set VCAPE bit
8167 //
8168 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8169 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
8170 }
8171
8172 //*****************************************************************************
8173 //
8181 //
8182 //*****************************************************************************
8183 static inline void
8184 EPWM_disableValleyCapture(uint32_t base)
8185 {
8186 //
8187 // Clear VCAPE bit
8188 //
8189 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8190 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
8191 }
8192
8193 //*****************************************************************************
8194 //
8206 //
8207 //*****************************************************************************
8208 static inline void
8209 EPWM_startValleyCapture(uint32_t base)
8210 {
8211 //
8212 // Set VCAPSTART bit
8213 //
8214 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8215 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
8216 CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
8217 }
8218
8219 //*****************************************************************************
8220 //
8232 //
8233 //*****************************************************************************
8234 static inline void
8235 EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
8236 {
8237 //
8238 // Write to TRIGSEL bits
8239 //
8240 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8241 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8242 ~(uint16_t)CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
8243 (uint16_t)((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
8244 }
8245
8246 //*****************************************************************************
8247 //
8264 //
8265 //*****************************************************************************
8266 static inline void
8267 EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount,
8268 uint16_t stopCount)
8269 {
8270 //
8271 // Check the arguments
8272 //
8273 DebugP_assert((startCount < 16U) && (stopCount < 16U));
8274
8275 //
8276 // Write to STARTEDGE and STOPEDGE bits
8277 //
8278 HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
8279 ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8280 ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
8281 ((uint32_t)startCount | ((uint32_t)stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
8282 }
8283
8284 //*****************************************************************************
8285 //
8293 //
8294 //*****************************************************************************
8295 static inline void
8296 EPWM_enableValleyHWDelay(uint32_t base)
8297 {
8298 //
8299 // Set EDGEFILTDLYSEL bit
8300 //
8301 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8302 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
8303 CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
8304 }
8305
8306 //*****************************************************************************
8307 //
8315 //
8316 //*****************************************************************************
8317 static inline void
8318 EPWM_disableValleyHWDelay(uint32_t base)
8319 {
8320 //
8321 // Clear EDGEFILTDLYSEL bit
8322 //
8323 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8324 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8325 ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
8326 }
8327
8328 //*****************************************************************************
8329 //
8338 //
8339 //*****************************************************************************
8340 static inline void
8341 EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
8342 {
8343 //
8344 // Write to SWVDELVAL bits
8345 //
8346 HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
8347 }
8348
8349 //*****************************************************************************
8350 //
8359 //
8360 //*****************************************************************************
8361 static inline void
8362 EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
8363 {
8364 //
8365 // Write to VDELAYDIV bits
8366 //
8367 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8368 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8369 ~(uint16_t)CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
8370 (uint16_t)((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
8371 }
8372
8373 //*****************************************************************************
8374 //
8387 //
8388 //*****************************************************************************
8389 static inline bool
8390 EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
8391 {
8392 bool status = true;
8393 if(edge == EPWM_VALLEY_COUNT_START_EDGE)
8394 {
8395 if((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) & CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK)
8396 == CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK)
8397 {
8398 status = true;
8399 }
8400 else
8401 {
8402 status = false;
8403 }
8404 }
8405 else
8406 {
8407 if((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8408 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
8409 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK)
8410 {
8411 status = true;
8412 }
8413 else
8414 {
8415 status = false;
8416 }
8417 }
8418
8419 return status;
8420 }
8421 //*****************************************************************************
8422 //
8433 //
8434 //*****************************************************************************
8435 static inline uint16_t
8436 EPWM_getValleyCount(uint32_t base)
8437 {
8438 //
8439 // Read VCNTVAL register
8440 //
8441 return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
8442 }
8443
8444 //*****************************************************************************
8445 //
8453 //
8454 //*****************************************************************************
8455 static inline uint16_t
8456 EPWM_getValleyHWDelay(uint32_t base)
8457 {
8458 //
8459 // Read HWVDELVAL register
8460 //
8461 return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
8462 }
8463
8464 //*****************************************************************************
8465 //
8475 //
8476 //*****************************************************************************
8477 static inline void
8478 EPWM_enableGlobalLoad(uint32_t base)
8479 {
8480 //
8481 // Shadow to active load is controlled globally
8482 //
8483 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8484 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
8485 }
8486
8487 //*****************************************************************************
8488 //
8497 //
8498 //*****************************************************************************
8499 static inline void
8500 EPWM_disableGlobalLoad(uint32_t base)
8501 {
8502 //
8503 // Shadow to active load is controlled individually
8504 //
8505 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8506 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
8507 }
8508
8509 //*****************************************************************************
8510 //
8536 //
8537 //*****************************************************************************
8538 static inline void
8539 EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
8540 {
8541 //
8542 // Set the Global shadow to active load pulse
8543 //
8544 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8545 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
8546 ~(uint16_t)CSL_EPWM_GLDCTL_GLDMODE_MASK) |
8547 (uint16_t)((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
8548 }
8549
8550 //*****************************************************************************
8551 //
8563 //
8564 //*****************************************************************************
8565 static inline void
8566 EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
8567 {
8568 //
8569 // Check the arguments
8570 //
8571 DebugP_assert(prescalePulseCount < 8U);
8572
8573 //
8574 // Set the number of counts that have to occur before
8575 // a load strobe is issued
8576 //
8577 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8578 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
8579 ((uint32_t)prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
8580 }
8581
8582 //*****************************************************************************
8583 //
8593 //
8594 //*****************************************************************************
8595 static inline uint16_t
8596 EPWM_getGlobalLoadEventCount(uint32_t base)
8597 {
8598 //
8599 // Return the number of events that have occurred
8600 //
8601 return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
8602 CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
8603 }
8604
8605 //*****************************************************************************
8606 //
8616 //
8617 //*****************************************************************************
8618 static inline void
8619 EPWM_disableGlobalLoadOneShotMode(uint32_t base)
8620 {
8621 //
8622 // Enable global continuous shadow to active load
8623 //
8624 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8625 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
8626 ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8627 }
8628
8629 //*****************************************************************************
8630 //
8640 //
8641 //*****************************************************************************
8642 static inline void
8643 EPWM_enableGlobalLoadOneShotMode(uint32_t base)
8644 {
8645 //
8646 // Enable global continuous shadow to active load
8647 //
8648 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8649 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8650 }
8651
8652 //*****************************************************************************
8653 //
8663 //
8664 //*****************************************************************************
8665 static inline void
8666 EPWM_setGlobalLoadOneShotLatch(uint32_t base)
8667 {
8668 //
8669 // Set a one shot Global shadow load pulse.
8670 //
8671 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8672 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
8673 }
8674
8675 //*****************************************************************************
8676 //
8685 //
8686 //*****************************************************************************
8687 static inline void
8688 EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
8689 {
8690 //
8691 // Force a Software Global shadow load pulse
8692 //
8693 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8694 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
8695 }
8696
8697 //*****************************************************************************
8698 //
8720 //
8721 //*****************************************************************************
8722 static inline void
8723 EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
8724 {
8725 //
8726 // Check the arguments
8727 //
8728 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8729
8730 //
8731 // The register specified by loadRegister is loaded globally
8732 //
8733 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8734 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
8735 }
8736
8737 //*****************************************************************************
8738 //
8761 //
8762 //*****************************************************************************
8763 static inline void
8764 EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
8765 {
8766 //
8767 // Check the arguments
8768 //
8769 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8770
8771 //
8772 // The register specified by loadRegister is loaded by individual
8773 // register configuration setting
8774 //
8775 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8776 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
8777 }
8778
8779 //*****************************************************************************
8780 //
8790 //
8791 //*****************************************************************************
8792 static inline void
8793 EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
8794 {
8795 //
8796 // Write the Key to EPWMLOCK register
8797 //
8798 HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
8799 ((uint32_t)EPWM_LOCK_KEY | ((uint32_t)registerGroup)));
8800 }
8801
8802 //
8803 // Minimum Dead Band
8804 //
8805 //*****************************************************************************
8806 //
8815 //
8816 //*****************************************************************************
8817 static inline void
8818 EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
8819 {
8820 if(block == EPWM_MINDB_BLOCK_A)
8821 {
8822 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8823 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8824 CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8825 }
8826 else
8827 {
8828 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8829 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8830 CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8831 }
8832 }
8833
8834 //*****************************************************************************
8835 //
8844 //
8845 //*****************************************************************************
8846 static inline void
8847 EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
8848 {
8849 if(block == EPWM_MINDB_BLOCK_A)
8850 {
8851 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8852 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8853 ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8854 }
8855 else
8856 {
8857 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8858 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8859 ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8860 }
8861 }
8862
8863 //*****************************************************************************
8864 //
8875 //
8876 //*****************************************************************************
8877 static inline void
8878 EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block,
8879 uint32_t invert)
8880 {
8881 if(block == EPWM_MINDB_BLOCK_A)
8882 {
8883 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8884 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8885 ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
8886 (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
8887 }
8888 else
8889 {
8890 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8891 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8892 ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
8893 (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
8894 }
8895 }
8896
8897 //*****************************************************************************
8898 //
8910 //
8911 //*****************************************************************************
8912 static inline void
8913 EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block,
8914 uint32_t referenceSignal)
8915 {
8916 if(block == EPWM_MINDB_BLOCK_A)
8917 {
8918 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8919 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8920 ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
8921 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
8922 }
8923 else
8924 {
8925 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8926 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8927 ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
8928 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
8929 }
8930 }
8931
8932 //*****************************************************************************
8933 //
8944 //
8945 //*****************************************************************************
8946 static inline void
8947 EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block,
8948 uint32_t blockingSignal)
8949 {
8950 if(block == EPWM_MINDB_BLOCK_A)
8951 {
8952 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8953 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8954 ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
8955 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
8956 }
8957 else
8958 {
8959 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8960 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8961 ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
8962 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
8963 }
8964 }
8965
8966 //*****************************************************************************
8967 //
8977 //
8978 //*****************************************************************************
8979 static inline void
8980 EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block,
8981 uint32_t referenceSignal)
8982 {
8983 if(block == EPWM_MINDB_BLOCK_A)
8984 {
8985 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8986 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8987 ~CSL_EPWM_MINDBCFG_SELA_MASK) |
8988 (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
8989 }
8990 else
8991 {
8992 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8993 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8994 ~CSL_EPWM_MINDBCFG_SELB_MASK) |
8995 (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
8996 }
8997 }
8998
8999 //*****************************************************************************
9000 //
9009 //
9010 //*****************************************************************************
9011 static inline uint32_t
9012 EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
9013 {
9014 uint32_t retval;
9015
9016 if(block == EPWM_MINDB_BLOCK_A)
9017 {
9018 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9019 CSL_EPWM_MINDBDLY_DELAYA_MASK);
9020 }
9021 else
9022 {
9023 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9024 CSL_EPWM_MINDBDLY_DELAYB_MASK);
9025 }
9026
9027 return retval;
9028 }
9029
9030 //*****************************************************************************
9031 //
9042 //
9043 //*****************************************************************************
9044 static inline void
9045 EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
9046 {
9047 if(block == EPWM_MINDB_BLOCK_A)
9048 {
9049 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
9050 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9051 ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
9052 (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
9053 }
9054 else
9055 {
9056 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
9057 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
9058 ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
9059 (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
9060 }
9061 }
9062
9063 //
9064 // Illegal Combo Logic
9065 //
9066 //*****************************************************************************
9067 //
9076 //
9077 //*****************************************************************************
9078 static inline void
9079 EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
9080 {
9081 if(block == EPWM_MINDB_BLOCK_A)
9082 {
9083 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9084 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9085 ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
9086 }
9087 else
9088 {
9089 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9090 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9091 ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
9092 }
9093 }
9094
9095 //*****************************************************************************
9096 //
9105 //
9106 //*****************************************************************************
9107 static inline void
9108 EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
9109 {
9110 if(block == EPWM_MINDB_BLOCK_A)
9111 {
9112 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9113 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
9114 CSL_EPWM_LUTCTLA_BYPASS_MASK));
9115 }
9116 else
9117 {
9118 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9119 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
9120 CSL_EPWM_LUTCTLB_BYPASS_MASK));
9121 }
9122 }
9123
9124 //*****************************************************************************
9125 //
9135 //
9136 //*****************************************************************************
9137 static inline void
9138 EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
9139 {
9140 if(block == EPWM_MINDB_BLOCK_A)
9141 {
9142 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9143 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9144 ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
9145 (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
9146 }
9147 else
9148 {
9149 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9150 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9151 ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
9152 (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
9153 }
9154 }
9155
9156 //*****************************************************************************
9157 //
9169 //
9170 //*****************************************************************************
9171 static inline void
9172 EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
9173 {
9174 if(block == EPWM_MINDB_BLOCK_A)
9175 {
9176 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9177 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9178 ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
9179 (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
9180 (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
9181 }
9182 else if(block == EPWM_MINDB_BLOCK_B)
9183 {
9184 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9185 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9186 ~(CSL_EPWM_LUTCTLB_LUTDEC0_MAX <<
9187 (CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))) |
9188 (force<<(CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))));
9189 }
9190 else
9191 {
9192 /* do nothing */
9193 }
9194 }
9195
9196 //*****************************************************************************
9197 //
9214 //
9215 //*****************************************************************************
9216 static inline void
9217 HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
9218 {
9219 //
9220 // Check the arguments
9221 //
9222 DebugP_assert(phaseCount <= 0xFFFFFFFFU);
9223
9224 //
9225 // Write to TBPHS:TBPHSHR bits
9226 //
9227 HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount<<8U);
9228 }
9229
9230 //*****************************************************************************
9231 //
9244 //
9245 //*****************************************************************************
9246 static inline void
9247 HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
9248 {
9249 //
9250 // Check the arguments
9251 //
9252 DebugP_assert(hrPhaseCount <= CSL_EPWM_TBPHS_TBPHSHR_MAX);
9253
9254 //
9255 // Write to TBPHSHR bits
9256 //
9257 HW_WR_REG32(base + CSL_EPWM_TBPHS,
9258 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
9259 ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
9260 ((uint32_t)hrPhaseCount << (CSL_EPWM_TBPHS_TBPHSHR_SHIFT + 8U))));
9261 }
9262
9263 //*****************************************************************************
9264 //
9279 //
9280 //*****************************************************************************
9281 static inline void
9282 HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
9283 {
9284 //
9285 // Check the arguments
9286 //
9287 DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
9288
9289 //
9290 // Write to TBPRDHR bits
9291 //
9292 HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
9293 }
9294
9295 //*****************************************************************************
9296 //
9304 //
9305 //*****************************************************************************
9306 static inline uint16_t
9307 HRPWM_getHiResTimeBasePeriod(uint32_t base)
9308 {
9309 //
9310 // Read from TBPRDHR bit
9311 //
9312 return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR) >> 8U);
9313 }
9314
9315 //*****************************************************************************
9316 //
9339 //
9340 //*****************************************************************************
9341 static inline void
9342 HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel,
9343 HRPWM_MEPEdgeMode mepEdgeMode)
9344 {
9345 //
9346 // Set the edge mode
9347 //
9348 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9349 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9350 ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
9351 ((uint16_t)mepEdgeMode << (uint16_t)channel)));
9352 }
9353
9354 //*****************************************************************************
9355 //
9376 //
9377 //*****************************************************************************
9378 static inline void
9379 HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel,
9380 HRPWM_MEPCtrlMode mepCtrlMode)
9381 {
9382 //
9383 // Set the MEP control
9384 //
9385 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9386 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9387 ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
9388 ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
9389 }
9390
9391 //*****************************************************************************
9392 //
9414 //
9415 //*****************************************************************************
9416 static inline void
9417 HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel,
9418 HRPWM_LoadMode loadEvent)
9419 {
9420 //
9421 // Set the CMPAHR or CMPBHR load mode
9422 //
9423 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9424 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9425 ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
9426 ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
9427 }
9428
9429 //*****************************************************************************
9430 //
9441 //
9442 //*****************************************************************************
9443 static inline void
9444 HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
9445 {
9446 //
9447 // Set output swap mode
9448 //
9449 if(enableOutputSwap)
9450 {
9451 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9452 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
9453 }
9454 else
9455 {
9456 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9457 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
9458 }
9459 }
9460
9461 //*****************************************************************************
9462 //
9474 //
9475 //*****************************************************************************
9476 static inline void
9477 HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
9478 {
9479 //
9480 // Set the output on ePWM B
9481 //
9482 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9483 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(uint16_t)(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
9484 (uint16_t)((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
9485 }
9486
9487 //*****************************************************************************
9488 //
9497 //
9498 //*****************************************************************************
9499 static inline void
9500 HRPWM_enableAutoConversion(uint32_t base)
9501 {
9502 //
9503 // Enable MEP automatic scale
9504 //
9505 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9506 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
9507 }
9508
9509 //*****************************************************************************
9510 //
9519 //
9520 //*****************************************************************************
9521 static inline void
9522 HRPWM_disableAutoConversion(uint32_t base)
9523 {
9524 //
9525 // Disable MEP automatic scale
9526 //
9527 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9528 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
9529 }
9530
9531 //*****************************************************************************
9532 //
9540 //
9541 //*****************************************************************************
9542 static inline void
9543 HRPWM_enablePeriodControl(uint32_t base)
9544 {
9545 //
9546 // Set HRPE bit
9547 //
9548 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9549 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
9550 }
9551
9552 //*****************************************************************************
9553 //
9561 //
9562 //*****************************************************************************
9563 static inline void
9564 HRPWM_disablePeriodControl(uint32_t base)
9565 {
9566 //
9567 // Clear HRPE bit
9568 //
9569 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9570 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
9571 }
9572
9573 //*****************************************************************************
9574 //
9583 //
9584 //*****************************************************************************
9585 static inline void
9586 HRPWM_enablePhaseShiftLoad(uint32_t base)
9587 {
9588 //
9589 // Set TBPHSHRLOADE bit
9590 //
9591 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9592 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9593 }
9594
9595 //*****************************************************************************
9596 //
9604 //
9605 //*****************************************************************************
9606 static inline void
9607 HRPWM_disablePhaseShiftLoad(uint32_t base)
9608 {
9609 //
9610 // Clear TBPHSHRLOADE bit
9611 //
9612 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9613 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9614 }
9615
9616 //*****************************************************************************
9617 //
9637 //
9638 //*****************************************************************************
9639 static inline void
9640 HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
9641 {
9642 //
9643 // Set the PWMSYNC source
9644 //
9645
9646 //
9647 // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD
9648 // or HRPWM_PWMSYNC_SOURCE_ZERO
9649 //
9650 if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP)
9651 {
9652 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9653 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
9654 ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
9655 (uint16_t)((uint16_t)syncPulseSource << 1U)));
9656 }
9657 else
9658 {
9659 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9660 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~(uint16_t)CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
9661 (uint16_t)((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
9662 }
9663 }
9664
9665 //*****************************************************************************
9666 //
9675 //
9676 //*****************************************************************************
9677 static inline void
9678 HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
9679 {
9680 //
9681 // Check the arguments
9682 //
9683 DebugP_assert(trremVal <= CSL_EPWM_TRREM_TRREM_MAX);
9684
9685 //
9686 // Set Translator Remainder value
9687 //
9688 HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
9689 }
9690
9691 //*****************************************************************************
9692 //
9710 //
9711 //*****************************************************************************
9712 static inline void
9713 HRPWM_setCounterCompareValue(uint32_t base,
9714 HRPWM_CounterCompareModule compModule,
9715 uint32_t compCount)
9716 {
9717 //
9718 // Check the arguments
9719 //
9720 DebugP_assert(compCount <= 0xFFFFFFFFU);
9721
9722 //
9723 // Write to counter compare registers
9724 //
9725 if(compModule == HRPWM_COUNTER_COMPARE_A)
9726 {
9727 //
9728 // Write to CMPA:CMPAHR
9729 //
9730 HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
9731 }
9732 else
9733 {
9734 //
9735 // Write to CMPB:CMPBHR
9736 //
9737 HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
9738 }
9739 }
9740
9741 //*****************************************************************************
9742 //
9756 //
9757 //*****************************************************************************
9758 static inline uint32_t
9759 HRPWM_getCounterCompareValue(uint32_t base,
9760 HRPWM_CounterCompareModule compModule)
9761 {
9762 uint32_t compCount;
9763
9764 //
9765 // Get counter compare value for selected module
9766 //
9767 if(compModule == HRPWM_COUNTER_COMPARE_A)
9768 {
9769 //
9770 // Read from CMPAHR
9771 //
9772 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
9773 }
9774 else
9775 {
9776 //
9777 // Read from CMPBHR
9778 //
9779 compCount = HW_RD_REG32(base + CSL_EPWM_CMPB);
9780 }
9781
9782 return(compCount>>8U);
9783 }
9784
9785 //*****************************************************************************
9786 //
9802 //
9803 //*****************************************************************************
9804 static inline void
9805 HRPWM_setHiResCounterCompareValue(uint32_t base,
9806 HRPWM_CounterCompareModule compModule,
9807 uint16_t hrCompCount)
9808 {
9809 //
9810 // Check the arguments
9811 //
9812 DebugP_assert((hrCompCount << 8U) <= CSL_EPWM_CMPA_CMPAHR_MAX);
9813
9814 //
9815 // Write to the high resolution counter compare registers
9816 //
9817 if(compModule == HRPWM_COUNTER_COMPARE_A)
9818 {
9819 //
9820 // Write to CMPAHR
9821 //
9822 HW_WR_REG32(base + CSL_EPWM_CMPA,
9823 (HW_RD_REG32(base + CSL_EPWM_CMPA) & ~CSL_EPWM_CMPA_CMPAHR_MASK) | (((uint32_t)hrCompCount << (uint32_t)8U) & CSL_EPWM_CMPA_CMPAHR_MASK));
9824 }
9825 else
9826 {
9827 //
9828 // Write to CMPBHR
9829 //
9830 HW_WR_REG32(base + CSL_EPWM_CMPB,
9831 (HW_RD_REG32(base + CSL_EPWM_CMPB) & ~CSL_EPWM_CMPA_CMPAHR_MASK) | (((uint32_t)hrCompCount << (uint32_t)8U) & CSL_EPWM_CMPA_CMPAHR_MASK));
9832 }
9833 }
9834
9835 //*****************************************************************************
9836 //
9849 //
9850 //*****************************************************************************
9851 static inline uint16_t
9852 HRPWM_getHiResCounterCompareValueOnly(uint32_t base,
9853 HRPWM_CounterCompareModule compModule)
9854 {
9855 uint16_t hrCompCount;
9856
9857 //
9858 // Get counter compare value for selected module
9859 //
9860 if(compModule == HRPWM_COUNTER_COMPARE_A)
9861 {
9862 //
9863 // Read from CMPAHR
9864 //
9865 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
9866 }
9867 else
9868 {
9869 //
9870 // Read from CMPBHR
9871 //
9872 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
9873 }
9874
9875 return(hrCompCount >> 8U);
9876 }
9877
9878 //*****************************************************************************
9879 //
9892 //
9893 //*****************************************************************************
9894 static inline void
9895 HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
9896 {
9897 //
9898 // Check the arguments
9899 //
9900 DebugP_assert(hrRedCount <= CSL_EPWM_DBREDHR_DBREDHR_MAX);
9901
9902 //
9903 // Set the High Resolution RED (Rising Edge Delay) count only
9904 //
9905 HW_WR_REG16(base + CSL_EPWM_DBREDHR,
9906 (HW_RD_REG16(base + CSL_EPWM_DBREDHR) & ~CSL_EPWM_DBREDHR_DBREDHR_MASK ) |
9907 ((uint32_t)hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
9908 }
9909
9910 //*****************************************************************************
9911 //
9923 //
9924 //*****************************************************************************
9925 static inline void
9926 HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
9927 {
9928 //
9929 // Check the arguments
9930 //
9931 DebugP_assert(hrFedCount <= CSL_EPWM_DBFEDHR_DBFEDHR_MAX);
9932
9933 //
9934 // Set the high resolution FED (Falling Edge Delay) count
9935 //
9936 HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
9937 (HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
9938 ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK) |
9939 ((uint32_t)hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
9940 }
9941
9942 //*****************************************************************************
9943 //
9954 //
9955 //*****************************************************************************
9956 static inline void
9957 HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
9958 {
9959 //
9960 // Check the arguments
9961 //
9962 DebugP_assert(mepCount <= CSL_OTTOCAL_HRMSTEP_HRMSTEP_MAX);
9963
9964 //
9965 // Set HRPWM MEP count
9966 //
9967 HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
9968 ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
9969 ((uint32_t)mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT)));
9970 }
9971
9972 //*****************************************************************************
9973 //
9991 //
9992 //*****************************************************************************
9993 static inline void
9994 HRPWM_setDeadbandMEPEdgeSelect(uint32_t base,
9995 HRPWM_MEPDeadBandEdgeMode mepDBEdge)
9996 {
9997 //
9998 // Set the HRPWM DB edge mode
9999 //
10000 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
10001 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~(uint16_t)CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
10002 (uint16_t)((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
10003 }
10004
10005 //*****************************************************************************
10006 //
10021 //
10022 //*****************************************************************************
10023 static inline void
10024 HRPWM_setRisingEdgeDelayLoadMode(uint32_t base,
10025 HRPWM_LoadMode loadEvent)
10026 {
10027 //
10028 // Set the HRPWM RED load mode
10029 //
10030 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
10031 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~(uint16_t)CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
10032 (uint16_t)((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
10033 }
10034
10035 //*****************************************************************************
10036 //
10051 //
10052 //*****************************************************************************
10053 static inline void
10054 HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
10055 {
10056 //
10057 // Set the HRPWM FED load mode
10058 //
10059 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
10060 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~(uint16_t)CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
10061 (uint16_t)((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
10062 }
10063
10064 //*****************************************************************************
10065 //
10079 //
10080 //*****************************************************************************
10081 static inline void
10082 HRPWM_setXCMPRegValue(uint32_t base, HRPWM_XCMPReg xcmpReg,
10083 uint16_t xcmpvalue)
10084 {
10085 uint32_t registerOffset;
10086
10087 //
10088 // Get the register offset for the Counter compare
10089 //
10090 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
10091
10092 //
10093 // Write to the xcmp registers.
10094 //
10095 HW_WR_REG16(registerOffset, xcmpvalue);
10096 }
10097 //
10098 // XCMP related APIs
10099 //
10100 //*****************************************************************************
10101 //
10109 //
10110 //*****************************************************************************
10111
10112 static inline void
10113 EPWM_enableXCMPMode(uint32_t base)
10114 {
10115 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10116
10117 HW_WR_REG32(registerOffset,
10118 (HW_RD_REG32(registerOffset) | CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
10119 }
10120
10121 //*****************************************************************************
10122 //
10130 //
10131 //*****************************************************************************
10132 static inline void
10133 EPWM_disableXCMPMode(uint32_t base)
10134 {
10135 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10136
10137 HW_WR_REG32(registerOffset,
10138 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
10139 }
10140
10141
10142 //*****************************************************************************
10143 //
10151 //
10152 //*****************************************************************************
10153
10154 static inline void
10155 EPWM_enableSplitXCMP(uint32_t base)
10156 {
10157 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10158 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
10159
10160 HW_WR_REG32(registerOffset,
10161 (HW_RD_REG32(registerOffset) | ((uint32_t) CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
10162 }
10163
10164 //*****************************************************************************
10165 //
10173 //
10174 //*****************************************************************************
10175
10176 static inline void
10177 EPWM_disableSplitXCMP(uint32_t base)
10178 {
10179 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10180 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
10181
10182 HW_WR_REG32(registerOffset,
10183 (HW_RD_REG32(registerOffset) & ~( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
10184
10185 }
10186
10187 //*****************************************************************************
10188 //
10193
10206 //
10207 //*****************************************************************************
10208
10209 static inline void
10210 EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
10211 {
10212 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10213 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_SHIFT;
10214
10215 HW_WR_REG32(registerOffset,
10216 ( (HW_RD_REG32(registerOffset) & ~(uint32_t)CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_MASK) | ( (uint32_t)alloctype << offset )));
10217 }
10218
10219 //*****************************************************************************
10220 //
10225
10233 //
10234 //*****************************************************************************
10235
10236 static inline void
10237 EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
10238 {
10239 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10240 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_SHIFT;
10241
10242 HW_WR_REG32(registerOffset,
10243 ( (HW_RD_REG32(registerOffset) & ~(uint32_t)CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_MASK) | ( (uint32_t)alloctype << offset )));
10244 }
10245
10246 //*****************************************************************************
10247 //
10261 //
10262 //*****************************************************************************
10263
10264 static inline void
10265 EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg,
10266 uint16_t xcmpvalue)
10267 {
10268 uint32_t registerOffset;
10269
10270 //
10271 // Get the register offset for the Counter compare
10272 //
10273 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
10274
10275 //
10276 // Write to the xcmp registers.
10277 //
10278 HW_WR_REG16(registerOffset + 0x2U, xcmpvalue);
10279 }
10280 //*****************************************************************************
10281 //
10296 //
10297 //*****************************************************************************
10298 static inline void
10299 EPWM_setCMPShadowRegValue(uint32_t base, EPWM_XCompareReg cmpReg,
10300 uint16_t cmpvalue)
10301 {
10302 //
10303 // Check the arguments
10304 //
10305 uint32_t registerOffset;
10306 registerOffset = base + CSL_EPWM_CMPC_SHDW1 + (uint32_t)cmpReg;
10307
10308 //
10309 // Write to the CMPC/D Shadow registers.
10310 //
10311 HW_WR_REG16(registerOffset, cmpvalue);
10312 }
10313
10314 //*****************************************************************************
10315 //
10332 //
10333 //*****************************************************************************
10334 static inline void
10335 EPWM_setXMINMAXRegValue(uint32_t base, EPWM_XMinMaxReg xminmaxReg,
10336 uint16_t xcmpvalue)
10337 {
10338 //
10339 // Check the arguments
10340 //
10341 uint32_t registerOffset;
10342 registerOffset = base + CSL_EPWM_XMINMAX_ACTIVE + (uint16_t)xminmaxReg;
10343
10344 //
10345 // Write to the XMINMAX register.
10346 //
10347 HW_WR_REG16(registerOffset, xcmpvalue);
10348 }
10349 //*****************************************************************************
10350 //
10386 //
10387 //*****************************************************************************
10388 static inline void
10389 EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset,
10390 EPWM_ActionQualifierOutputModule epwmOutput,
10391 EPWM_ActionQualifierOutput output,
10392 EPWM_XCMPActionQualifierOutputEvent event)
10393 {
10394 uint32_t registerOffset;
10395
10396 //
10397 // Get the register offset
10398 //
10399
10400 if(shadowset == EPWM_XCMP_ACTIVE)
10401 {
10402 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_ACTIVE + (uint16_t)((uint16_t)epwmOutput/(uint32_t)2);
10403
10404 HW_WR_REG16(base + registerOffset,
10405 ((HW_RD_REG16(base + registerOffset) &
10406 ~(CSL_EPWM_XAQCTLA_ACTIVE_XCMP1_MAX << (uint16_t)event)) |
10407 ((uint16_t)output << (uint16_t)event)));
10408 }
10409 else if(shadowset == EPWM_XCMP_SHADOW1)
10410 {
10411 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_SHDW1 + (uint16_t)((uint16_t)epwmOutput/(uint32_t)2);
10412
10413 HW_WR_REG16(base + registerOffset,
10414 ((HW_RD_REG16(base + registerOffset) &
10415 ~(CSL_EPWM_XAQCTLA_SHDW1_XCMP1_MAX << (uint16_t)event)) |
10416 ((uint16_t)output << (uint16_t)event)));
10417 }
10418 else if(shadowset == EPWM_XCMP_SHADOW2)
10419 {
10420 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_SHDW2 + (uint16_t)((uint16_t)epwmOutput/(uint32_t)2);
10421
10422 HW_WR_REG16(base + registerOffset,
10423 ((HW_RD_REG16(base + registerOffset) &
10424 ~(CSL_EPWM_XAQCTLA_SHDW2_XCMP1_MAX << (uint16_t)event)) |
10425 ((uint16_t)output << (uint16_t)event)));
10426 }
10427 else if(shadowset == EPWM_XCMP_SHADOW3)
10428 {
10429 registerOffset = (uint32_t)CSL_EPWM_XAQCTLA_SHDW3 + (uint32_t)((uint16_t)epwmOutput/(uint32_t)2);
10430
10431 HW_WR_REG16(base + registerOffset,
10432 ((HW_RD_REG16(base + registerOffset) &
10433 ~(CSL_EPWM_XAQCTLA_SHDW3_XCMP1_MAX << (uint16_t)event)) |
10434 ((uint16_t)output << (uint16_t)event)));
10435 }
10436 else
10437 {
10438 /* do nothing */
10439 }
10440
10441 }
10442
10443 //*****************************************************************************
10444 //
10452 //
10453 //*****************************************************************************
10454
10455 static inline void
10456 EPWM_enableXLoad(uint32_t base)
10457 {
10458 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
10459
10460 HW_WR_REG32(registerOffset,
10461 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_STARTLD_MASK ));
10462 }
10463
10464 //*****************************************************************************
10465 //
10473 //
10474 //*****************************************************************************
10475 static inline void
10476 EPWM_disableXLoad(uint32_t base)
10477 {
10478 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
10479
10480 HW_WR_REG32(registerOffset,
10481 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOAD_STARTLD_MASK ));
10482 }
10483 //*****************************************************************************
10484 //
10493 //
10494 //*****************************************************************************
10495 static inline void
10496 EPWM_forceXLoad(uint32_t base)
10497 {
10498 //
10499 // Check the arguments
10500 //
10501 uint32_t registerOffset;
10502 registerOffset = base + CSL_EPWM_XLOAD;
10503
10504 HW_WR_REG32(registerOffset,
10505 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_FRCLD_MASK ));
10506 }
10507 //*****************************************************************************
10508 //
10513
10519 //
10520 //*****************************************************************************
10521
10522 static inline void
10523 EPWM_setXCMPLoadMode(uint32_t base,EPWM_XCMPXloadCtlLoadMode mode)
10524 {
10525 uint32_t registerOffset;
10526
10527 //
10528 // Get the register offset
10529 //
10530 registerOffset = base + CSL_EPWM_XLOADCTL;
10531
10532 if(mode == EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE)
10533 {
10534 HW_WR_REG32(registerOffset,
10535 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_LOADMODE_MASK));
10536 }
10537 else if(mode == EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE)
10538 {
10539 HW_WR_REG32(registerOffset,
10540 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOADCTL_LOADMODE_MASK));
10541 }
10542 else
10543 {
10544 /* do nothing */
10545 }
10546 }
10547
10548 //*****************************************************************************
10549 //
10554
10562 //
10563 //*****************************************************************************
10564 static inline void
10565 EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
10566 {
10567 uint32_t registerOffset;
10568
10569 //
10570 // Get the register offset
10571 //
10572 registerOffset = base + CSL_EPWM_XLOADCTL;
10573
10574 HW_WR_REG32(registerOffset,
10575 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWLEVEL_MASK) |
10576 (uint32_t)((uint16_t)level << CSL_EPWM_XLOADCTL_SHDWLEVEL_SHIFT)));
10577 }
10578
10579 //*****************************************************************************
10580 //
10585
10593 //
10594 //*****************************************************************************
10595 static inline void
10596 EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
10597 {
10598 uint32_t registerOffset;
10599
10600 //
10601 // Get the register offset
10602 //
10603 registerOffset = base + CSL_EPWM_XLOADCTL;
10604
10605 HW_WR_REG32(registerOffset,
10606 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_MASK) |
10607 (uint32_t)((uint16_t)ptr << CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_SHIFT)));
10608 }
10609
10610 //*****************************************************************************
10611 //
10617
10626 //
10627 //*****************************************************************************
10628 static inline void
10629 EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
10630 {
10631 uint32_t registerOffset;
10632 //
10633 // Get the register offset
10634 //
10635 registerOffset = base + CSL_EPWM_XLOADCTL;
10636
10637 if(bufferset == EPWM_XCMP_SHADOW2)
10638 {
10639 HW_WR_REG32(registerOffset,
10640 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF2PRD_MASK))
10641 | ((uint32_t)count<<CSL_EPWM_XLOADCTL_RPTBUF2PRD_SHIFT)) );
10642 }
10643 else if(bufferset == EPWM_XCMP_SHADOW3)
10644 {
10645 HW_WR_REG32(registerOffset,
10646 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF3PRD_MASK))
10647 | ((uint32_t)count<<CSL_EPWM_XLOADCTL_RPTBUF3PRD_SHIFT)) );
10648 }
10649 else
10650 {
10651 /*do nothing */
10652 }
10653 }
10654
10655 //*************************************************
10656 //
10657 // DIODE EMULATION LOGIC APIs
10658 //
10659
10660 //*****************************************************************************
10661 //
10669 //
10670 //*****************************************************************************
10671
10672 static inline void
10673 EPWM_enableDiodeEmulationMode(uint32_t base)
10674 {
10675 uint32_t registerOffset;
10676 //
10677 // Get the register offset
10678 //
10679 registerOffset = base + CSL_EPWM_DECTL;
10680
10681 HW_WR_REG32(registerOffset,
10682 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_ENABLE_MAX ));
10683
10684 }
10685
10686 //*****************************************************************************
10687 //
10695 //
10696 //*****************************************************************************
10697
10698 static inline void
10699 EPWM_disableDiodeEmulationMode(uint32_t base)
10700 {
10701 uint32_t registerOffset;
10702 //
10703 // Get the register offset
10704 //
10705 registerOffset = base + CSL_EPWM_DECTL;
10706
10707 HW_WR_REG32(registerOffset,
10708 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_ENABLE_MAX ));
10709
10710 }
10711
10712 //*****************************************************************************
10713 //
10718
10727 //
10728 //*****************************************************************************
10729
10730 static inline void
10731 EPWM_setDiodeEmulationMode(uint32_t base,EPWM_DiodeEmulationMode mode)
10732 {
10733 uint32_t registerOffset;
10734
10735 //
10736 // Get the register offset
10737 //
10738 registerOffset = base + CSL_EPWM_DECTL;
10739
10740 if(mode == EPWM_DIODE_EMULATION_CBC)
10741 {
10742 HW_WR_REG32(registerOffset,
10743 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_MODE_MASK));
10744 }
10745 else if(mode == EPWM_DIODE_EMULATION_OST)
10746 {
10747 HW_WR_REG32(registerOffset,
10748 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_MODE_MASK));
10749 }
10750 else
10751 {
10752 /* do nothing */
10753 }
10754 }
10755
10756 //*****************************************************************************
10757 //
10767 //
10768 //*****************************************************************************
10769
10770 static inline void
10771 EPWM_setDiodeEmulationReentryDelay(uint32_t base,uint8_t delay)
10772 {
10773 uint32_t registerOffset;
10774 //
10775 // Get the register offset
10776 //
10777 registerOffset = base + CSL_EPWM_DECTL;
10778
10779 HW_WR_REG32(registerOffset,
10780 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DECTL_REENTRYDLY_MASK))
10781 | ((uint32_t)delay<<CSL_EPWM_DECTL_REENTRYDLY_SHIFT)) );
10782 }
10783
10784 //*****************************************************************************
10785 //
10801 //*****************************************************************************
10802
10803 static inline void
10804 EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source,
10805 uint32_t tripLorH)
10806 {
10807 uint32_t registerOffset;
10808 //
10809 // Get the register offset
10810 //
10811 registerOffset = base + CSL_EPWM_DECOMPSEL;
10812
10813 if(tripLorH == EPWM_DE_TRIPL)
10814 {
10815 HW_WR_REG32(registerOffset,
10816 ((HW_RD_REG32(registerOffset) &
10817 ~CSL_EPWM_DECOMPSEL_TRIPL_MASK) |
10818 ((uint32_t)source<<CSL_EPWM_DECOMPSEL_TRIPL_SHIFT)));
10819 }
10820 else if(tripLorH == EPWM_DE_TRIPH)
10821 {
10822 HW_WR_REG32(registerOffset,
10823 ((HW_RD_REG32(registerOffset) &
10824 ~CSL_EPWM_DECOMPSEL_TRIPH_MASK) |
10825 ((uint32_t)source<<CSL_EPWM_DECOMPSEL_TRIPH_SHIFT)));
10826 }
10827 else
10828 {
10829 /* do nothing */
10830 }
10831
10832 }
10833
10834 //*****************************************************************************
10835 //
10852 //*****************************************************************************
10853
10854 static inline void
10855 EPWM_selectDiodeEmulationPWMsignal(uint32_t base,uint32_t channel,
10856 EPWM_DiodeEmulationSignal signal)
10857 {
10858 uint32_t registerOffset;
10859 //
10860 // Get the register offset
10861 //
10862 registerOffset = base + CSL_EPWM_DEACTCTL;
10863
10864 if(channel == EPWM_DE_CHANNEL_A)
10865 {
10866 HW_WR_REG32(registerOffset,
10867 ((HW_RD_REG32(registerOffset) &
10868 ~CSL_EPWM_DEACTCTL_PWMA_MASK) |
10869 ((uint32_t)signal<<CSL_EPWM_DEACTCTL_PWMA_SHIFT)));
10870 }
10871 else
10872 {
10873 HW_WR_REG32(registerOffset,
10874 ((HW_RD_REG32(registerOffset) &
10875 ~CSL_EPWM_DEACTCTL_PWMB_MASK) |
10876 ((uint32_t)signal<<CSL_EPWM_DEACTCTL_PWMB_SHIFT)));
10877 }
10878 }
10879
10880 //*****************************************************************************
10881 //
10896 //*****************************************************************************
10897
10898 static inline void
10899 EPWM_selectDiodeEmulationTripSignal(uint32_t base,uint32_t channel,
10900 uint32_t signal)
10901 {
10902 uint32_t registerOffset;
10903 //
10904 // Get the register offset
10905 //
10906 registerOffset = base + CSL_EPWM_DEACTCTL;
10907
10908 if(channel == EPWM_DE_CHANNEL_A)
10909 {
10910 HW_WR_REG32(registerOffset,
10911 ((HW_RD_REG32(registerOffset) &
10912 ~CSL_EPWM_DEACTCTL_TRIPSELA_MASK) |
10913 (signal<<CSL_EPWM_DEACTCTL_TRIPSELA_SHIFT)));
10914 }
10915 else
10916 {
10917 HW_WR_REG32(registerOffset,
10918 ((HW_RD_REG32(registerOffset) &
10919 ~CSL_EPWM_DEACTCTL_TRIPSELB_MASK) |
10920 (signal<<CSL_EPWM_DEACTCTL_TRIPSELB_SHIFT)));
10921 }
10922 }
10923
10924 //*****************************************************************************
10925 //
10931 //*****************************************************************************
10932
10933 static inline void
10934 EPWM_nobypassDiodeEmulationLogic(uint32_t base)
10935 {
10936 uint32_t registerOffset;
10937 //
10938 // Get the register offset
10939 //
10940 registerOffset = base + CSL_EPWM_DEACTCTL;
10941
10942 HW_WR_REG32(registerOffset,
10943 (HW_RD_REG32(registerOffset) &
10944 ~(CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10945
10946 }
10947
10948 //*****************************************************************************
10949 //
10955 //*****************************************************************************
10956
10957 static inline void
10958 EPWM_bypassDiodeEmulationLogic(uint32_t base)
10959 {
10960 uint32_t registerOffset;
10961 //
10962 // Get the register offset
10963 //
10964 registerOffset = base + CSL_EPWM_DEACTCTL;
10965
10966 HW_WR_REG32(registerOffset,
10967 (HW_RD_REG32(registerOffset) |
10968 (CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10969
10970 }
10971
10972 //*****************************************************************************
10973 //
10979 //*****************************************************************************
10980
10981 static inline void
10982 EPWM_forceDiodeEmulationActive(uint32_t base)
10983 {
10984 uint32_t registerOffset;
10985 //
10986 // Get the register offset
10987 //
10988 registerOffset = base + CSL_EPWM_DEFRC;
10989
10990 HW_WR_REG32(registerOffset,
10991 (HW_RD_REG32(registerOffset) | CSL_EPWM_DEFRC_DEACTIVE_MASK));
10992
10993 }
10994
10995 //*****************************************************************************
10996 //
11002 //*****************************************************************************
11003
11004 static inline void
11005 EPWM_clearDiodeEmulationActive(uint32_t base)
11006 {
11007 uint32_t registerOffset;
11008 //
11009 // Get the register offset
11010 //
11011 registerOffset = base + CSL_EPWM_DECLR;
11012
11013 HW_WR_REG32(registerOffset,
11014 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECLR_DEACTIVE_MASK));
11015
11016 }
11017 //*****************************************************************************
11018 //
11024 //*****************************************************************************
11025
11026
11027 static inline void
11028 EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
11029 {
11030 uint32_t registerOffset;
11031 //
11032 // Get the register offset
11033 //
11034 registerOffset = base + CSL_EPWM_DEMONCTL;
11035
11036 HW_WR_REG32(registerOffset,
11037 (HW_RD_REG32(registerOffset) |
11038 (CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
11039 }
11040
11041 //*****************************************************************************
11042 //
11048 //*****************************************************************************
11049
11050 static inline void
11051 EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
11052 {
11053 uint32_t registerOffset;
11054 //
11055 // Get the register offset
11056 //
11057 registerOffset = base + CSL_EPWM_DEMONCTL;
11058
11059 HW_WR_REG32(registerOffset,
11060 (HW_RD_REG32(registerOffset) &
11061 ~(CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
11062 }
11063
11064 //*****************************************************************************
11065 //
11077 //*****************************************************************************
11078
11079 static inline void
11080 EPWM_setDiodeEmulationMonitorModeStep(uint32_t base,uint32_t direction,
11081 uint8_t stepsize)
11082 {
11083 uint32_t registerOffset;
11084 //
11085 // Get the register offset
11086 //
11087 registerOffset = base + CSL_EPWM_DEMONSTEP;
11088
11089 if(direction == EPWM_DE_COUNT_UP)
11090 {
11091 HW_WR_REG32(registerOffset,
11092 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DEMONSTEP_INCSTEP_MASK)
11093 | ((uint32_t)stepsize<<CSL_EPWM_DEMONSTEP_INCSTEP_SHIFT));
11094 }
11095 else if(direction == EPWM_DE_COUNT_DOWN)
11096 {
11097 HW_WR_REG32(registerOffset,
11098 ((HW_RD_REG32(registerOffset) &
11099 ~CSL_EPWM_DEMONSTEP_DECSTEP_MASK) |
11100 ((uint32_t)stepsize<<CSL_EPWM_DEMONSTEP_DECSTEP_SHIFT)));
11101 }
11102 else
11103 {
11104 /* do nothing */
11105 }
11106 }
11107
11108 //*****************************************************************************
11109 //
11117 //*****************************************************************************
11118 static inline void
11119 EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base,uint16_t threshold)
11120 {
11121 uint32_t registerOffset;
11122 //
11123 // Get the register offset
11124 //
11125 registerOffset = base + CSL_EPWM_DEMONTHRES;
11126
11127 HW_WR_REG32(registerOffset,
11128 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DEMONTHRES_THRESHOLD_MASK))
11129 | ((uint32_t)threshold<<CSL_EPWM_DEMONTHRES_THRESHOLD_SHIFT)) );
11130 }
11131
11132
11133 //*****************************************************************************
11134 //
11149 //
11150 //*****************************************************************************
11151 extern void
11152 EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode);
11153 //*****************************************************************************
11154 //
11164 //
11165 //*****************************************************************************
11166 extern void
11167 EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams);
11168 //*****************************************************************************
11169 //
11170 // Close the Doxygen group.
11172 //
11173 //*****************************************************************************
11174
11175 //*****************************************************************************
11176 //
11177 // Mark the end of the C bindings section for C++ compilers.
11178 //
11179 //*****************************************************************************
11180 #ifdef __cplusplus
11181 }
11182 #endif
11183
11184 #endif // EPWM_V1_H_
EPWM_TZ_ACTION_HIGH
@ EPWM_TZ_ACTION_HIGH
high voltage state
Definition: etpwm.h:979
HRPWM_LOAD_ON_CNTR_ZERO_PERIOD
@ HRPWM_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:1916
EPWM_disableInterruptEventCountInit
static void EPWM_disableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6103
EPWM_setDeadBandOutputSwapMode
static void EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, bool enableSwapMode)
Definition: etpwm.h:4414
HRPWM_XCMP6_SHADOW3
@ HRPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2062
EPWM_enableADCTriggerEventCountInit
static void EPWM_enableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6575
EPWM_AQ_OUTPUT_HIGH_UP_T1
@ EPWM_AQ_OUTPUT_HIGH_UP_T1
T1 event on count up and set output pins to high.
Definition: etpwm.h:688
EPWM_getValleyHWDelay
static uint16_t EPWM_getValleyHWDelay(uint32_t base)
Definition: etpwm.h:8456
EPWM_getDigitalCompareEdgeFilterEdgeStatus
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
Definition: etpwm.h:7109
EPWM_TimeBaseCountMode
EPWM_TimeBaseCountMode
Definition: etpwm.h:359
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22
Trip source is INPUTXBAR out22 signal.
Definition: etpwm.h:2412
HRPWM_XCMP1_SHADOW2
@ HRPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2033
EPWM_TZ_ACTION_LOW
@ EPWM_TZ_ACTION_LOW
low voltage state
Definition: etpwm.h:980
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8
Sync-in source is EPWM8 sync-out signal.
Definition: etpwm.h:205
EPWM_getCycleByCycleTripZoneFlagStatus
static uint16_t EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5578
EPWM_ActionQualifierLoadMode
EPWM_ActionQualifierLoadMode
Definition: etpwm.h:521
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP10
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP10
Sync-in source is ECAP10 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:273
EPWM_LINK_WITH_EPWM_5
@ EPWM_LINK_WITH_EPWM_5
link current ePWM with ePWM5
Definition: etpwm.h:406
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP13
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP13
Sync-in source is ECAP13 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:279
HRPWM_XTBPRD_ACTIVE
@ HRPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:2011
EPWM_setFallingEdgeDelayCountShadowLoadMode
static void EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_FallingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4747
EPWM_selectPeriodLoadEvent
static void EPWM_selectPeriodLoadEvent(uint32_t base, EPWM_PeriodShadowLoadMode shadowLoadMode)
Definition: etpwm.h:3034
EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD
Clear CBC pulse when counter equals zero or period.
Definition: etpwm.h:1152
EPWM_setupEPWMLinks
static void EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, EPWM_LinkComponent linkComp)
Definition: etpwm.h:3378
EPWM_XCMP_XLOADCTL_SHDWLEVEL
EPWM_XCMP_XLOADCTL_SHDWLEVEL
Definition: etpwm.h:2313
HRPWM_setMEPEdgeSelect
static void HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, HRPWM_MEPEdgeMode mepEdgeMode)
Definition: etpwm.h:9342
EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2
Sync-in source is FSI-RX2 RX Trigger 2 signal.
Definition: etpwm.h:313
EPWM_SOC_A
@ EPWM_SOC_A
SOC A.
Definition: etpwm.h:1281
EPWM_DC_EVENT_1
@ EPWM_DC_EVENT_1
Digital Compare Event number 1.
Definition: etpwm.h:1491
EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD
@ EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:527
EPWM_AQ_SW_OUTPUT_HIGH
@ EPWM_AQ_SW_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:613
EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD
@ EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD
Time base counter equals zero or period.
Definition: etpwm.h:1418
EPWM_DE_TRIP_SRC_CMPSSB1
@ EPWM_DE_TRIP_SRC_CMPSSB1
Trip source is CMPSSB1 signal.
Definition: etpwm.h:2454
EPWM_HSCLOCK_DIVIDER_2
@ EPWM_HSCLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:168
EPWM_LINK_WITH_EPWM_9
@ EPWM_LINK_WITH_EPWM_9
link current ePWM with ePWM9
Definition: etpwm.h:410
HRPWM_setMEPStep
static void HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
Definition: etpwm.h:9957
HRPWM_XTBPRD_SHADOW1
@ HRPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2030
EPWM_startValleyCapture
static void EPWM_startValleyCapture(uint32_t base)
Definition: etpwm.h:8209
EPWM_setXCMPShadowRepeatBufxCount
static void EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
Definition: etpwm.h:10629
EPWM_disableOneShotSync
static void EPWM_disableOneShotSync(uint32_t base)
Definition: etpwm.h:3079
EPWM_XCMP2_SHADOW3
@ EPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2152
EPWM_GL_LOAD_PULSE_CNTR_CMPC_U
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_U
load when counter is equal to cmpc and cmpc is incrementing
Definition: etpwm.h:1576
EPWM_enableValleyHWDelay
static void EPWM_enableValleyHWDelay(uint32_t base)
Definition: etpwm.h:8296
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18
Trip source is INPUTXBAR out18 signal.
Definition: etpwm.h:2404
EPWM_selectCycleByCycleTripZoneClearEvent
static void EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, EPWM_CycleByCycleTripZoneClearMode clearEvent)
Definition: etpwm.h:5637
EPWM_setChopperFreq
static void EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
Definition: etpwm.h:4961
EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1
Sync-in source is C2K Timesync xbar sync pwm out1 signal.
Definition: etpwm.h:291
EPWM_enableTripZoneOutput
static void EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5816
EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO
@ EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO
shadow to active load occurs when time base counter reaches 0.
Definition: etpwm.h:375
EPWM_DE_TRIP_SRC_CMPSSB0
@ EPWM_DE_TRIP_SRC_CMPSSB0
Trip source is CMPSSB0 signal.
Definition: etpwm.h:2452
EPWM_REGISTER_GROUP_TRIP_ZONE
@ EPWM_REGISTER_GROUP_TRIP_ZONE
Trip zone register group.
Definition: etpwm.h:1733
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24
Sync-in source is EPWM24 sync-out signal.
Definition: etpwm.h:237
EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U
Digital Compare event A/B 1 while counting up.
Definition: etpwm.h:1028
EPWM_forceDiodeEmulationActive
static void EPWM_forceDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10982
EPWM_COMP_LOAD_ON_CNTR_ZERO
@ EPWM_COMP_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:482
EPWM_ActionQualifierContForce
EPWM_ActionQualifierContForce
Definition: etpwm.h:739
EPWM_DE_SYNC_INV_TRIPHorL
@ EPWM_DE_SYNC_INV_TRIPHorL
synchronized and inverted version of TRIPH or TRIPL signal
Definition: etpwm.h:2479
EPWM_getTimeBaseCounterValue
static uint16_t EPWM_getTimeBaseCounterValue(uint32_t base)
Definition: etpwm.h:3122
EPWM_getADCTriggerEventCount
static uint16_t EPWM_getADCTriggerEventCount(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6708
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16
Trip source is INPUTXBAR out16 signal.
Definition: etpwm.h:2400
EPWM_DE_HIGH
@ EPWM_DE_HIGH
a constant high signal
Definition: etpwm.h:2483
EPWM_enableTripZoneAdvAction
static void EPWM_enableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:5216
EPWM_setCounterCompareValue_opt_cmpA
static void EPWM_setCounterCompareValue_opt_cmpA(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3610
HRPWM_PWMSYNC_SOURCE_ZERO
@ HRPWM_PWMSYNC_SOURCE_ZERO
Counter equals zero.
Definition: etpwm.h:1946
HRPWM_PWMSYNC_SOURCE_COMPD_UP
@ HRPWM_PWMSYNC_SOURCE_COMPD_UP
Counter equals COMPD when counting up.
Definition: etpwm.h:1952
HRPWM_setHiResFallingEdgeDelayOnly
static void HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
Definition: etpwm.h:9926
EPWM_setActionQualifierActionComplete
static void EPWM_setActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierEventAction action)
Definition: etpwm.h:4087
EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD
Clear CBC latch when counter equals zero or period.
Definition: etpwm.h:1550
EPWM_CLOCK_DIVIDER_32
@ EPWM_CLOCK_DIVIDER_32
Divide clock by 32.
Definition: etpwm.h:154
EPWM_setFallingEdgeDelayCount
static void EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
Definition: etpwm.h:4855
EPWM_XCMP_4_CMPA
@ EPWM_XCMP_4_CMPA
Allocate XCMP1 - XCMP4 registers to CMPA.
Definition: etpwm.h:2262
EPWM_XCMP_SHADOW1
#define EPWM_XCMP_SHADOW1
XCMP set = Shadow 2.
Definition: etpwm.h:2078
EPWM_XMIN_SHADOW1
@ EPWM_XMIN_SHADOW1
XMIN_SHADOW1.
Definition: etpwm.h:2208
EPWM_setCounterCompareValue_opt_cmpD
static void EPWM_setCounterCompareValue_opt_cmpD(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3667
EPWM_COMP_LOAD_FREEZE
@ EPWM_COMP_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:488
EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0
Sync-in source is C2K Timesync xbar sync pwm out0 signal.
Definition: etpwm.h:289
EPWM_DE_TRIP_SRC_CMPSSB2
@ EPWM_DE_TRIP_SRC_CMPSSB2
Trip source is CMPSSB2 signal.
Definition: etpwm.h:2456
EPWM_DC_EDGEFILT_EDGECNT_6
@ EPWM_DC_EDGEFILT_EDGECNT_6
Digital Compare Edge filter edge count = 7.
Definition: etpwm.h:1718
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP12
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP12
Sync-in source is ECAP12 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:277
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12
Trip source is INPUTXBAR out12 signal.
Definition: etpwm.h:2392
EPWM_SignalParams::dutyValA
Float32 dutyValA
Desired ePWMxA Signal Duty.
Definition: etpwm.h:2605
EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO
load on sync or when counter equals zero
Definition: etpwm.h:531
HRPWM_XCMPReg
HRPWM_XCMPReg
Definition: etpwm.h:1993
EPWM_forceActionQualifierSWAction
static void EPWM_forceActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput)
Definition: etpwm.h:4368
EPWM_XCMP2_ACTIVE
@ EPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:2095
EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO
@ EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO
Clear CBC latch when counter equals zero.
Definition: etpwm.h:1546
EPWM_LINK_WITH_EPWM_22
@ EPWM_LINK_WITH_EPWM_22
link current ePWM with ePWM22
Definition: etpwm.h:423
EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1
T1 event on count down and no change in the output pins.
Definition: etpwm.h:692
EPWM_setEmulationMode
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
HRPWM_XCMP6_SHADOW1
@ HRPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2024
EPWM_LINK_WITH_EPWM_16
@ EPWM_LINK_WITH_EPWM_16
link current ePWM with ePWM16
Definition: etpwm.h:417
EPWM_DigitalCompareEdgeFilterEdgeCount
EPWM_DigitalCompareEdgeFilterEdgeCount
Definition: etpwm.h:1704
EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA
Time base counter down equals COMPA and set output pins to high.
Definition: etpwm.h:653
EPWM_selectDigitalCompareTripInput
static void EPWM_selectDigitalCompareTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:6787
EPWM_TripZoneDigitalCompareOutput
EPWM_TripZoneDigitalCompareOutput
Definition: etpwm.h:931
EPWM_TripZoneAdvancedEvent
EPWM_TripZoneAdvancedEvent
Definition: etpwm.h:991
EPWM_XCMP5_SHADOW3
@ EPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2158
EPWM_FED_LOAD_ON_CNTR_PERIOD
@ EPWM_FED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:846
EPWM_clearADCTriggerFlag
static void EPWM_clearADCTriggerFlag(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6544
EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD
@ EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:486
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9
Sync-in source is ECAP9 sync-out signal.
Definition: etpwm.h:271
EPWM_XCMP1_SHADOW1
@ EPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2112
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0
Sync-in source is ECAP0 sync-out signal.
Definition: etpwm.h:253
EPWM_XCMP_ACTIVE
#define EPWM_XCMP_ACTIVE
< XCMP set = Active
Definition: etpwm.h:2076
HRPWM_setMEPControlMode
static void HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, HRPWM_MEPCtrlMode mepCtrlMode)
Definition: etpwm.h:9379
EPWM_setDigitalCompareEventSyncMode
static void EPWM_setDigitalCompareEventSyncMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareSyncMode syncMode)
Definition: etpwm.h:7289
EPWM_DB_POLARITY_ACTIVE_HIGH
@ EPWM_DB_POLARITY_ACTIVE_HIGH
DB polarity is not inverted.
Definition: etpwm.h:782
EPWM_setActionQualifierContSWForceShadowMode
static void EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, EPWM_ActionQualifierContForce mode)
Definition: etpwm.h:4206
EPWM_DB_RED
@ EPWM_DB_RED
DB RED (Rising Edge Delay) mode.
Definition: etpwm.h:770
EPWM_XCompareReg
EPWM_XCompareReg
Definition: etpwm.h:2177
EPWM_LINK_WITH_EPWM_24
@ EPWM_LINK_WITH_EPWM_24
link current ePWM with ePWM24
Definition: etpwm.h:425
EPWM_ActionQualifierTriggerSource
EPWM_ActionQualifierTriggerSource
Definition: etpwm.h:547
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1
Time base counter equals XCMP1.
Definition: etpwm.h:2228
HRPWM_MEP_PHASE_CTRL
@ HRPWM_MEP_PHASE_CTRL
TBPHSHR controls MEP edge.
Definition: etpwm.h:1899
EPWM_SYNC_OUT_SOURCE_M
#define EPWM_SYNC_OUT_SOURCE_M
Definition: etpwm.h:79
EPWM_COUNTER_COMPARE_D
@ EPWM_COUNTER_COMPARE_D
counter compare D
Definition: etpwm.h:470
EPWM_CMPD_SHADOW1
@ EPWM_CMPD_SHADOW1
CMPD_SHADOW1.
Definition: etpwm.h:2181
EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW
@ EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW
Event when DCxL high DCxH low.
Definition: etpwm.h:951
EPWM_XMinMaxReg
EPWM_XMinMaxReg
Definition: etpwm.h:2200
EPWM_LINK_TBPRD
@ EPWM_LINK_TBPRD
link TBPRD:TBPRDHR registers
Definition: etpwm.h:443
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29
Trip source is INPUTXBAR out29 signal.
Definition: etpwm.h:2426
EPWM_INT_TBCTR_D_CMPD
#define EPWM_INT_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1236
EPWM_TZ_ADV_ACTION_EVENT_TZA_U
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_U
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up.
Definition: etpwm.h:999
EPWM_SOC_TBCTR_PERIOD
@ EPWM_SOC_TBCTR_PERIOD
Time-base counter equal to period.
Definition: etpwm.h:1298
EPWM_getGlobalLoadEventCount
static uint16_t EPWM_getGlobalLoadEventCount(uint32_t base)
Definition: etpwm.h:8596
HRPWM_XCMP5_SHADOW1
@ HRPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2022
EPWM_setTripZoneAdvDigitalCompareActionB
static void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5432
HRPWM_XCMP3_SHADOW3
@ HRPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2056
EPWM_AQ_OUTPUT_TOGGLE_ZERO
@ EPWM_AQ_OUTPUT_TOGGLE_ZERO
Time base counter equals zero and toggle the output pins.
Definition: etpwm.h:631
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18
Sync-in source is EPWM18 sync-out signal.
Definition: etpwm.h:225
HRPWM_setDeadbandMEPEdgeSelect
static void HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, HRPWM_MEPDeadBandEdgeMode mepDBEdge)
Definition: etpwm.h:9994
EPWM_DE_TRIP_SRC_CMPSSB4
@ EPWM_DE_TRIP_SRC_CMPSSB4
Trip source is CMPSSB4 signal.
Definition: etpwm.h:2460
EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT
Digital compare filter event.
Definition: etpwm.h:556
HRPWM_DB_MEP_CTRL_RED
@ HRPWM_DB_MEP_CTRL_RED
MEP controls Rising Edge Delay.
Definition: etpwm.h:1980
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0
Sync-in source is EPWM0 sync-out signal.
Definition: etpwm.h:189
EPWM_SOC_TBCTR_D_CMPC
@ EPWM_SOC_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1308
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14
Trip source is INPUTXBAR out14 signal.
Definition: etpwm.h:2396
EPWM_setOneShotSyncOutTrigger
static void EPWM_setOneShotSyncOutTrigger(uint32_t base, EPWM_OneShotSyncOutTrigger trigger)
Definition: etpwm.h:2893
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA
Time base counter down equals COMPA.
Definition: etpwm.h:574
EPWM_ActionQualifierEventAction
EPWM_ActionQualifierEventAction
Definition: etpwm.h:623
EPWM_disableXCMPMode
static void EPWM_disableXCMPMode(uint32_t base)
Definition: etpwm.h:10133
EPWM_setDigitalCompareWindowOffset
static void EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
Definition: etpwm.h:7134
EPWM_XCMP_6_CMPA
@ EPWM_XCMP_6_CMPA
Allocate XCMP1 - XCMP6 registers to CMPA.
Definition: etpwm.h:2266
EPWM_CMPD_SHADOW3
@ EPWM_CMPD_SHADOW3
CMPD_SHADOW3.
Definition: etpwm.h:2189
EPWM_SignalParams::tbClkDiv
EPWM_ClockDivider tbClkDiv
Time Base Counter Clock Divider.
Definition: etpwm.h:2610
EPWM_AQ_OUTPUT_NO_CHANGE
@ EPWM_AQ_OUTPUT_NO_CHANGE
No change in the output pins.
Definition: etpwm.h:597
EPWM_DE_TRIP_SRC_CMPSSA0
@ EPWM_DE_TRIP_SRC_CMPSSA0
Trip source is CMPSSA0 signal.
Definition: etpwm.h:2432
EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1
Digital compare event B 1.
Definition: etpwm.h:550
HRPWM_setHiResRisingEdgeDelay
static void HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
Definition: etpwm.h:9895
EPWM_XTBPRD_SHADOW3
@ EPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2166
EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1
Sync-in source is FSI-RX1 RX Trigger 1 signal.
Definition: etpwm.h:303
HRPWM_LOAD_ON_CNTR_ZERO
@ HRPWM_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:1912
EPWM_setMinDeadBandDelay
static void EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
Definition: etpwm.h:9045
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27
Sync-in source is EPWM27 sync-out signal.
Definition: etpwm.h:243
EPWM_XCMP3_SHADOW3
@ EPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2154
EPWM_LINK_WITH_EPWM_12
@ EPWM_LINK_WITH_EPWM_12
link current ePWM with ePWM12
Definition: etpwm.h:413
HRPWM_setChannelBOutputPath
static void HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
Definition: etpwm.h:9477
EPWM_enableInterrupt
static void EPWM_enableInterrupt(uint32_t base)
Definition: etpwm.h:5867
EPWM_setCMPShadowRegValue
static void EPWM_setCMPShadowRegValue(uint32_t base, EPWM_XCompareReg cmpReg, uint16_t cmpvalue)
Definition: etpwm.h:10299
EPWM_disableTripZoneAdvAction
static void EPWM_disableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:5237
EPWM_clearDiodeEmulationActive
static void EPWM_clearDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:11005
EPWM_DB_INPUT_EPWMA
#define EPWM_DB_INPUT_EPWMA
Input signal is ePWMA.
Definition: etpwm.h:793
HRPWM_XCMP5_ACTIVE
@ HRPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:2003
EPWM_setDeadBandCounterClock
static void EPWM_setDeadBandCounterClock(uint32_t base, EPWM_DeadBandClockMode clockMode)
Definition: etpwm.h:4802
EPWM_OSHT_SYNC_OUT_TRIG_RELOAD
@ EPWM_OSHT_SYNC_OUT_TRIG_RELOAD
Trigger is OSHT reload.
Definition: etpwm.h:335
EPWM_AQ_OUTPUT_HIGH_ZERO
@ EPWM_AQ_OUTPUT_HIGH_ZERO
Time base counter equals zero and set output pins to high.
Definition: etpwm.h:629
EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD
load on sync event or when counter is equal to period
Definition: etpwm.h:1572
HRPWM_ChannelBOutput
HRPWM_ChannelBOutput
Definition: etpwm.h:1928
EPWM_LINK_WITH_EPWM_2
@ EPWM_LINK_WITH_EPWM_2
link current ePWM with ePWM2
Definition: etpwm.h:403
EPWM_enableIllegalComboLogic
static void EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:9079
HRPWM_disablePeriodControl
static void HRPWM_disablePeriodControl(uint32_t base)
Definition: etpwm.h:9564
EPWM_DB_OUTPUT_A
@ EPWM_DB_OUTPUT_A
DB output is ePWMA.
Definition: etpwm.h:758
EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD
Clear CBC pulse when counter equals period.
Definition: etpwm.h:1150
EPWM_TripZoneDigitalCompareOutputEvent
EPWM_TripZoneDigitalCompareOutputEvent
Definition: etpwm.h:945
EPWM_SHADOW_LOAD_MODE_SYNC
@ EPWM_SHADOW_LOAD_MODE_SYNC
shadow to active load occurs only when a SYNC occurs
Definition: etpwm.h:380
EPWM_setTimeBaseCounterMode
static void EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
Definition: etpwm.h:3003
EPWM_PeriodLoadMode
EPWM_PeriodLoadMode
Definition: etpwm.h:345
EPWM_SignalParams::sysClkInHz
Float32 sysClkInHz
SYSCLK Frequency(in Hz)
Definition: etpwm.h:2608
EPWM_CurrentLink
EPWM_CurrentLink
Definition: etpwm.h:400
EPWM_setDeadBandDelayPolarity
static void EPWM_setDeadBandDelayPolarity(uint32_t base, EPWM_DeadBandDelayMode delayMode, EPWM_DeadBandPolarity polarity)
Definition: etpwm.h:4509
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15
Sync-in source is EPWM15 sync-out signal.
Definition: etpwm.h:219
EPWM_HSCLOCK_DIVIDER_1
@ EPWM_HSCLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:167
EPWM_setChopperFirstPulseWidth
static void EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
Definition: etpwm.h:4993
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4
Sync-in source is EPWM4 sync-out signal.
Definition: etpwm.h:197
EPWM_HSCLOCK_DIVIDER_14
@ EPWM_HSCLOCK_DIVIDER_14
Divide clock by 14.
Definition: etpwm.h:174
EPWM_AQ_OUTPUT_LOW_DOWN_T2
@ EPWM_AQ_OUTPUT_LOW_DOWN_T2
T2 event on count down and set output pins to low.
Definition: etpwm.h:710
EPWM_DCxxTRIPSEL
#define EPWM_DCxxTRIPSEL
Definition: etpwm.h:2589
HRPWM_MEPCtrlMode
HRPWM_MEPCtrlMode
Definition: etpwm.h:1895
EPWM_DiodeEmulationSignal
EPWM_DiodeEmulationSignal
Definition: etpwm.h:2474
EPWM_REGISTER_GROUP_DIGITAL_COMPARE
@ EPWM_REGISTER_GROUP_DIGITAL_COMPARE
Digital compare group.
Definition: etpwm.h:1735
EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0
Sync-in source is FSI-RX3 RX Trigger 0 signal.
Definition: etpwm.h:317
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8
Time base counter equals XCMP8.
Definition: etpwm.h:2242
EPWM_XCMP_7_CMPA
@ EPWM_XCMP_7_CMPA
Allocate XCMP1 - XCMP7 registers to CMPA.
Definition: etpwm.h:2268
EPWM_disableFallingEdgeDelayCountShadowLoadMode
static void EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4773
EPWM_clearEventTriggerInterruptFlag
static void EPWM_clearEventTriggerInterruptFlag(uint32_t base)
Definition: etpwm.h:6057
EPWM_DigitalCompareTripInput
EPWM_DigitalCompareTripInput
Definition: etpwm.h:1346
HRPWM_XCMP4_ACTIVE
@ HRPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:2001
EPWM_AQ_SW_OUTPUT_LOW
@ EPWM_AQ_SW_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:612
EPWM_enableDigitalCompareTripCombinationInput
static void EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7755
EPWM_SyncInPulseSource
EPWM_SyncInPulseSource
Definition: etpwm.h:185
EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2
T2 event on count down and toggle the output pins.
Definition: etpwm.h:714
EPWM_selectMinimumDeadBandReferenceSignal
static void EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8980
EPWM_DeadBandControlLoadMode
EPWM_DeadBandControlLoadMode
Definition: etpwm.h:806
EPWM_ActionQualifierSWOutput
EPWM_ActionQualifierSWOutput
Definition: etpwm.h:610
EPWM_setValleyDelayDivider
static void EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
Definition: etpwm.h:8362
EPWM_AQ_OUTPUT_ON_T1_COUNT_UP
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_UP
T1 event on count up.
Definition: etpwm.h:580
EPWM_clearTripZoneFlag
static void EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
Definition: etpwm.h:5674
HRPWM_setFallingEdgeDelayLoadMode
static void HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:10054
EPWM_ADCStartOfConversionType
EPWM_ADCStartOfConversionType
Definition: etpwm.h:1280
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28
Trip source is INPUTXBAR out28 signal.
Definition: etpwm.h:2424
EPWM_XCMP_2_CMPA
@ EPWM_XCMP_2_CMPA
Allocate XCMP1 - XCMP2 registers to CMPA.
Definition: etpwm.h:2258
EPWM_setValleyTriggerSource
static void EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
Definition: etpwm.h:8235
EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY
Definition: etpwm.h:1669
EPWM_setCountModeAfterSync
static void EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
Definition: etpwm.h:2655
EPWM_setTripZoneAdvAction
static void EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, EPWM_TripZoneAdvancedAction tzAdvAction)
Definition: etpwm.h:5330
EPWM_GL_LOAD_PULSE_SYNC
@ EPWM_GL_LOAD_PULSE_SYNC
load on sync event
Definition: etpwm.h:1568
EPWM_disableDigitalCompareWindowInverseMode
static void EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6880
EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO
load on sync event or when counter is equal to zero
Definition: etpwm.h:1570
EPWM_setChopperDutyCycle
static void EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
Definition: etpwm.h:4929
EPWM_INT_TBCTR_ETINTMIX
#define EPWM_INT_TBCTR_ETINTMIX
Time-base counter based on mix events.
Definition: etpwm.h:1220
EPWM_XCMP5_SHADOW1
@ EPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2120
EPWM_LINK_WITH_EPWM_18
@ EPWM_LINK_WITH_EPWM_18
link current ePWM with ePWM18
Definition: etpwm.h:419
EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA
Time base counter down equals COMPA and no change in the output pins.
Definition: etpwm.h:649
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25
Trip source is INPUTXBAR out25 signal.
Definition: etpwm.h:2418
EPWM_XCMP_XLOADCTL_SHDWLEVEL_0
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_0
Only Active register is available.
Definition: etpwm.h:2315
EPWM_setInterruptEventCount
static void EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:6004
EPWM_nobypassDiodeEmulationLogic
static void EPWM_nobypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10934
EPWM_CLOCK_DIVIDER_8
@ EPWM_CLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:152
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3
Trip source is INPUTXBAR out3 signal.
Definition: etpwm.h:2374
EPWM_TZ_ADV_ACTION_EVENT_TZA_D
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_D
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down.
Definition: etpwm.h:997
EPWM_getSyncStatus
static bool EPWM_getSyncStatus(uint32_t base)
Definition: etpwm.h:3188
HRPWM_XCMP7_SHADOW2
@ HRPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2045
HRPWM_XCMP8_SHADOW1
@ HRPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2028
EPWM_TZ_ADV_ACTION_LOW
@ EPWM_TZ_ADV_ACTION_LOW
low voltage state
Definition: etpwm.h:1013
EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:492
EPWM_COUNTER_MODE_UP
@ EPWM_COUNTER_MODE_UP
Up - count mode.
Definition: etpwm.h:360
EPWM_SOC_TBCTR_U_CMPD
@ EPWM_SOC_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1312
EPWM_setADCTriggerSource
static void EPWM_setADCTriggerSource(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, EPWM_ADCStartOfConversionSource socSource, uint16_t mixedSource)
Definition: etpwm.h:6315
EPWM_disableSplitXCMP
static void EPWM_disableSplitXCMP(uint32_t base)
Definition: etpwm.h:10177
EPWM_enableMinimumDeadBand
static void EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8818
EPWM_HSCLOCK_DIVIDER_6
@ EPWM_HSCLOCK_DIVIDER_6
Divide clock by 6.
Definition: etpwm.h:170
EPWM_XCMP_1_CMPA
@ EPWM_XCMP_1_CMPA
Allocate XCMP1 register to CMPA.
Definition: etpwm.h:2256
EPWM_getTripZoneFlagStatus
static uint16_t EPWM_getTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5546
EPWM_REGISTER_GROUP_GLOBAL_LOAD
@ EPWM_REGISTER_GROUP_GLOBAL_LOAD
Global load register group.
Definition: etpwm.h:1732
EPWM_GL_LOAD_PULSE_CNTR_PERIOD
@ EPWM_GL_LOAD_PULSE_CNTR_PERIOD
load when counter is equal to period
Definition: etpwm.h:1564
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2
Time base counter equals XCMP2.
Definition: etpwm.h:2230
EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2
T2 event on count up and no change in the output pins.
Definition: etpwm.h:700
EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0
Sync-in source is FSI-RX0 RX Trigger 0 signal.
Definition: etpwm.h:293
EPWM_getTimeBasePeriod
static uint16_t EPWM_getTimeBasePeriod(uint32_t base)
Definition: etpwm.h:3305
EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2
Sync-in source is FSI-RX0 RX Trigger 2 signal.
Definition: etpwm.h:297
EPWM_setValleySWDelayValue
static void EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
Definition: etpwm.h:8341
EPWM_DC_MODULE_A
@ EPWM_DC_MODULE_A
Digital Compare Module A.
Definition: etpwm.h:1476
EPWM_AQ_OUTPUT_A
@ EPWM_AQ_OUTPUT_A
ePWMxA output
Definition: etpwm.h:728
EPWM_GlobalLoadTrigger
EPWM_GlobalLoadTrigger
Definition: etpwm.h:1560
EPWM_HSCLOCK_DIVIDER_10
@ EPWM_HSCLOCK_DIVIDER_10
Divide clock by 10.
Definition: etpwm.h:172
EPWM_LINK_WITH_EPWM_0
@ EPWM_LINK_WITH_EPWM_0
link current ePWM with ePWM0
Definition: etpwm.h:401
EPWM_COUNT_MODE_DOWN_AFTER_SYNC
@ EPWM_COUNT_MODE_DOWN_AFTER_SYNC
Count down after sync event.
Definition: etpwm.h:137
EPWM_DC_WINDOW_START_TBCTR_ZERO
@ EPWM_DC_WINDOW_START_TBCTR_ZERO
Time base counter equals zero.
Definition: etpwm.h:1416
EPWM_AQ_OUTPUT_TOGGLE
@ EPWM_AQ_OUTPUT_TOGGLE
Toggle the output pins.
Definition: etpwm.h:600
EPWM_DigitalCompareCBCLatchClearEvent
EPWM_DigitalCompareCBCLatchClearEvent
Definition: etpwm.h:1544
EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1
Digital compare event A 1.
Definition: etpwm.h:548
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP14
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP14
Sync-in source is ECAP14 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:281
EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO
Shadow buffer 2 is in use.
Definition: etpwm.h:2338
EPWM_disableDiodeEmulationMonitorModeControl
static void EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:11051
EPWM_AQ_OUTPUT_HIGH_DOWN_T1
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T1
T1 event on count down and set output pins to high.
Definition: etpwm.h:696
EPWM_XCMP3_SHADOW1
@ EPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2116
EPWM_getDigitalCompareCaptureStatus
static bool EPWM_getDigitalCompareCaptureStatus(uint32_t base)
Definition: etpwm.h:7702
EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE
@ EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE
Valley capture trigged by software.
Definition: etpwm.h:1625
EPWM_setGlobalLoadOneShotLatch
static void EPWM_setGlobalLoadOneShotLatch(uint32_t base)
Definition: etpwm.h:8666
EPWM_AQ_SW_DISABLED
@ EPWM_AQ_SW_DISABLED
Software forcing disabled.
Definition: etpwm.h:611
HRPWM_XCMP3_SHADOW1
@ HRPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2018
EPWM_ADCStartOfConversionSource
EPWM_ADCStartOfConversionSource
Definition: etpwm.h:1292
HRPWM_XCMP5_SHADOW3
@ HRPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2060
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23
Trip source is INPUTXBAR out23 signal.
Definition: etpwm.h:2414
EPWM_disableDigitalCompareTripCombinationInput
static void EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7804
HRPWM_PWMSYNC_SOURCE_COMPD_DOWN
@ HRPWM_PWMSYNC_SOURCE_COMPD_DOWN
Counter equals COMPD when counting down.
Definition: etpwm.h:1954
EPWM_EmulationMode
EPWM_EmulationMode
Definition: etpwm.h:120
EPWM_XMIN_SHADOW3
@ EPWM_XMIN_SHADOW3
XMIN_SHADOW3.
Definition: etpwm.h:2216
EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2
Trip zone 2.
Definition: etpwm.h:553
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP11
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP11
Sync-in source is ECAP11 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:275
EPWM_DC_WINDOW_SOURCE_DCBEVT2
@ EPWM_DC_WINDOW_SOURCE_DCBEVT2
DC filter signal source is DCBEVT2.
Definition: etpwm.h:1461
EPWM_INT_TBCTR_U_CMPC
#define EPWM_INT_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1224
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25
Sync-in source is EPWM25 sync-out signal.
Definition: etpwm.h:239
EPWM_DC_EDGEFILT_EDGECNT_2
@ EPWM_DC_EDGEFILT_EDGECNT_2
Digital Compare Edge filter edge count = 3.
Definition: etpwm.h:1710
EPWM_INT_TBCTR_D_CMPB
#define EPWM_INT_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1234
EPWM_XCMP_ALLOC_CMPA
EPWM_XCMP_ALLOC_CMPA
Values that can be passed to EPWM_allocAXCMP() as the alloctype parameter.
Definition: etpwm.h:2252
EPWM_XMIN_ACTIVE
@ EPWM_XMIN_ACTIVE
XMIN_ACTIVE.
Definition: etpwm.h:2204
EPWM_LINK_WITH_EPWM_20
@ EPWM_LINK_WITH_EPWM_20
link current ePWM with ePWM20
Definition: etpwm.h:421
EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD
@ EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:830
EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2
Digital compare event A 2.
Definition: etpwm.h:549
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6
Time base counter equals XCMP6.
Definition: etpwm.h:2238
HRPWM_XCMP3_SHADOW2
@ HRPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2037
HRPWM_setSyncPulseSource
static void HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
Definition: etpwm.h:9640
HRPWM_setHiResTimeBasePeriod
static void HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
Definition: etpwm.h:9282
EPWM_LINK_WITH_EPWM_30
@ EPWM_LINK_WITH_EPWM_30
link current ePWM with ePWM30
Definition: etpwm.h:431
EPWM_enableDigitalCompareADCTrigger
static void EPWM_enableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7334
EPWM_DC_TYPE_DCAL
@ EPWM_DC_TYPE_DCAL
Digital Compare A Low.
Definition: etpwm.h:1333
EPWM_CounterCompareModule
EPWM_CounterCompareModule
Definition: etpwm.h:466
EPWM_SignalParams::tbHSClkDiv
EPWM_HSClockDivider tbHSClkDiv
Time Base Counter HS Clock Divider.
Definition: etpwm.h:2611
EPWM_XTBPRD_SHADOW1
@ EPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2128
EPWM_OSHT_SYNC_OUT_TRIG_SYNC
@ EPWM_OSHT_SYNC_OUT_TRIG_SYNC
Trigger is OSHT sync.
Definition: etpwm.h:334
HRPWM_CounterCompareModule
HRPWM_CounterCompareModule
Definition: etpwm.h:1964
EPWM_TZ_EVENT_DCXL_LOW
@ EPWM_TZ_EVENT_DCXL_LOW
Event when DCxL low.
Definition: etpwm.h:949
EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D
Digital Compare event A/B 1 while counting down.
Definition: etpwm.h:1030
HRPWM_setPhaseShift
static void HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
Definition: etpwm.h:9217
EPWM_DigitalCompareSyncMode
EPWM_DigitalCompareSyncMode
Definition: etpwm.h:1516
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15
Trip source is INPUTXBAR out15 signal.
Definition: etpwm.h:2398
EPWM_setTimeBaseCounter
static void EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
Definition: etpwm.h:2630
EPWM_COUNTER_COMPARE_A
@ EPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:467
EPWM_DC_EDGEFILT_MODE_BOTH
@ EPWM_DC_EDGEFILT_MODE_BOTH
Definition: etpwm.h:1694
EPWM_LINK_WITH_EPWM_13
@ EPWM_LINK_WITH_EPWM_13
link current ePWM with ePWM13
Definition: etpwm.h:414
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16
Sync-in source is EPWM16 sync-out signal.
Definition: etpwm.h:221
EPWM_SignalParams
Definition: etpwm.h:2603
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB
Time base counter up equals COMPB.
Definition: etpwm.h:576
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4
Sync-in source is ECAP4 sync-out signal.
Definition: etpwm.h:261
EPWM_XCMP1_SHADOW2
@ EPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2131
EPWM_enableTripZoneSignals
static void EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:5046
EPWM_DC_TRIP_TRIPIN13
@ EPWM_DC_TRIP_TRIPIN13
Trip 13.
Definition: etpwm.h:1359
HRPWM_XCMP7_SHADOW3
@ HRPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2064
EPWM_DC_EDGEFILT_EDGECNT_7
@ EPWM_DC_EDGEFILT_EDGECNT_7
Definition: etpwm.h:1720
HRPWM_XCMP2_SHADOW1
@ HRPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2016
EPWM_AQ_OUTPUT_B
@ EPWM_AQ_OUTPUT_B
ePWMxB output
Definition: etpwm.h:729
EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR
@ EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR
Trip zone clear group.
Definition: etpwm.h:1734
EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD
Time base counter equals period.
Definition: etpwm.h:570
EPWM_disableDigitalCompareBlankingWindow
static void EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6837
EPWM_SOC_TBCTR_ZERO
@ EPWM_SOC_TBCTR_ZERO
Time-base counter equal to zero.
Definition: etpwm.h:1296
EPWM_LINK_WITH_EPWM_29
@ EPWM_LINK_WITH_EPWM_29
link current ePWM with ePWM29
Definition: etpwm.h:430
EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY
Definition: etpwm.h:1675
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31
Trip source is INPUTXBAR out31 signal.
Definition: etpwm.h:2430
EPWM_setCounterCompareValue_opt_cmpC
static void EPWM_setCounterCompareValue_opt_cmpC(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3648
EPWM_LINK_WITH_EPWM_14
@ EPWM_LINK_WITH_EPWM_14
link current ePWM with ePWM14
Definition: etpwm.h:415
EPWM_setActionQualifierT1TriggerSource
static void EPWM_setActionQualifierT1TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3873
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17
Sync-in source is EPWM17 sync-out signal.
Definition: etpwm.h:223
EPWM_MINDB_BLOCK_A
#define EPWM_MINDB_BLOCK_A
Values that can be passed to.
Definition: etpwm.h:1747
EPWM_ActionQualifierOutputEvent
EPWM_ActionQualifierOutputEvent
Definition: etpwm.h:566
EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD
load on sync or when counter equals period
Definition: etpwm.h:533
EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE
Load mode is LOADMULTIPLE.
Definition: etpwm.h:2302
EPWM_DC_EDGEFILT_EDGECNT_0
@ EPWM_DC_EDGEFILT_EDGECNT_0
Digital Compare Edge filter edge count = 0.
Definition: etpwm.h:1706
EPWM_AQ_LOAD_ON_CNTR_ZERO
@ EPWM_AQ_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:523
EPWM_DC_TYPE_DCAH
@ EPWM_DC_TYPE_DCAH
Digital Compare A High.
Definition: etpwm.h:1332
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1
Sync-in source is EPWM1 sync-out signal.
Definition: etpwm.h:191
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31
Sync-in source is EPWM31 sync-out signal.
Definition: etpwm.h:251
EPWM_XCMP8_SHADOW3
@ EPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2164
HRPWM_OUTPUT_ON_B_INV_A
@ HRPWM_OUTPUT_ON_B_INV_A
Definition: etpwm.h:1932
EPWM_setGlobalLoadTrigger
static void EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
Definition: etpwm.h:8539
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3
Sync-in source is EPWM3 sync-out signal.
Definition: etpwm.h:195
EPWM_TZ_ACTION_EVENT_TZB
@ EPWM_TZ_ACTION_EVENT_TZB
TZ1 - TZ6, DCBEVT2, DCBEVT1.
Definition: etpwm.h:963
EPWM_getEventTriggerInterruptStatus
static bool EPWM_getEventTriggerInterruptStatus(uint32_t base)
Definition: etpwm.h:6036
EPWM_setXCMPActionQualifierAction
static void EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_XCMPActionQualifierOutputEvent event)
Definition: etpwm.h:10389
EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:494
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4
Time base counter equals XCMP4.
Definition: etpwm.h:2234
EPWM_CLOCK_DIVIDER_64
@ EPWM_CLOCK_DIVIDER_64
Divide clock by 64.
Definition: etpwm.h:155
EPWM_AQ_OUTPUT_TOGGLE_UP_T1
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T1
T1 event on count up and toggle the output pins.
Definition: etpwm.h:690
EPWM_selectDiodeEmulationTripSignal
static void EPWM_selectDiodeEmulationTripSignal(uint32_t base, uint32_t channel, uint32_t signal)
Definition: etpwm.h:10899
EPWM_allocAXCMP
static void EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
Definition: etpwm.h:10210
EPWM_LINK_WITH_EPWM_3
@ EPWM_LINK_WITH_EPWM_3
link current ePWM with ePWM3
Definition: etpwm.h:404
EPWM_SignalParams::tbCtrMode
EPWM_TimeBaseCountMode tbCtrMode
Time Base Counter Mode.
Definition: etpwm.h:2609
EPWM_setPhaseShift
static void EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
Definition: etpwm.h:3256
EPWM_enableDiodeEmulationMode
static void EPWM_enableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:10673
EPWM_DigitalCompareType
EPWM_DigitalCompareType
Definition: etpwm.h:1331
EPWM_COMP_LOAD_ON_SYNC_ONLY
@ EPWM_COMP_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:496
EPWM_REGISTER_GROUP_HR
@ EPWM_REGISTER_GROUP_HR
HRPWM register group.
Definition: etpwm.h:1731
EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA
Time base counter down equals COMPA and toggle the output pins.
Definition: etpwm.h:655
EPWM_LINK_WITH_EPWM_21
@ EPWM_LINK_WITH_EPWM_21
link current ePWM with ePWM21
Definition: etpwm.h:422
EPWM_forceEventTriggerInterrupt
static void EPWM_forceEventTriggerInterrupt(uint32_t base)
Definition: etpwm.h:6204
EPWM_selectXbarInput
static void EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
Definition: etpwm.h:9138
EPWM_setDiodeEmulationMode
static void EPWM_setDiodeEmulationMode(uint32_t base, EPWM_DiodeEmulationMode mode)
Definition: etpwm.h:10731
EPWM_DeadBandOutput
EPWM_DeadBandOutput
Definition: etpwm.h:757
EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U
Digital Compare event A/B 2 while counting up.
Definition: etpwm.h:1032
EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1
Sync-in source is FSI-RX0 RX Trigger 1 signal.
Definition: etpwm.h:295
EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
@ EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
Stop when counter completes whole cycle.
Definition: etpwm.h:124
EPWM_TZ_ADV_ACTION_EVENT_TZB_D
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_D
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down.
Definition: etpwm.h:993
EPWM_disableValleyHWDelay
static void EPWM_disableValleyHWDelay(uint32_t base)
Definition: etpwm.h:8318
EPWM_SOC_TBCTR_MIXED_EVENT
@ EPWM_SOC_TBCTR_MIXED_EVENT
Time-base counter equal to zero or period.
Definition: etpwm.h:1300
EPWM_setXCMPShadowBufPtrLoadOnce
static void EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
Definition: etpwm.h:10596
EPWM_setClockPrescaler
static void EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, EPWM_HSClockDivider highSpeedPrescaler)
Definition: etpwm.h:2701
EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB
Time base counter up equals COMPB and toggle the output pins.
Definition: etpwm.h:663
EPWM_getDigitalCompareBlankingWindowLengthCount
static uint16_t EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
Definition: etpwm.h:7196
EPWM_AQ_OUTPUT_LOW_UP_CMPB
@ EPWM_AQ_OUTPUT_LOW_UP_CMPB
Time base counter up equals COMPB and set output pins to low.
Definition: etpwm.h:659
EPWM_RED_LOAD_ON_CNTR_ZERO
@ EPWM_RED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:826
EPWM_HSCLOCK_DIVIDER_8
@ EPWM_HSCLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:171
EPWM_TZ_DC_OUTPUT_A2
@ EPWM_TZ_DC_OUTPUT_A2
Digital Compare output 2 A.
Definition: etpwm.h:933
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13
Trip source is INPUTXBAR out13 signal.
Definition: etpwm.h:2394
EPWM_SignalParams::dutyValB
Float32 dutyValB
Desired ePWMxB Signal Duty.
Definition: etpwm.h:2606
EPWM_lockRegisters
static void EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
Definition: etpwm.h:8793
HRPWM_disableAutoConversion
static void HRPWM_disableAutoConversion(uint32_t base)
Definition: etpwm.h:9522
EPWM_DE_TRIP_SRC_CMPSSA2
@ EPWM_DE_TRIP_SRC_CMPSSA2
Trip source is CMPSSA2 signal.
Definition: etpwm.h:2436
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12
Sync-in source is EPWM12 sync-out signal.
Definition: etpwm.h:213
HRPWM_XCMP2_ACTIVE
@ HRPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:1997
EPWM_INT_TBCTR_D_CMPC
#define EPWM_INT_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1228
EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2
T2 event on count down and no change in the output pins.
Definition: etpwm.h:708
EPWM_AQ_OUTPUT_TOGGLE_UP_T2
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T2
T2 event on count up and toggle the output pins.
Definition: etpwm.h:706
EPWM_XCMP8_ACTIVE
@ EPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:2107
EPWM_enableXLoad
static void EPWM_enableXLoad(uint32_t base)
Definition: etpwm.h:10456
EPWM_TZ_ACTION_DISABLE
@ EPWM_TZ_ACTION_DISABLE
disable action
Definition: etpwm.h:981
EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN
@ EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN
ePWM sync
Definition: etpwm.h:555
EPWM_forceADCTriggerEventCountInit
static void EPWM_forceADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6634
EPWM_getMinDeadBandDelay
static uint32_t EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
Definition: etpwm.h:9012
HRPWM_XCMP6_ACTIVE
@ HRPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:2005
EPWM_XCMP_NONE_CMPA
@ EPWM_XCMP_NONE_CMPA
Allocate 0 XCMP registers to CMPA.
Definition: etpwm.h:2254
EPWM_disableIllegalComboLogic
static void EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:9108
EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD
@ EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD
load on sync event or when counter is equal to period or zero
Definition: etpwm.h:1574
EPWM_disableActionQualifierShadowLoadMode
static void EPWM_disableActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule)
Definition: etpwm.h:3834
EPWM_setADCTriggerEventPrescale
static void EPWM_setADCTriggerEventPrescale(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t preScaleCount)
Definition: etpwm.h:6462
EPWM_enableInterruptEventCountInit
static void EPWM_enableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6080
EPWM_DiodeEmulationTripSource
EPWM_DiodeEmulationTripSource
Definition: etpwm.h:2366
EPWM_enableDigitalCompareCounterCapture
static void EPWM_enableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7618
EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE
Shadow buffer 1 is in use.
Definition: etpwm.h:2336
EPWM_DC_WINDOW_SOURCE_DCAEVT1
@ EPWM_DC_WINDOW_SOURCE_DCAEVT1
DC filter signal source is DCAEVT1.
Definition: etpwm.h:1458
EPWM_DigitalCompareEvent
EPWM_DigitalCompareEvent
Definition: etpwm.h:1490
HRPWM_enableAutoConversion
static void HRPWM_enableAutoConversion(uint32_t base)
Definition: etpwm.h:9500
EPWM_LINK_COMP_B
@ EPWM_LINK_COMP_B
link COMPB registers
Definition: etpwm.h:445
EPWM_LINK_WITH_EPWM_6
@ EPWM_LINK_WITH_EPWM_6
link current ePWM with ePWM6
Definition: etpwm.h:407
EPWM_enableDigitalCompareWindowInverseMode
static void EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6859
EPWM_XCMP4_SHADOW3
@ EPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2156
EPWM_LINK_WITH_EPWM_15
@ EPWM_LINK_WITH_EPWM_15
link current ePWM with ePWM15
Definition: etpwm.h:416
HRPWM_MEP_DUTY_PERIOD_CTRL
@ HRPWM_MEP_DUTY_PERIOD_CTRL
CMPAHR/CMPBHR or TBPRDHR controls MEP edge.
Definition: etpwm.h:1897
EPWM_disableDeadBandControlShadowLoadMode
static void EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
Definition: etpwm.h:4663
EPWM_DE_TRIP_SRC_CMPSSA5
@ EPWM_DE_TRIP_SRC_CMPSSA5
Trip source is CMPSSA5 signal.
Definition: etpwm.h:2442
EPWM_DB_POLARITY_ACTIVE_LOW
@ EPWM_DB_POLARITY_ACTIVE_LOW
DB polarity is inverted.
Definition: etpwm.h:783
EPWM_setRisingEdgeDelayCountShadowLoadMode
static void EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_RisingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4692
EPWM_TZ_ADV_ACTION_DISABLE
@ EPWM_TZ_ADV_ACTION_DISABLE
disable action
Definition: etpwm.h:1015
EPWM_CLOCK_DIVIDER_4
@ EPWM_CLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:151
EPWM_DC_EVENT_INPUT_SYNCED
@ EPWM_DC_EVENT_INPUT_SYNCED
DC input signal is synced with TBCLK.
Definition: etpwm.h:1518
EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD
@ EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD
Time base counter equals period and no change in the output pins.
Definition: etpwm.h:633
EPWM_LINK_DBRED
@ EPWM_LINK_DBRED
link DBRED registers
Definition: etpwm.h:449
EPWM_ValleyCounterEdge
EPWM_ValleyCounterEdge
Definition: etpwm.h:1649
EPWM_LockRegisterGroup
EPWM_LockRegisterGroup
Definition: etpwm.h:1730
EPWM_SYNC_IN_PULSE_SRC_DISABLE
@ EPWM_SYNC_IN_PULSE_SRC_DISABLE
Disable Sync-in.
Definition: etpwm.h:187
EPWM_setFallingEdgeDeadBandDelayInput
static void EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4581
EPWM_configureSignal
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE
Shadow buffer 3 is in use.
Definition: etpwm.h:2340
EPWM_SyncCountMode
EPWM_SyncCountMode
Definition: etpwm.h:136
EPWM_RED_LOAD_FREEZE
@ EPWM_RED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:832
EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0
Sync-in source is FSI-RX1 RX Trigger 0 signal.
Definition: etpwm.h:301
EPWM_HSCLOCK_DIVIDER_12
@ EPWM_HSCLOCK_DIVIDER_12
Divide clock by 12.
Definition: etpwm.h:173
HRPWM_Channel
HRPWM_Channel
Definition: etpwm.h:1865
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21
Sync-in source is EPWM21 sync-out signal.
Definition: etpwm.h:231
EPWM_setDeadBandControlShadowLoadMode
static void EPWM_setDeadBandControlShadowLoadMode(uint32_t base, EPWM_DeadBandControlLoadMode loadMode)
Definition: etpwm.h:4638
EPWM_DC_TRIP_TRIPIN4
@ EPWM_DC_TRIP_TRIPIN4
Trip 4.
Definition: etpwm.h:1350
EPWM_HSClockDivider
EPWM_HSClockDivider
Definition: etpwm.h:166
EPWM_RED_LOAD_ON_CNTR_PERIOD
@ EPWM_RED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:828
HRPWM_setOutputSwapMode
static void HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
Definition: etpwm.h:9444
EPWM_AQ_OUTPUT_LOW_DOWN_CMPA
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPA
Time base counter down equals COMPA and set output pins to low.
Definition: etpwm.h:651
EPWM_disableIndependentPulseLogic
static void EPWM_disableIndependentPulseLogic(uint32_t base)
Definition: etpwm.h:7970
HRPWM_MEP_CTRL_DISABLE
@ HRPWM_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1879
EPWM_AQ_OUTPUT_NO_CHANGE_ZERO
@ EPWM_AQ_OUTPUT_NO_CHANGE_ZERO
Time base counter equals zero and no change in the output pins.
Definition: etpwm.h:625
EPWM_DE_TRIP_SRC_CMPSSA1
@ EPWM_DE_TRIP_SRC_CMPSSA1
Trip source is CMPSSA1 signal.
Definition: etpwm.h:2434
EPWM_selectCaptureTripInput
static void EPWM_selectCaptureTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, uint8_t dcType)
Definition: etpwm.h:8027
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19
Trip source is INPUTXBAR out19 signal.
Definition: etpwm.h:2406
EPWM_AQ_OUTPUT_LOW
@ EPWM_AQ_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:598
EPWM_XCMP_1_CMPB
@ EPWM_XCMP_1_CMPB
Allocate XCMP5 register to CMPB.
Definition: etpwm.h:2282
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8
Trip source is INPUTXBAR out8 signal.
Definition: etpwm.h:2384
EPWM_getTimeBaseCounterDirection
static uint16_t EPWM_getTimeBaseCounterDirection(uint32_t base)
Definition: etpwm.h:3232
HRPWM_LoadMode
HRPWM_LoadMode
Definition: etpwm.h:1910
EPWM_XCMP1_ACTIVE
@ EPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:2093
EPWM_selectMinimumDeadBandAndOrLogic
static void EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8913
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19
Sync-in source is EPWM19 sync-out signal.
Definition: etpwm.h:227
EPWM_getDigitalCompareCaptureCount
static uint16_t EPWM_getDigitalCompareCaptureCount(uint32_t base)
Definition: etpwm.h:7725
EPWM_setDigitalCompareBlankingEvent
static void EPWM_setDigitalCompareBlankingEvent(uint32_t base, EPWM_DigitalCompareBlankingPulse blankingPulse, uint16_t mixedSource)
Definition: etpwm.h:6910
EPWM_INT_TBCTR_U_CMPD
#define EPWM_INT_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1232
EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE
Load mode is LOADONCE.
Definition: etpwm.h:2300
EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1
Sync-in source is FSI-RX3 RX Trigger 1 signal.
Definition: etpwm.h:319
EPWM_LINK_XLOAD
@ EPWM_LINK_XLOAD
link XLOAD registers
Definition: etpwm.h:451
EPWM_TZ_ADV_ACTION_EVENT_TZB_U
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_U
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up.
Definition: etpwm.h:995
EPWM_TZ_EVENT_DC_DISABLED
@ EPWM_TZ_EVENT_DC_DISABLED
Event is disabled.
Definition: etpwm.h:946
EPWM_XCMP_XLOADCTL_SHDWLEVEL_3
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_3
SHDW3, SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2321
EPWM_getInterruptEventCount
static uint16_t EPWM_getInterruptEventCount(uint32_t base)
Definition: etpwm.h:6182
HRPWM_XCMP8_SHADOW2
@ HRPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2047
EPWM_setDigitalCompareCounterShadowMode
static void EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
Definition: etpwm.h:7665
EPWM_SignalParams::freqInHz
Float32 freqInHz
Desired Signal Frequency(in Hz)
Definition: etpwm.h:2604
EPWM_ACTION_QUALIFIER_A
@ EPWM_ACTION_QUALIFIER_A
Action Qualifier A.
Definition: etpwm.h:510
EPWM_DE_TRIPH
#define EPWM_DE_TRIPH
Definition: etpwm.h:2516
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11
Sync-in source is EPWM11 sync-out signal.
Definition: etpwm.h:211
EPWM_DE_TRIP_SRC_CMPSSB5
@ EPWM_DE_TRIP_SRC_CMPSSB5
Trip source is CMPSSB5 signal.
Definition: etpwm.h:2462
EPWM_DE_TRIP_SRC_CMPSSA4
@ EPWM_DE_TRIP_SRC_CMPSSA4
Trip source is CMPSSA4 signal.
Definition: etpwm.h:2440
EPWM_XCMP_SHADOW3
#define EPWM_XCMP_SHADOW3
Definition: etpwm.h:2082
EPWM_TripZoneEvent
EPWM_TripZoneEvent
Definition: etpwm.h:961
HRPWM_XCMP5_SHADOW2
@ HRPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2041
HRPWM_XCMP3_ACTIVE
@ HRPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:1999
EPWM_DC_TRIP_COMBINATION
@ EPWM_DC_TRIP_COMBINATION
All Trips (Trip1 - Trip 15) are selected.
Definition: etpwm.h:1362
EPWM_GL_LOAD_PULSE_GLOBAL_FORCE
@ EPWM_GL_LOAD_PULSE_GLOBAL_FORCE
load on global force
Definition: etpwm.h:1584
EPWM_DC_TRIP_TRIPIN15
@ EPWM_DC_TRIP_TRIPIN15
Trip 15.
Definition: etpwm.h:1361
EPWM_disableGlobalLoadOneShotMode
static void EPWM_disableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8619
EPWM_INT_TBCTR_D_CMPA
#define EPWM_INT_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1226
EPWM_DigitalCompareBlankingPulse
EPWM_DigitalCompareBlankingPulse
Definition: etpwm.h:1412
HRPWM_getHiResCounterCompareValueOnly
static uint16_t HRPWM_getHiResCounterCompareValueOnly(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9852
EPWM_forceSyncPulse
static void EPWM_forceSyncPulse(uint32_t base)
Definition: etpwm.h:2728
EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY
Definition: etpwm.h:1672
EPWM_ValleyDelayMode
EPWM_ValleyDelayMode
Definition: etpwm.h:1661
EPWM_LINK_WITH_EPWM_11
@ EPWM_LINK_WITH_EPWM_11
link current ePWM with ePWM11
Definition: etpwm.h:412
EPWM_CLOCK_DIVIDER_1
@ EPWM_CLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:149
EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA
Time base counter up equals COMPA and no change in the output pins.
Definition: etpwm.h:641
EPWM_XCMP_3_CMPA
@ EPWM_XCMP_3_CMPA
Allocate XCMP1 - XCMP3 registers to CMPA.
Definition: etpwm.h:2260
EPWM_CAPTURE_GATE
#define EPWM_CAPTURE_GATE
Capture Gate.
Definition: etpwm.h:2553
EPWM_setSyncInPulseSource
static void EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
Definition: etpwm.h:2768
EPWM_DE_TRIP_SRC_CMPSSB8
@ EPWM_DE_TRIP_SRC_CMPSSB8
Trip source is CMPSSB8 signal.
Definition: etpwm.h:2468
EPWM_TZ_ACTION_HIGH_Z
@ EPWM_TZ_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:978
EPWM_allocBXCMP
static void EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
Definition: etpwm.h:10237
HRPWM_LOAD_ON_CNTR_PERIOD
@ HRPWM_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:1914
EPWM_setTripZoneAdvDigitalCompareActionA
static void EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5381
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6
Trip source is INPUTXBAR out6 signal.
Definition: etpwm.h:2380
EPWM_setDigitalCompareEdgeFilterMode
static void EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, EPWM_DigitalCompareEdgeFilterMode edgeMode)
Definition: etpwm.h:7027
EPWM_LINK_WITH_EPWM_23
@ EPWM_LINK_WITH_EPWM_23
link current ePWM with ePWM23
Definition: etpwm.h:424
EPWM_EMULATION_STOP_AFTER_NEXT_TB
@ EPWM_EMULATION_STOP_AFTER_NEXT_TB
Stop after next Time Base counter increment or decrement.
Definition: etpwm.h:122
EPWM_setGlobalLoadEventPrescale
static void EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
Definition: etpwm.h:8566
EPWM_SOC_TBCTR_D_CMPA
@ EPWM_SOC_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1306
EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL
@ EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL
signal source is unfiltered (DCAEVT1/2)
Definition: etpwm.h:1504
EPWM_SignalParams::invertSignalB
bool invertSignalB
Invert ePWMxB Signal if true.
Definition: etpwm.h:2607
EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2
Sync-in source is FSI-RX1 RX Trigger 2 signal.
Definition: etpwm.h:305
EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN
T2 event on count down.
Definition: etpwm.h:586
EPWM_setActionQualifierAction
static void EPWM_setActionQualifierAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_ActionQualifierOutputEvent event)
Definition: etpwm.h:3963
EPWM_DB_FED
@ EPWM_DB_FED
DB FED (Falling Edge Delay) mode.
Definition: etpwm.h:771
EPWM_disableMinimumDeadBand
static void EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8847
EPWM_TZ_DC_OUTPUT_B2
@ EPWM_TZ_DC_OUTPUT_B2
Digital Compare output 2 B.
Definition: etpwm.h:935
EPWM_setCounterCompareValue
static void EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, uint16_t compCount)
Definition: etpwm.h:3567
EPWM_TZ_ADV_ACTION_HIGH_Z
@ EPWM_TZ_ADV_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:1011
EPWM_getDigitalCompareBlankingWindowOffsetCount
static uint16_t EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
Definition: etpwm.h:7176
EPWM_invertMinimumDeadBandSignal
static void EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block, uint32_t invert)
Definition: etpwm.h:8878
EPWM_DE_TRIP_SRC_CMPSSA8
@ EPWM_DE_TRIP_SRC_CMPSSA8
Trip source is CMPSSA8 signal.
Definition: etpwm.h:2448
EPWM_DC_TYPE_DCBL
@ EPWM_DC_TYPE_DCBL
Digital Compare B Low.
Definition: etpwm.h:1335
EPWM_CLOCK_DIVIDER_2
@ EPWM_CLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:150
EPWM_DeadBandDelayMode
EPWM_DeadBandDelayMode
Definition: etpwm.h:769
EPWM_invertCaptureInputPolarity
static void EPWM_invertCaptureInputPolarity(uint32_t base, uint8_t polSel)
Definition: etpwm.h:7922
EPWM_enableDigitalCompareEdgeFilter
static void EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6978
HRPWM_XCMP4_SHADOW1
@ HRPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2020
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26
Sync-in source is EPWM26 sync-out signal.
Definition: etpwm.h:241
EPWM_DC_EDGEFILT_EDGECNT_3
@ EPWM_DC_EDGEFILT_EDGECNT_3
Digital Compare Edge filter edge count = 4.
Definition: etpwm.h:1712
HRPWM_LOAD_ON_CMPB_EQ
@ HRPWM_LOAD_ON_CMPB_EQ
load on translater event CMPB-3
Definition: etpwm.h:1918
EPWM_INT_TBCTR_U_CMPA
#define EPWM_INT_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1222
EPWM_setCounterCompareShadowLoadMode
static void EPWM_setCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule, EPWM_CounterCompareLoadMode loadMode)
Definition: etpwm.h:3439
EPWM_OneShotSyncOutTrigger
EPWM_OneShotSyncOutTrigger
Definition: etpwm.h:333
EPWM_setXCMPRegValue
static void EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:10265
EPWM_setRisingEdgeDelayCount
static void EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
Definition: etpwm.h:4828
EPWM_enableSplitXCMP
static void EPWM_enableSplitXCMP(uint32_t base)
Definition: etpwm.h:10155
EPWM_configCaptureGateInputPolarity
static void EPWM_configCaptureGateInputPolarity(uint32_t base, uint8_t polSel)
Definition: etpwm.h:7894
EPWM_TZ_EVENT_DCXH_HIGH
@ EPWM_TZ_EVENT_DCXH_HIGH
Event when DCxH high.
Definition: etpwm.h:948
EPWM_CLOCK_DIVIDER_16
@ EPWM_CLOCK_DIVIDER_16
Divide clock by 16.
Definition: etpwm.h:153
EPWM_DC_TRIP_TRIPIN12
@ EPWM_DC_TRIP_TRIPIN12
Trip 12.
Definition: etpwm.h:1358
EPWM_XCMP_2_CMPB
@ EPWM_XCMP_2_CMPB
Allocate XCMP5 - XCMP6 registers to CMPB.
Definition: etpwm.h:2284
EPWM_disableDiodeEmulationMode
static void EPWM_disableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:10699
EPWM_XCMP5_SHADOW2
@ EPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2139
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5
Trip source is INPUTXBAR out5 signal.
Definition: etpwm.h:2378
EPWM_LINK_WITH_EPWM_10
@ EPWM_LINK_WITH_EPWM_10
link current ePWM with ePWM10
Definition: etpwm.h:411
EPWM_enableADCTrigger
static void EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6232
EPWM_DC_TRIP_TRIPIN10
@ EPWM_DC_TRIP_TRIPIN10
Trip 10.
Definition: etpwm.h:1356
EPWM_XMIN_SHADOW2
@ EPWM_XMIN_SHADOW2
XMIN_SHADOW2.
Definition: etpwm.h:2212
HRPWM_XCMP8_SHADOW3
@ HRPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2066
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2
Sync-in source is ECAP2 sync-out signal.
Definition: etpwm.h:257
EPWM_setADCTriggerEventCountInitValue
static void EPWM_setADCTriggerEventCountInitValue(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t eventCount)
Definition: etpwm.h:6664
HRPWM_MEPDeadBandEdgeMode
HRPWM_MEPDeadBandEdgeMode
Definition: etpwm.h:1976
EPWM_SOC_TBCTR_U_CMPC
@ EPWM_SOC_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1304
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4
Trip source is INPUTXBAR out4 signal.
Definition: etpwm.h:2376
EPWM_VALLEY_COUNT_STOP_EDGE
@ EPWM_VALLEY_COUNT_STOP_EDGE
Valley count stop edge.
Definition: etpwm.h:1651
EPWM_COUNTER_MODE_STOP_FREEZE
@ EPWM_COUNTER_MODE_STOP_FREEZE
Stop - Freeze counter.
Definition: etpwm.h:363
EPWM_setCounterCompareValue_opt_cmpB
static void EPWM_setCounterCompareValue_opt_cmpB(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3629
EPWM_LINK_WITH_EPWM_17
@ EPWM_LINK_WITH_EPWM_17
link current ePWM with ePWM17
Definition: etpwm.h:418
EPWM_setDigitalCompareCBCLatchMode
static void EPWM_setDigitalCompareCBCLatchMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchMode latchMode)
Definition: etpwm.h:7467
EPWM_forceGlobalLoadOneShotEvent
static void EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
Definition: etpwm.h:8688
EPWM_getValleyEdgeStatus
static bool EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
Definition: etpwm.h:8390
EPWM_ActionQualifierOutput
EPWM_ActionQualifierOutput
Definition: etpwm.h:596
EPWM_DC_EDGEFILT_MODE_RISING
@ EPWM_DC_EDGEFILT_MODE_RISING
Digital Compare Edge filter low to high edge mode.
Definition: etpwm.h:1690
EPWM_TZ_ACTION_EVENT_DCBEVT2
@ EPWM_TZ_ACTION_EVENT_DCBEVT2
DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:967
EPWM_AQ_OUTPUT_LOW_UP_T1
@ EPWM_AQ_OUTPUT_LOW_UP_T1
T1 event on count up and set output pins to low.
Definition: etpwm.h:686
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14
Sync-in source is EPWM14 sync-out signal.
Definition: etpwm.h:217
EPWM_XCMP2_SHADOW1
@ EPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2114
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7
Trip source is INPUTXBAR out7 signal.
Definition: etpwm.h:2382
HRPWM_PWMSYNC_SOURCE_COMPC_DOWN
@ HRPWM_PWMSYNC_SOURCE_COMPC_DOWN
Counter equals COMPC when counting down.
Definition: etpwm.h:1950
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10
Sync-in source is EPWM10 sync-out signal.
Definition: etpwm.h:209
EPWM_ClockDivider
EPWM_ClockDivider
Definition: etpwm.h:148
EPWM_DB_INPUT_DB_RED
#define EPWM_DB_INPUT_DB_RED
Input signal is the output of Rising Edge delay.
Definition: etpwm.h:797
EPWM_LinkComponent
EPWM_LinkComponent
Definition: etpwm.h:442
EPWM_disableSyncOutPulseSource
static void EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2860
EPWM_disableADCTriggerEventCountInit
static void EPWM_disableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6605
EPWM_GL_LOAD_PULSE_CNTR_CMPD_D
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_D
load when counter is equal to cmpd and cmpd is decrementing
Definition: etpwm.h:1582
EPWM_XMAX_SHADOW1
@ EPWM_XMAX_SHADOW1
XMAX_SHADOW1.
Definition: etpwm.h:2206
HRPWM_SyncPulseSource
HRPWM_SyncPulseSource
Definition: etpwm.h:1942
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17
Trip source is INPUTXBAR out17 signal.
Definition: etpwm.h:2402
EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO
Valley capture trigged by when counter is equal to zero.
Definition: etpwm.h:1627
EPWM_AQ_OUTPUT_LOW_DOWN_CMPB
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPB
Time base counter down equals COMPB and set output pins to low.
Definition: etpwm.h:667
EPWM_DigitalCompareModule
EPWM_DigitalCompareModule
Definition: etpwm.h:1475
EPWM_getADCTriggerFlagStatus
static bool EPWM_getADCTriggerFlagStatus(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6517
EPWM_FED_LOAD_FREEZE
@ EPWM_FED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:850
EPWM_DigitalCompareCBCLatchMode
EPWM_DigitalCompareCBCLatchMode
Definition: etpwm.h:1530
EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3
Sync-in source is FSI-RX1 RX Trigger 3 signal.
Definition: etpwm.h:307
EPWM_SOC_B
@ EPWM_SOC_B
SOC B.
Definition: etpwm.h:1282
HRPWM_XCMP7_ACTIVE
@ HRPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:2007
EPWM_PERIOD_SHADOW_LOAD
@ EPWM_PERIOD_SHADOW_LOAD
PWM Period register access is through shadow register.
Definition: etpwm.h:347
EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D
Digital Compare event A/B 2 while counting down.
Definition: etpwm.h:1034
EPWM_DC_EDGEFILT_EDGECNT_1
@ EPWM_DC_EDGEFILT_EDGECNT_1
Digital Compare Edge filter edge count = 2.
Definition: etpwm.h:1708
HRPWM_setHiResCounterCompareValue
static void HRPWM_setHiResCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint16_t hrCompCount)
Definition: etpwm.h:9805
EPWM_DC_EVENT_SOURCE_FILT_SIGNAL
@ EPWM_DC_EVENT_SOURCE_FILT_SIGNAL
signal source is filtered (DCEVTFILT)
Definition: etpwm.h:1506
EPWM_DE_TRIP_SRC_CMPSSA3
@ EPWM_DE_TRIP_SRC_CMPSSA3
Trip source is CMPSSA3 signal.
Definition: etpwm.h:2438
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23
Sync-in source is EPWM23 sync-out signal.
Definition: etpwm.h:235
EPWM_LINK_WITH_EPWM_8
@ EPWM_LINK_WITH_EPWM_8
link current ePWM with ePWM8
Definition: etpwm.h:409
EPWM_AQ_OUTPUT_HIGH_UP_CMPB
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPB
Time base counter up equals COMPB and set output pins to high.
Definition: etpwm.h:661
EPWM_getTimeBaseCounterOverflowStatus
static bool EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
Definition: etpwm.h:3143
EPWM_DE_TRIP_SRC_CMPSSA9
@ EPWM_DE_TRIP_SRC_CMPSSA9
Trip source is CMPSSA9 signal.
Definition: etpwm.h:2450
EPWM_COUNTER_COMPARE_B
@ EPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:468
EPWM_SOC_DCxEVT1
@ EPWM_SOC_DCxEVT1
Event is based on DCxEVT1.
Definition: etpwm.h:1294
EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1
T1 event on count up and no change in the output pins.
Definition: etpwm.h:684
EPWM_DC_CBC_LATCH_ENABLED
@ EPWM_DC_CBC_LATCH_ENABLED
DC cycle-by-cycle(CBC) latch is enabled.
Definition: etpwm.h:1534
EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1
Trip zone 1.
Definition: etpwm.h:552
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28
Sync-in source is EPWM28 sync-out signal.
Definition: etpwm.h:245
EPWM_setXMINMAXRegValue
static void EPWM_setXMINMAXRegValue(uint32_t base, EPWM_XMinMaxReg xminmaxReg, uint16_t xcmpvalue)
Definition: etpwm.h:10335
EPWM_ValleyTriggerSource
EPWM_ValleyTriggerSource
Definition: etpwm.h:1623
EPWM_DC_TRIP_TRIPIN6
@ EPWM_DC_TRIP_TRIPIN6
Trip 6.
Definition: etpwm.h:1352
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5
Sync-in source is ECAP5 sync-out signal.
Definition: etpwm.h:263
EPWM_TZ_ADV_ACTION_TOGGLE
@ EPWM_TZ_ADV_ACTION_TOGGLE
toggle the output
Definition: etpwm.h:1014
EPWM_LINK_COMP_A
@ EPWM_LINK_COMP_A
link COMPA registers
Definition: etpwm.h:444
EPWM_enableGlobalLoad
static void EPWM_enableGlobalLoad(uint32_t base)
Definition: etpwm.h:8478
EPWM_disableValleyCapture
static void EPWM_disableValleyCapture(uint32_t base)
Definition: etpwm.h:8184
EPWM_TZ_ADV_ACTION_HIGH
@ EPWM_TZ_ADV_ACTION_HIGH
high voltage state
Definition: etpwm.h:1012
EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1
Valley capture trigged by DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:1637
EPWM_AdditionalActionQualifierEventAction
EPWM_AdditionalActionQualifierEventAction
Definition: etpwm.h:682
EPWM_configureDiodeEmulationTripSources
static void EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source, uint32_t tripLorH)
Definition: etpwm.h:10804
EPWM_XCMP7_SHADOW2
@ EPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2143
EPWM_forceCaptureEventLoad
static void EPWM_forceCaptureEventLoad(uint32_t base)
Definition: etpwm.h:7993
EPWM_enableChopper
static void EPWM_enableChopper(uint32_t base)
Definition: etpwm.h:4883
HRPWM_XTBPRD_SHADOW2
@ HRPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2049
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO
Time base counter equals zero.
Definition: etpwm.h:568
EPWM_DC_TRIP_TRIPIN3
@ EPWM_DC_TRIP_TRIPIN3
Trip 3.
Definition: etpwm.h:1349
EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1
Sync-in source is FSI-RX2 RX Trigger 1 signal.
Definition: etpwm.h:311
EPWM_enablePhaseShiftLoad
static void EPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2955
EPWM_setTripZoneDigitalCompareEventCondition
static void EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, EPWM_TripZoneDigitalCompareOutput dcType, EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
Definition: etpwm.h:5189
EPWM_AQ_SW_IMMEDIATE_LOAD
@ EPWM_AQ_SW_IMMEDIATE_LOAD
No shadow load mode. Immediate mode only.
Definition: etpwm.h:747
EPWM_DC_WINDOW_SOURCE_DCBEVT1
@ EPWM_DC_WINDOW_SOURCE_DCBEVT1
DC filter signal source is DCBEVT1.
Definition: etpwm.h:1460
EPWM_clearTimeBaseCounterOverflowEvent
static void EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
Definition: etpwm.h:3166
EPWM_DeadBandPolarity
EPWM_DeadBandPolarity
Definition: etpwm.h:781
EPWM_DC_TRIP_TRIPIN7
@ EPWM_DC_TRIP_TRIPIN7
Trip 7.
Definition: etpwm.h:1353
EPWM_LINK_WITH_EPWM_28
@ EPWM_LINK_WITH_EPWM_28
link current ePWM with ePWM28
Definition: etpwm.h:429
HRPWM_MEPEdgeMode
HRPWM_MEPEdgeMode
Definition: etpwm.h:1877
EPWM_disableADCTrigger
static void EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6265
EPWM_DB_LOAD_FREEZE
@ EPWM_DB_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:814
HRPWM_setCounterCompareShadowLoadEvent
static void HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9417
EPWM_disableCaptureTripCombinationInput
static void EPWM_disableCaptureTripCombinationInput(uint32_t base, uint16_t tripInput, uint8_t dcType)
Definition: etpwm.h:8123
EPWM_XCMP7_SHADOW3
@ EPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2162
EPWM_enableDiodeEmulationMonitorModeControl
static void EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:11028
EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL
No Shadow buffer is in use.
Definition: etpwm.h:2334
EPWM_enableDigitalCompareBlankingWindow
static void EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6816
EPWM_DC_WINDOW_START_TBCTR_PERIOD
@ EPWM_DC_WINDOW_START_TBCTR_PERIOD
Time base counter equals period.
Definition: etpwm.h:1414
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11
Trip source is INPUTXBAR out11 signal.
Definition: etpwm.h:2390
EPWM_TripZoneAdvancedAction
EPWM_TripZoneAdvancedAction
Definition: etpwm.h:1010
EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY
Definition: etpwm.h:1666
EPWM_CMPC_SHADOW2
@ EPWM_CMPC_SHADOW2
CMPC_SHADOW2.
Definition: etpwm.h:2183
HRPWM_MEP_CTRL_RISING_EDGE
@ HRPWM_MEP_CTRL_RISING_EDGE
MEP controls rising edge.
Definition: etpwm.h:1881
EPWM_DC_TRIP_TRIPIN14
@ EPWM_DC_TRIP_TRIPIN14
Trip 14.
Definition: etpwm.h:1360
EPWM_DE_CHANNEL_A
#define EPWM_DE_CHANNEL_A
< Diode emulation channel A
Definition: etpwm.h:2492
HRPWM_disablePhaseShiftLoad
static void HRPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:9607
EPWM_disableTripZoneOutput
static void EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5843
EPWM_XCMP_8_CMPA
@ EPWM_XCMP_8_CMPA
Allocate XCMP1 - XCMP8 registers to CMPA.
Definition: etpwm.h:2270
EPWM_XCMP6_SHADOW3
@ EPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2160
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26
Trip source is INPUTXBAR out26 signal.
Definition: etpwm.h:2420
EPWM_AQ_OUTPUT_TOGGLE_PERIOD
@ EPWM_AQ_OUTPUT_TOGGLE_PERIOD
Time base counter equals period and toggle the output pins.
Definition: etpwm.h:639
EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD
Valley capture trigged when counter is equal to zero or period.
Definition: etpwm.h:1631
EPWM_setActionQualifierSWAction
static void EPWM_setActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output)
Definition: etpwm.h:4328
EPWM_disableGlobalLoadRegisters
static void EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8764
EPWM_COUNTER_MODE_UP_DOWN
@ EPWM_COUNTER_MODE_UP_DOWN
Up - down - count mode.
Definition: etpwm.h:362
EPWM_DC_TRIP_TRIPIN11
@ EPWM_DC_TRIP_TRIPIN11
Trip 11.
Definition: etpwm.h:1357
EPWM_enableOneShotSync
static void EPWM_enableOneShotSync(uint32_t base)
Definition: etpwm.h:3057
EPWM_enableSyncOutPulseSource
static void EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2815
DebugP.h
EPWM_setAdditionalActionQualifierActionComplete
static void EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_AdditionalActionQualifierEventAction action)
Definition: etpwm.h:4166
EPWM_TripZoneAction
EPWM_TripZoneAction
Definition: etpwm.h:977
HRPWM_DB_MEP_CTRL_RED_FED
@ HRPWM_DB_MEP_CTRL_RED_FED
MEP controls both Falling and Rising edge delay.
Definition: etpwm.h:1984
EPWM_XCMP6_ACTIVE
@ EPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:2103
EPWM_LOCK_KEY
#define EPWM_LOCK_KEY
Definition: etpwm.h:2594
HRPWM_MEP_CTRL_FALLING_EDGE
@ HRPWM_MEP_CTRL_FALLING_EDGE
MEP controls falling edge.
Definition: etpwm.h:1883
EPWM_DE_TRIP_SRC_CMPSSB3
@ EPWM_DE_TRIP_SRC_CMPSSB3
Trip source is CMPSSB3 signal.
Definition: etpwm.h:2458
EPWM_DE_TRIP_SRC_CMPSSB6
@ EPWM_DE_TRIP_SRC_CMPSSB6
Trip source is CMPSSB6 signal.
Definition: etpwm.h:2464
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8
Sync-in source is ECAP8 sync-out signal.
Definition: etpwm.h:269
EPWM_DC_CBC_LATCH_DISABLED
@ EPWM_DC_CBC_LATCH_DISABLED
DC cycle-by-cycle(CBC) latch is disabled.
Definition: etpwm.h:1532
EPWM_LINK_GLDCTL2
@ EPWM_LINK_GLDCTL2
link GLDCTL2 registers
Definition: etpwm.h:448
EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD
Valley capture trigged by when counter is equal period.
Definition: etpwm.h:1629
EPWM_TripZoneAdvDigitalCompareEvent
EPWM_TripZoneAdvDigitalCompareEvent
Definition: etpwm.h:1026
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9
Trip source is INPUTXBAR out9 signal.
Definition: etpwm.h:2386
EPWM_selectMinimumDeadBandBlockingSignal
static void EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block, uint32_t blockingSignal)
Definition: etpwm.h:8947
EPWM_DigitalCompareEventSource
EPWM_DigitalCompareEventSource
Definition: etpwm.h:1502
EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC
@ EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC
Definition: etpwm.h:378
EPWM_setDiodeEmulationMonitorCounterThreshold
static void EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base, uint16_t threshold)
Definition: etpwm.h:11119
EPWM_enableCaptureTripCombinationInput
static void EPWM_enableCaptureTripCombinationInput(uint32_t base, uint16_t tripInput, uint8_t dcType)
Definition: etpwm.h:8071
EPWM_XCMP_ALLOC_CMPB
EPWM_XCMP_ALLOC_CMPB
Values that can be passed to EPWM_allocBXCMP() as the alloctype parameter.
Definition: etpwm.h:2280
EPWM_AQ_OUTPUT_ON_T2_COUNT_UP
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_UP
T2 event on count up.
Definition: etpwm.h:584
EPWM_enableIndependentPulseLogic
static void EPWM_enableIndependentPulseLogic(uint32_t base)
Definition: etpwm.h:7946
EPWM_getOneShotTripZoneFlagStatus
static uint16_t EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5608
EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB
Time base counter down equals COMPB and toggle the output pins.
Definition: etpwm.h:671
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7
Time base counter equals XCMP7.
Definition: etpwm.h:2240
HRPWM_OUTPUT_ON_B_NORMAL
@ HRPWM_OUTPUT_ON_B_NORMAL
ePWMxB output is normal.
Definition: etpwm.h:1930
EPWM_setTripZoneAction
static void EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, EPWM_TripZoneAction tzAction)
Definition: etpwm.h:5279
EPWM_FED_LOAD_ON_CNTR_ZERO
@ EPWM_FED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:844
EPWM_DigitalCompareEdgeFilterMode
EPWM_DigitalCompareEdgeFilterMode
Definition: etpwm.h:1688
EPWM_disableCaptureInEvent
static void EPWM_disableCaptureInEvent(uint32_t base)
Definition: etpwm.h:7865
HRPWM_XCMP6_SHADOW2
@ HRPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2043
EPWM_LINK_WITH_EPWM_7
@ EPWM_LINK_WITH_EPWM_7
link current ePWM with ePWM7
Definition: etpwm.h:408
EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB
Time base counter up equals COMPB and no change in the output pins.
Definition: etpwm.h:657
EPWM_setDigitalCompareFilterInput
static void EPWM_setDigitalCompareFilterInput(uint32_t base, EPWM_DigitalCompareFilterInput filterInput)
Definition: etpwm.h:6951
HRPWM_XCMP1_ACTIVE
@ HRPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:1995
EPWM_AQ_OUTPUT_LOW_DOWN_T1
@ EPWM_AQ_OUTPUT_LOW_DOWN_T1
T1 event on count down and set output pins to low.
Definition: etpwm.h:694
EPWM_INT_TBCTR_U_CMPB
#define EPWM_INT_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1230
EPWM_DC_EDGEFILT_EDGECNT_5
@ EPWM_DC_EDGEFILT_EDGECNT_5
Digital Compare Edge filter edge count = 6.
Definition: etpwm.h:1716
EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD
@ EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:848
EPWM_TZ_EVENT_DCXL_HIGH
@ EPWM_TZ_EVENT_DCXL_HIGH
Event when DCxL high.
Definition: etpwm.h:950
EPWM_TZ_ACTION_EVENT_DCAEVT1
@ EPWM_TZ_ACTION_EVENT_DCAEVT1
DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:964
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP15
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP15
Sync-in source is ECAP15 sync-out signal. Note : these are not applicable for AM263x.
Definition: etpwm.h:283
EPWM_TZ_EVENT_DCXH_LOW
@ EPWM_TZ_EVENT_DCXH_LOW
Event when DCxH low.
Definition: etpwm.h:947
EPWM_AQ_OUTPUT_HIGH_UP_CMPA
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPA
Time base counter up equals COMPA and set output pins to high.
Definition: etpwm.h:645
EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3
Sync-in source is FSI-RX0 RX Trigger 3 signal.
Definition: etpwm.h:299
EPWM_forceInterruptEventCountInit
static void EPWM_forceInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6129
EPWM_getDigitalCompareEdgeFilterEdgeCount
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
Definition: etpwm.h:7086
EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:490
EPWM_AQ_OUTPUT_HIGH
@ EPWM_AQ_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:599
EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD
load when counter is equal to zero or period
Definition: etpwm.h:1566
HRPWM_DB_MEP_CTRL_DISABLE
@ HRPWM_DB_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1978
EPWM_DC_TRIP_TRIPIN9
@ EPWM_DC_TRIP_TRIPIN9
Trip 9.
Definition: etpwm.h:1355
EPWM_XCMP3_ACTIVE
@ EPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:2097
EPWM_enableGlobalLoadOneShotMode
static void EPWM_enableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8643
EPWM_RisingEdgeDelayLoadMode
EPWM_RisingEdgeDelayLoadMode
Definition: etpwm.h:824
EPWM_SOC_TBCTR_D_CMPB
@ EPWM_SOC_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1314
EPWM_CycleByCycleTripZoneClearMode
EPWM_CycleByCycleTripZoneClearMode
Definition: etpwm.h:1146
EPWM_DE_COUNT_UP
#define EPWM_DE_COUNT_UP
Values that can be passed to EPWM_setDiodeEmulationMonitorModeStep()
Definition: etpwm.h:2503
EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD
shadow mode load when counter equals period
Definition: etpwm.h:743
EPWM_VALLEY_COUNT_START_EDGE
@ EPWM_VALLEY_COUNT_START_EDGE
Valley count start edge.
Definition: etpwm.h:1650
EPWM_XCMPActionQualifierOutputEvent
EPWM_XCMPActionQualifierOutputEvent
Values that can be passed to EPWM_setXCMPActionQualifierAction() as the event parameter.
Definition: etpwm.h:2226
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2
Trip source is INPUTXBAR out2 signal.
Definition: etpwm.h:2372
EPWM_DE_TRIP_SRC_CMPSSA7
@ EPWM_DE_TRIP_SRC_CMPSSA7
Trip source is CMPSSA7 signal.
Definition: etpwm.h:2446
EPWM_LINK_WITH_EPWM_27
@ EPWM_LINK_WITH_EPWM_27
link current ePWM with ePWM27
Definition: etpwm.h:428
EPWM_DC_EDGEFILT_MODE_FALLING
@ EPWM_DC_EDGEFILT_MODE_FALLING
Digital Compare Edge filter both edges mode.
Definition: etpwm.h:1692
EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD
shadow mode load when counter equals zero or period
Definition: etpwm.h:745
EPWM_XCMP8_SHADOW2
@ EPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2145
HRPWM_setHiResPhaseShift
static void HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
Definition: etpwm.h:9247
EPWM_XCMP3_SHADOW2
@ EPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2135
EPWM_DC_EVENT_2
@ EPWM_DC_EVENT_2
Digital Compare Event number 2.
Definition: etpwm.h:1492
HRPWM_XCMP2_SHADOW2
@ HRPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2035
EPWM_COUNTER_COMPARE_C
@ EPWM_COUNTER_COMPARE_C
counter compare C
Definition: etpwm.h:469
EPWM_disableDigitalCompareCounterCapture
static void EPWM_disableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7639
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6
Sync-in source is ECAP6 sync-out signal.
Definition: etpwm.h:265
EPWM_enableTripZoneInterrupt
static void EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5472
EPWM_setLutDecX
static void EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
Definition: etpwm.h:9172
EPWM_LINK_WITH_EPWM_19
@ EPWM_LINK_WITH_EPWM_19
link current ePWM with ePWM19
Definition: etpwm.h:420
EPWM_AQ_OUTPUT_LOW_PERIOD
@ EPWM_AQ_OUTPUT_LOW_PERIOD
Time base counter equals period and set output pins to low.
Definition: etpwm.h:635
EPWM_DiodeEmulationMode
EPWM_DiodeEmulationMode
Definition: etpwm.h:2352
EPWM_XCMP1_SHADOW3
@ EPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2150
EPWM_XCMP4_SHADOW1
@ EPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2118
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7
Sync-in source is ECAP7 sync-out signal.
Definition: etpwm.h:267
EPWM_setDigitalCompareWindowLength
static void EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
Definition: etpwm.h:7156
EPWM_setDiodeEmulationReentryDelay
static void EPWM_setDiodeEmulationReentryDelay(uint32_t base, uint8_t delay)
Definition: etpwm.h:10771
EPWM_CMPC_SHADOW1
@ EPWM_CMPC_SHADOW1
CMPC_SHADOW1.
Definition: etpwm.h:2179
EPWM_disableRisingEdgeDelayCountShadowLoadMode
static void EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4718
EPWM_DB_COUNTER_CLOCK_HALF_CYCLE
@ EPWM_DB_COUNTER_CLOCK_HALF_CYCLE
Dead band counter runs at 2*TBCLK rate.
Definition: etpwm.h:864
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5
Sync-in source is EPWM5 sync-out signal.
Definition: etpwm.h:199
EPWM_DC_TRIP_TRIPIN2
@ EPWM_DC_TRIP_TRIPIN2
Trip 2.
Definition: etpwm.h:1348
EPWM_XCMP_4_CMPB
@ EPWM_XCMP_4_CMPB
Allocate XCMP5 - XCMP8 registers to CMPB.
Definition: etpwm.h:2288
EPWM_forceXLoad
static void EPWM_forceXLoad(uint32_t base)
Definition: etpwm.h:10496
EPWM_getCounterCompareShadowStatus
static bool EPWM_getCounterCompareShadowStatus(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3740
EPWM_CMPD_SHADOW2
@ EPWM_CMPD_SHADOW2
CMPD_SHADOW2.
Definition: etpwm.h:2185
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3
Time base counter equals XCMP3.
Definition: etpwm.h:2232
EPWM_setPeriodLoadMode
static void EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
Definition: etpwm.h:2922
EPWM_AQ_OUTPUT_HIGH_DOWN_T2
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T2
T2 event on count down and set output pins to high.
Definition: etpwm.h:712
EPWM_setActionQualifierShadowLoadMode
static void EPWM_setActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule, EPWM_ActionQualifierLoadMode loadMode)
Definition: etpwm.h:3792
EPWM_setActionQualifierContSWForceAction
static void EPWM_setActionQualifierContSWForceAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierSWOutput output)
Definition: etpwm.h:4242
HRPWM_XCMP1_SHADOW1
@ HRPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2014
EPWM_SOC_TBCTR_U_CMPB
@ EPWM_SOC_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1310
EPWM_selectDiodeEmulationPWMsignal
static void EPWM_selectDiodeEmulationPWMsignal(uint32_t base, uint32_t channel, EPWM_DiodeEmulationSignal signal)
Definition: etpwm.h:10855
HRPWM_XCMP1_SHADOW3
@ HRPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2052
EPWM_FallingEdgeDelayLoadMode
EPWM_FallingEdgeDelayLoadMode
Definition: etpwm.h:842
EPWM_disablePhaseShiftLoad
static void EPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2976
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB
Time base counter down equals COMPB.
Definition: etpwm.h:578
EPWM_DE_LOW
@ EPWM_DE_LOW
a constant low signal
Definition: etpwm.h:2481
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0
Trip source is INPUTXBAR out0 signal.
Definition: etpwm.h:2368
EPWM_clearOneShotTripZoneFlag
static void EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
Definition: etpwm.h:5749
EPWM_DB_OUTPUT_B
@ EPWM_DB_OUTPUT_B
DB output is ePWMB.
Definition: etpwm.h:759
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20
Trip source is INPUTXBAR out20 signal.
Definition: etpwm.h:2408
EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO
Clear CBC pulse when counter equals zero.
Definition: etpwm.h:1148
EPWM_GL_LOAD_PULSE_CNTR_CMPD_U
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_U
load when counter is equal to cmpd and cmpd is incrementing
Definition: etpwm.h:1580
EPWM_setXCMPShadowLevel
static void EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
Definition: etpwm.h:10565
HRPWM_COUNTER_COMPARE_A
@ HRPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:1965
EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO
shadow mode load when counter equals zero
Definition: etpwm.h:741
EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1
T1 event on count down and toggle the output pins.
Definition: etpwm.h:698
EPWM_AQ_LOAD_ON_SYNC_ONLY
@ EPWM_AQ_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:537
HRPWM_XCMP4_SHADOW3
@ HRPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2058
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13
Sync-in source is EPWM13 sync-out signal.
Definition: etpwm.h:215
EPWM_LINK_COMP_D
@ EPWM_LINK_COMP_D
link COMPD registers
Definition: etpwm.h:447
EPWM_COUNT_MODE_UP_AFTER_SYNC
@ EPWM_COUNT_MODE_UP_AFTER_SYNC
Count up after sync event.
Definition: etpwm.h:138
EPWM_DC_EDGEFILT_EDGECNT_4
@ EPWM_DC_EDGEFILT_EDGECNT_4
Digital Compare Edge filter edge count = 5.
Definition: etpwm.h:1714
EPWM_enableValleyCapture
static void EPWM_enableValleyCapture(uint32_t base)
Definition: etpwm.h:8163
EPWM_setDeadBandDelayMode
static void EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, bool enableDelayMode)
Definition: etpwm.h:4462
EPWM_DE_TRIP_SRC_CMPSSB7
@ EPWM_DE_TRIP_SRC_CMPSSB7
Trip source is CMPSSB7 signal.
Definition: etpwm.h:2466
EPWM_CMPC_SHADOW3
@ EPWM_CMPC_SHADOW3
CMPC_SHADOW3.
Definition: etpwm.h:2187
EPWM_AQ_OUTPUT_HIGH_UP_T2
@ EPWM_AQ_OUTPUT_HIGH_UP_T2
T2 event on count up and set output pins to high.
Definition: etpwm.h:704
EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB
Time base counter down equals COMPB and no change in the output pins.
Definition: etpwm.h:665
EPWM_setActionQualifierT2TriggerSource
static void EPWM_setActionQualifierT2TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3908
EPWM_disableTripZoneSignals
static void EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:5089
EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA
Time base counter up equals COMPA and toggle the output pins.
Definition: etpwm.h:647
HRPWM_setXCMPRegValue
static void HRPWM_setXCMPRegValue(uint32_t base, HRPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:10082
EPWM_DC_TRIP_TRIPIN8
@ EPWM_DC_TRIP_TRIPIN8
Trip 8.
Definition: etpwm.h:1354
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30
Sync-in source is EPWM30 sync-out signal.
Definition: etpwm.h:249
EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2
Sync-in source is FSI-RX3 RX Trigger 2 signal.
Definition: etpwm.h:321
EPWM_XCMP8_SHADOW1
@ EPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2126
EPWM_DB_INPUT_EPWMB
#define EPWM_DB_INPUT_EPWMB
Input signal is ePWMB.
Definition: etpwm.h:795
EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5
Time base counter equals XCMP5.
Definition: etpwm.h:2236
EPWM_SOC_TBCTR_U_CMPA
@ EPWM_SOC_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1302
EPWM_LINK_WITH_EPWM_26
@ EPWM_LINK_WITH_EPWM_26
link current ePWM with ePWM26
Definition: etpwm.h:427
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1
Trip source is INPUTXBAR out1 signal.
Definition: etpwm.h:2370
EPWM_DE_TRIP_SRC_CMPSSA6
@ EPWM_DE_TRIP_SRC_CMPSSA6
Trip source is CMPSSA6 signal.
Definition: etpwm.h:2444
EPWM_XCMP_5_CMPA
@ EPWM_XCMP_5_CMPA
Allocate XCMP1 - XCMP5 registers to CMPA.
Definition: etpwm.h:2264
EPWM_clearCycleByCycleTripZoneFlag
static void EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
Definition: etpwm.h:5712
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24
Trip source is INPUTXBAR out24 signal.
Definition: etpwm.h:2416
EPWM_ACTION_QUALIFIER_B
@ EPWM_ACTION_QUALIFIER_B
Action Qualifier B.
Definition: etpwm.h:511
HRPWM_XCMP8_ACTIVE
@ HRPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:2009
EPWM_DC_MODULE_B
@ EPWM_DC_MODULE_B
Digital Compare Module B.
Definition: etpwm.h:1477
EPWM_DB_LOAD_ON_CNTR_PERIOD
@ EPWM_DB_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:810
EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1
Valley capture trigged by DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:1633
EPWM_PERIOD_DIRECT_LOAD
@ EPWM_PERIOD_DIRECT_LOAD
PWM Period register access is directly.
Definition: etpwm.h:349
EPWM_DCxCTL_STEP
#define EPWM_DCxCTL_STEP
Defines to be used by the driver.
Definition: etpwm.h:2588
EPWM_XCMPReg
EPWM_XCMPReg
Definition: etpwm.h:2091
EPWM_LINK_DBFED
@ EPWM_LINK_DBFED
link DBFED registers
Definition: etpwm.h:450
EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN
T1 event on count down.
Definition: etpwm.h:582
HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE
@ HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE
MEP controls both rising and falling edge.
Definition: etpwm.h:1885
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1
Sync-in source is ECAP1 sync-out signal.
Definition: etpwm.h:255
DebugP_assert
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:187
EPWM_ActionQualifierModule
EPWM_ActionQualifierModule
Definition: etpwm.h:509
EPWM_ActionQualifierOutputModule
EPWM_ActionQualifierOutputModule
Definition: etpwm.h:727
EPWM_LINK_WITH_EPWM_25
@ EPWM_LINK_WITH_EPWM_25
link current ePWM with ePWM25
Definition: etpwm.h:426
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30
Trip source is INPUTXBAR out30 signal.
Definition: etpwm.h:2428
EPWM_forceADCTrigger
static void EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6748
EPWM_DC_EVENT_INPUT_NOT_SYNCED
@ EPWM_DC_EVENT_INPUT_NOT_SYNCED
DC input signal is not synced with TBCLK.
Definition: etpwm.h:1520
EPWM_setDiodeEmulationMonitorModeStep
static void EPWM_setDiodeEmulationMonitorModeStep(uint32_t base, uint32_t direction, uint8_t stepsize)
Definition: etpwm.h:11080
EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2
Digital compare event B 2.
Definition: etpwm.h:551
HRPWM_XCMP2_SHADOW3
@ HRPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2054
EPWM_DigitalCompareFilterInput
EPWM_DigitalCompareFilterInput
Definition: etpwm.h:1457
EPWM_setXCMPLoadMode
static void EPWM_setXCMPLoadMode(uint32_t base, EPWM_XCMPXloadCtlLoadMode mode)
Definition: etpwm.h:10523
EPWM_TZ_DC_OUTPUT_B1
@ EPWM_TZ_DC_OUTPUT_B1
Digital Compare output 1 B.
Definition: etpwm.h:934
EPWM_enableTripZone2Signals
static void EPWM_enableTripZone2Signals(uint32_t base, uint16_t tzSignal)
Definition: etpwm.h:5118
EPWM_AQ_OUTPUT_LOW_UP_CMPA
@ EPWM_AQ_OUTPUT_LOW_UP_CMPA
Time base counter up equals COMPA and set output pins to low.
Definition: etpwm.h:643
EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load on sync or when counter equals zero or period
Definition: etpwm.h:535
EPWM_LINK_WITH_EPWM_1
@ EPWM_LINK_WITH_EPWM_1
link current ePWM with ePWM1
Definition: etpwm.h:402
EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2
Valley capture trigged by DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:1639
EPWM_LINK_WITH_EPWM_4
@ EPWM_LINK_WITH_EPWM_4
link current ePWM with ePWM4
Definition: etpwm.h:405
EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0
Sync-in source is FSI-RX2 RX Trigger 0 signal.
Definition: etpwm.h:309
EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD
@ EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:812
EPWM_disableXLoad
static void EPWM_disableXLoad(uint32_t base)
Definition: etpwm.h:10476
EPWM_AQ_OUTPUT_LOW_UP_T2
@ EPWM_AQ_OUTPUT_LOW_UP_T2
T2 event on count up and set output pins to low.
Definition: etpwm.h:702
EPWM_getValleyCount
static uint16_t EPWM_getValleyCount(uint32_t base)
Definition: etpwm.h:8436
EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3
Trip zone 3.
Definition: etpwm.h:554
EPWM_disableDigitalCompareEdgeFilter
static void EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:7000
EPWM_COUNTER_MODE_DOWN
@ EPWM_COUNTER_MODE_DOWN
Down - count mode.
Definition: etpwm.h:361
HRPWM_enablePhaseShiftLoad
static void HRPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:9586
EPWM_XMAX_SHADOW2
@ EPWM_XMAX_SHADOW2
XMAX_SHADOW2.
Definition: etpwm.h:2210
EPWM_DE_TRIP_SRC_CMPSSB9
@ EPWM_DE_TRIP_SRC_CMPSSB9
Trip source is CMPSSB9 signal.
Definition: etpwm.h:2470
EPWM_SOC_TBCTR_D_CMPD
@ EPWM_SOC_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1316
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20
Sync-in source is EPWM20 sync-out signal.
Definition: etpwm.h:229
EPWM_enableXCMPMode
static void EPWM_enableXCMPMode(uint32_t base)
Definition: etpwm.h:10113
EPWM_enableCaptureInEvent
static void EPWM_enableCaptureInEvent(uint32_t base)
Definition: etpwm.h:7840
EPWM_DIODE_EMULATION_OST
@ EPWM_DIODE_EMULATION_OST
Diode Emulation mode is One Shot.
Definition: etpwm.h:2356
HRPWM_CHANNEL_B
@ HRPWM_CHANNEL_B
HRPWM B.
Definition: etpwm.h:1867
EPWM_disableCounterCompareShadowLoadMode
static void EPWM_disableCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3509
HRPWM_enablePeriodControl
static void HRPWM_enablePeriodControl(uint32_t base)
Definition: etpwm.h:9543
EPWM_XCMP4_SHADOW2
@ EPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2137
EPWM_DE_SYNC_TRIPHorL
@ EPWM_DE_SYNC_TRIPHorL
synchronized version of TRIPH or TRIPL signal
Definition: etpwm.h:2477
EPWM_TZ_ACTION_EVENT_DCBEVT1
@ EPWM_TZ_ACTION_EVENT_DCBEVT1
DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:966
EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD
Clear CBC latch when counter equals period.
Definition: etpwm.h:1548
EPWM_GL_LOAD_PULSE_CNTR_ZERO
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO
load when counter is equal to zero
Definition: etpwm.h:1562
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9
Sync-in source is EPWM9 sync-out signal.
Definition: etpwm.h:207
EPWM_DIODE_EMULATION_CBC
@ EPWM_DIODE_EMULATION_CBC
Diode Emulation mode is Cycle by Cycle.
Definition: etpwm.h:2354
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21
Trip source is INPUTXBAR out21 signal.
Definition: etpwm.h:2410
EPWM_disableInterrupt
static void EPWM_disableInterrupt(uint32_t base)
Definition: etpwm.h:5888
EPWM_disableGlobalLoad
static void EPWM_disableGlobalLoad(uint32_t base)
Definition: etpwm.h:8500
EPWM_setRisingEdgeDeadBandDelayInput
static void EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4543
EPWM_XMAX_ACTIVE
@ EPWM_XMAX_ACTIVE
XMAX_ACTIVE.
Definition: etpwm.h:2202
EPWM_XCMP_SHADOW2
#define EPWM_XCMP_SHADOW2
XCMP set = Shadow 3.
Definition: etpwm.h:2080
EPWM_selectDigitalCompareCBCLatchClearEvent
static void EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
Definition: etpwm.h:7525
HRPWM_COUNTER_COMPARE_B
@ HRPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:1966
HRPWM_setCounterCompareValue
static void HRPWM_setCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint32_t compCount)
Definition: etpwm.h:9713
EPWM_setValleyTriggerEdgeCounts
static void EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, uint16_t stopCount)
Definition: etpwm.h:8267
EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4
Sync-in source is Input XBAR out4 signal.
Definition: etpwm.h:285
EPWM_XCMP6_SHADOW2
@ EPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2141
EPWM_disableChopper
static void EPWM_disableChopper(uint32_t base)
Definition: etpwm.h:4904
EPWM_setActionQualifierContSWForceAction_opt_outputs
static void EPWM_setActionQualifierContSWForceAction_opt_outputs(uint32_t base, uint8_t outputAB)
Definition: etpwm.h:4298
EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3
Sync-in source is FSI-RX2 RX Trigger 3 signal.
Definition: etpwm.h:315
EPWM_disableDigitalCompareSyncEvent
static void EPWM_disableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7427
EPWM_LINK_COMP_C
@ EPWM_LINK_COMP_C
link COMPC registers
Definition: etpwm.h:446
EPWM_disableDigitalCompareADCTrigger
static void EPWM_disableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7365
HRPWM_XCMP7_SHADOW1
@ HRPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2026
EPWM_COMP_LOAD_ON_CNTR_PERIOD
@ EPWM_COMP_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:484
EPWM_HSCLOCK_DIVIDER_4
@ EPWM_HSCLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:169
EPWM_XCMP_3_CMPB
@ EPWM_XCMP_3_CMPB
Allocate XCMP5 - XCMP7 registers to CMPB.
Definition: etpwm.h:2286
HRPWM_DB_MEP_CTRL_FED
@ HRPWM_DB_MEP_CTRL_FED
MEP controls Falling Edge Delay.
Definition: etpwm.h:1982
EPWM_getCounterCompareValue
static uint16_t EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3690
EPWM_bypassDiodeEmulationLogic
static void EPWM_bypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10958
EPWM_startOneShotSync
static void EPWM_startOneShotSync(uint32_t base)
Definition: etpwm.h:3101
EPWM_AQ_OUTPUT_LOW_ZERO
@ EPWM_AQ_OUTPUT_LOW_ZERO
Time base counter equals zero and set output pins to low.
Definition: etpwm.h:627
EPWM_MINDB_BLOCK_B
#define EPWM_MINDB_BLOCK_B
Definition: etpwm.h:1749
HRPWM_setTranslatorRemainder
static void HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
Definition: etpwm.h:9678
HRPWM_XCMP4_SHADOW2
@ HRPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2039
EPWM_XTBPRD_ACTIVE
@ EPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:2109
EPWM_PeriodShadowLoadMode
EPWM_PeriodShadowLoadMode
Definition: etpwm.h:373
EPWM_DE_TRIPL
#define EPWM_DE_TRIPL
Values that can be passed to EPWM_configureDiodeEmulationTripSources()
Definition: etpwm.h:2514
EPWM_enableGlobalLoadRegisters
static void EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8723
EPWM_AQ_OUTPUT_HIGH_PERIOD
@ EPWM_AQ_OUTPUT_HIGH_PERIOD
Time base counter equals period and set output pins to high.
Definition: etpwm.h:637
EPWM_disableTripZone2Signals
static void EPWM_disableTripZone2Signals(uint32_t base, uint16_t tzSignal)
Definition: etpwm.h:5147
EPWM_CLOCK_DIVIDER_128
@ EPWM_CLOCK_DIVIDER_128
Divide clock by 128.
Definition: etpwm.h:156
EPWM_CounterCompareLoadMode
EPWM_CounterCompareLoadMode
Definition: etpwm.h:480
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6
Sync-in source is EPWM6 sync-out signal.
Definition: etpwm.h:201
EPWM_TZ_ACTION_EVENT_TZA
@ EPWM_TZ_ACTION_EVENT_TZA
TZ1 - TZ6, DCAEVT2, DCAEVT1.
Definition: etpwm.h:962
HRPWM_setRisingEdgeDelayLoadMode
static void HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:10024
EPWM_setDigitalCompareEventSource
static void EPWM_setDigitalCompareEventSource(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareEventSource dcEventSource)
Definition: etpwm.h:7234
HRPWM_XTBPRD_SHADOW3
@ HRPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2068
EPWM_XCMP6_SHADOW1
@ EPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2122
EPWM_AQ_LOAD_ON_CNTR_PERIOD
@ EPWM_AQ_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:525
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7
Sync-in source is EPWM7 sync-out signal.
Definition: etpwm.h:203
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3
Sync-in source is ECAP3 sync-out signal.
Definition: etpwm.h:259
EPWM_disableTripZoneInterrupt
static void EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5510
EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX
@ EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX
Time base counter blank pulse mix.
Definition: etpwm.h:1420
EPWM_DeadBandClockMode
EPWM_DeadBandClockMode
Definition: etpwm.h:860
EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2
Valley capture trigged by DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:1635
EPWM_XCMPXloadCtlLoadMode
EPWM_XCMPXloadCtlLoadMode
Definition: etpwm.h:2298
EPWM_XCMP4_ACTIVE
@ EPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:2099
EPWM_forceTripZoneEvent
static void EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
Definition: etpwm.h:5784
EPWM_setInterruptEventCountInitValue
static void EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:6154
HRPWM_PWMSYNC_SOURCE_PERIOD
@ HRPWM_PWMSYNC_SOURCE_PERIOD
Counter equals Period.
Definition: etpwm.h:1944
EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3
Sync-in source is FSI-RX3 RX Trigger 3 signal.
Definition: etpwm.h:323
HRPWM_getHiResTimeBasePeriod
static uint16_t HRPWM_getHiResTimeBasePeriod(uint32_t base)
Definition: etpwm.h:9307
EPWM_GL_LOAD_PULSE_CNTR_CMPC_D
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_D
load when counter is equal to cmpc and cmpc is decrementing
Definition: etpwm.h:1578
EPWM_DE_COUNT_DOWN
#define EPWM_DE_COUNT_DOWN
Definition: etpwm.h:2505
EPWM_XMAX_SHADOW3
@ EPWM_XMAX_SHADOW3
XMAX_SHADOW3.
Definition: etpwm.h:2214
EPWM_TZ_ACTION_EVENT_DCAEVT2
@ EPWM_TZ_ACTION_EVENT_DCAEVT2
DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:965
EPWM_setInterruptSource
static void EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource, uint16_t mixedSource)
Definition: etpwm.h:5924
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2
Sync-in source is EPWM2 sync-out signal.
Definition: etpwm.h:193
EPWM_DC_TYPE_DCBH
@ EPWM_DC_TYPE_DCBH
Digital Compare B High.
Definition: etpwm.h:1334
EPWM_enableDigitalCompareSyncEvent
static void EPWM_enableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7396
EPWM_clearSyncEvent
static void EPWM_clearSyncEvent(uint32_t base)
Definition: etpwm.h:3209
EPWM_XCMP_XLOADCTL_SHDWLEVEL_2
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_2
SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2319
EPWM_EMULATION_FREE_RUN
@ EPWM_EMULATION_FREE_RUN
Free run.
Definition: etpwm.h:126
EPWM_getDigitalCompareCBCLatchStatus
static bool EPWM_getDigitalCompareCBCLatchStatus(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent)
Definition: etpwm.h:7577
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22
Sync-in source is EPWM22 sync-out signal.
Definition: etpwm.h:233
EPWM_setDigitalCompareEdgeFilterEdgeCount
static void EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
Definition: etpwm.h:7061
EPWM_XCMP_XLOADCTL_SHDWLEVEL_1
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_1
SHDW1 and Active registers are available.
Definition: etpwm.h:2317
EPWM_AQ_LOAD_FREEZE
@ EPWM_AQ_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:529
EPWM_XCMP7_ACTIVE
@ EPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:2105
EPWM_DC_TRIP_TRIPIN5
@ EPWM_DC_TRIP_TRIPIN5
Trip 5.
Definition: etpwm.h:1351
HRPWM_PWMSYNC_SOURCE_COMPC_UP
@ HRPWM_PWMSYNC_SOURCE_COMPC_UP
Counter equals COMPC when counting up.
Definition: etpwm.h:1948
EPWM_VALLEY_DELAY_MODE_SW_DELAY
@ EPWM_VALLEY_DELAY_MODE_SW_DELAY
Delay value equals the offset value defines by software.
Definition: etpwm.h:1663
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10
Trip source is INPUTXBAR out10 signal.
Definition: etpwm.h:2388
EPWM_XTBPRD_SHADOW2
@ EPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2147
EPWM_XCMP2_SHADOW2
@ EPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2133
EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27
Trip source is INPUTXBAR out27 signal.
Definition: etpwm.h:2422
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA
Time base counter up equals COMPA.
Definition: etpwm.h:572
EPWM_XCMP7_SHADOW1
@ EPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2124
EPWM_XCMP5_ACTIVE
@ EPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:2101
EPWM_setTimeBasePeriod
static void EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
Definition: etpwm.h:3285
HRPWM_CHANNEL_A
@ HRPWM_CHANNEL_A
HRPWM A.
Definition: etpwm.h:1866
EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
@ EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
Dead band counter runs at TBCLK rate.
Definition: etpwm.h:862
EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20
Sync-in source is Input XBAR out20 signal.
Definition: etpwm.h:287
EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29
Sync-in source is EPWM29 sync-out signal.
Definition: etpwm.h:247
EPWM_XCMP_XLOADCTL_SHDWBUFPTR
EPWM_XCMP_XLOADCTL_SHDWBUFPTR
Definition: etpwm.h:2332
EPWM_DC_WINDOW_SOURCE_DCAEVT2
@ EPWM_DC_WINDOW_SOURCE_DCAEVT2
DC filter signal source is DCAEVT2.
Definition: etpwm.h:1459
EPWM_LINK_WITH_EPWM_31
@ EPWM_LINK_WITH_EPWM_31
link current ePWM with ePWM31
Definition: etpwm.h:432
HRPWM_getCounterCompareValue
static uint32_t HRPWM_getCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9759
EPWM_DC_TRIP_TRIPIN1
@ EPWM_DC_TRIP_TRIPIN1
Trip 1.
Definition: etpwm.h:1347
EPWM_DB_LOAD_ON_CNTR_ZERO
@ EPWM_DB_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:808
EPWM_TZ_DC_OUTPUT_A1
@ EPWM_TZ_DC_OUTPUT_A1
Digital Compare output 1 A.
Definition: etpwm.h:932
EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB
Time base counter down equals COMPB and set output pins to high.
Definition: etpwm.h:669