AM261x MCU+ SDK: soc_rcm.h File Reference

| AM261x MCU+ SDK 26.00.00 |

Data Structures | Macros | Functions
soc_rcm.h File Reference

Go to the source code of this file.

## Data Structures
struct | SOC_RcmClkSrcInfo
struct | SOC_RcmXTALInfo
struct | SOC_RcmADPLLJConfig_t
struct | SOC_RcmPllHsDivOutConfig

## Macros
#define | SOC_RCM_FREQ_MHZ2HZ(x) ((x) * 1000 * 1000)
#define | SOC_RCM_FREQ_HZ2MHZ(x) ((x) / (1000 * 1000))
#define | SOC_RCM_R5_FREQ_400MHZ (0x0U)
#define | SOC_RCM_R5_FREQ_500MHZ (0x1U)
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL
#define | RCM_PLL_HSDIV_OUTPUT_IDX0 (0)
#define | RCM_PLL_HSDIV_OUTPUT_IDX1 (1)
#define | RCM_PLL_HSDIV_OUTPUT_IDX2 (2)
#define | RCM_PLL_HSDIV_OUTPUT_IDX3 (3)
#define | RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)

## Enumerations
SOC Warm Reset Causes
enum | SOC_WarmResetCause { SOC_WarmResetCause_POWER_ON_RESET = 0x41U, SOC_WarmResetCause_MSS_WDT0 = 0x42U, SOC_WarmResetCause_MSS_WDT1 = 0x44U, SOC_WarmResetCause_MSS_WDT2 = 0x48U, SOC_WarmResetCause_MSS_WDT3 = 0x50U, SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ = 0x60U, SOC_WarmResetCause_EXT_PAD_RESET = 0x40U, SOC_WarmResetCause_HSM_WDT = 0xC0U, SOC_WarmResetCause_DBG_RESET = 0x140U, SOC_WarmResetCause_TEMP_SENSOR0_RESET = 0x240U, SOC_WarmResetCause_TEMP_SENSOR1_RESET = 0x440U }
SOC Warm Reset Sources
enum | SOC_WarmResetSource { SOC_WarmResetSource_PAD_BYPASS = CSL_TOP_RCM_WARM_RESET_CONFIG_PAD_BYPASS_MASK, SOC_WarmResetSource_DEBUGSS = CSL_TOP_RCM_WARM_RESET_CONFIG_DEBUGSS_RST_EN_MASK, SOC_WarmResetSource_TSENSE0 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE0_RST_EN_MASK, SOC_WarmResetSource_TSENSE1 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE1_RST_EN_MASK, SOC_WarmResetSource_WDOG0 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG0_RST_EN_MASK, SOC_WarmResetSource_WDOG1 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG1_RST_EN_MASK }
SOC programmable values for WARM_RSTTIME1/2/3 registers and
the corresponding delays in ns/us/ms.
enum | SOC_RcmWarm_ResetTime123 { SOC_WARM_RESET_PAD_TIME_500NS = 0U, SOC_WARM_RESET_PAD_TIME_1US, SOC_WARM_RESET_PAD_TIME_2US, SOC_WARM_RESET_PAD_TIME_4US, SOC_WARM_RESET_PAD_TIME_8US, SOC_WARM_RESET_PAD_TIME_16US, SOC_WARM_RESET_PAD_TIME_32US, SOC_WARM_RESET_PAD_TIME_64US, SOC_WARM_RESET_PAD_TIME_128US, SOC_WARM_RESET_PAD_TIME_256US, SOC_WARM_RESET_PAD_TIME_512US, SOC_WARM_RESET_PAD_TIME_1024US, SOC_WARM_RESET_PAD_TIME_2048US, SOC_WARM_RESET_PAD_TIME_4096US, SOC_WARM_RESET_PAD_TIME_8192US, SOC_WARM_RESET_PAD_TIME_16384US }
SOC RCM Reset Causes
enum | SOC_RcmResetCause { SOC_RcmResetCause_POWER_ON_RESET = 0x0U, SOC_RcmResetCause_WARM_RESET = 0x1U, SOC_RcmResetCause_STC_RESET = 0x2U, SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U, SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U, SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U, SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U, SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U, SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U, SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U, SOC_RcmResetCause_POR_RST_CTRL0 = 0xAU, SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xBU }
SOC R5F subsystems
enum | SOC_Rcmr5fssNum { r5fss0 = 0x0U, r5fss1 = 0x1U }
SOC Peripheral Ids
enum | SOC_RcmPeripheralId { SOC_RcmPeripheralId_MCAN0, SOC_RcmPeripheralId_MCAN1, SOC_RcmPeripheralId_OSPI0, SOC_RcmPeripheralId_OSPI1, SOC_RcmPeripheralId_RTI0, SOC_RcmPeripheralId_RTI1, SOC_RcmPeripheralId_RTI2, SOC_RcmPeripheralId_RTI3, SOC_RcmPeripheralId_WDT0, SOC_RcmPeripheralId_WDT1, SOC_RcmPeripheralId_MCSPI0, SOC_RcmPeripheralId_MCSPI1, SOC_RcmPeripheralId_MCSPI2, SOC_RcmPeripheralId_MCSPI3, SOC_RcmPeripheralId_MMC0, SOC_RcmPeripheralId_ICSSM0_CORE, SOC_RcmPeripheralId_ICSSM0_UART0, SOC_RcmPeripheralId_ICSSM1_CORE, SOC_RcmPeripheralId_ICSSM1_UART0, SOC_RcmPeripheralId_CPTS, SOC_RcmPeripheralId_CPSW_5_50_250, SOC_RcmPeripheralId_GPMC, SOC_RcmPeripheralId_CONTROLSS_PLL, SOC_RcmPeripheralId_I2C, SOC_RcmPeripheralId_LIN0_UART0, SOC_RcmPeripheralId_LIN1_UART1, SOC_RcmPeripheralId_LIN2_UART2, SOC_RcmPeripheralId_LIN3_UART3 }
SOC Peripheral clock sources
enum | SOC_RcmPeripheralClockSource { SOC_RcmPeripheralClockSource_XTALCLK, SOC_RcmPeripheralClockSource_SYS_CLK, SOC_RcmPeripheralClockSource_WUCPUCLK, SOC_RcmPeripheralClockSource_EXT_REFCLK, SOC_RcmPeripheralClockSource_RCCLK10M, SOC_RcmPeripheralClockSource_RCCLK32K, SOC_RcmPeripheralClockSource_CTPS_GENF0, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT3, SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2 }
SOC PLL frequency output IDs
enum | SOC_RcmPllFoutFreqId { RCM_PLL_FOUT_FREQID_CLK_500MHZ, RCM_PLL_FOUT_FREQID_CLK_900MHZ, RCM_PLL_FOUT_FREQID_CLK_960MHZ, RCM_PLL_FOUT_FREQID_CLK_1000MHZ, RCM_PLL_FOUT_FREQID_CLK_2000MHZ }
SOC XTAL frequency IDs
enum | SOC_RcmXtalFreqId { RCM_XTAL_FREQID_CLK_25MHZ }
enum | SOC_RcmPllId { RCM_PLLID_CORE, RCM_PLLID_ETH, RCM_PLLID_PER, RCM_PLLID_XTALCLK, RCM_PLLID_WUCPUCLK, RCM_PLLID_RCCLK32K, RCM_PLLID_RCCLK10M, RCM_PLLID_EXTREFCLK }
SOC HSDIVIDER IDs
enum | SOC_RcmPllHSDIVOutId { RCM_PLLHSDIV_OUT_0, RCM_PLLHSDIV_OUT_1, RCM_PLLHSDIV_OUT_2, RCM_PLLHSDIV_OUT_3, RCM_PLLHSDIV_OUT_NONE }

## Functions
void | SOC_rcmCoreApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
| Configure CORE PLL. More...
void | SOC_rcmEthApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
| Configure ETH PLL. More...
uint32_t | SOC_rcmCoreApllRelockPreRequisite (void)
| Pre-requisite sequence to Re-configure CORE PLL. More...
void | SOC_rcmSetR5ClockSource (uint32_t r5ClkSrc)
| Set R5 clock source. More...
void | SOC_rcmCoreApllHSDivConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
| Configure CORE PLL HSDIVIDERS. More...
void | SOC_rcmPerApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
| Configure PER PLL. More...
void | SOC_rcmsetR5SysClock (uint32_t cr5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
| Set R5FSS and Sysclk frequency (Root clock configuration) More...
void | SOC_rcmsetTraceClock (uint32_t traceFreqHz)
| Set Trace clock frequency. More...
void | SOC_rcmsetClkoutClock (uint32_t clkout0FreqHz, uint32_t clkout1FreqHz)
| Set CLKOUT clock frequency. More...
int32_t | SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
| Set module clock (IP clock configuration) More...
SOC_RcmResetCause | SOC_rcmGetResetCause (SOC_Rcmr5fssNum r5fssNum)
| Get R5FSS reset cause. More...
int32_t | SOC_rcmEnablePeripheralClock (SOC_RcmPeripheralId periphId, uint32_t enable)
| Enable/disable module clock (IP clock configuration) More...
int32_t | SOC_rcmSetR5Clock (uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
| Set R5SS0/R5SS1 and SysClk frequency. More...
uint32_t | SOC_rcmGetR5Clock (uint32_t cpuId)
| Get R5SS0/1 frequency. More...
void | SOC_rcmR5ConfigLockStep (uint32_t cpuId)
| Configure R5 in lock step mode. More...
void | SOC_rcmR5ConfigDualCore (uint32_t cpuId)
| Configure R5 in dual core mode. More...
void | SOC_rcmR5SS0TriggerReset (void)
| Trigger R5 core reset. More...
void | SOC_rcmCoreR5FUnhalt (uint32_t cpuId)
| Unhalt R5 cores. More...
void | SOC_rcmStartMemInitTCMA (uint32_t cpuId)
| Start memory initialization for R5 TCMA. More...
void | SOC_rcmWaitMemInitTCMA (uint32_t cpuId)
| Wait memory initialization to complete for R5 TCMA. More...
void | SOC_rcmStartMemInitTCMB (uint32_t cpuId)
| Start memory initialization for R5 TCMB. More...
void | SOC_rcmWaitMemInitTCMB (uint32_t cpuId)
| Wait memory initialization to complete for R5 TCMB. More...
void | SOC_rcmMemInitMailboxMemory (void)
| Wait memory initialization to complete for Mailbox memory. More...
void | SOC_rcmMemInitL2Memory (void)
| Wait memory initialization to complete for L2 Bank2 and Bank3 memory. More...
void | SOC_rcmR5SS0PowerOnReset (void)
| Reset R5SS0 Core. More...
void | SOC_rcmR5SS1TriggerReset (void)
| Trigger R5SS1 core reset. More...
void | SOC_rcmR5SS1PowerOnReset (void)
| Reset R5SS1 Core. More...
uint32_t | SOC_rcmIsR5FInLockStepMode (uint32_t r5fClusterGroupId)
| Return R5SS status operating in lockstep or dual core mode. More...
void | SOC_generateSwWarmReset (void)
| Generate SW WARM reset. More...
void | SOC_configureWarmResetSource (uint32_t source)
| Configure WARM reset source. More...
SOC_WarmResetCause | SOC_getWarmResetCause (void)
| Returns cause of WARM reset. More...
void | SOC_clearWarmResetCause (void)
| Clear Reset Cause register. More...
void | SOC_configureWarmResetOutputDelay (uint16_t opDelayValue)
| Program output delay on warm reset Pad 1. More...
void | SOC_configureWarmResetInputRiseDelay (uint16_t inpRiseDelayValue)
| Program input rise delay on warm reset Pad 2. More...
void | SOC_configureWarmResetInputFallDelay (uint16_t inpFallDelayValue)
| Program output delay on warm reset Pad 3. More...