AM261x MCU+ SDK: sdfm.h Source File

| AM261x MCU+ SDK 26.00.00 |

sdfm/v0/sdfm.h
Go to the documentation of this file.
1 /********************************************************************
2 * Copyright (C) 2021 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
42 #ifndef SDFM_V0_H_
43 #define SDFM_V0_H_
44
45 //*****************************************************************************
46 //
47 // If building with a C++ compiler, make all of the definitions in this header
48 // have a C binding.
49 //
50 //*****************************************************************************
51
52 #ifdef __cplusplus
53 extern "C"
54 {
55 #endif
56
57 //*****************************************************************************
58 //
60 //
61 //*****************************************************************************
62
63 #include <stdbool.h>
64 #include <stdint.h>
65 #include <drivers/hw_include/cslr_sdfm.h>
66 #include <drivers/hw_include/cslr_soc.h>
67 #include <drivers/hw_include/hw_types.h>
68 #include <kernel/dpl/DebugP.h>
69
70 //*****************************************************************************
71 //
72 // Defines for the API.
73 //
74 //*****************************************************************************
76 #define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C))
77
79 #define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U))
80
83 #define SDFM_GET_LOW_THRESHOLD_BOTH(C1, C2) \
84 ((((uint32_t)(SDFM_GET_LOW_THRESHOLD(C2))) << 16U) | \
85 ((uint32_t)(SDFM_GET_LOW_THRESHOLD(C1))))
86
89 #define SDFM_GET_HIGH_THRESHOLD_BOTH(C1, C2) \
90 ((((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C2))) << 16U) | \
91 ((uint32_t)(SDFM_GET_HIGH_THRESHOLD(C1))))
92
94 #define SDFM_SET_OSR(X) (((X) - 1) << 8U)
95
97 #define SDFM_SHIFT_VALUE(X) ((X) << 2U)
98
100 #define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L))
101
103 #define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U)
104
106 #define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X))
107
109 #define SDFM_FILTER_DISABLE (0x0U)
110 #define SDFM_FILTER_ENABLE (0x2U)
111
112 //*****************************************************************************
113 //
114 // Defines for SDFM register offsets. Added for internal use. Not to be used by
115 // application.
116 //
117 //*****************************************************************************
119 #define SDFM_SDFIL_OFFSET (CSL_SDFM_SDCTLPARM2 - CSL_SDFM_SDCTLPARM1)
120
122 #define SDFM_DIGFIL_OFFSET (CSL_SDFM_SDCOMP2CTL - CSL_SDFM_SDCOMP1CTL)
123
125 #define SDFM_SDFLT1CMPHx_OFFSET (CSL_SDFM_SDFLT1CMPH2 - CSL_SDFM_SDFLT1CMPH1)
126
128 #define SDFM_SDFLT1CMPLx_OFFSET (CSL_SDFM_SDFLT1CMPL2 - CSL_SDFM_SDFLT1CMPL1)
129
130 //*****************************************************************************
131 //
132 // Define to mask out the bits in the SDCOMPHFILCTL register that aren't
133 // associated with comparator event filter configurations. Added for internal
134 // use, not to be used in application code.
135 //
136 //*****************************************************************************
137 #define SDFM_COMPEVT_FILTER_CONFIG_M (CSL_SDFM_SDCOMP1EVT1FLTCTL_SAMPWIN_MASK | \
138 CSL_SDFM_SDCOMP1EVT1FLTCTL_THRESH_MASK)
139
140 //*****************************************************************************
141 //
142 // Define to mask out the bits in the SDCOMPLOCK register that aren't
143 // associated with lock configuration. Added for internal use, not to be used
144 // in application code.
145 //
146 //*****************************************************************************
147 #define SDFM_COMPEVT_FILTER_LOCK_M (SDFM_SDCOMPLOCK_SDCOMPCTL | \
148 SDFM_SDCOMPLOCK_COMP)
149
150 //*****************************************************************************
151 //
152 // Values that can be passed to SDFM_enableSynchronizer() or
153 // SDFM_disableSynchronizer() as syncConfig parameter.
154 //
155 //*****************************************************************************
157 #define SDFM_CLOCK_SYNCHRONIZER CSL_SDFM_SDCTLPARM1_SDCLKSYNC_MASK
158 #define SDFM_DATA_SYNCHRONIZER CSL_SDFM_SDCTLPARM1_SDDATASYNC_MASK
160
161 //*****************************************************************************
162 //
164 //
165 //*****************************************************************************
166 #define SDFM_OUTPUT_WITHIN_THRESHOLD (0)
167 #define SDFM_OUTPUT_ABOVE_THRESHOLD (1)
168 #define SDFM_OUTPUT_BELOW_THRESHOLD (2)
169
170 //*****************************************************************************
171 //
174 //
175 //*****************************************************************************
176 #define SDFM_FILTER_1 (0)
177 #define SDFM_FILTER_2 (1)
178 #define SDFM_FILTER_3 (2)
179 #define SDFM_FILTER_4 (3)
180
181 //*****************************************************************************
182 //
185 //
186 //*****************************************************************************
188 #define SDFM_FILTER_SINC_FAST (0x00)
189 #define SDFM_FILTER_SINC_1 (0x10)
191 #define SDFM_FILTER_SINC_2 (0x20)
193 #define SDFM_FILTER_SINC_3 (0x30)
195
196 //*****************************************************************************
197 //
200 //
201 //*****************************************************************************
203 #define SDFM_MODULATOR_CLK_EQUAL_DATA_RATE (0)
204
205 //*****************************************************************************
206 //
209 //
210 //*****************************************************************************
212 #define SDFM_DATA_FORMAT_16_BIT (0)
213 #define SDFM_DATA_FORMAT_32_BIT (1)
215
216 //*****************************************************************************
217 //
220 //
221 //*****************************************************************************
223 #define SDFM_DATA_READY_SOURCE_DIRECT (0)
224 #define SDFM_DATA_READY_SOURCE_FIFO (1)
226
227 //*****************************************************************************
228 //
231 //
232 //*****************************************************************************
233 #define SDFM_SYNC_PWM0_SOCA (0)
234 #define SDFM_SYNC_PWM0_SOCB (1)
235 #define SDFM_SYNC_PWM1_SOCA (2)
236 #define SDFM_SYNC_PWM1_SOCB (3)
237 #define SDFM_SYNC_PWM2_SOCA (4)
238 #define SDFM_SYNC_PWM2_SOCB (5)
239 #define SDFM_SYNC_PWM3_SOCA (6)
240 #define SDFM_SYNC_PWM3_SOCB (7)
241 #define SDFM_SYNC_PWM4_SOCA (8)
242 #define SDFM_SYNC_PWM4_SOCB (9)
243 #define SDFM_SYNC_PWM5_SOCA (10)
244 #define SDFM_SYNC_PWM5_SOCB (11)
245 #define SDFM_SYNC_PWM6_SOCA (12)
246 #define SDFM_SYNC_PWM6_SOCB (13)
247 #define SDFM_SYNC_PWM7_SOCA (14)
248 #define SDFM_SYNC_PWM7_SOCB (15)
249 #define SDFM_SYNC_PWM8_SOCA (16)
250 #define SDFM_SYNC_PWM8_SOCB (17)
251 #define SDFM_SYNC_PWM9_SOCA (18)
252 #define SDFM_SYNC_PWM9_SOCB (19)
253 #define SDFM_SYNC_PWM10_SOCA (20)
254 #define SDFM_SYNC_PWM10_SOCB (21)
255 #define SDFM_SYNC_PWM11_SOCA (22)
256 #define SDFM_SYNC_PWM11_SOCB (23)
257 #define SDFM_SYNC_PWM12_SOCA (24)
258 #define SDFM_SYNC_PWM12_SOCB (25)
259 #define SDFM_SYNC_PWM13_SOCA (26)
260 #define SDFM_SYNC_PWM13_SOCB (27)
261 #define SDFM_SYNC_PWM14_SOCA (28)
262 #define SDFM_SYNC_PWM14_SOCB (29)
263 #define SDFM_SYNC_PWM15_SOCA (30)
264 #define SDFM_SYNC_PWM15_SOCB (31)
265 #define SDFM_SYNC_PWM16_SOCA (32)
266 #define SDFM_SYNC_PWM16_SOCB (33)
267 #define SDFM_SYNC_PWM17_SOCA (34)
268 #define SDFM_SYNC_PWM17_SOCB (35)
269 #define SDFM_SYNC_PWM18_SOCA (36)
270 #define SDFM_SYNC_PWM18_SOCB (37)
271 #define SDFM_SYNC_PWM19_SOCA (38)
272 #define SDFM_SYNC_PWM19_SOCB (39)
273 #define SDFM_SYNC_PWM20_SOCA (40)
274 #define SDFM_SYNC_PWM20_SOCB (41)
275 #define SDFM_SYNC_PWM21_SOCA (42)
276 #define SDFM_SYNC_PWM21_SOCB (43)
277 #define SDFM_SYNC_PWM22_SOCA (44)
278 #define SDFM_SYNC_PWM22_SOCB (45)
279 #define SDFM_SYNC_PWM23_SOCA (46)
280 #define SDFM_SYNC_PWM23_SOCB (47)
281 #define SDFM_SYNC_PWM24_SOCA (48)
282 #define SDFM_SYNC_PWM24_SOCB (49)
283 #define SDFM_SYNC_PWM25_SOCA (50)
284 #define SDFM_SYNC_PWM25_SOCB (51)
285 #define SDFM_SYNC_PWM26_SOCA (52)
286 #define SDFM_SYNC_PWM26_SOCB (53)
287 #define SDFM_SYNC_PWM27_SOCA (54)
288 #define SDFM_SYNC_PWM27_SOCB (55)
289 #define SDFM_SYNC_PWM28_SOCA (56)
290 #define SDFM_SYNC_PWM28_SOCB (57)
291 #define SDFM_SYNC_PWM29_SOCA (58)
292 #define SDFM_SYNC_PWM29_SOCB (59)
293 #define SDFM_SYNC_PWM30_SOCA (60)
294 #define SDFM_SYNC_PWM30_SOCB (61)
295 #define SDFM_SYNC_PWM31_SOCA (62)
296 #define SDFM_SYNC_PWM31_SOCB (63)
297
298 //*****************************************************************************
299 //
302 //
303 //*****************************************************************************
305 #define SDFM_FIFO_NOT_CLEARED_ON_SYNC (0)
306 #define SDFM_FIFO_CLEARED_ON_SYNC (1)
308
309 //*****************************************************************************
310 //
313 //
314 //*****************************************************************************
316 #define SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC (0)
317 #define SDFM_AUTO_CLEAR_WAIT_FOR_SYNC (1)
319
320 //*****************************************************************************
321 //
324 //
325 //*****************************************************************************
326 #define SDFM_COMP_EVENT_1 CSL_SDFM_SDCPARM1_CEVT1SEL_SHIFT
327 #define SDFM_COMP_EVENT_2 CSL_SDFM_SDCPARM1_CEVT2SEL_SHIFT
328
329 //*****************************************************************************
330 //
333 //
334 //*****************************************************************************
336 #define SDFM_COMP_EVENT_SRC_COMPH1 (0)
337 #define SDFM_COMP_EVENT_SRC_COMPH1_L1 (1)
339 #define SDFM_COMP_EVENT_SRC_COMPH2 (2)
341 #define SDFM_COMP_EVENT_SRC_COMPH2_L2 (3)
343 #define SDFM_COMP_EVENT_SRC_COMPL1 (0)
345 #define SDFM_COMP_EVENT_SRC_COMPL2 (2)
347
348 //*****************************************************************************
349 //
352 //
353 //*****************************************************************************
355 #define SDFM_CLK_SOURCE_CHANNEL_CLK (0x0)
356 #define SDFM_CLK_SOURCE_SD1_CLK CSL_SDFM_SDCTLPARM1_SDCLKSEL_MASK
358
359 //*****************************************************************************
360 //
363 //
364 //*****************************************************************************
366 #define SDFM_COMPHOUT_SOURCE_COMPHIN (0x0)
367 #define SDFM_COMPHOUT_SOURCE_FILTER (0x8)
369
370 //*****************************************************************************
371 //
374 //
375 //*****************************************************************************
377 #define SDFM_COMPLOUT_SOURCE_COMPLIN (0x000)
378 #define SDFM_COMPLOUT_SOURCE_FILTER (0x800)
380
381 //*****************************************************************************
382 //
385 //
386 //*****************************************************************************
387 typedef struct
388 {
389 uint16_t sampleWindow;
390 uint16_t threshold;
391 uint16_t clkPrescale;
392 } SDFM_CompEventFilterConfig;
393
394 //*****************************************************************************
395 //
396 // Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt
397 // as intFlags parameter
398 //
399 //*****************************************************************************
401 #define SDFM_MODULATOR_FAILURE_INTERRUPT (0x200U)
402 #define SDFM_CEVT2_INTERRUPT (0x40U)
404 #define SDFM_CEVT1_INTERRUPT (0x20U)
406 #define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT (0x1U)
408 #define SDFM_FIFO_INTERRUPT (0x1000U)
410 #define SDFM_FIFO_OVERFLOW_INTERRUPT (0x8000U)
412
413 //*****************************************************************************
414 //
415 // Values that can be passed to SDFM_clearInterruptFlag flags parameter
416 //
417 //*****************************************************************************
419 #define SDFM_MAIN_INTERRUPT_FLAG (0x80000000U)
420 #define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG (0x1U)
422 #define SDFM_FILTER_1_LOW_THRESHOLD_FLAG (0x2U)
424 #define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG (0x4U)
426 #define SDFM_FILTER_2_LOW_THRESHOLD_FLAG (0x8U)
428 #define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG (0x10U)
430 #define SDFM_FILTER_3_LOW_THRESHOLD_FLAG (0x20U)
432 #define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG (0x40U)
434 #define SDFM_FILTER_4_LOW_THRESHOLD_FLAG (0x80U)
436 #define SDFM_FILTER_1_MOD_FAILED_FLAG (0x100U)
438 #define SDFM_FILTER_2_MOD_FAILED_FLAG (0x200U)
440 #define SDFM_FILTER_3_MOD_FAILED_FLAG (0x400U)
442 #define SDFM_FILTER_4_MOD_FAILED_FLAG (0x800U)
444 #define SDFM_FILTER_1_NEW_DATA_FLAG (0x1000U)
446 #define SDFM_FILTER_2_NEW_DATA_FLAG (0x2000U)
448 #define SDFM_FILTER_3_NEW_DATA_FLAG (0x4000U)
450 #define SDFM_FILTER_4_NEW_DATA_FLAG (0x8000U)
452 #define SDFM_FILTER_1_FIFO_OVERFLOW_FLAG (0x10000U)
454 #define SDFM_FILTER_2_FIFO_OVERFLOW_FLAG (0x20000U)
456 #define SDFM_FILTER_3_FIFO_OVERFLOW_FLAG (0x40000U)
458 #define SDFM_FILTER_4_FIFO_OVERFLOW_FLAG (0x80000U)
460 #define SDFM_FILTER_1_FIFO_INTERRUPT_FLAG (0x100000U)
462 #define SDFM_FILTER_2_FIFO_INTERRUPT_FLAG (0x200000U)
464 #define SDFM_FILTER_3_FIFO_INTERRUPT_FLAG (0x400000U)
466 #define SDFM_FILTER_4_FIFO_INTERRUPT_FLAG (0x800000U)
468
469 //*****************************************************************************
470 //
480 //
481 //*****************************************************************************
482 static inline void
483 SDFM_enableExternalReset(uint32_t base, uint32_t filterNumber)
484 {
485 //
486 // Set the SDSYNCEN bit
487 //
488 HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
489 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
490 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
491 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
492 CSL_SDFM_SDDFPARM1_SDSYNCEN_MASK);
493 }
494
495 //*****************************************************************************
496 //
506 //*****************************************************************************
507 static inline void
508 SDFM_disableExternalReset(uint32_t base, uint32_t filterNumber)
509 {
510 //
511 // Clear the SDSYNCEN bit
512 //
513 HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
514 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
515 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
516 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
517 ~CSL_SDFM_SDDFPARM1_SDSYNCEN_MASK);
518 }
519
520 //*****************************************************************************
521 //
530 //
531 //*****************************************************************************
532 static inline void
533 SDFM_enableFilter(uint32_t base, uint32_t filterNumber)
534 {
535 //
536 // Set the FEN bit
537 //
538 HW_WR_REG16((base + CSL_SDFM_SDDFPARM1 +
539 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
540 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
541 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
542 CSL_SDFM_SDDFPARM1_FEN_MASK);
543 }
544
545 //*****************************************************************************
546 //
556 //*****************************************************************************
557 static inline void
558 SDFM_disableFilter(uint32_t base, uint32_t filterNumber)
559 {
560 //
561 // Clear the FEN bit
562 //
563 HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 +
564 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
565 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 +
566 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
567 ~CSL_SDFM_SDDFPARM1_FEN_MASK);
568 }
569
570 //*****************************************************************************
571 //
581 //
582 //*****************************************************************************
583 static inline void
584 SDFM_enableFIFOBuffer(uint32_t base, uint32_t filterNumber)
585 {
586 //
587 // Set the FFEN bit
588 //
589 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 +
590 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
591 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
592 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
593 CSL_SDFM_SDFIFOCTL1_FFEN_MASK);
594 }
595
596 //*****************************************************************************
597 //
607 //
608 //*****************************************************************************
609 static inline void
610 SDFM_disableFIFOBuffer(uint32_t base, uint32_t filterNumber)
611 {
612 //
613 // Clear the FFEN bit
614 //
615 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 +
616 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
617 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
618 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
619 ~CSL_SDFM_SDFIFOCTL1_FFEN_MASK);
620 }
621
622 //*****************************************************************************
623 //
634 //
635 //*****************************************************************************
636 static inline bool
637 SDFM_getZeroCrossTripStatus(uint32_t base, uint32_t filterNumber)
638 {
639 return(((HW_RD_REG16(base + CSL_SDFM_SDSTATUS) >> (uint16_t)filterNumber) &
640 0x1U) == 1U);
641 }
642
643 //*****************************************************************************
644 //
654 //
655 //*****************************************************************************
656 static inline void
657 SDFM_clearZeroCrossTripStatus(uint32_t base, uint32_t filterNumber)
658 {
659 //
660 // Set SDCTL MIE bit
661 //
662 HW_WR_REG16((base + CSL_SDFM_SDCTL),
663 HW_RD_REG16(base + CSL_SDFM_SDCTL) | (1U << filterNumber));
664 }
665
666 //*****************************************************************************
667 //
676 //
677 //*****************************************************************************
678 static inline void
679 SDFM_enableComparator(uint32_t base, uint32_t filterNumber)
680 {
681 //
682 // Set CEN bit
683 //
684 HW_WR_REG16((base + CSL_SDFM_SDCPARM1 +
685 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
686 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
687 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
688 CSL_SDFM_SDCPARM1_CEN_MASK);
689 }
690
691 //*****************************************************************************
692 //
701 //
702 //*****************************************************************************
703 static inline void
704 SDFM_disableComparator(uint32_t base, uint32_t filterNumber)
705 {
706 //
707 // Clear CEN bit
708 //
709 HW_WR_REG16((base + CSL_SDFM_SDCPARM1 +
710 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)),
711 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
712 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
713 ~CSL_SDFM_SDCPARM1_CEN_MASK);
714 }
715
716 //*****************************************************************************
717 //
746 //
747 //*****************************************************************************
748 static inline void
749 SDFM_selectCompEventSource(uint32_t base, uint32_t filterNumber,
750 uint32_t compEventNum,
751 uint32_t compEventSource)
752 {
753 uint32_t address;
754 address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber *
755 SDFM_SDFIL_OFFSET);
756
757 //
758 // Select source for selected comparator event
759 //
760 HW_WR_REG16(address,
761 (HW_RD_REG16(address) & ~((uint16_t)0x2U << compEventNum)) |
762 ((uint16_t)compEventSource << compEventNum) );
763 }
764
765 //*****************************************************************************
766 //
777 //*****************************************************************************
778 static inline void
779 SDFM_setFilterType(uint32_t base, uint32_t filterNumber,
780 uint32_t filterType)
781 {
782 uint32_t address;
783
784 address = base + CSL_SDFM_SDDFPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
785
786 //
787 // Write to SST bits
788 //
789 HW_WR_REG16(address,
790 (HW_RD_REG16(address) & (~CSL_SDFM_SDDFPARM1_SST_MASK)) |
791 ((uint16_t)filterType << 6U));
792 }
793
794 //*****************************************************************************
795 //
808 //*****************************************************************************
809 static inline void
810 SDFM_setFilterOverSamplingRatio(uint32_t base, uint32_t filterNumber,
811 uint16_t overSamplingRatio)
812 {
813 uint32_t address;
814
815 DebugP_assert(overSamplingRatio < 256U);
816
817 address = base + CSL_SDFM_SDDFPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
818
819 //
820 // Write to DOSR bits
821 //
822 HW_WR_REG16(address,
823 (HW_RD_REG16(address) & (~CSL_SDFM_SDDFPARM1_DOSR_MASK)) | overSamplingRatio);
824 }
825
826 //*****************************************************************************
827 //
841 //*****************************************************************************
842 static inline void
843 SDFM_setupModulatorClock(uint32_t base, uint32_t filterNumber,
844 uint32_t clockMode)
845 {
846 uint32_t address;
847
848 address = base + CSL_SDFM_SDCTLPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
849
850 //
851 // Write to MOD bits
852 //
853 HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDCTLPARM1_MOD_MASK)) |
854 (uint16_t)clockMode);
855
856 //
857 // Enable data and clock synchronizer
858 //
859 HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
860 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
861 HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
862 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
863 (SDFM_CLOCK_SYNCHRONIZER | SDFM_DATA_SYNCHRONIZER));
864 }
865
866 //*****************************************************************************
867 //
878 //
879 //*****************************************************************************
880 static inline void
881 SDFM_setOutputDataFormat(uint32_t base, uint32_t filterNumber,
882 uint32_t dataFormat)
883 {
884 uint32_t address;
885
886 address = base + CSL_SDFM_SDDPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
887
888 //
889 // Write to DR bit
890 //
891 HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDDPARM1_DR_MASK)) |
892 ((uint16_t)dataFormat << 10U));
893 }
894
895 //*****************************************************************************
896 //
909 //
910 //*****************************************************************************
911 static inline void
912 SDFM_setDataShiftValue(uint32_t base, uint32_t filterNumber,
913 uint16_t shiftValue)
914 {
915 uint32_t address;
916
917 DebugP_assert(shiftValue < 32U);
918
919 address = base + CSL_SDFM_SDDPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
920
921 //
922 // Write to SH bit
923 //
924 HW_WR_REG16(address, (HW_RD_REG16(address) & (~CSL_SDFM_SDDPARM1_SH_MASK)) |
925 (shiftValue << CSL_SDFM_SDDPARM1_SH_SHIFT));
926 }
927
928
929 //*****************************************************************************
930 //
945 //
946 //*****************************************************************************
947 static inline void
948 SDFM_setCompFilterHighThreshold(uint32_t base, uint32_t filterNumber,
949 uint32_t highThreshold)
950 {
951 uint32_t address;
952
953 DebugP_assert((uint16_t)highThreshold <= CSL_SDFM_SDFLT1CMPH1_HLT_MASK);
954 DebugP_assert((uint16_t)(highThreshold >> 16U) <= CSL_SDFM_SDFLT1CMPH2_HLT2_MASK);
955
956 address = base + CSL_SDFM_SDFLT1CMPH1 +
957 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
958
959 //
960 // Write to HLT bit
961 //
962 HW_WR_REG16(address,
963 (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPH1_HLT_MASK) |
964 (uint16_t)highThreshold);
965 HW_WR_REG16(address + SDFM_SDFLT1CMPHx_OFFSET,
966 (HW_RD_REG16(address + SDFM_SDFLT1CMPHx_OFFSET) &
967 ~CSL_SDFM_SDFLT1CMPH2_HLT2_MASK) | (uint16_t)(highThreshold >> 16U));
968 }
969
970 //*****************************************************************************
971 //
986 //
987 //*****************************************************************************
988 static inline void
989 SDFM_setCompFilterLowThreshold(uint32_t base, uint32_t filterNumber,
990 uint32_t lowThreshold)
991 {
992 uint32_t address;
993
994 DebugP_assert((uint16_t)lowThreshold <= CSL_SDFM_SDFLT1CMPL1_LLT_MASK);
995 DebugP_assert((uint16_t)(lowThreshold >> 16U) <= CSL_SDFM_SDFLT1CMPL2_LLT2_MASK);
996
997 address = base + CSL_SDFM_SDFLT1CMPL1 +
998 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
999
1000 //
1001 // Write to LLT bit.
1002 //
1003 HW_WR_REG16(address, (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPL1_LLT_MASK) |
1004 (uint16_t)lowThreshold);
1005 HW_WR_REG16(address + SDFM_SDFLT1CMPLx_OFFSET,
1006 (HW_RD_REG16(address + SDFM_SDFLT1CMPLx_OFFSET) &
1007 ~CSL_SDFM_SDFLT1CMPL2_LLT2_MASK) | (uint16_t)(lowThreshold >> 16U));
1008 }
1009 //*****************************************************************************
1010 //
1021 //
1022 //*****************************************************************************
1023 static inline void
1024 SDFM_setCompFilterZeroCrossThreshold(uint32_t base,
1025 uint32_t filterNumber,
1026 uint16_t zeroCrossThreshold)
1027 {
1028 uint32_t address;
1029
1030 DebugP_assert(zeroCrossThreshold < 0x7FFFU);
1031
1032 address = base + CSL_SDFM_SDFLT1CMPHZ + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1033
1034 //
1035 // Write to ZCT bit
1036 //
1037 HW_WR_REG16(address,
1038 (HW_RD_REG16(address) & ~CSL_SDFM_SDFLT1CMPHZ_HLTZ_MASK) | zeroCrossThreshold);
1039
1040 }
1041
1042 //*****************************************************************************
1043 //
1052 //
1053 //*****************************************************************************
1054 static inline void
1055 SDFM_enableZeroCrossEdgeDetect(uint32_t base, uint32_t filterNumber)
1056 {
1057 //
1058 // Set ZCEN bit
1059 //
1060 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 +
1061 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
1062 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
1063 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
1064 CSL_SDFM_SDCPARM1_HZEN_MASK);
1065 }
1066
1067 //*****************************************************************************
1068 //
1077 //
1078 //*****************************************************************************
1079 static inline void
1080 SDFM_disableZeroCrossEdgeDetect(uint32_t base, uint32_t filterNumber)
1081 {
1082 //
1083 // Clear ZCEN bit
1084 //
1085 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 +
1086 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
1087 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 +
1088 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
1089 ~CSL_SDFM_SDCPARM1_HZEN_MASK);
1090 }
1091
1092 //*****************************************************************************
1093 //
1109 //
1110 //*****************************************************************************
1111 static inline void
1112 SDFM_enableInterrupt(uint32_t base, uint32_t filterNumber,
1113 uint16_t intFlags)
1114 {
1115 uint16_t offset;
1116
1117 offset = (uint16_t)filterNumber * SDFM_SDFIL_OFFSET;
1118
1119 //
1120 // Low, high threshold, Modulator failure
1121 //
1122 if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
1123 SDFM_CEVT2_INTERRUPT |
1124 SDFM_CEVT1_INTERRUPT)) != 0U)
1125 {
1126 //
1127 // Set IEL or IEH or MFIE bit of CSL_SDFM_SDCPARMx
1128 //
1129 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 + offset,
1130 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 + offset) |
1131 (intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
1132 SDFM_CEVT2_INTERRUPT |
1133 SDFM_CEVT1_INTERRUPT)));
1134 }
1135
1136 //
1137 // Data filter acknowledge interrupt
1138 //
1139 if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U)
1140 {
1141 HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 + offset,
1142 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 + offset) |
1143 CSL_SDFM_SDDFPARM1_AE_MASK);
1144 }
1145
1146 //
1147 // FIFO , FIFO overflow interrupt
1148 //
1149 if((intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)) != 0U)
1150 {
1151 //
1152 // Set OVFIEN or FFIEN bits of CSL_SDFM_SDFIFOCTLx
1153 //
1154 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset,
1155 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset) |
1156 (intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)));
1157 }
1158 }
1159
1160 //*****************************************************************************
1161 //
1177 //
1178 //*****************************************************************************
1179 static inline void
1180 SDFM_disableInterrupt(uint32_t base, uint32_t filterNumber,
1181 uint16_t intFlags)
1182 {
1183 uint16_t offset;
1184
1185 offset = (uint16_t)filterNumber * SDFM_SDFIL_OFFSET;
1186
1187 //
1188 // Low, high threshold, modulator failure interrupts
1189 //
1190 if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
1191 SDFM_CEVT2_INTERRUPT |
1192 SDFM_CEVT1_INTERRUPT)) != 0U)
1193 {
1194 //
1195 // Set IEL or IEH or MFIE bit of CSL_SDFM_SDCPARMx
1196 //
1197 HW_WR_REG16(base + CSL_SDFM_SDCPARM1 + offset,
1198 HW_RD_REG16(base + CSL_SDFM_SDCPARM1 + offset) &
1199 ~(intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT |
1200 SDFM_CEVT2_INTERRUPT |
1201 SDFM_CEVT1_INTERRUPT)));
1202 }
1203
1204 //
1205 // Data filter acknowledge interrupt
1206 //
1207 if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U)
1208 {
1209 HW_WR_REG16(base + CSL_SDFM_SDDFPARM1 + offset,
1210 HW_RD_REG16(base + CSL_SDFM_SDDFPARM1 + offset) &
1211 ~CSL_SDFM_SDDFPARM1_AE_MASK);
1212 }
1213
1214 //
1215 // FIFO , FIFO overflow interrupt
1216 //
1217 if((intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)) != 0U)
1218 {
1219 //
1220 // Set OVFIEN or FFIEN bits of CSL_SDFM_SDFIFOCTLx
1221 //
1222 HW_WR_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset,
1223 HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 + offset) &
1224 ~(intFlags & (SDFM_FIFO_INTERRUPT | SDFM_FIFO_OVERFLOW_INTERRUPT)));
1225 }
1226 }
1227
1228 //*****************************************************************************
1229 //
1241 //*****************************************************************************
1242 static inline void
1243 SDFM_setComparatorFilterType(uint32_t base, uint32_t filterNumber,
1244 uint32_t filterType)
1245 {
1246 uint32_t address;
1247
1248 address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1249
1250 //
1251 // Write to CS1_CS0 bits
1252 //
1253 HW_WR_REG16(address,
1254 (HW_RD_REG16(address) & (~CSL_SDFM_SDCPARM1_CS1_CS0_MASK)) |
1255 ((uint16_t)filterType << 3U));
1256 }
1257
1258 //*****************************************************************************
1259 //
1272 //*****************************************************************************
1273 static inline void
1274 SDFM_setCompFilterOverSamplingRatio(uint32_t base,
1275 uint32_t filterNumber,
1276 uint16_t overSamplingRatio)
1277 {
1278 uint32_t address;
1279
1280 DebugP_assert(overSamplingRatio < 32U);
1281
1282 address = base + CSL_SDFM_SDCPARM1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1283
1284 //
1285 // Write to COSR bits
1286 //
1287 HW_WR_REG16(address,
1288 (HW_RD_REG16(address) & (~CSL_SDFM_SDCPARM1_COSR_MASK)) |
1289 overSamplingRatio);
1290 }
1291
1292 //*****************************************************************************
1293 //
1304 //*****************************************************************************
1305 static inline uint32_t
1306 SDFM_getFilterData(uint32_t base, uint32_t filterNumber)
1307 {
1308 //
1309 // Read SDDATA bits
1310 //
1311 return(HW_RD_REG32(base + CSL_SDFM_SDDATA1 +
1312 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)));
1313 }
1314
1315 //*****************************************************************************
1316 //
1333 //*****************************************************************************
1334 static inline uint32_t
1335 SDFM_getThresholdStatus(uint32_t base, uint32_t filterNumber)
1336 {
1337 //
1338 // Read SDIFLG high/low threshold bits
1339 //
1340 return((uint32_t)((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1341 (2U * (uint16_t)filterNumber)) & 0x3U));
1342 }
1343
1344 //*****************************************************************************
1345 //
1356 //*****************************************************************************
1357 static inline bool
1358 SDFM_getModulatorStatus(uint32_t base, uint32_t filterNumber)
1359 {
1360 //
1361 // Read SDIFLG MF1, MF2, MF3 OR MF4 bits
1362 //
1363 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1364 ((uint16_t)filterNumber + 8U)) & 0x1U) != 0x1U);
1365 }
1366
1367 //*****************************************************************************
1368 //
1379 //*****************************************************************************
1380 static inline bool
1381 SDFM_getNewFilterDataStatus(uint32_t base, uint32_t filterNumber)
1382 {
1383 //
1384 // Read SDIFLG AF1, AF2, AF3 OR AF4 bits
1385 //
1386 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1387 ((uint16_t)filterNumber + 12U)) & 0x1U) == 0x1U);
1388 }
1389
1390 //*****************************************************************************
1391 //
1403 //*****************************************************************************
1404 static inline bool
1405 SDFM_getFIFOOverflowStatus(uint32_t base, uint32_t filterNumber)
1406 {
1407 //
1408 // Read SDIFLG SDFFOVF1, SDFFOVF2, SDFFOVF3 OR SDFFOVF4 bits
1409 //
1410 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1411 ((uint16_t)filterNumber + 16U)) & 0x1U) == 0x1U);
1412 }
1413
1414 //*****************************************************************************
1415 //
1427 //*****************************************************************************
1428 static inline bool
1429 SDFM_getFIFOISRStatus(uint32_t base, uint32_t filterNumber)
1430 {
1431 //
1432 // Read SDIFLG SDFFINT1, SDFFINT2, SDFFINT3 OR SDFFINT4 bits
1433 //
1434 return(((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >>
1435 ((uint16_t)filterNumber + 20U)) & 0x1U) == 0x1U);
1436 }
1437
1438 //*****************************************************************************
1439 //
1449 //*****************************************************************************
1450 static inline bool
1451 SDFM_getIsrStatus(uint32_t base)
1452 {
1453 //
1454 // Read SDIFLG MIF
1455 //
1456 return((HW_RD_REG32(base + CSL_SDFM_SDIFLG) >> 31U) == 0x1U);
1457 }
1458
1459 //*****************************************************************************
1460 //
1484 //*****************************************************************************
1485 static inline void
1486 SDFM_clearInterruptFlag(uint32_t base, uint32_t flag)
1487 {
1488 DebugP_assert((flag & 0x80FFFFFFU) == flag);
1489
1490 //
1491 // Write to SDIFLGCLR register
1492 //
1493 HW_WR_REG32((base + CSL_SDFM_SDIFLGCLR),
1494 HW_RD_REG32(base + CSL_SDFM_SDIFLGCLR) | flag);
1495 }
1496
1497 //*****************************************************************************
1498 //
1507 //*****************************************************************************
1508 static inline void
1509 SDFM_enableMainInterrupt(uint32_t base)
1510 {
1511 //
1512 // Set SDCTL MIE bit
1513 //
1514 HW_WR_REG16(base + CSL_SDFM_SDCTL,
1515 HW_RD_REG16(base + CSL_SDFM_SDCTL) | CSL_SDFM_SDCTL_MIE_MASK);
1516 }
1517
1518 //*****************************************************************************
1519 //
1528 //*****************************************************************************
1529 static inline void
1530 SDFM_disableMainInterrupt(uint32_t base)
1531 {
1532 //
1533 // Clear SDCTL MIE bit
1534 //
1535 HW_WR_REG16(base + CSL_SDFM_SDCTL,
1536 HW_RD_REG16(base + CSL_SDFM_SDCTL) & ~CSL_SDFM_SDCTL_MIE_MASK);
1537 }
1538
1539 //*****************************************************************************
1540 //
1549 //*****************************************************************************
1550 static inline void
1551 SDFM_enableMainFilter(uint32_t base)
1552 {
1553 //
1554 // Set SDMFILEN MFE bit
1555 //
1556 HW_WR_REG16(base + CSL_SDFM_SDMFILEN,
1557 HW_RD_REG16(base + CSL_SDFM_SDMFILEN) | CSL_SDFM_SDMFILEN_MFE_MASK);
1558 }
1559
1560 //*****************************************************************************
1561 //
1570 //*****************************************************************************
1571 static inline void
1572 SDFM_disableMainFilter(uint32_t base)
1573 {
1574 //
1575 // Clear SDMFILEN MFE bit
1576 //
1577 HW_WR_REG16(base + CSL_SDFM_SDMFILEN,
1578 HW_RD_REG16(base + CSL_SDFM_SDMFILEN) & ~CSL_SDFM_SDMFILEN_MFE_MASK);
1579 }
1580
1581 //*****************************************************************************
1582 //
1591 //
1592 //*****************************************************************************
1593 static inline uint16_t
1594 SDFM_getFIFODataCount(uint32_t base, uint32_t filterNumber)
1595 {
1596 //
1597 // Read SDFFST
1598 //
1599 return((HW_RD_REG16(base + CSL_SDFM_SDFIFOCTL1 +
1600 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
1601 CSL_SDFM_SDFIFOCTL1_SDFFST_MASK) >> CSL_SDFM_SDFIFOCTL1_SDFFST_SHIFT);
1602 }
1603
1604 //*****************************************************************************
1605 //
1615 //
1616 //*****************************************************************************
1617 static inline uint16_t
1618 SDFM_getComparatorSincData(uint32_t base, uint32_t filterNumber)
1619 {
1620 //
1621 // Read SDCDATA
1622 //
1623 return(HW_RD_REG16(base + CSL_SDFM_SDCDATA1 +
1624 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)));
1625 }
1626
1627 //*****************************************************************************
1628 //
1639 //
1640 //*****************************************************************************
1641 static inline uint32_t
1642 SDFM_getFIFOData(uint32_t base, uint32_t filterNumber)
1643 {
1644 //
1645 // Read SDDATFIFO
1646 //
1647 return(HW_RD_REG32(base + CSL_SDFM_SDDATFIFO1 +
1648 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)));
1649 }
1650
1651 //*****************************************************************************
1652 //
1664 //
1665 //*****************************************************************************
1666 static inline void
1667 SDFM_setFIFOInterruptLevel(uint32_t base, uint32_t filterNumber,
1668 uint16_t fifoLevel)
1669 {
1670 uint32_t address;
1671
1672 DebugP_assert(fifoLevel <= 16U);
1673
1674 address = base + CSL_SDFM_SDFIFOCTL1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1675
1676 //
1677 // Write to SDFFIL bit
1678 //
1679 HW_WR_REG16(address,
1680 ((HW_RD_REG16(address) & (~CSL_SDFM_SDFIFOCTL1_SDFFIL_MASK)) | fifoLevel));
1681 }
1682
1683 //*****************************************************************************
1684 //
1697 //
1698 //*****************************************************************************
1699 static inline void
1700 SDFM_setDataReadyInterruptSource(uint32_t base, uint32_t filterNumber,
1701 uint32_t dataReadySource)
1702 {
1703 uint32_t address;
1704
1705 address = base + CSL_SDFM_SDFIFOCTL1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1706
1707 //
1708 // Write to DRINTSEL
1709 //
1710 HW_WR_REG16(address,
1711 (HW_RD_REG16(address) & ~CSL_SDFM_SDFIFOCTL1_DRINTSEL_MASK) |
1712 ((uint16_t)dataReadySource << 14U));
1713 }
1714
1715 //*****************************************************************************
1716 //
1726 //
1727 //*****************************************************************************
1728 static inline bool
1729 SDFM_getWaitForSyncStatus(uint32_t base, uint32_t filterNumber)
1730 {
1731 //
1732 // Read WTSYNFLG bit
1733 //
1734 return(((HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1735 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
1736 CSL_SDFM_SDSYNC1_WTSYNFLG_MASK) >> 7U) == 0x1U);
1737 }
1738
1739 //*****************************************************************************
1740 //
1749 //
1750 //*****************************************************************************
1751 static inline void
1752 SDFM_clearWaitForSyncFlag(uint32_t base, uint32_t filterNumber)
1753 {
1754 //
1755 // Clear WTSYNCLR bit
1756 //
1757 HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
1758 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
1759 HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1760 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
1761 CSL_SDFM_SDSYNC1_WTSYNCLR_MASK);
1762 }
1763
1764 //*****************************************************************************
1765 //
1775 //
1776 //*****************************************************************************
1777 static inline void
1778 SDFM_enableWaitForSync(uint32_t base, uint32_t filterNumber)
1779 {
1780 //
1781 // Set WTSYNCEN bit
1782 //
1783 HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
1784 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
1785 HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1786 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) |
1787 CSL_SDFM_SDSYNC1_WTSYNCEN_MASK);
1788 }
1789
1790 //*****************************************************************************
1791 //
1801 //
1802 //*****************************************************************************
1803 static inline void
1804 SDFM_disableWaitForSync(uint32_t base, uint32_t filterNumber)
1805 {
1806 //
1807 // Clear WTSYNCEN bit
1808 //
1809 HW_WR_REG16(base + CSL_SDFM_SDSYNC1 +
1810 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
1811 HW_RD_REG16(base + CSL_SDFM_SDSYNC1 +
1812 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) &
1813 ~CSL_SDFM_SDSYNC1_WTSYNCEN_MASK);
1814 }
1815
1816 //*****************************************************************************
1817 //
1830 //
1831 //*****************************************************************************
1832 static inline void
1833 SDFM_setPWMSyncSource(uint32_t base, uint32_t filterNumber,
1834 uint32_t syncSource)
1835 {
1836 uint32_t address;
1837
1838 address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1839
1840 //
1841 // Write to SYNCSEL bits
1842 //
1843 HW_WR_REG16(address,
1844 (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_SYNCSEL_MASK) |
1845 (uint16_t)syncSource);
1846 }
1847
1848 //*****************************************************************************
1849 //
1863 //
1864 //*****************************************************************************
1865 static inline void
1866 SDFM_setFIFOClearOnSyncMode(uint32_t base, uint32_t filterNumber,
1867 uint32_t fifoClearSyncMode)
1868 {
1869 uint32_t address;
1870
1871 address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1872
1873 //
1874 // Write to FFSYNCCLREN bit
1875 //
1876 HW_WR_REG16(address,
1877 (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_FFSYNCCLREN_MASK) |
1878 ((uint16_t)fifoClearSyncMode << 9U));
1879 }
1880
1881 //*****************************************************************************
1882 //
1898 //
1899 //*****************************************************************************
1900 static inline void
1901 SDFM_setWaitForSyncClearMode(uint32_t base, uint32_t filterNumber,
1902 uint32_t syncClearMode)
1903 {
1904 uint32_t address;
1905
1906 address = base + CSL_SDFM_SDSYNC1 + ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1907
1908 //
1909 // Write to WTSCLREN bit
1910 //
1911 HW_WR_REG16(address,
1912 (HW_RD_REG16(address) & ~CSL_SDFM_SDSYNC1_WTSCLREN_MASK) |
1913 ((uint16_t)syncClearMode << 10U));
1914 }
1915
1916 //*****************************************************************************
1917 //
1930 //
1931 //*****************************************************************************
1932 static inline void
1933 SDFM_selectClockSource(uint32_t base, uint32_t filterNumber,
1934 uint32_t clkSource)
1935 {
1936 uint32_t address;
1937
1938 address = base + CSL_SDFM_SDCTLPARM1 +
1939 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET);
1940
1941 //
1942 // Select SDFM clock source.
1943 //
1944 HW_WR_REG16(address,
1945 (HW_RD_REG16(address) & ~(CSL_SDFM_SDCTLPARM1_SDCLKSEL_MASK)) |
1946 (uint16_t)clkSource);
1947 }
1948
1949 //*****************************************************************************
1950 //
1963 //
1964 //*****************************************************************************
1965 static inline void
1966 SDFM_enableSynchronizer(uint32_t base, uint32_t filterNumber,
1967 uint16_t syncConfig)
1968 {
1969 //
1970 // Select SDFM clock source.
1971 //
1972 HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
1973 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
1974 HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
1975 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) | syncConfig);
1976 }
1977
1978 //*****************************************************************************
1979 //
1992 //
1993 //*****************************************************************************
1994 static inline void
1995 SDFM_disableSynchronizer(uint32_t base, uint32_t filterNumber,
1996 uint16_t syncConfig)
1997 {
1998 //
1999 // Select SDFM clock source.
2000 //
2001 HW_WR_REG16(base + CSL_SDFM_SDCTLPARM1 +
2002 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET),
2003 HW_RD_REG16(base + CSL_SDFM_SDCTLPARM1 +
2004 ((uint32_t)filterNumber * SDFM_SDFIL_OFFSET)) & ~syncConfig);
2005 }
2006
2007 //*****************************************************************************
2008 //
2021 //
2022 //*****************************************************************************
2023 static inline void
2024 SDFM_selectCompEventHighSource(uint32_t base, uint32_t filterNumber,
2025 uint32_t source)
2026 {
2027 uint32_t address;
2028 address = base + CSL_SDFM_SDCOMP1CTL +
2029 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET);
2030
2031 //
2032 // Set COMPHOUT source.
2033 //
2034 HW_WR_REG16(address,
2035 (HW_RD_REG16(address) & ~CSL_SDFM_SDCOMP1CTL_CEVT1DIGFILTSEL_MASK) |
2036 (uint16_t)source);
2037 }
2038
2039 //*****************************************************************************
2040 //
2053 //
2054 //*****************************************************************************
2055 static inline void
2056 SDFM_selectCompEventLowSource(uint32_t base, uint32_t filterNumber,
2057 uint32_t source)
2058 {
2059 uint32_t address;
2060 address = base + CSL_SDFM_SDCOMP1CTL +
2061 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET);
2062
2063 //
2064 // Set COMPLOUT source.
2065 //
2066 HW_WR_REG16(address,
2067 (HW_RD_REG16(address) & ~CSL_SDFM_SDCOMP1CTL_CEVT2DIGFILTSEL_MASK) |
2068 (uint16_t)source);
2069 }
2070
2071 //*****************************************************************************
2072 //
2081 //
2082 //*****************************************************************************
2083 static inline void
2084 SDFM_initCompEventLowFilter(uint32_t base, uint32_t filterNumber)
2085 {
2086 //
2087 // Initialize comparator event low filter.
2088 //
2089 HW_WR_REG16(base + CSL_SDFM_SDCOMP1EVT2FLTCTL +
2090 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET),
2091 HW_RD_REG16(base + CSL_SDFM_SDCOMP1EVT2FLTCTL +
2092 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET)) |
2093 (uint16_t)CSL_SDFM_SDCOMP1EVT2FLTCTL_FILINIT_MASK);
2094 }
2095
2096 //*****************************************************************************
2097 //
2106 //
2107 //*****************************************************************************
2108 static inline void
2109 SDFM_initCompEventHighFilter(uint32_t base, uint32_t filterNumber)
2110 {
2111 //
2112 // Initialize comparator event high filter.
2113 //
2114 HW_WR_REG16(base + CSL_SDFM_SDCOMP1EVT1FLTCTL +
2115 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET),
2116 HW_RD_REG16(base + CSL_SDFM_SDCOMP1EVT1FLTCTL +
2117 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET)) |
2118 (uint16_t)CSL_SDFM_SDCOMP1EVT1FLTCTL_FILINIT_MASK);
2119 }
2120
2121 //*****************************************************************************
2122 //
2136 //
2137 //*****************************************************************************
2138 static inline void
2139 SDFM_lockCompEventFilterConfig(uint32_t base, uint32_t filterNumber,
2140 uint16_t lockConfig)
2141 {
2142 //
2143 // Lock comparator event filter related configurations.
2144 //
2145 HW_WR_REG16(base + CSL_SDFM_SDCOMP1LOCK +
2146 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET),
2147 HW_RD_REG16(base + CSL_SDFM_SDCOMP1LOCK +
2148 ((uint32_t)filterNumber * SDFM_DIGFIL_OFFSET)) | lockConfig);
2149 }
2150
2151 //*****************************************************************************
2152 //
2153 // Prototypes for the APIs.
2154 //
2155 //*****************************************************************************
2156 //*****************************************************************************
2157 //
2202 //*****************************************************************************
2203 extern void
2204 SDFM_configComparator(uint32_t base, uint16_t config1,
2205 uint32_t config2, uint16_t config3);
2206
2207 //*****************************************************************************
2208 //
2264 //*****************************************************************************
2265 extern void
2266 SDFM_configEnhancedComparator(uint32_t base, uint16_t filterConfig,
2267 uint32_t highLowThreshold1,
2268 uint32_t highLowThreshold2,
2269 uint16_t zeroCrossThreshold);
2270
2271 //*****************************************************************************
2272 //
2314 //*****************************************************************************
2315 extern void
2316 SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2);
2317
2318 //*****************************************************************************
2319 //
2348 //*****************************************************************************
2349 extern void
2350 SDFM_configZeroCrossComparator(uint32_t base, uint16_t config1,
2351 uint16_t config2);
2352
2353 //*****************************************************************************
2354 //
2397 //*****************************************************************************
2398 extern void
2399 SDFM_configDataFilterFIFO(uint32_t base, uint16_t config1, uint16_t config2);
2400
2401 //*****************************************************************************
2402 //
2413 //
2414 //*****************************************************************************
2415 extern void
2416 SDFM_configCompEventLowFilter(uint32_t base, uint32_t filterNumber,
2417 const SDFM_CompEventFilterConfig *config);
2418
2419 //*****************************************************************************
2420 //
2431 //
2432 //*****************************************************************************
2433 extern void
2434 SDFM_configCompEventHighFilter(uint32_t base, uint32_t filterNumber,
2435 const SDFM_CompEventFilterConfig *config);
2436
2437 //*****************************************************************************
2438 //
2439 // Close the Doxygen group.
2441 //
2442 //*****************************************************************************
2443
2444 //*****************************************************************************
2445 //
2446 // Mark the end of the C bindings section for C++ compilers.
2447 //
2448 //*****************************************************************************
2449 #ifdef __cplusplus
2450 }
2451 #endif
2452 #endif // SDFM_V0_H_
SDFM_configEnhancedComparator
void SDFM_configEnhancedComparator(uint32_t base, uint16_t filterConfig, uint32_t highLowThreshold1, uint32_t highLowThreshold2, uint16_t zeroCrossThreshold)
SDFM_disableZeroCrossEdgeDetect
static void SDFM_disableZeroCrossEdgeDetect(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1080
SDFM_selectClockSource
static void SDFM_selectClockSource(uint32_t base, uint32_t filterNumber, uint32_t clkSource)
Definition: sdfm/v0/sdfm.h:1933
SDFM_setFIFOInterruptLevel
static void SDFM_setFIFOInterruptLevel(uint32_t base, uint32_t filterNumber, uint16_t fifoLevel)
Definition: sdfm/v0/sdfm.h:1667
SDFM_setFIFOClearOnSyncMode
static void SDFM_setFIFOClearOnSyncMode(uint32_t base, uint32_t filterNumber, uint32_t fifoClearSyncMode)
Definition: sdfm/v0/sdfm.h:1866
SDFM_FIFO_OVERFLOW_INTERRUPT
#define SDFM_FIFO_OVERFLOW_INTERRUPT
Interrupt on FIFO overflow.
Definition: sdfm/v0/sdfm.h:411
SDFM_setCompFilterHighThreshold
static void SDFM_setCompFilterHighThreshold(uint32_t base, uint32_t filterNumber, uint32_t highThreshold)
Definition: sdfm/v0/sdfm.h:948
SDFM_selectCompEventHighSource
static void SDFM_selectCompEventHighSource(uint32_t base, uint32_t filterNumber, uint32_t source)
Definition: sdfm/v0/sdfm.h:2024
SDFM_getFilterData
static uint32_t SDFM_getFilterData(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1306
SDFM_disableComparator
static void SDFM_disableComparator(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:704
SDFM_initCompEventHighFilter
static void SDFM_initCompEventHighFilter(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:2109
SDFM_CEVT2_INTERRUPT
#define SDFM_CEVT2_INTERRUPT
Interrupt on CEVT2 (Comparator Event 2).
Definition: sdfm/v0/sdfm.h:403
SDFM_setOutputDataFormat
static void SDFM_setOutputDataFormat(uint32_t base, uint32_t filterNumber, uint32_t dataFormat)
Definition: sdfm/v0/sdfm.h:881
SDFM_enableWaitForSync
static void SDFM_enableWaitForSync(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1778
SDFM_enableMainInterrupt
static void SDFM_enableMainInterrupt(uint32_t base)
Definition: sdfm/v0/sdfm.h:1509
SDFM_setCompFilterOverSamplingRatio
static void SDFM_setCompFilterOverSamplingRatio(uint32_t base, uint32_t filterNumber, uint16_t overSamplingRatio)
Definition: sdfm/v0/sdfm.h:1274
SDFM_configZeroCrossComparator
void SDFM_configZeroCrossComparator(uint32_t base, uint16_t config1, uint16_t config2)
SDFM_setComparatorFilterType
static void SDFM_setComparatorFilterType(uint32_t base, uint32_t filterNumber, uint32_t filterType)
Definition: sdfm/v0/sdfm.h:1243
SDFM_initCompEventLowFilter
static void SDFM_initCompEventLowFilter(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:2084
SDFM_disableExternalReset
static void SDFM_disableExternalReset(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:508
SDFM_configCompEventLowFilter
void SDFM_configCompEventLowFilter(uint32_t base, uint32_t filterNumber, const SDFM_CompEventFilterConfig *config)
SDFM_setupModulatorClock
static void SDFM_setupModulatorClock(uint32_t base, uint32_t filterNumber, uint32_t clockMode)
Definition: sdfm/v0/sdfm.h:843
SDFM_CLOCK_SYNCHRONIZER
#define SDFM_CLOCK_SYNCHRONIZER
Define for Clock synchronizer Configuration.
Definition: sdfm/v0/sdfm.h:157
SDFM_selectCompEventSource
static void SDFM_selectCompEventSource(uint32_t base, uint32_t filterNumber, uint32_t compEventNum, uint32_t compEventSource)
Definition: sdfm/v0/sdfm.h:749
SDFM_CompEventFilterConfig::sampleWindow
uint16_t sampleWindow
Sample window size.
Definition: sdfm/v0/sdfm.h:389
SDFM_enableExternalReset
static void SDFM_enableExternalReset(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:483
SDFM_lockCompEventFilterConfig
static void SDFM_lockCompEventFilterConfig(uint32_t base, uint32_t filterNumber, uint16_t lockConfig)
Definition: sdfm/v0/sdfm.h:2139
SDFM_SDFIL_OFFSET
#define SDFM_SDFIL_OFFSET
< SD filter offset
Definition: sdfm/v0/sdfm.h:119
SDFM_disableInterrupt
static void SDFM_disableInterrupt(uint32_t base, uint32_t filterNumber, uint16_t intFlags)
Definition: sdfm/v0/sdfm.h:1180
SDFM_disableMainInterrupt
static void SDFM_disableMainInterrupt(uint32_t base)
Definition: sdfm/v0/sdfm.h:1530
SDFM_setFilterType
static void SDFM_setFilterType(uint32_t base, uint32_t filterNumber, uint32_t filterType)
Definition: sdfm/v0/sdfm.h:779
SDFM_configComparator
void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2, uint16_t config3)
SDFM_getComparatorSincData
static uint16_t SDFM_getComparatorSincData(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1618
SDFM_selectCompEventLowSource
static void SDFM_selectCompEventLowSource(uint32_t base, uint32_t filterNumber, uint32_t source)
Definition: sdfm/v0/sdfm.h:2056
SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT
#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT
Interrupt on Acknowledge flag.
Definition: sdfm/v0/sdfm.h:407
SDFM_SDFLT1CMPLx_OFFSET
#define SDFM_SDFLT1CMPLx_OFFSET
Definition: sdfm/v0/sdfm.h:128
SDFM_getFIFOISRStatus
static bool SDFM_getFIFOISRStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1429
SDFM_setWaitForSyncClearMode
static void SDFM_setWaitForSyncClearMode(uint32_t base, uint32_t filterNumber, uint32_t syncClearMode)
Definition: sdfm/v0/sdfm.h:1901
SDFM_DIGFIL_OFFSET
#define SDFM_DIGFIL_OFFSET
Offset between high threshold 1 & 2 registers.
Definition: sdfm/v0/sdfm.h:122
SDFM_setCompFilterLowThreshold
static void SDFM_setCompFilterLowThreshold(uint32_t base, uint32_t filterNumber, uint32_t lowThreshold)
Definition: sdfm/v0/sdfm.h:989
SDFM_CompEventFilterConfig::clkPrescale
uint16_t clkPrescale
Sample clock pre-scale.
Definition: sdfm/v0/sdfm.h:391
SDFM_FIFO_INTERRUPT
#define SDFM_FIFO_INTERRUPT
Interrupt on FIFO level.
Definition: sdfm/v0/sdfm.h:409
SDFM_DATA_SYNCHRONIZER
#define SDFM_DATA_SYNCHRONIZER
Define for Data Synchronizer Configuration.
Definition: sdfm/v0/sdfm.h:159
SDFM_getThresholdStatus
static uint32_t SDFM_getThresholdStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1335
SDFM_getZeroCrossTripStatus
static bool SDFM_getZeroCrossTripStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:637
SDFM_getFIFOData
static uint32_t SDFM_getFIFOData(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1642
SDFM_setDataShiftValue
static void SDFM_setDataShiftValue(uint32_t base, uint32_t filterNumber, uint16_t shiftValue)
Definition: sdfm/v0/sdfm.h:912
SDFM_getIsrStatus
static bool SDFM_getIsrStatus(uint32_t base)
Definition: sdfm/v0/sdfm.h:1451
SDFM_enableFilter
static void SDFM_enableFilter(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:533
SDFM_getNewFilterDataStatus
static bool SDFM_getNewFilterDataStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1381
SDFM_setDataReadyInterruptSource
static void SDFM_setDataReadyInterruptSource(uint32_t base, uint32_t filterNumber, uint32_t dataReadySource)
Definition: sdfm/v0/sdfm.h:1700
SDFM_SDFLT1CMPHx_OFFSET
#define SDFM_SDFLT1CMPHx_OFFSET
Offset between low threshold 1 & 2 registers.
Definition: sdfm/v0/sdfm.h:125
SDFM_clearInterruptFlag
static void SDFM_clearInterruptFlag(uint32_t base, uint32_t flag)
Definition: sdfm/v0/sdfm.h:1486
SDFM_getFIFODataCount
static uint16_t SDFM_getFIFODataCount(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1594
SDFM_disableFilter
static void SDFM_disableFilter(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:558
DebugP.h
SDFM_getModulatorStatus
static bool SDFM_getModulatorStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1358
SDFM_getFIFOOverflowStatus
static bool SDFM_getFIFOOverflowStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1405
SDFM_configDataFilterFIFO
void SDFM_configDataFilterFIFO(uint32_t base, uint16_t config1, uint16_t config2)
SDFM_disableMainFilter
static void SDFM_disableMainFilter(uint32_t base)
Definition: sdfm/v0/sdfm.h:1572
SDFM_disableSynchronizer
static void SDFM_disableSynchronizer(uint32_t base, uint32_t filterNumber, uint16_t syncConfig)
Definition: sdfm/v0/sdfm.h:1995
SDFM_setPWMSyncSource
static void SDFM_setPWMSyncSource(uint32_t base, uint32_t filterNumber, uint32_t syncSource)
Definition: sdfm/v0/sdfm.h:1833
SDFM_enableMainFilter
static void SDFM_enableMainFilter(uint32_t base)
Definition: sdfm/v0/sdfm.h:1551
SDFM_configCompEventHighFilter
void SDFM_configCompEventHighFilter(uint32_t base, uint32_t filterNumber, const SDFM_CompEventFilterConfig *config)
SDFM_enableZeroCrossEdgeDetect
static void SDFM_enableZeroCrossEdgeDetect(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1055
SDFM_clearZeroCrossTripStatus
static void SDFM_clearZeroCrossTripStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:657
SDFM_CompEventFilterConfig::threshold
uint16_t threshold
Majority voting threshold.
Definition: sdfm/v0/sdfm.h:390
SDFM_disableWaitForSync
static void SDFM_disableWaitForSync(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1804
SDFM_configDataFilter
void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2)
SDFM_enableComparator
static void SDFM_enableComparator(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:679
DebugP_assert
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:187
SDFM_getWaitForSyncStatus
static bool SDFM_getWaitForSyncStatus(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1729
SDFM_clearWaitForSyncFlag
static void SDFM_clearWaitForSyncFlag(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:1752
SDFM_enableFIFOBuffer
static void SDFM_enableFIFOBuffer(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:584
SDFM_enableSynchronizer
static void SDFM_enableSynchronizer(uint32_t base, uint32_t filterNumber, uint16_t syncConfig)
Definition: sdfm/v0/sdfm.h:1966
SDFM_MODULATOR_FAILURE_INTERRUPT
#define SDFM_MODULATOR_FAILURE_INTERRUPT
Interrupt is generated if Modulator fails.
Definition: sdfm/v0/sdfm.h:401
SDFM_setFilterOverSamplingRatio
static void SDFM_setFilterOverSamplingRatio(uint32_t base, uint32_t filterNumber, uint16_t overSamplingRatio)
Definition: sdfm/v0/sdfm.h:810
SDFM_enableInterrupt
static void SDFM_enableInterrupt(uint32_t base, uint32_t filterNumber, uint16_t intFlags)
Definition: sdfm/v0/sdfm.h:1112
SDFM_disableFIFOBuffer
static void SDFM_disableFIFOBuffer(uint32_t base, uint32_t filterNumber)
Definition: sdfm/v0/sdfm.h:610
SDFM_CompEventFilterConfig
Definition: sdfm/v0/sdfm.h:388
SDFM_setCompFilterZeroCrossThreshold
static void SDFM_setCompFilterZeroCrossThreshold(uint32_t base, uint32_t filterNumber, uint16_t zeroCrossThreshold)
Definition: sdfm/v0/sdfm.h:1024
SDFM_CEVT1_INTERRUPT
#define SDFM_CEVT1_INTERRUPT
Interrupt on CEVT1 (Comparator Event 1).
Definition: sdfm/v0/sdfm.h:405