AM261x MCU+ SDK: sdl_stc.h Source File

| AM261x MCU+ SDK 26.00.00 |

stc/v0/sdl_stc.h
Go to the documentation of this file.
1 /********************************************************************
2 * Copyright (C) 2022 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * Name : sdl_stc.h
33 */
51 #ifndef SDL_STC_H_
52 #define SDL_STC_H_
53
54 #ifdef __cplusplus
55 extern "C"
56 {
57 #endif
58
59 /* ========================================================================== */
60 /* Include Files */
61 /* ========================================================================== */
62
63
64 #include <stdbool.h>
65 #include <stdint.h>
66 #include <sdl/include/hw_types.h>
67 #include <sdl/include/sdl_types.h>
68 #include <sdl/sdlr.h>
69 #include <sdl/stc/v0/soc/sdl_soc_stc.h>
70 #include <sdl/soc.h>
71
72
96 /**************************************************************************
97 * STC Parameters:
98 **************************************************************************/
105 /*
106 * STC Parameters R5F
107 */
108
109 #define STC_MSS_INTERVAL_NUM (uint32_t)(1U)
110 #define STC_MSS_LP_SCAN_MODE (uint32_t)(0U)
111 #define STC_MSS_CODEC_SPREAD_MODE (uint32_t)(1U)
112 #define STC_MSS_CAP_IDLE_CYCLE (uint32_t)(3U)
113 #define STC_MSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)
114 #define STC_MSS_MAX_RUN_TIME (uint32_t)(0xFFFFFFFFU)
115 #define STC_MSS_CLK_DIV (uint32_t)(1U)
116 #define STC_ROM_START_ADDRESS (uint32_t)(0U)
117 #define STC_pROM_START_ADDRESS (uint32_t)(1U)
118
119
120 /*
121 * STC Parameters DSP
122 */
123
124 #define STC_DSS_INTERVAL_NUM (uint32_t)(1U)
125 #define STC_DSS_LP_SCAN_MODE (uint32_t)(0U)
126 #define STC_DSS_CODEC_SPREAD_MODE (uint32_t)(1U)
127 #define STC_DSS_CAP_IDLE_CYCLE (uint32_t)(3U)
128 #define STC_DSS_SCANEN_HIGH_CAP_IDLE_CYCLE (uint32_t)(3U)
129 #define STC_DSS_MAX_RUN_TIME (uint32_t)(0xFFFFFFFFU)
130 #define STC_DSS_CLK_DIV (uint32_t)(1U)
131 #define STC_ROM_START_ADDRESS (uint32_t)(0U)
132 #define STC_pROM_START_ADDRESS (uint32_t)(1U)
133
134
135
139 /* ========================================================================== */
140 /* Structures */
141 /* ========================================================================== */
142
143
153 typedef struct
154 {
156 uint32_t lpScanMode;
158 uint32_t codecSpreadMode;
160 uint32_t capIdleCycle;
162 uint32_t scanEnHighCap_idleCycle;
163
164 }SDL_STC_ScanModeconfig;
165
166
167
168 typedef struct
169 {
171 uint32_t intervalNum;
173 uint32_t maxRunTime;
175 uint32_t clkDiv;
177 uint32_t romStartAddress;
179 uint32_t pRomStartAdd;
181 SDL_STC_ScanModeconfig modeConfig;
182
183 }SDL_STC_Config;
184
185
194 typedef enum
195 {
197 SDL_STC_COMPLETED_SUCCESS,
199 SDL_STC_COMPLETED_FAILURE,
201 SDL_STC_NOT_COMPLETED,
203 SDL_STC_NOT_RUN,
205 INVALID_RESULT
206
207 }SDL_STC_TestResult;
208
209 typedef enum
210 {
212 SDL_STC_TEST,
214 SDL_STC_NEG_TEST,
215 /* Invalid test type */
216 INVALID_TEST
217
218 }SDL_STC_TestType;
219
223 /* ========================================================================== */
224 /* Global Variables */
225 /* ========================================================================== */
226
227 /* None */
228
229
230 /* ========================================================================== */
231 /* Function Declarations */
232 /* ========================================================================== */
233
250 int32_t SDL_STC_getStatus(SDL_STC_Inst instance);
251
266 int32_t SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType,SDL_STC_Config *pConfig);
280 static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType);
288 static int32_t SDL_STC_runTest(SDL_STC_Inst instance );
296 static void SDL_STC_delay(int32_t count);
304 static void SDL_Delay(void);
312 void SDL_STC_dspInit(void);
313
318 /**************************************************************************
319 * Register Overlay Structure
320 **************************************************************************/
321
322 typedef struct
323 {
325 volatile uint32_t STCGCR0;
327 volatile uint32_t STCGCR1;
329 volatile uint32_t STCTPR;
331 volatile uint32_t STC_CADDR;
333 volatile uint32_t STCCICR;
335 volatile uint32_t STCGSTAT;
337 volatile uint32_t STCFSTAT;
339 volatile uint32_t STCSCSCR;
341 volatile uint32_t STC_CADDR2;
343 volatile uint32_t STC_CLKDIV;
345 volatile uint32_t STC_SEGPLR;
347 volatile uint32_t SEG0_START_ADDR;
349 volatile uint32_t SEG1_START_ADDR;
351 volatile uint32_t SEG2_START_ADDR;
353 volatile uint32_t SEG3_START_ADDR;
354
355
357 volatile uint32_t CORE1_CURMISR_0;
359 volatile uint32_t CORE1_CURMISR_1;
361 volatile uint32_t CORE1_CURMISR_2;
363 volatile uint32_t CORE1_CURMISR_3;
365 volatile uint32_t CORE1_CURMISR_4;
367 volatile uint32_t CORE1_CURMISR_5;
369 volatile uint32_t CORE1_CURMISR_6;
371 volatile uint32_t CORE1_CURMISR_7;
373 volatile uint32_t CORE1_CURMISR_8;
375 volatile uint32_t CORE1_CURMISR_9;
377 volatile uint32_t CORE1_CURMISR_10;
379 volatile uint32_t CORE1_CURMISR_11;
381 volatile uint32_t CORE1_CURMISR_12;
383 volatile uint32_t CORE1_CURMISR_13;
385 volatile uint32_t CORE1_CURMISR_14;
387 volatile uint32_t CORE1_CURMISR_15;
389 volatile uint32_t CORE1_CURMISR_16;
391 volatile uint32_t CORE1_CURMISR_17;
393 volatile uint32_t CORE1_CURMISR_18;
395 volatile uint32_t CORE1_CURMISR_19;
397 volatile uint32_t CORE1_CURMISR_20;
399 volatile uint32_t CORE1_CURMISR_21;
401 volatile uint32_t CORE1_CURMISR_22;
403 volatile uint32_t CORE1_CURMISR_23;
405 volatile uint32_t CORE1_CURMISR_24;
407 volatile uint32_t CORE1_CURMISR_25;
409 volatile uint32_t CORE1_CURMISR_26;
411 volatile uint32_t CORE1_CURMISR_27;
412
413 } SDL_stcRegs;
414
415
416
417 /**************************************************************************
418 * Register Macros
419 **************************************************************************/
420
421 #define SDL_STC_STCGCR0 (0x00000000U)
422 #define SDL_STC_STCGCR1 (0x00000004U)
423 #define SDL_STC_STCTPR (0x00000008U)
424 #define SDL_STC_CADDR (0x0000000CU)
425 #define SDL_STC_STCCICR (0x00000010U)
426 #define SDL_STC_STCGSTAT (0x00000014U)
427 #define SDL_STC_STCFSTAT (0x00000018U)
428 #define SDL_STC_STCSCSCR (0x0000001CU)
429 #define SDL_STC_CADDR2 (0x00000020U)
430 #define SDL_STC_CLKDIV (0x00000024U)
431 #define SDL_STC_SEGPLR (0x00000028U)
432 #define SDL_STC_SEG0_START_ADDR (0x0000002CU)
433 #define SDL_STC_SEG1_START_ADDR (0x00000030U)
434 #define SDL_STC_SEG2_START_ADDR (0x00000034U)
435 #define SDL_STC_SEG3_START_ADDR (0x00000038U)
436
437
438 /**************************************************************************
439 * Field Definition Macros
440 **************************************************************************/
441
442
443 /* STC_CTRL0 */
444
445 #define SDL_STC_STCGCR0_INTCOUNT_B16_MASK (0xFFFF0000U)
446 #define SDL_STC_STCGCR0_INTCOUNT_B16_SHIFT (16U)
447 #define SDL_STC_STCGCR0_INTCOUNT_B16_MAX (0xFFFF0000U)
448
449 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MASK (0x00000700U)
450 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_SHIFT (8U)
451 #define SDL_STC_STCGCR0_CAP_IDLE_CYCLE_MAX (0x00000700U)
452
453 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MASK (0x000000E0U)
454 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_SHIFT (5U)
455 #define SDL_STC_STCGCR0_SCANEN_HIGH_CAP_IDLE_CYCLE_MAX (0x000000E0U)
456
457 #define SDL_STC_STCGCR0_RS_CNT_B1_MASK (0x00000003U)
458 #define SDL_STC_STCGCR0_RS_CNT_B1_SHIFT (0U)
459
460
461 /* STC_CTRL1 */
462
463 #define SDL_STC_SEG0_CORE_SEL_MASK (0x00000F00U)
464 #define SDL_STC_SEG0_CORE_SEL_SHIFT (8U)
465 #define SDL_STC_SEG0_CORE_SEL_ENABLE (0x1U)
466
467
468 #define SDL_STC_CODEC_SPREAD_MODE_MASK (0x00000040U)
469 #define SDL_STC_CODEC_SPREAD_MODE_SHIFT (6U)
470 #define SDL_STC_CODEC_SPREAD_MODE_ENABLE (0x1U)
471 #define SDL_STC_CODEC_SPREAD_MODE_DISABLE (0x0U)
472
473 #define SDL_STC_LP_SCAN_MODE_MASK (0x00000020U)
474 #define SDL_STC_LP_SCAN_MODE_SHIFT (5U)
475 #define SDL_STC_LP_SCAN_MODE_ENABLE (0x1U)
476 #define SDL_STC_LP_SCAN_MODE_DISABLE (0x0U)
477
478
479 #define SDL_STC_ROM_ACCESS_INV_MASK (0x00000010U)
480 #define SDL_STC_ROM_ACCESS_INV_SHIFT (4U)
481 #define SDL_STC_ROM_ACCESS_INV_DISABLE (0x0U)
482
483 #define SDL_STC_ST_ENA_B4_MASK (0x0000000FU)
484 #define SDL_STC_ST_ENA_B4_SHIFT (0x00000000U)
485 #define SDL_STC_ST_ENA_B4_ENABLE (0xAU)
486
487
488
489 /* STC_STCTPR */
490
491 #define SDL_STC_TO_PRELOAD_MASK (0xFFFFFFFFU)
492 #define SDL_STC_TO_PRELOAD_SHIFT (0x00000000U)
493 #define SDL_STC_TO_PRELOAD_MAX (0xFFFFFFFFU)
494
495 /* STC_CADDR */
496
497 #define SDL_STC_ADDR1_MASK (0xFFFFFFFFU)
498 #define SDL_STC_ADDR1_SHIFT (0x00000000U)
499
500
501 /* STC_STCCICR */
502
503 #define SDL_STC_CORE2_ICOUNT_MASK (0xFFFF0000U)
504 #define SDL_STC_CORE2_ICOUNT_SHIFT (16U)
505
506 #define SDL_STC_CORE1_ICOUNT_MASK (0x0000FFFFU)
507 #define SDL_STC_CORE1_ICOUNT_SHIFT (0x00000000U)
508
509
510 /* STC_STCGSTAT */
511
512 #define SDL_STC_ST_ACTIVE_MASK (0x00000F00U)
513 #define SDL_STC_ST_ACTIVE_SHIFT (8U)
514 #define SDL_STC_ST_ACTIVE_ENABLE (0xAU)
515
516
517 #define SDL_STC_TEST_FAIL_MASK (0x00000002U)
518 #define SDL_STC_TEST_FAIL_SHIFT (1U)
519 #define SDL_STC_TEST_FAIL_ENABLE (0x1U)
520 #define SDL_STC_TEST_FAIL_DISABLE (0x0U)
521
522 #define SDL_STC_TEST_DONE_MASK (0x00000001U)
523 #define SDL_STC_TEST_DONE_SHIFT (0U)
524 #define SDL_STC_TEST_DONE_ENABLE (0x1U)
525 #define SDL_STC_TEST_DONE_DISABLE (0x0U)
526
527 /* STC_STCFSTAT */
528
529 #define SDL_STC_FSEG_ID_MASK (0x00000018U)
530 #define SDL_STC_FSEG_ID_SHIFT (3U)
531
532
533 #define SDL_STC_TO_ER_B1_MASK (0x00000004U)
534 #define SDL_STC_TO_ER_B1_SHIFT (2U)
535 #define SDL_STC_TO_ER_B1_ENABLE (0x1U)
536 #define SDL_STC_TO_ER_B1_DISABLE (0x0U)
537
538 #define SDL_STC_CPU2_FAIL_B1_MASK (0x00000002U)
539 #define SDL_STC_CPU2_FAIL_B1_SHIFT (0x1U)
540 #define SDL_STC_CPU2_FAIL_B1_ENABLE (0x1U)
541 #define SDL_STC_CPU2_FAIL_B1_DISABLE (0x0U)
542
543 #define SDL_STC_CPU1_FAIL_B1_MASK (0x00000001U)
544 #define SDL_STC_CPU1_FAIL_B1_SHIFT (0U)
545 #define SDL_STC_CPU1_FAIL_B1_ENABLE (0x1U)
546 #define SDL_STC_CPU1_FAIL_B1_DISABLE (0x0U)
547
548 /* STCSCSCR */
549
550 #define SDL_STC_FAULT_INS_B1_MASK (0x00000010U)
551 #define SDL_STC_FAULT_INS_B1_SHIFT (4U)
552 #define SDL_STC_FAULT_INS_B1_ENABLE (0x1U)
553 #define SDL_STC_FAULT_INS_B1_DISABLE (0x0U)
554
555
556 #define SDL_STC_SELF_CHECK_KEY_B4_MASK (0x0000000FU)
557 #define SDL_STC_SELF_CHECK_KEY_B4_SHIFT (0U)
558 #define SDL_STC_SELF_CHECK_KEY_B4_ENABLE (0xAU)
559 #define SDL_STC_SELF_CHECK_KEY_B4_DISABLE (0U)
560
561
562
563 /* STC_CADDR2 */
564
565 #define SDL_STC_ADDR2_MASK (0xFFFFFFFFU)
566 #define SDL_STC_ADDR2_SHIFT (0x00000000U)
567
568 /* STC_CLKDIV */
569
570 #define SDL_STC_CLKDIV0_MASK (0x07000000U)
571 #define SDL_STC_CLKDIV0_SHIFT (24U)
572 #define SDL_STC_CLKDIV1_MASK (0x00070000U)
573 #define SDL_STC_CLKDIV1_SHIFT (16U)
574 #define SDL_STC_CLKDIV2_MASK (0x00000700U)
575 #define SDL_STC_CLKDIV2_SHIFT (8U)
576 #define SDL_STC_CLKDIV3_MASK (0x00000007U)
577 #define SDL_STC_CLKDIV3_SHIFT (0U)
578
579 /* STC_SEGPLR */
580
581 #define SDL_STC_SEGPLR_MASK (0x00000003U)
582 #define SDL_STC_SEGPLR_SHIFT (0U)
583
584 /* SEG0_START_ADDR */
585
586 #define SDL_STC_SEG0_START_ADDR_MASK (0x000FFFFFU)
587 #define SDL_STC_SEG0_START_ADDR_SHIFT (0U)
588
589 /* SEG1_START_ADDR */
590
591 #define SDL_STC_SEG1_START_ADDR0_MASK (0x000FFFFFU)
592 #define SDL_STC_SEG1_START_ADDR0_SHIFT (0U)
593
594 /* SEG2_START_ADDR */
595
596 #define SDL_STC_SEG2_START_ADDR0_MASK (0x000FFFFFU)
597 #define SDL_STC_SEG2_START_ADDR0_SHIFT (0U)
598
599 /* SEG3_START_ADDR */
600
601 #define SDL_STC_SEG3_START_ADDR0_MASK (0x000FFFFFU)
602 #define SDL_STC_SEG3_START_ADDR0_SHIFT (0U)
603
604 /* MSS_RCM */
605 #define SDL_MSS_STC_RESET_MASK (0x00000004U)
606 #define SDL_MSS_STC_RESET_SHIFT (2U)
607
608 #define SDL_MSS_STC_RESET_CLEAR_MASK (0x00000007)
609 #define SDL_MSS_STC_RESET_CLEAR_SHIFT (0U)
610 #define SDL_MSS_STC_RESET_CLEAR_ENABLE (0x7U)
611
612 /* DSS_RCM */
613 #define SDL_DSS_STC_RESET_MASK (0x00000020U)
614 #define SDL_DSS_STC_RESET_SHIFT (5U)
615
616
617 /*DSS_ICFG*/
618 #define SDL_DSS_DSP_ICFG_PDCCMD_GEMPD_MASK (0x00010000U)
619 #define SDL_DSS_DSP_ICFG_PDCCMD_GEMPD_SHIFT (16U)
620
621 #ifdef __cplusplus
622 }
623 #endif
624 #endif /* SDLR_STC_H_ */
SDL_stcRegs::CORE1_CURMISR_8
volatile uint32_t CORE1_CURMISR_8
Definition: stc/v0/sdl_stc.h:373
SDL_stcRegs::STCSCSCR
volatile uint32_t STCSCSCR
Definition: stc/v0/sdl_stc.h:339
SDL_stcRegs::CORE1_CURMISR_24
volatile uint32_t CORE1_CURMISR_24
Definition: stc/v0/sdl_stc.h:405
SDL_stcRegs::CORE1_CURMISR_13
volatile uint32_t CORE1_CURMISR_13
Definition: stc/v0/sdl_stc.h:383
SDL_stcRegs::CORE1_CURMISR_4
volatile uint32_t CORE1_CURMISR_4
Definition: stc/v0/sdl_stc.h:365
SDL_STC_getStatus
int32_t SDL_STC_getStatus(SDL_STC_Inst instance)
This API is used to get status for STC result.
SDL_STC_COMPLETED_FAILURE
@ SDL_STC_COMPLETED_FAILURE
Definition: stc/v0/sdl_stc.h:199
SDL_STC_Config::intervalNum
uint32_t intervalNum
Definition: stc/v0/sdl_stc.h:171
SDL_stcRegs::CORE1_CURMISR_0
volatile uint32_t CORE1_CURMISR_0
Definition: stc/v0/sdl_stc.h:357
SDL_stcRegs::CORE1_CURMISR_14
volatile uint32_t CORE1_CURMISR_14
Definition: stc/v0/sdl_stc.h:385
SDL_STC_NEG_TEST
@ SDL_STC_NEG_TEST
Definition: stc/v0/sdl_stc.h:214
SDL_stcRegs::CORE1_CURMISR_18
volatile uint32_t CORE1_CURMISR_18
Definition: stc/v0/sdl_stc.h:393
SDL_stcRegs::SEG0_START_ADDR
volatile uint32_t SEG0_START_ADDR
Definition: stc/v0/sdl_stc.h:347
SDL_STC_TestResult
SDL_STC_TestResult
Definition: stc/v0/sdl_stc.h:195
SDL_stcRegs::CORE1_CURMISR_21
volatile uint32_t CORE1_CURMISR_21
Definition: stc/v0/sdl_stc.h:399
SDL_stcRegs::CORE1_CURMISR_25
volatile uint32_t CORE1_CURMISR_25
Definition: stc/v0/sdl_stc.h:407
SDL_stcRegs::STC_CADDR2
volatile uint32_t STC_CADDR2
Definition: stc/v0/sdl_stc.h:341
SDL_stcRegs::CORE1_CURMISR_10
volatile uint32_t CORE1_CURMISR_10
Definition: stc/v0/sdl_stc.h:377
SDL_STC_NOT_COMPLETED
@ SDL_STC_NOT_COMPLETED
Definition: stc/v0/sdl_stc.h:201
SDL_stcRegs::CORE1_CURMISR_3
volatile uint32_t CORE1_CURMISR_3
Definition: stc/v0/sdl_stc.h:363
SDL_STC_ScanModeconfig::codecSpreadMode
uint32_t codecSpreadMode
Definition: stc/v0/sdl_stc.h:158
SDL_stcRegs::CORE1_CURMISR_15
volatile uint32_t CORE1_CURMISR_15
Definition: stc/v0/sdl_stc.h:387
SDL_stcRegs::CORE1_CURMISR_9
volatile uint32_t CORE1_CURMISR_9
Definition: stc/v0/sdl_stc.h:375
SDL_stcRegs::CORE1_CURMISR_11
volatile uint32_t CORE1_CURMISR_11
Definition: stc/v0/sdl_stc.h:379
SDL_STC_dspInit
void SDL_STC_dspInit(void)
This API is used to initialize all the required configuration in RCM & CTRL Module for performing DSP...
SDL_STC_Inst
SDL_STC_Inst
Definition: sdl_stc_soc.h:79
SDL_STC_ScanModeconfig::capIdleCycle
uint32_t capIdleCycle
Definition: stc/v0/sdl_stc.h:160
SDL_stcRegs::STCGSTAT
volatile uint32_t STCGSTAT
Definition: stc/v0/sdl_stc.h:335
SDL_STC_ScanModeconfig
Structure containing parameters for STC module configuration.
Definition: stc/v0/sdl_stc.h:154
SDL_STC_TEST
@ SDL_STC_TEST
Definition: stc/v0/sdl_stc.h:212
SDL_stcRegs::CORE1_CURMISR_22
volatile uint32_t CORE1_CURMISR_22
Definition: stc/v0/sdl_stc.h:401
SDL_stcRegs::CORE1_CURMISR_17
volatile uint32_t CORE1_CURMISR_17
Definition: stc/v0/sdl_stc.h:391
SDL_STC_runTest
static int32_t SDL_STC_runTest(SDL_STC_Inst instance)
This API is used to enable the STC module.
SDL_stcRegs::CORE1_CURMISR_2
volatile uint32_t CORE1_CURMISR_2
Definition: stc/v0/sdl_stc.h:361
SDL_stcRegs::CORE1_CURMISR_6
volatile uint32_t CORE1_CURMISR_6
Definition: stc/v0/sdl_stc.h:369
SDL_stcRegs::CORE1_CURMISR_7
volatile uint32_t CORE1_CURMISR_7
Definition: stc/v0/sdl_stc.h:371
SDL_stcRegs::CORE1_CURMISR_19
volatile uint32_t CORE1_CURMISR_19
Definition: stc/v0/sdl_stc.h:395
SDL_STC_Config
Definition: stc/v0/sdl_stc.h:169
INVALID_TEST
@ INVALID_TEST
Definition: stc/v0/sdl_stc.h:216
SDL_stcRegs::CORE1_CURMISR_12
volatile uint32_t CORE1_CURMISR_12
Definition: stc/v0/sdl_stc.h:381
SDL_stcRegs::STC_CLKDIV
volatile uint32_t STC_CLKDIV
Definition: stc/v0/sdl_stc.h:343
SDL_stcRegs::SEG1_START_ADDR
volatile uint32_t SEG1_START_ADDR
Definition: stc/v0/sdl_stc.h:349
SDL_STC_NOT_RUN
@ SDL_STC_NOT_RUN
Definition: stc/v0/sdl_stc.h:203
SDL_Delay
static void SDL_Delay(void)
This API is used to execute asm nop operation.
SDL_STC_Config::maxRunTime
uint32_t maxRunTime
Definition: stc/v0/sdl_stc.h:173
SDL_STC_selfTest
int32_t SDL_STC_selfTest(SDL_STC_Inst instance, SDL_STC_TestType testType, SDL_STC_Config *pConfig)
This API is used to run the STC module.
SDL_STC_COMPLETED_SUCCESS
@ SDL_STC_COMPLETED_SUCCESS
Definition: stc/v0/sdl_stc.h:197
SDL_STC_delay
static void SDL_STC_delay(int32_t count)
This API is used to provide delay for processor core.
SDL_stcRegs::STCTPR
volatile uint32_t STCTPR
Definition: stc/v0/sdl_stc.h:329
SDL_STC_TestType
SDL_STC_TestType
Definition: stc/v0/sdl_stc.h:210
SDL_STC_configure
static int32_t SDL_STC_configure(SDL_STC_Inst instance, SDL_STC_Config *pConfig, SDL_STC_TestType testType)
This API is used to configure STC module.
INVALID_RESULT
@ INVALID_RESULT
Definition: stc/v0/sdl_stc.h:205
SDL_stcRegs::CORE1_CURMISR_5
volatile uint32_t CORE1_CURMISR_5
Definition: stc/v0/sdl_stc.h:367
SDL_stcRegs::STCGCR1
volatile uint32_t STCGCR1
Definition: stc/v0/sdl_stc.h:327
SDL_stcRegs::STCCICR
volatile uint32_t STCCICR
Definition: stc/v0/sdl_stc.h:333
SDL_stcRegs::CORE1_CURMISR_20
volatile uint32_t CORE1_CURMISR_20
Definition: stc/v0/sdl_stc.h:397
SDL_STC_Config::clkDiv
uint32_t clkDiv
Definition: stc/v0/sdl_stc.h:175
SDL_STC_Config::modeConfig
SDL_STC_ScanModeconfig modeConfig
Definition: stc/v0/sdl_stc.h:181
SDL_stcRegs::STCFSTAT
volatile uint32_t STCFSTAT
Definition: stc/v0/sdl_stc.h:337
sdlr.h
This file contains the macro definations for Register layer.
SDL_STC_ScanModeconfig::scanEnHighCap_idleCycle
uint32_t scanEnHighCap_idleCycle
Definition: stc/v0/sdl_stc.h:162
SDL_stcRegs
Definition: stc/v0/sdl_stc.h:323
SDL_stcRegs::CORE1_CURMISR_26
volatile uint32_t CORE1_CURMISR_26
Definition: stc/v0/sdl_stc.h:409
SDL_stcRegs::STC_CADDR
volatile uint32_t STC_CADDR
Definition: stc/v0/sdl_stc.h:331
SDL_stcRegs::SEG3_START_ADDR
volatile uint32_t SEG3_START_ADDR
Definition: stc/v0/sdl_stc.h:353
SDL_stcRegs::CORE1_CURMISR_1
volatile uint32_t CORE1_CURMISR_1
Definition: stc/v0/sdl_stc.h:359
SDL_stcRegs::CORE1_CURMISR_23
volatile uint32_t CORE1_CURMISR_23
Definition: stc/v0/sdl_stc.h:403
SDL_stcRegs::CORE1_CURMISR_27
volatile uint32_t CORE1_CURMISR_27
Definition: stc/v0/sdl_stc.h:411
SDL_STC_Config::romStartAddress
uint32_t romStartAddress
Definition: stc/v0/sdl_stc.h:177
SDL_stcRegs::STC_SEGPLR
volatile uint32_t STC_SEGPLR
Definition: stc/v0/sdl_stc.h:345
SDL_stcRegs::STCGCR0
volatile uint32_t STCGCR0
Definition: stc/v0/sdl_stc.h:325
SDL_stcRegs::SEG2_START_ADDR
volatile uint32_t SEG2_START_ADDR
Definition: stc/v0/sdl_stc.h:351
SDL_STC_Config::pRomStartAdd
uint32_t pRomStartAdd
Definition: stc/v0/sdl_stc.h:179
SDL_stcRegs::CORE1_CURMISR_16
volatile uint32_t CORE1_CURMISR_16
Definition: stc/v0/sdl_stc.h:389
SDL_STC_ScanModeconfig::lpScanMode
uint32_t lpScanMode
Definition: stc/v0/sdl_stc.h:156