AM261x MCU+ SDK: SIPC_MailboxConfig Struct Reference

| AM261x MCU+ SDK 26.00.00 |

Data Fields
SIPC_MailboxConfig Struct Reference

## Detailed Description

This structure describes the mailbox information to send a message from core A to core B.

## Data Fields
uint32_t | writeDoneMailboxBaseAddr
uint32_t | readReqMailboxBaseAddr
uint32_t | readReqMailboxClrBaseAddr
uint8_t | wrIntrBitPos
uint8_t | rdIntrBitPos
SIPC_SwQueue * | swQ

## Field Documentation

## ◆ writeDoneMailboxBaseAddr

uint32_t SIPC_MailboxConfig::writeDoneMailboxBaseAddr

Mailbox register address at which core will post interrupt

## ◆ readReqMailboxBaseAddr

uint32_t SIPC_MailboxConfig::readReqMailboxBaseAddr

Mailbox register address at which core will receive interrupt

## ◆ readReqMailboxClrBaseAddr

uint32_t SIPC_MailboxConfig::readReqMailboxClrBaseAddr

Mailbox register address to clear interrupt

## ◆ wrIntrBitPos

uint8_t SIPC_MailboxConfig::wrIntrBitPos

Bit pos in the mailbox register which should be set to post the interrupt to other core

## ◆ rdIntrBitPos

uint8_t SIPC_MailboxConfig::rdIntrBitPos

Bit pos in the mailbox register which should cleared clear an interrupt by the other core

## ◆ swQ

SIPC_SwQueue* SIPC_MailboxConfig::swQ

Infomration about the SW queue associated with this HW mailbox