AM261x MCU+ SDK: sdl_ecc_bus_safety_soc.h Source File

| AM261x MCU+ SDK 26.00.00 |

sdl_ecc_bus_safety_soc.h
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1 /*
2 * Copyright (c) 2022-25 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
39 #ifndef SDL_MSS_CR5_SOC_H_
40 #define SDL_MSS_CR5_SOC_H_
41
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45
46 #include <sdl/include/am261x/sdlr_soc_baseaddress.h>
47 #include <sdl/include/am261x/sdlr_mss_ctrl.h>
48
49 #ifdef _cplusplus
50 extern "C" {
51 #endif
52
53 /* ========================================================================== */
54 /* Macros & Typedefs */
55 /* ========================================================================== */
56 #define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE
57 #define DWORD (0x20U)
58 #define SDL_MSS_CTRL_MSS_CR5A0_AHB_BASE (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE)
59 #define SDL_MSS_CTRL_MSS_CR5B0_AHB_BASE (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE)
60 #define SDL_MSS_CTRL_MSS_CR5A0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)
61 #define SDL_MSS_CTRL_MSS_CR5B0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)
62
63 #define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020U)
64 #define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020U)
65 #define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE)
66 #define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE)
67 #define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)
68 #define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)
69 #define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE+0x3FFFU)
70 #define SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE+0X1FFCU-DWORD)
71 #define SDL_CORE_VBUSP_START (0x50800000U)
72 #define SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START+0X1FFCU)
73 #define SDL_PERI_VBUSP_START (0x50200000U)
74 #define SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START+0X7FFFFCU)
75 #define SDL_L2OCRAM_BANK0 (SDL_L2OCRAM_U_BASE)
76 #define SDL_L2OCRAM_BANK0_END (SDL_L2OCRAM_U_BASE + 0x7FFFFU)
77 #define SDL_L2OCRAM_BANK1 (SDL_L2OCRAM_U_BASE + 0x80000U)
78 #define SDL_L2OCRAM_BANK1_END (SDL_L2OCRAM_U_BASE + 0xFFFFFU)
79 #define SDL_L2OCRAM_BANK2 (SDL_L2OCRAM_U_BASE + 0x100000U)
80 #define SDL_L2OCRAM_BANK2_END (SDL_L2OCRAM_U_BASE + 0x17FFFFU)
81 #define SDL_MSS_QSPI_U_BASE (SDL_QSPI0_U_BASE)
82 #define SDL_MSS_QSPI_U_SIZE (0x000001D8U)
83 #define SDL_MSS_QSPI_U_END (SDL_MSS_QSPI_U_BASE + SDL_MSS_QSPI_U_SIZE)
84 #define SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)
85 #define SDL_MSS_MCRC_U_SIZE (0x000001E4U)
86 #define SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)
87
88 #define SDL_MSS_CR5A_AXI_RD_START (0x35000000U)
89 #define SDL_MSS_CR5A_AXI_RD_END (0x350003FFU-8U)
90 #define SDL_MSS_CR5A_AXI_WR_START (0x35000000U)
91 #define SDL_MSS_CR5A_AXI_WR_END (0x350003FFU-8U)
92 #define SDL_MSS_CR5A_AXI_S_START (SDL_R5SS0_CORE0_TCMB_U_BASE)
93 #define SDL_MSS_CR5A_AXI_S_END (SDL_R5SS0_CORE0_TCMB_U_BASE + 0xFFFFU)
94
95 #define SDL_MSS_CR5B_AXI_RD_START (0x35000000U)
96 #define SDL_MSS_CR5B_AXI_RD_END (0x350003FFU-8U)
97 #define SDL_MSS_CR5B_AXI_WR_START (0x35000000U)
98 #define SDL_MSS_CR5B_AXI_WR_END (0x350003FFU-8U)
99 #define SDL_MSS_CR5B_AXI_S_START (SDL_R5SS0_CORE1_TCMB_U_BASE)
100 #define SDL_MSS_CR5B_AXI_S_END (SDL_R5SS0_CORE1_TCMB_U_BASE + 0x7FFFU)
101
102 #define SDL_MSS_CTRL_TPCC_A0_WR_BASE (0x52A40000U)
103 #define SDL_MSS_CTRL_TPCC_A0_WR_END (0x52A40400U-8U)
104
105 #define SDL_MSS_CTRL_TPCC_A1_WR_BASE (0x52A60000U)
106 #define SDL_MSS_CTRL_TPCC_A1_WR_END (0x52A60400U-8U)
107
108 #define SDL_MSS_CTRL_TPCC_A0_RD_BASE (0x52A40000U)
109 #define SDL_MSS_CTRL_TPCC_A0_RD_END (0x52A40400U-8U)
110
111 #define SDL_MSS_CTRL_TPCC_A1_RD_BASE (0x52A60000U)
112 #define SDL_MSS_CTRL_TPCC_A1_RD_END (0x52A60400U-8U)
113
114 #define SDL_MSS_VBUSP_BASE (0x35000000U)
115 #define SDL_MSS_VBUSP_BASE_END (0x350003FFU-8U)
116
117 #define SDL_MSS_VBUSP_PERI_BASE (0x35000000U)
118 #define SDL_MSS_VBUSP_PERI_BASE_END (0x350003FFU-8U)
119
120 #define SDL_MSS_CPSW_BASE (0x52800000U)
121 #define SDL_MSS_CPSW_BASE_END (0x52800400U-8U)
122
123 #define SDL_QSPI_U_BASE (0x48200000U)
124 #define SDL_QSPI_U_BASE_END (0x482001FFU-8U)
125
126 #define SDL_MCRC_U_BASE (0x35000000U)
127 #define SDL_MCRC_U_BASE_END (0x350003FFU-8U)
128
129 #define SDL_SCRP0_U_BASE (0x48000000U)
130 #define SDL_SCRP0_U_BASE_END (0x4803FFFFU-8U)
131
132 #define SDL_SCRP1_U_BASE (0x48000000U)
133 #define SDL_SCRP1_U_BASE_END (0x4803FFFFU-8U)
134
135 #define SDL_ICSSM0_PDSP0_U_BASE (SDL_ICSSM0_INTERNAL_U_BASE)
136 #define SDL_ICSSM0_PDSP0_U_SIZE (0x000000FFU)
137 #define SDL_ICSSM0_PDSP0_U_BASE_END (0x48038000U-8U)
138
139 #define SDL_ICSSM0_PDSP1_U_BASE (SDL_ICSSM0_INTERNAL_U_BASE)
140 #define SDL_ICSSM0_PDSP1_U_SIZE (0x000000FFU)
141 #define SDL_ICSSM0_PDSP1_U_BASE_END (0x48038000U-8U)
142
143 #define SDL_ICSSM0_S_BASE (SDL_ICSSM0_INTERNAL_U_BASE)
144 #define SDL_ICSSM0_S_SIZE (0x000000FFU)
145 #define SDL_ICSSM0_S_BASE_END (0x48038000U-8U)
146
147 #define SDL_ICSSM1_PDSP0_U_BASE (SDL_ICSS_M_ICSSM_1_PR1_PDSP0_IRAM_U_BASE)
148 #define SDL_ICSSM1_PDSP0_U_SIZE (0x000000FFU)
149 #define SDL_ICSSM1_PDSP0_U_BASE_END (SDL_ICSS_M_ICSSM_1_PR1_PDSP0_IRAM_U_BASE+SDL_ICSSM1_PDSP0_U_SIZE)
150
151 #define SDL_ICSSM1_PDSP1_U_BASE (SDL_ICSS_M_ICSSM_1_PR1_PDSP1_IRAM_U_BASE)
152 #define SDL_ICSSM1_PDSP1_U_SIZE (0x000000FFU)
153 #define SDL_ICSSM1_PDSP1_U_BASE_END (SDL_ICSS_M_ICSSM_1_PR1_PDSP1_IRAM_U_BASE+SDL_ICSSM1_PDSP1_U_SIZE)
154
155 #define SDL_ICSSM1_S_BASE (SDL_ICSS_M_ICSSM_1_PR1_CFG_SLV_U_BASE)
156 #define SDL_ICSSM1_S_SIZE (0x000000FFU)
157 #define SDL_ICSSM1_S_BASE_END (SDL_ICSS_M_ICSSM_1_PR1_CFG_SLV_U_BASE+SDL_ICSSM1_S_SIZE)
158
159 #define SDL_DAP_U_BASE (SDL_TOP_RCM_U_BASE)
160 #define SDL_DAP_U_BASE_END (SDL_TOP_RCM_U_BASE + (0x1FFFU-8U))
161
162 #define SDL_GPMC0_CFG_U_BASE_END (SDL_GPMC0_CFG_U_BASE+0X3FCU-DWORD)
163
164 #define SDL_OSPI_U_BASE SDL_FLASH_CONFIG_REG6_U_BASE
165 #define SDL_OSPI_U_BASE_END (SDL_FLASH_CONFIG_REG6_U_BASE+0x00001FFU)
166
167 #define SDL_USB_RD_U_BASE (SDL_USB_RAM0_U_BASE)
168 #define SDL_USB_RD_U_BASE_END (SDL_USB_RAM0_U_BASE + 0x00007FFCU)
169
170 #define SDL_USB_WR_U_BASE (SDL_USB_RAM0_U_BASE)
171 #define SDL_USB_WR_U_BASE_END (SDL_USB_RAM0_U_BASE + 0x00007FFCU)
172
173 #define SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)
174 #define SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)
175 #define SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)
176
177 #define SDL_ECC_BUS_SAFETY_MSS_READABLE_NODE 1U
178 #define SDL_ECC_BUS_SAFETY_MSS_WRITABLE_NODE 0U
179
180 #define SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE 4U
181 #define SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE 32U
182 #define SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG1_SIZE 16U
183 #define SDL_MSS_CTRL_MSS_VBUSP_VBUSM_ERRAGG0_SIZE (SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE + \
184 SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE)
185
186 /* nodeReadable1 and nodeReadable2 are arranged by bit field for */
187 /* each busSftyNode based on MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG, */
188 /* MSS_VBUSM_SAFETY_H_ERRAGG and MSS_VBUSM_SAFETY_L_ERRAGG */
189 /* For example 0xxxxxx30U, here '30(0x0011)' means 4th */
190 /* node(CR5A_AXI_RD) and 5th node(CR5B_AXI_RD) are readable */
191 #define SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_1_MASK 0x01800030U
192 #define SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_2_MASK 0x00002000U
193
194 /* Macro defines Ecc Bus Safety Nodes in the MSS Subsystem */
195
196 /* Aggregated_VBUSP_error_H nodes */
197 /* Listed as per MMR MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG */
198 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 0U
199 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 1U
200 #define SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 2U
201 #define SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 3U
202
203 /* Aggregated_VBUSM_error_H and Aggregated_VBUSM_error_L nodes */
204 /* Listed as per MMR MSS_CTRL MSS_VBUSM_SAFETY_H_ERRAGG */
205 /* and MSS_VBUSM_SAFETY_L_ERRAGG 0 Register */
206 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 4U
207 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 5U
208 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 6U
209 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 7U
210 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 8U
211 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 9U
212 #define SDL_ECC_BUS_SAFETY_DAP 16U
213 #define SDL_ECC_BUS_SAFETY_MSS_HSM_VBUSM_ERRH 17U
214 #define SDL_ECC_BUS_SAFETY_MSS_CPSW 18U
215 #define SDL_ECC_BUS_SAFETY_MSS_L2_A 19U
216 #define SDL_ECC_BUS_SAFETY_MSS_L2_B 20U
217 #define SDL_ECC_BUS_SAFETY_MSS_L2_C 21U
218 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 23U
219 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 24U
220 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 25U
221 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 26U
222 #define SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC0_RD 27U
223 #define SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC0_WR 28U
224 #define SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC1_RD 29U
225 #define SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC1_WR 30U
226 #define SDL_ECC_BUS_SAFETY_MSS_ICSSM0_PDSP0 31U
227 #define SDL_ECC_BUS_SAFETY_MSS_ICSSM0_PDSP1 32U
228 #define SDL_ECC_BUS_SAFETY_MSS_OSPI 33U
229 #define SDL_ECC_BUS_SAFETY_MSS_MCRC 34U
230 #define SDL_ECC_BUS_SAFETY_MSS_HSM_DTHE 35U
231
232
233 /* Listed as per MMR MSS_CTRL MSS_VBUSM_SAFETY_H_ERRAGG */
234 /* and MSS_VBUSM_SAFETY_L_ERRAGG 1 Register */
235 #define SDL_ECC_BUS_SAFETY_MSS_SCRP0 36U
236 #define SDL_ECC_BUS_SAFETY_MSS_SCRP1 37U
237 #define SDL_ECC_BUS_SAFETY_MSS_HSM_S 38U
238 #define SDL_ECC_BUS_SAFETY_MSS_ICSSM0_S 39U
239 #define SDL_ECC_BUS_SAFETY_MSS_MBOX 40U
240 #define SDL_ECC_BUS_SAFETY_MSS_STM_STIM 41U
241 #define SDL_ECC_BUS_SAFETY_MSS_MMC 42U
242 #define SDL_ECC_BUS_SAFETY_MSS_GPMC 43U
243 #define SDL_ECC_BUS_SAFETY_MSS_ICSSM1_PDSP0 46U
244 #define SDL_ECC_BUS_SAFETY_MSS_ICSSM1_PDSP1 47U
245 #define SDL_ECC_BUS_SAFETY_MSS_ICSSM1_S 48U
246 #define SDL_ECC_BUS_SAFETY_MSS_OSPI1 49U
247 #define SDL_ECC_BUS_SAFETY_MSS_USBSS_WR 50U
248 #define SDL_ECC_BUS_SAFETY_MSS_USBSS_RD 51U
249
250
251 #define SDL_ECC_BUS_SAFETY_SEC_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)
252 #define SDL_ECC_BUS_SAFETY_SEC_END_NODE (SDL_ECC_BUS_SAFETY_MSS_USBSS_RD)
253
254 #define SDL_ECC_BUS_SAFETY_DED_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)
255 #define SDL_ECC_BUS_SAFETY_DED_END_NODE (SDL_ECC_BUS_SAFETY_MSS_USBSS_RD)
256
257 #ifdef _cplusplus
258 }
259
260 #endif /*extern "C" */
261
262 #endif
263