AM261x MCU+ SDK: sdlr_pbist.h Source File

| AM261x MCU+ SDK 26.00.00 |

sdlr_pbist.h
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1 /********************************************************************
2 * Copyright (C) 2020-2022 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * Name : sdlr_pbist.h
33 */
34 #ifndef SDLR_PBIST_H_
35 #define SDLR_PBIST_H_
36
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41
42 #include <stdint.h>
43
44 /**************************************************************************
45 * Hardware Region :
46 **************************************************************************/
47
48
49 /**************************************************************************
50 * Register Overlay Structure
51 **************************************************************************/
52
53 typedef struct {
54 volatile uint32_t RF0L; /* Register Files / Instruction Registers */
55 volatile uint32_t RF1L; /* Register Files / Instruction Registers */
56 volatile uint32_t RF2L; /* Register Files / Instruction Registers */
57 volatile uint32_t RF3L; /* Register Files / Instruction Registers */
58 volatile uint32_t RF4L; /* Register Files / Instruction Registers */
59 volatile uint32_t RF5L; /* Register Files / Instruction Registers */
60 volatile uint32_t RF6L; /* Register Files / Instruction Registers */
61 volatile uint32_t RF7L; /* Register Files / Instruction Registers */
62 volatile uint32_t RF8L; /* Register Files / Instruction Registers */
63 volatile uint32_t RF9L; /* Register Files / Instruction Registers */
64 volatile uint32_t RF10L; /* Register Files / Instruction Registers */
65 volatile uint32_t RF11L; /* Register Files / Instruction Registers */
66 volatile uint32_t RF12L; /* Register Files / Instruction Registers */
67 volatile uint32_t RF13L; /* Register Files / Instruction Registers */
68 volatile uint32_t RF14L; /* Register Files / Instruction Registers */
69 volatile uint32_t RF15L; /* Register Files / Instruction Registers */
70 volatile uint32_t RF0U; /* Register Files / Instruction Registers */
71 volatile uint32_t RF1U; /* Register Files / Instruction Registers */
72 volatile uint32_t RF2U; /* Register Files / Instruction Registers */
73 volatile uint32_t RF3U; /* Register Files / Instruction Registers */
74 volatile uint32_t RF4U; /* Register Files / Instruction Registers */
75 volatile uint32_t RF5U; /* Register Files / Instruction Registers */
76 volatile uint32_t RF6U; /* Register Files / Instruction Registers */
77 volatile uint32_t RF7U; /* Register Files / Instruction Registers */
78 volatile uint32_t RF8U; /* Register Files / Instruction Registers */
79 volatile uint32_t RF9U; /* Register Files / Instruction Registers */
80 volatile uint32_t RF10U; /* Register Files / Instruction Registers */
81 volatile uint32_t RF11U; /* Register Files / Instruction Registers */
82 volatile uint32_t RF12U; /* Register Files / Instruction Registers */
83 volatile uint32_t RF13U; /* Register Files / Instruction Registers */
84 volatile uint32_t RF14U; /* Register Files / Instruction Registers */
85 volatile uint32_t RF15U; /* Register Files / Instruction Registers */
86 volatile uint8_t Resv_256[128];
87 volatile uint32_t A0; /* Variable Address Registers */
88 volatile uint32_t A1; /* Variable Address Registers */
89 volatile uint32_t A2; /* Variable Address Registers */
90 volatile uint32_t A3; /* Variable Address Registers */
91 volatile uint32_t L0; /* Variable Loop Count Registers */
92 volatile uint32_t L1; /* Variable Loop Count Registers */
93 volatile uint32_t L2; /* Variable Loop Count Registers */
94 volatile uint32_t L3; /* Variable Loop Count Registers */
95 volatile uint32_t D; /* Data Registers */
96 volatile uint32_t E; /* Data Registers */
97 volatile uint8_t Resv_304[8];
98 volatile uint32_t CA0; /* Constant Address Registers */
99 volatile uint32_t CA1; /* Constant Address Registers */
100 volatile uint32_t CA2; /* Constant Address Registers */
101 volatile uint32_t CA3; /* Constant Address Registers */
102 volatile uint32_t CL0; /* Constant Loop Count Registers */
103 volatile uint32_t CL1; /* Constant Loop Count Registers */
104 volatile uint32_t CL2; /* Constant Loop Count Registers */
105 volatile uint32_t CL3; /* Constant Loop Count Registers */
106 volatile uint32_t I0; /* Constant Increment Registers */
107 volatile uint32_t I1; /* Constant Increment Registers */
108 volatile uint32_t I2; /* Constant Increment Registers */
109 volatile uint32_t I3; /* Constant Increment Registers */
110 volatile uint32_t RAMT; /* RAM Configuration Register */
111 volatile uint32_t DLR; /* Datalogger Register */
112 volatile uint32_t CMS; /* Clock-Mux Select Register */
113 volatile uint32_t STR; /* Program Control Register */
114 volatile uint64_t SCR; /* Address Scrambling Register */
115 volatile uint32_t CSR; /* Chip Select Register */
116 volatile uint32_t FDLY; /* Fail Delay Register */
117 volatile uint32_t PACT; /* PACT Register */
118 volatile uint32_t PID; /* PBIST_ID Register */
119 volatile uint32_t OVER; /* Override Register */
120 volatile uint8_t Resv_400[4];
121 volatile uint64_t FSRF; /* Fail Status Fail Register */
122 volatile uint64_t FSRC; /* Fail Status Count Register */
123 volatile uint64_t FSRA; /* Fail Status Address Register */
124 volatile uint32_t FSRDL0; /* Fail Status Data Registers */
125 volatile uint8_t Resv_432[4];
126 volatile uint32_t FSRDL1; /* Fail Status Data Registers */
127 volatile uint32_t MARGIN_MODE; /* Fail Status Fail Register */
128 volatile uint32_t WRENZ; /* Fail Status Fail Register */
129 volatile uint32_t PAGE_PGS; /* Fail Status Fail Register */
130 volatile uint32_t ROM; /* ROM Mask Register */
131 volatile uint32_t ALGO; /* Algorithm Mask Register */
132 #if defined(IP_VERSION_PBIST_V0)
133 volatile uint32_t RINFOL; /* RAM Info Mask Register */
134 volatile uint32_t RINFOU; /* RAM Info Mask Register */
135 #elif defined(IP_VERSION_PBIST_V0_1)
136 volatile uint64_t RINFO; /* RAM Info Mask Register */
137 #endif
138 } SDL_pbistRegs;
139
140
141 /**************************************************************************
142 * Register Macros
143 **************************************************************************/
144
145 #define SDL_PBIST_RF0L (0x00000000U)
146 #define SDL_PBIST_RF1L (0x00000004U)
147 #define SDL_PBIST_RF2L (0x00000008U)
148 #define SDL_PBIST_RF3L (0x0000000CU)
149 #define SDL_PBIST_RF4L (0x00000010U)
150 #define SDL_PBIST_RF5L (0x00000014U)
151 #define SDL_PBIST_RF6L (0x00000018U)
152 #define SDL_PBIST_RF7L (0x0000001CU)
153 #define SDL_PBIST_RF8L (0x00000020U)
154 #define SDL_PBIST_RF9L (0x00000024U)
155 #define SDL_PBIST_RF10L (0x00000028U)
156 #define SDL_PBIST_RF11L (0x0000002CU)
157 #define SDL_PBIST_RF12L (0x00000030U)
158 #define SDL_PBIST_RF13L (0x00000034U)
159 #define SDL_PBIST_RF14L (0x00000038U)
160 #define SDL_PBIST_RF15L (0x0000003CU)
161 #define SDL_PBIST_RF0U (0x00000040U)
162 #define SDL_PBIST_RF1U (0x00000044U)
163 #define SDL_PBIST_RF2U (0x00000048U)
164 #define SDL_PBIST_RF3U (0x0000004CU)
165 #define SDL_PBIST_RF4U (0x00000050U)
166 #define SDL_PBIST_RF5U (0x00000054U)
167 #define SDL_PBIST_RF6U (0x00000058U)
168 #define SDL_PBIST_RF7U (0x0000005CU)
169 #define SDL_PBIST_RF8U (0x00000060U)
170 #define SDL_PBIST_RF9U (0x00000064U)
171 #define SDL_PBIST_RF10U (0x00000068U)
172 #define SDL_PBIST_RF11U (0x0000006CU)
173 #define SDL_PBIST_RF12U (0x00000070U)
174 #define SDL_PBIST_RF13U (0x00000074U)
175 #define SDL_PBIST_RF14U (0x00000078U)
176 #define SDL_PBIST_RF15U (0x0000007CU)
177 #define SDL_PBIST_A0 (0x00000100U)
178 #define SDL_PBIST_A1 (0x00000104U)
179 #define SDL_PBIST_A2 (0x00000108U)
180 #define SDL_PBIST_A3 (0x0000010CU)
181 #define SDL_PBIST_L0 (0x00000110U)
182 #define SDL_PBIST_L1 (0x00000114U)
183 #define SDL_PBIST_L2 (0x00000118U)
184 #define SDL_PBIST_L3 (0x0000011CU)
185 #define SDL_PBIST_D (0x00000120U)
186 #define SDL_PBIST_E (0x00000124U)
187 #define SDL_PBIST_CA0 (0x00000130U)
188 #define SDL_PBIST_CA1 (0x00000134U)
189 #define SDL_PBIST_CA2 (0x00000138U)
190 #define SDL_PBIST_CA3 (0x0000013CU)
191 #define SDL_PBIST_CL0 (0x00000140U)
192 #define SDL_PBIST_CL1 (0x00000144U)
193 #define SDL_PBIST_CL2 (0x00000148U)
194 #define SDL_PBIST_CL3 (0x0000014CU)
195 #define SDL_PBIST_I0 (0x00000150U)
196 #define SDL_PBIST_I1 (0x00000154U)
197 #define SDL_PBIST_I2 (0x00000158U)
198 #define SDL_PBIST_I3 (0x0000015CU)
199 #define SDL_PBIST_RAMT (0x00000160U)
200 #define SDL_PBIST_DLR (0x00000164U)
201 #define SDL_PBIST_CMS (0x00000168U)
202 #define SDL_PBIST_STR (0x0000016CU)
203 #define SDL_PBIST_SCR (0x00000170U)
204 #define SDL_PBIST_CSR (0x00000178U)
205 #define SDL_PBIST_FDLY (0x0000017CU)
206 #define SDL_PBIST_PACT (0x00000180U)
207 #define SDL_PBIST_PID (0x00000184U)
208 #define SDL_PBIST_OVER (0x00000188U)
209 #define SDL_PBIST_FSRF (0x00000190U)
210 #define SDL_PBIST_FSRC (0x00000198U)
211 #define SDL_PBIST_FSRA (0x000001A0U)
212 #define SDL_PBIST_FSRDL0 (0x000001A8U)
213 #define SDL_PBIST_FSRDL1 (0x000001B0U)
214 #define SDL_PBIST_MARGIN_MODE (0x000001B4U)
215 #define SDL_PBIST_WRENZ (0x000001B8U)
216 #define SDL_PBIST_PAGE_PGS (0x000001BCU)
217 #define SDL_PBIST_ROM (0x000001C0U)
218 #define SDL_PBIST_ALGO (0x000001C4U)
219 #define SDL_PBIST_RINFO (0x000001C8U)
220
221 /**************************************************************************
222 * Field Definition Macros
223 **************************************************************************/
224
225
226 /* RF0L */
227
228 #define SDL_PBIST_RF0L_RF0L_MASK (0xFFFFFFFFU)
229 #define SDL_PBIST_RF0L_RF0L_SHIFT (0x00000000U)
230 #define SDL_PBIST_RF0L_RF0L_MAX (0xFFFFFFFFU)
231
232 /* RF1L */
233
234 #define SDL_PBIST_RF1L_RF1L_MASK (0xFFFFFFFFU)
235 #define SDL_PBIST_RF1L_RF1L_SHIFT (0x00000000U)
236 #define SDL_PBIST_RF1L_RF1L_MAX (0xFFFFFFFFU)
237
238 /* RF2L */
239
240 #define SDL_PBIST_RF2L_RF2L_MASK (0xFFFFFFFFU)
241 #define SDL_PBIST_RF2L_RF2L_SHIFT (0x00000000U)
242 #define SDL_PBIST_RF2L_RF2L_MAX (0xFFFFFFFFU)
243
244 /* RF3L */
245
246 #define SDL_PBIST_RF3L_RF3L_MASK (0xFFFFFFFFU)
247 #define SDL_PBIST_RF3L_RF3L_SHIFT (0x00000000U)
248 #define SDL_PBIST_RF3L_RF3L_MAX (0xFFFFFFFFU)
249
250 /* RF4L */
251
252 #define SDL_PBIST_RF4L_RF4L_MASK (0xFFFFFFFFU)
253 #define SDL_PBIST_RF4L_RF4L_SHIFT (0x00000000U)
254 #define SDL_PBIST_RF4L_RF4L_MAX (0xFFFFFFFFU)
255
256 /* RF5L */
257
258 #define SDL_PBIST_RF5L_RF5L_MASK (0xFFFFFFFFU)
259 #define SDL_PBIST_RF5L_RF5L_SHIFT (0x00000000U)
260 #define SDL_PBIST_RF5L_RF5L_MAX (0xFFFFFFFFU)
261
262 /* RF6L */
263
264 #define SDL_PBIST_RF6L_RF6L_MASK (0xFFFFFFFFU)
265 #define SDL_PBIST_RF6L_RF6L_SHIFT (0x00000000U)
266 #define SDL_PBIST_RF6L_RF6L_MAX (0xFFFFFFFFU)
267
268 /* RF7L */
269
270 #define SDL_PBIST_RF7L_RF7L_MASK (0xFFFFFFFFU)
271 #define SDL_PBIST_RF7L_RF7L_SHIFT (0x00000000U)
272 #define SDL_PBIST_RF7L_RF7L_MAX (0xFFFFFFFFU)
273
274 /* RF8L */
275
276 #define SDL_PBIST_RF8L_RF8L_MASK (0xFFFFFFFFU)
277 #define SDL_PBIST_RF8L_RF8L_SHIFT (0x00000000U)
278 #define SDL_PBIST_RF8L_RF8L_MAX (0xFFFFFFFFU)
279
280 /* RF9L */
281
282 #define SDL_PBIST_RF9L_RF9L_MASK (0xFFFFFFFFU)
283 #define SDL_PBIST_RF9L_RF9L_SHIFT (0x00000000U)
284 #define SDL_PBIST_RF9L_RF9L_MAX (0xFFFFFFFFU)
285
286 /* RF10L */
287
288 #define SDL_PBIST_RF10L_RF10L_MASK (0xFFFFFFFFU)
289 #define SDL_PBIST_RF10L_RF10L_SHIFT (0x00000000U)
290 #define SDL_PBIST_RF10L_RF10L_MAX (0xFFFFFFFFU)
291
292 /* RF11L */
293
294 #define SDL_PBIST_RF11L_RF11L_MASK (0xFFFFFFFFU)
295 #define SDL_PBIST_RF11L_RF11L_SHIFT (0x00000000U)
296 #define SDL_PBIST_RF11L_RF11L_MAX (0xFFFFFFFFU)
297
298 /* RF12L */
299
300 #define SDL_PBIST_RF12L_RF12L_MASK (0xFFFFFFFFU)
301 #define SDL_PBIST_RF12L_RF12L_SHIFT (0x00000000U)
302 #define SDL_PBIST_RF12L_RF12L_MAX (0xFFFFFFFFU)
303
304 /* RF13L */
305
306 #define SDL_PBIST_RF13L_RF13L_MASK (0xFFFFFFFFU)
307 #define SDL_PBIST_RF13L_RF13L_SHIFT (0x00000000U)
308 #define SDL_PBIST_RF13L_RF13L_MAX (0xFFFFFFFFU)
309
310 /* RF14L */
311
312 #define SDL_PBIST_RF14L_RF14L_MASK (0xFFFFFFFFU)
313 #define SDL_PBIST_RF14L_RF14L_SHIFT (0x00000000U)
314 #define SDL_PBIST_RF14L_RF14L_MAX (0xFFFFFFFFU)
315
316 /* RF15L */
317
318 #define SDL_PBIST_RF15L_RF15L_MASK (0xFFFFFFFFU)
319 #define SDL_PBIST_RF15L_RF15L_SHIFT (0x00000000U)
320 #define SDL_PBIST_RF15L_RF15L_MAX (0xFFFFFFFFU)
321
322 /* RF0U */
323
324 #define SDL_PBIST_RF0U_RF0U_MASK (0xFFFFFFFFU)
325 #define SDL_PBIST_RF0U_RF0U_SHIFT (0x00000000U)
326 #define SDL_PBIST_RF0U_RF0U_MAX (0xFFFFFFFFU)
327
328 /* RF1U */
329
330 #define SDL_PBIST_RF1U_RF1U_MASK (0xFFFFFFFFU)
331 #define SDL_PBIST_RF1U_RF1U_SHIFT (0x00000000U)
332 #define SDL_PBIST_RF1U_RF1U_MAX (0xFFFFFFFFU)
333
334 /* RF2U */
335
336 #define SDL_PBIST_RF2U_RF2U_MASK (0xFFFFFFFFU)
337 #define SDL_PBIST_RF2U_RF2U_SHIFT (0x00000000U)
338 #define SDL_PBIST_RF2U_RF2U_MAX (0xFFFFFFFFU)
339
340 /* RF3U */
341
342 #define SDL_PBIST_RF3U_RF3U_MASK (0xFFFFFFFFU)
343 #define SDL_PBIST_RF3U_RF3U_SHIFT (0x00000000U)
344 #define SDL_PBIST_RF3U_RF3U_MAX (0xFFFFFFFFU)
345
346 /* RF4U */
347
348 #define SDL_PBIST_RF4U_RF4U_MASK (0xFFFFFFFFU)
349 #define SDL_PBIST_RF4U_RF4U_SHIFT (0x00000000U)
350 #define SDL_PBIST_RF4U_RF4U_MAX (0xFFFFFFFFU)
351
352 /* RF5U */
353
354 #define SDL_PBIST_RF5U_RF5U_MASK (0xFFFFFFFFU)
355 #define SDL_PBIST_RF5U_RF5U_SHIFT (0x00000000U)
356 #define SDL_PBIST_RF5U_RF5U_MAX (0xFFFFFFFFU)
357
358 /* RF6U */
359
360 #define SDL_PBIST_RF6U_RF6U_MASK (0xFFFFFFFFU)
361 #define SDL_PBIST_RF6U_RF6U_SHIFT (0x00000000U)
362 #define SDL_PBIST_RF6U_RF6U_MAX (0xFFFFFFFFU)
363
364 /* RF7U */
365
366 #define SDL_PBIST_RF7U_RF7U_MASK (0xFFFFFFFFU)
367 #define SDL_PBIST_RF7U_RF7U_SHIFT (0x00000000U)
368 #define SDL_PBIST_RF7U_RF7U_MAX (0xFFFFFFFFU)
369
370 /* RF8U */
371
372 #define SDL_PBIST_RF8U_RF8U_MASK (0xFFFFFFFFU)
373 #define SDL_PBIST_RF8U_RF8U_SHIFT (0x00000000U)
374 #define SDL_PBIST_RF8U_RF8U_MAX (0xFFFFFFFFU)
375
376 /* RF9U */
377
378 #define SDL_PBIST_RF9U_RF9U_MASK (0xFFFFFFFFU)
379 #define SDL_PBIST_RF9U_RF9U_SHIFT (0x00000000U)
380 #define SDL_PBIST_RF9U_RF9U_MAX (0xFFFFFFFFU)
381
382 /* RF10U */
383
384 #define SDL_PBIST_RF10U_RF10U_MASK (0xFFFFFFFFU)
385 #define SDL_PBIST_RF10U_RF10U_SHIFT (0x00000000U)
386 #define SDL_PBIST_RF10U_RF10U_MAX (0xFFFFFFFFU)
387
388 /* RF11U */
389
390 #define SDL_PBIST_RF11U_RF11U_MASK (0xFFFFFFFFU)
391 #define SDL_PBIST_RF11U_RF11U_SHIFT (0x00000000U)
392 #define SDL_PBIST_RF11U_RF11U_MAX (0xFFFFFFFFU)
393
394 /* RF12U */
395
396 #define SDL_PBIST_RF12U_RF12U_MASK (0xFFFFFFFFU)
397 #define SDL_PBIST_RF12U_RF12U_SHIFT (0x00000000U)
398 #define SDL_PBIST_RF12U_RF12U_MAX (0xFFFFFFFFU)
399
400 /* RF13U */
401
402 #define SDL_PBIST_RF13U_RF13U_MASK (0xFFFFFFFFU)
403 #define SDL_PBIST_RF13U_RF13U_SHIFT (0x00000000U)
404 #define SDL_PBIST_RF13U_RF13U_MAX (0xFFFFFFFFU)
405
406 /* RF14U */
407
408 #define SDL_PBIST_RF14U_RF14U_MASK (0xFFFFFFFFU)
409 #define SDL_PBIST_RF14U_RF14U_SHIFT (0x00000000U)
410 #define SDL_PBIST_RF14U_RF14U_MAX (0xFFFFFFFFU)
411
412 /* RF15U */
413
414 #define SDL_PBIST_RF15U_RF15U_MASK (0xFFFFFFFFU)
415 #define SDL_PBIST_RF15U_RF15U_SHIFT (0x00000000U)
416 #define SDL_PBIST_RF15U_RF15U_MAX (0xFFFFFFFFU)
417
418 /* A0 */
419
420 #define SDL_PBIST_A0_A0_MASK (0x0000FFFFU)
421 #define SDL_PBIST_A0_A0_SHIFT (0x00000000U)
422 #define SDL_PBIST_A0_A0_MAX (0x0000FFFFU)
423
424 /* A1 */
425
426 #define SDL_PBIST_A1_A1_MASK (0x0000FFFFU)
427 #define SDL_PBIST_A1_A1_SHIFT (0x00000000U)
428 #define SDL_PBIST_A1_A1_MAX (0x0000FFFFU)
429
430 /* A2 */
431
432 #define SDL_PBIST_A2_A2_MASK (0x0000FFFFU)
433 #define SDL_PBIST_A2_A2_SHIFT (0x00000000U)
434 #define SDL_PBIST_A2_A2_MAX (0x0000FFFFU)
435
436 /* A3 */
437
438 #define SDL_PBIST_A3_A3_MASK (0x0000FFFFU)
439 #define SDL_PBIST_A3_A3_SHIFT (0x00000000U)
440 #define SDL_PBIST_A3_A3_MAX (0x0000FFFFU)
441
442 /* L0 */
443
444 #define SDL_PBIST_L0_L0_MASK (0x0000FFFFU)
445 #define SDL_PBIST_L0_L0_SHIFT (0x00000000U)
446 #define SDL_PBIST_L0_L0_MAX (0x0000FFFFU)
447
448 /* L1 */
449
450 #define SDL_PBIST_L1_L1_MASK (0x0000FFFFU)
451 #define SDL_PBIST_L1_L1_SHIFT (0x00000000U)
452 #define SDL_PBIST_L1_L1_MAX (0x0000FFFFU)
453
454 /* L2 */
455
456 #define SDL_PBIST_L2_L2_MASK (0x0000FFFFU)
457 #define SDL_PBIST_L2_L2_SHIFT (0x00000000U)
458 #define SDL_PBIST_L2_L2_MAX (0x0000FFFFU)
459
460 /* L3 */
461
462 #define SDL_PBIST_L3_L3_MASK (0x0000FFFFU)
463 #define SDL_PBIST_L3_L3_SHIFT (0x00000000U)
464 #define SDL_PBIST_L3_L3_MAX (0x0000FFFFU)
465
466 /* D */
467
468 #define SDL_PBIST_D_D0_MASK (0x0000FFFFU)
469 #define SDL_PBIST_D_D0_SHIFT (0x00000000U)
470 #define SDL_PBIST_D_D0_MAX (0x0000FFFFU)
471
472 #define SDL_PBIST_D_D1_MASK (0xFFFF0000U)
473 #define SDL_PBIST_D_D1_SHIFT (0x00000010U)
474 #define SDL_PBIST_D_D1_MAX (0x0000FFFFU)
475
476 /* E */
477
478 #define SDL_PBIST_E_E0_MASK (0x0000FFFFU)
479 #define SDL_PBIST_E_E0_SHIFT (0x00000000U)
480 #define SDL_PBIST_E_E0_MAX (0x0000FFFFU)
481
482 #define SDL_PBIST_E_E1_MASK (0xFFFF0000U)
483 #define SDL_PBIST_E_E1_SHIFT (0x00000010U)
484 #define SDL_PBIST_E_E1_MAX (0x0000FFFFU)
485
486 /* CA0 */
487
488 #define SDL_PBIST_CA0_CA0_MASK (0x0000FFFFU)
489 #define SDL_PBIST_CA0_CA0_SHIFT (0x00000000U)
490 #define SDL_PBIST_CA0_CA0_MAX (0x0000FFFFU)
491
492 /* CA1 */
493
494 #define SDL_PBIST_CA1_CA1_MASK (0x0000FFFFU)
495 #define SDL_PBIST_CA1_CA1_SHIFT (0x00000000U)
496 #define SDL_PBIST_CA1_CA1_MAX (0x0000FFFFU)
497
498 /* CA2 */
499
500 #define SDL_PBIST_CA2_CA2_MASK (0x0000FFFFU)
501 #define SDL_PBIST_CA2_CA2_SHIFT (0x00000000U)
502 #define SDL_PBIST_CA2_CA2_MAX (0x0000FFFFU)
503
504 /* CA3 */
505
506 #define SDL_PBIST_CA3_CA3_MASK (0x0000FFFFU)
507 #define SDL_PBIST_CA3_CA3_SHIFT (0x00000000U)
508 #define SDL_PBIST_CA3_CA3_MAX (0x0000FFFFU)
509
510 /* CL0 */
511
512 #define SDL_PBIST_CL0_CL0_MASK (0x0000FFFFU)
513 #define SDL_PBIST_CL0_CL0_SHIFT (0x00000000U)
514 #define SDL_PBIST_CL0_CL0_MAX (0x0000FFFFU)
515
516 /* CL1 */
517
518 #define SDL_PBIST_CL1_CL1_MASK (0x0000FFFFU)
519 #define SDL_PBIST_CL1_CL1_SHIFT (0x00000000U)
520 #define SDL_PBIST_CL1_CL1_MAX (0x0000FFFFU)
521
522 /* CL2 */
523
524 #define SDL_PBIST_CL2_CL2_MASK (0x0000FFFFU)
525 #define SDL_PBIST_CL2_CL2_SHIFT (0x00000000U)
526 #define SDL_PBIST_CL2_CL2_MAX (0x0000FFFFU)
527
528 /* CL3 */
529
530 #define SDL_PBIST_CL3_CL3_MASK (0x0000FFFFU)
531 #define SDL_PBIST_CL3_CL3_SHIFT (0x00000000U)
532 #define SDL_PBIST_CL3_CL3_MAX (0x0000FFFFU)
533
534 /* I0 */
535
536 #define SDL_PBIST_I0_I0_MASK (0x0000FFFFU)
537 #define SDL_PBIST_I0_I0_SHIFT (0x00000000U)
538 #define SDL_PBIST_I0_I0_MAX (0x0000FFFFU)
539
540 /* I1 */
541
542 #define SDL_PBIST_I1_I0_MASK (0x0000FFFFU)
543 #define SDL_PBIST_I1_I0_SHIFT (0x00000000U)
544 #define SDL_PBIST_I1_I0_MAX (0x0000FFFFU)
545
546 /* I2 */
547
548 #define SDL_PBIST_I2_I0_MASK (0x0000FFFFU)
549 #define SDL_PBIST_I2_I0_SHIFT (0x00000000U)
550 #define SDL_PBIST_I2_I0_MAX (0x0000FFFFU)
551
552 /* I3 */
553
554 #define SDL_PBIST_I3_I0_MASK (0x0000FFFFU)
555 #define SDL_PBIST_I3_I0_SHIFT (0x00000000U)
556 #define SDL_PBIST_I3_I0_MAX (0x0000FFFFU)
557
558 /* RAMT */
559
560 #define SDL_PBIST_RAMT_RLS_MASK (0x00000003U)
561 #define SDL_PBIST_RAMT_RLS_SHIFT (0x00000000U)
562 #define SDL_PBIST_RAMT_RLS_MAX (0x00000003U)
563
564 #define SDL_PBIST_RAMT_PLS_MASK (0x0000003CU)
565 #define SDL_PBIST_RAMT_PLS_SHIFT (0x00000002U)
566 #define SDL_PBIST_RAMT_PLS_MAX (0x0000000FU)
567
568 #define SDL_PBIST_RAMT_DWR_MASK (0x0000FF00U)
569 #define SDL_PBIST_RAMT_DWR_SHIFT (0x00000008U)
570 #define SDL_PBIST_RAMT_DWR_MAX (0x000000FFU)
571
572 #define SDL_PBIST_RAMT_RDS_MASK (0x00FF0000U)
573 #define SDL_PBIST_RAMT_RDS_SHIFT (0x00000010U)
574 #define SDL_PBIST_RAMT_RDS_MAX (0x000000FFU)
575
576 #define SDL_PBIST_RAMT_RGS_MASK (0xFF000000U)
577 #define SDL_PBIST_RAMT_RGS_SHIFT (0x00000018U)
578 #define SDL_PBIST_RAMT_RGS_MAX (0x000000FFU)
579
580 /* DLR */
581
582 #define SDL_PBIST_DLR_DLR0_DCM_MASK (0x00000001U)
583 #define SDL_PBIST_DLR_DLR0_DCM_SHIFT (0x00000000U)
584 #define SDL_PBIST_DLR_DLR0_DCM_MAX (0x00000001U)
585
586 #define SDL_PBIST_DLR_DLR0_IDDQ_MASK (0x00000002U)
587 #define SDL_PBIST_DLR_DLR0_IDDQ_SHIFT (0x00000001U)
588 #define SDL_PBIST_DLR_DLR0_IDDQ_MAX (0x00000001U)
589
590 #define SDL_PBIST_DLR_DLR0_ROM_MASK (0x00000004U)
591 #define SDL_PBIST_DLR_DLR0_ROM_SHIFT (0x00000002U)
592 #define SDL_PBIST_DLR_DLR0_ROM_MAX (0x00000001U)
593
594 #define SDL_PBIST_DLR_DLR0_TCK_MASK (0x00000008U)
595 #define SDL_PBIST_DLR_DLR0_TCK_SHIFT (0x00000003U)
596 #define SDL_PBIST_DLR_DLR0_TCK_MAX (0x00000001U)
597
598 #define SDL_PBIST_DLR_DLR0_CAM_MASK (0x00000010U)
599 #define SDL_PBIST_DLR_DLR0_CAM_SHIFT (0x00000004U)
600 #define SDL_PBIST_DLR_DLR0_CAM_MAX (0x00000001U)
601
602 #define SDL_PBIST_DLR_DLR0_ECAM_MASK (0x00000020U)
603 #define SDL_PBIST_DLR_DLR0_ECAM_SHIFT (0x00000005U)
604 #define SDL_PBIST_DLR_DLR0_ECAM_MAX (0x00000001U)
605
606 #define SDL_PBIST_DLR_DLR0_CFMM_MASK (0x00000040U)
607 #define SDL_PBIST_DLR_DLR0_CFMM_SHIFT (0x00000006U)
608 #define SDL_PBIST_DLR_DLR0_CFMM_MAX (0x00000001U)
609
610 #define SDL_PBIST_DLR_DLR0_TSM_MASK (0x00000080U)
611 #define SDL_PBIST_DLR_DLR0_TSM_SHIFT (0x00000007U)
612 #define SDL_PBIST_DLR_DLR0_TSM_MAX (0x00000001U)
613
614 #define SDL_PBIST_DLR_DLR1_MISR_MASK (0x00000100U)
615 #define SDL_PBIST_DLR_DLR1_MISR_SHIFT (0x00000008U)
616 #define SDL_PBIST_DLR_DLR1_MISR_MAX (0x00000001U)
617
618 #define SDL_PBIST_DLR_DLR1_GNG_MASK (0x00000200U)
619 #define SDL_PBIST_DLR_DLR1_GNG_SHIFT (0x00000009U)
620 #define SDL_PBIST_DLR_DLR1_GNG_MAX (0x00000001U)
621
622 #define SDL_PBIST_DLR_DLR1_RTM_MASK (0x00000400U)
623 #define SDL_PBIST_DLR_DLR1_RTM_SHIFT (0x0000000AU)
624 #define SDL_PBIST_DLR_DLR1_RTM_MAX (0x00000001U)
625
626 #define SDL_PBIST_DLR_BRP_MASK (0x00FF0000U)
627 #define SDL_PBIST_DLR_BRP_SHIFT (0x00000010U)
628 #define SDL_PBIST_DLR_BRP_MAX (0x000000FFU)
629
630 /* CMS */
631
632 #define SDL_PBIST_CMS_CMS_MASK (0x0000000FU)
633 #define SDL_PBIST_CMS_CMS_SHIFT (0x00000000U)
634 #define SDL_PBIST_CMS_CMS_MAX (0x0000000FU)
635
636 /* STR */
637
638 #define SDL_PBIST_STR_START_MASK (0x00000001U)
639 #define SDL_PBIST_STR_START_SHIFT (0x00000000U)
640 #define SDL_PBIST_STR_START_MAX (0x00000001U)
641
642 #define SDL_PBIST_STR_RES_MASK (0x00000002U)
643 #define SDL_PBIST_STR_RES_SHIFT (0x00000001U)
644 #define SDL_PBIST_STR_RES_MAX (0x00000001U)
645
646 #define SDL_PBIST_STR_STOP_MASK (0x00000004U)
647 #define SDL_PBIST_STR_STOP_SHIFT (0x00000002U)
648 #define SDL_PBIST_STR_STOP_MAX (0x00000001U)
649
650 #define SDL_PBIST_STR_STEP_MASK (0x00000008U)
651 #define SDL_PBIST_STR_STEP_SHIFT (0x00000003U)
652 #define SDL_PBIST_STR_STEP_MAX (0x00000001U)
653
654 #define SDL_PBIST_STR_CHK_MASK (0x00000010U)
655 #define SDL_PBIST_STR_CHK_SHIFT (0x00000004U)
656 #define SDL_PBIST_STR_CHK_MAX (0x00000001U)
657
658 /* SCR */
659
660 #define SDL_PBIST_SCR_SCR0_MASK (0x00000000000000FFU)
661 #define SDL_PBIST_SCR_SCR0_SHIFT (0x0000000000000000U)
662 #define SDL_PBIST_SCR_SCR0_MAX (0x00000000000000FFU)
663
664 #define SDL_PBIST_SCR_SCR1_MASK (0x000000000000FF00U)
665 #define SDL_PBIST_SCR_SCR1_SHIFT (0x0000000000000008U)
666 #define SDL_PBIST_SCR_SCR1_MAX (0x00000000000000FFU)
667
668 #define SDL_PBIST_SCR_SCR2_MASK (0x0000000000FF0000U)
669 #define SDL_PBIST_SCR_SCR2_SHIFT (0x0000000000000010U)
670 #define SDL_PBIST_SCR_SCR2_MAX (0x00000000000000FFU)
671
672 #define SDL_PBIST_SCR_SCR3_MASK (0x00000000FF000000U)
673 #define SDL_PBIST_SCR_SCR3_SHIFT (0x0000000000000018U)
674 #define SDL_PBIST_SCR_SCR3_MAX (0x00000000000000FFU)
675
676 #define SDL_PBIST_SCR_SCR4_MASK (0x000000FF00000000U)
677 #define SDL_PBIST_SCR_SCR4_SHIFT (0x0000000000000020U)
678 #define SDL_PBIST_SCR_SCR4_MAX (0x00000000000000FFU)
679
680 #define SDL_PBIST_SCR_SCR5_MASK (0x0000FF0000000000U)
681 #define SDL_PBIST_SCR_SCR5_SHIFT (0x0000000000000028U)
682 #define SDL_PBIST_SCR_SCR5_MAX (0x00000000000000FFU)
683
684 #define SDL_PBIST_SCR_SCR6_MASK (0x00FF000000000000U)
685 #define SDL_PBIST_SCR_SCR6_SHIFT (0x0000000000000030U)
686 #define SDL_PBIST_SCR_SCR6_MAX (0x00000000000000FFU)
687
688 #define SDL_PBIST_SCR_SCR7_MASK (0xFF00000000000000U)
689 #define SDL_PBIST_SCR_SCR7_SHIFT (0x0000000000000038U)
690 #define SDL_PBIST_SCR_SCR7_MAX (0x00000000000000FFU)
691
692 /* CSR */
693
694 #define SDL_PBIST_CSR_CSR0_MASK (0x000000FFU)
695 #define SDL_PBIST_CSR_CSR0_SHIFT (0x00000000U)
696 #define SDL_PBIST_CSR_CSR0_MAX (0x000000FFU)
697
698 #define SDL_PBIST_CSR_CSR1_MASK (0x0000FF00U)
699 #define SDL_PBIST_CSR_CSR1_SHIFT (0x00000008U)
700 #define SDL_PBIST_CSR_CSR1_MAX (0x000000FFU)
701
702 #define SDL_PBIST_CSR_CSR2_MASK (0x00FF0000U)
703 #define SDL_PBIST_CSR_CSR2_SHIFT (0x00000010U)
704 #define SDL_PBIST_CSR_CSR2_MAX (0x000000FFU)
705
706 #define SDL_PBIST_CSR_CSR3_MASK (0xFF000000U)
707 #define SDL_PBIST_CSR_CSR3_SHIFT (0x00000018U)
708 #define SDL_PBIST_CSR_CSR3_MAX (0x000000FFU)
709
710 /* FDLY */
711
712 #define SDL_PBIST_FDLY_FDLY_MASK (0x000000FFU)
713 #define SDL_PBIST_FDLY_FDLY_SHIFT (0x00000000U)
714 #define SDL_PBIST_FDLY_FDLY_MAX (0x000000FFU)
715
716 /* PACT */
717
718 #define SDL_PBIST_PACT_PACT_MASK (0x00000001U)
719 #define SDL_PBIST_PACT_PACT_SHIFT (0x00000000U)
720 #define SDL_PBIST_PACT_PACT_MAX (0x00000001U)
721
722 /* PID */
723
724 #define SDL_PBIST_PID_PID_MASK (0x0000001FU)
725 #define SDL_PBIST_PID_PID_SHIFT (0x00000000U)
726 #define SDL_PBIST_PID_PID_MAX (0x0000001FU)
727
728 /* OVER */
729
730 #define SDL_PBIST_OVER_RINFO_MASK (0x00000001U)
731 #define SDL_PBIST_OVER_RINFO_SHIFT (0x00000000U)
732 #define SDL_PBIST_OVER_RINFO_MAX (0x00000001U)
733
734 #define SDL_PBIST_OVER_READ_MASK (0x00000002U)
735 #define SDL_PBIST_OVER_READ_SHIFT (0x00000001U)
736 #define SDL_PBIST_OVER_READ_MAX (0x00000001U)
737
738 #define SDL_PBIST_OVER_MM_MASK (0x00000004U)
739 #define SDL_PBIST_OVER_MM_SHIFT (0x00000002U)
740 #define SDL_PBIST_OVER_MM_MAX (0x00000001U)
741
742 #define SDL_PBIST_OVER_ALGO_MASK (0x00000008U)
743 #define SDL_PBIST_OVER_ALGO_SHIFT (0x00000003U)
744 #define SDL_PBIST_OVER_ALGO_MAX (0x00000001U)
745
746 /* FSRF */
747
748 #define SDL_PBIST_FSRF_FRSF0_MASK (0x0000000000000001U)
749 #define SDL_PBIST_FSRF_FRSF0_SHIFT (0x0000000000000000U)
750 #define SDL_PBIST_FSRF_FRSF0_MAX (0x0000000000000001U)
751
752 #define SDL_PBIST_FSRF_FRSF1_MASK (0x0000000100000000U)
753 #define SDL_PBIST_FSRF_FRSF1_SHIFT (0x0000000000000020U)
754 #define SDL_PBIST_FSRF_FRSF1_MAX (0x0000000000000001U)
755
756 /* FSRC */
757
758 #define SDL_PBIST_FSRC_FSRC0_MASK (0x000000000000000FU)
759 #define SDL_PBIST_FSRC_FSRC0_SHIFT (0x0000000000000000U)
760 #define SDL_PBIST_FSRC_FSRC0_MAX (0x000000000000000FU)
761
762 #define SDL_PBIST_FSRC_FSRC1_MASK (0x0000000F00000000U)
763 #define SDL_PBIST_FSRC_FSRC1_SHIFT (0x0000000000000020U)
764 #define SDL_PBIST_FSRC_FSRC1_MAX (0x000000000000000FU)
765
766 /* FSRA */
767
768 #define SDL_PBIST_FSRA_FSRA0_MASK (0x000000000000FFFFU)
769 #define SDL_PBIST_FSRA_FSRA0_SHIFT (0x0000000000000000U)
770 #define SDL_PBIST_FSRA_FSRA0_MAX (0x000000000000FFFFU)
771
772 #define SDL_PBIST_FSRA_FSRA1_MASK (0x0000FFFF00000000U)
773 #define SDL_PBIST_FSRA_FSRA1_SHIFT (0x0000000000000020U)
774 #define SDL_PBIST_FSRA_FSRA1_MAX (0x000000000000FFFFU)
775
776 /* FSRDL0 */
777
778 #define SDL_PBIST_FSRDL0_FSRDL0_MASK (0xFFFFFFFFU)
779 #define SDL_PBIST_FSRDL0_FSRDL0_SHIFT (0x00000000U)
780 #define SDL_PBIST_FSRDL0_FSRDL0_MAX (0xFFFFFFFFU)
781
782 /* FSRDL1 */
783
784 #define SDL_PBIST_FSRDL1_FSRDL1_MASK (0xFFFFFFFFU)
785 #define SDL_PBIST_FSRDL1_FSRDL1_SHIFT (0x00000000U)
786 #define SDL_PBIST_FSRDL1_FSRDL1_MAX (0xFFFFFFFFU)
787
788 /* MARGIN_MODE */
789
790 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK (0x00000003U)
791 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_SHIFT (0x00000000U)
792 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MAX (0x00000003U)
793
794 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK (0x0000000CU)
795 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT (0x00000002U)
796 #define SDL_PBIST_MARGIN_MODE_PBIST_DFT_READ_MAX (0x00000003U)
797
798 /* WRENZ */
799
800 #define SDL_PBIST_WRENZ_WRENZ_MASK (0x00000003U)
801 #define SDL_PBIST_WRENZ_WRENZ_SHIFT (0x00000000U)
802 #define SDL_PBIST_WRENZ_WRENZ_MAX (0x00000003U)
803
804 /* PAGE_PGS */
805
806 #define SDL_PBIST_PAGE_PGS_PGS_MASK (0x00000003U)
807 #define SDL_PBIST_PAGE_PGS_PGS_SHIFT (0x00000000U)
808 #define SDL_PBIST_PAGE_PGS_PGS_MAX (0x00000003U)
809
810 /* ROM */
811
812 #define SDL_PBIST_ROM_ROM_MASK (0x00000003U)
813 #define SDL_PBIST_ROM_ROM_SHIFT (0x00000000U)
814 #define SDL_PBIST_ROM_ROM_MAX (0x00000003U)
815
816 /* ALGO */
817
818 #define SDL_PBIST_ALGO_ALGO_0_MASK (0x000000FFU)
819 #define SDL_PBIST_ALGO_ALGO_0_SHIFT (0x00000000U)
820 #define SDL_PBIST_ALGO_ALGO_0_MAX (0x000000FFU)
821
822 #define SDL_PBIST_ALGO_ALGO_1_MASK (0x0000FF00U)
823 #define SDL_PBIST_ALGO_ALGO_1_SHIFT (0x00000008U)
824 #define SDL_PBIST_ALGO_ALGO_1_MAX (0x000000FFU)
825
826 #define SDL_PBIST_ALGO_ALGO_2_MASK (0x00FF0000U)
827 #define SDL_PBIST_ALGO_ALGO_2_SHIFT (0x00000010U)
828 #define SDL_PBIST_ALGO_ALGO_2_MAX (0x000000FFU)
829
830 #define SDL_PBIST_ALGO_ALGO_3_MASK (0xFF000000U)
831 #define SDL_PBIST_ALGO_ALGO_3_SHIFT (0x00000018U)
832 #define SDL_PBIST_ALGO_ALGO_3_MAX (0x000000FFU)
833
834 /* RINFO */
835
836 #define SDL_PBIST_RINFO_L0_MASK (0x00000000000000FFU)
837 #define SDL_PBIST_RINFO_L0_SHIFT (0x0000000000000000U)
838 #define SDL_PBIST_RINFO_L0_MAX (0x00000000000000FFU)
839
840 #define SDL_PBIST_RINFO_L1_MASK (0x000000000000FF00U)
841 #define SDL_PBIST_RINFO_L1_SHIFT (0x0000000000000008U)
842 #define SDL_PBIST_RINFO_L1_MAX (0x00000000000000FFU)
843
844 #define SDL_PBIST_RINFO_L2_MASK (0x0000000000FF0000U)
845 #define SDL_PBIST_RINFO_L2_SHIFT (0x0000000000000010U)
846 #define SDL_PBIST_RINFO_L2_MAX (0x00000000000000FFU)
847
848 #define SDL_PBIST_RINFO_L3_MASK (0x00000000FF000000U)
849 #define SDL_PBIST_RINFO_L3_SHIFT (0x0000000000000018U)
850 #define SDL_PBIST_RINFO_L3_MAX (0x00000000000000FFU)
851
852 #define SDL_PBIST_RINFO_U0_MASK (0x000000FF00000000U)
853 #define SDL_PBIST_RINFO_U0_SHIFT (0x0000000000000020U)
854 #define SDL_PBIST_RINFO_U0_MAX (0x00000000000000FFU)
855
856 #define SDL_PBIST_RINFO_U1_MASK (0x0000FF0000000000U)
857 #define SDL_PBIST_RINFO_U1_SHIFT (0x0000000000000028U)
858 #define SDL_PBIST_RINFO_U1_MAX (0x00000000000000FFU)
859
860 #define SDL_PBIST_RINFO_U2_MASK (0x00FF000000000000U)
861 #define SDL_PBIST_RINFO_U2_SHIFT (0x0000000000000030U)
862 #define SDL_PBIST_RINFO_U2_MAX (0x00000000000000FFU)
863
864 #define SDL_PBIST_RINFO_U3_MASK (0xFF00000000000000U)
865 #define SDL_PBIST_RINFO_U3_SHIFT (0x0000000000000038U)
866 #define SDL_PBIST_RINFO_U3_MAX (0x00000000000000FFU)
867
868 #ifdef __cplusplus
869 }
870 #endif
871 #endif
SDL_pbistRegs::RF5U
volatile uint32_t RF5U
Definition: sdlr_pbist.h:75
SDL_pbistRegs::PACT
volatile uint32_t PACT
Definition: sdlr_pbist.h:117
SDL_pbistRegs::FSRF
volatile uint64_t FSRF
Definition: sdlr_pbist.h:121
SDL_pbistRegs
Definition: sdlr_pbist.h:53
SDL_pbistRegs::I0
volatile uint32_t I0
Definition: sdlr_pbist.h:106
SDL_pbistRegs::PAGE_PGS
volatile uint32_t PAGE_PGS
Definition: sdlr_pbist.h:129
SDL_pbistRegs::RF1U
volatile uint32_t RF1U
Definition: sdlr_pbist.h:71
SDL_pbistRegs::FSRC
volatile uint64_t FSRC
Definition: sdlr_pbist.h:122
SDL_pbistRegs::A2
volatile uint32_t A2
Definition: sdlr_pbist.h:89
SDL_pbistRegs::RF12U
volatile uint32_t RF12U
Definition: sdlr_pbist.h:82
SDL_pbistRegs::CA3
volatile uint32_t CA3
Definition: sdlr_pbist.h:101
SDL_pbistRegs::I3
volatile uint32_t I3
Definition: sdlr_pbist.h:109
SDL_pbistRegs::ALGO
volatile uint32_t ALGO
Definition: sdlr_pbist.h:131
SDL_pbistRegs::DLR
volatile uint32_t DLR
Definition: sdlr_pbist.h:111
SDL_pbistRegs::I1
volatile uint32_t I1
Definition: sdlr_pbist.h:107
SDL_pbistRegs::A0
volatile uint32_t A0
Definition: sdlr_pbist.h:87
SDL_pbistRegs::CL0
volatile uint32_t CL0
Definition: sdlr_pbist.h:102
SDL_pbistRegs::RF12L
volatile uint32_t RF12L
Definition: sdlr_pbist.h:66
SDL_pbistRegs::CL1
volatile uint32_t CL1
Definition: sdlr_pbist.h:103
SDL_pbistRegs::CMS
volatile uint32_t CMS
Definition: sdlr_pbist.h:112
SDL_pbistRegs::RF4L
volatile uint32_t RF4L
Definition: sdlr_pbist.h:58
SDL_pbistRegs::FSRDL0
volatile uint32_t FSRDL0
Definition: sdlr_pbist.h:124
SDL_pbistRegs::CL2
volatile uint32_t CL2
Definition: sdlr_pbist.h:104
SDL_pbistRegs::FDLY
volatile uint32_t FDLY
Definition: sdlr_pbist.h:116
SDL_pbistRegs::RF15U
volatile uint32_t RF15U
Definition: sdlr_pbist.h:85
SDL_pbistRegs::RF3U
volatile uint32_t RF3U
Definition: sdlr_pbist.h:73
SDL_pbistRegs::RF9L
volatile uint32_t RF9L
Definition: sdlr_pbist.h:63
SDL_pbistRegs::RF8L
volatile uint32_t RF8L
Definition: sdlr_pbist.h:62
SDL_pbistRegs::CA0
volatile uint32_t CA0
Definition: sdlr_pbist.h:98
SDL_pbistRegs::ROM
volatile uint32_t ROM
Definition: sdlr_pbist.h:130
SDL_pbistRegs::I2
volatile uint32_t I2
Definition: sdlr_pbist.h:108
SDL_pbistRegs::RF13L
volatile uint32_t RF13L
Definition: sdlr_pbist.h:67
SDL_pbistRegs::CA2
volatile uint32_t CA2
Definition: sdlr_pbist.h:100
SDL_pbistRegs::RF14U
volatile uint32_t RF14U
Definition: sdlr_pbist.h:84
SDL_pbistRegs::MARGIN_MODE
volatile uint32_t MARGIN_MODE
Definition: sdlr_pbist.h:127
SDL_pbistRegs::CA1
volatile uint32_t CA1
Definition: sdlr_pbist.h:99
SDL_pbistRegs::RF13U
volatile uint32_t RF13U
Definition: sdlr_pbist.h:83
SDL_pbistRegs::RF0U
volatile uint32_t RF0U
Definition: sdlr_pbist.h:70
SDL_pbistRegs::RF7L
volatile uint32_t RF7L
Definition: sdlr_pbist.h:61
SDL_pbistRegs::RF2U
volatile uint32_t RF2U
Definition: sdlr_pbist.h:72
SDL_pbistRegs::CL3
volatile uint32_t CL3
Definition: sdlr_pbist.h:105
SDL_pbistRegs::RF9U
volatile uint32_t RF9U
Definition: sdlr_pbist.h:79
SDL_pbistRegs::RF8U
volatile uint32_t RF8U
Definition: sdlr_pbist.h:78
SDL_pbistRegs::L1
volatile uint32_t L1
Definition: sdlr_pbist.h:92
SDL_pbistRegs::RF5L
volatile uint32_t RF5L
Definition: sdlr_pbist.h:59
SDL_pbistRegs::D
volatile uint32_t D
Definition: sdlr_pbist.h:95
SDL_pbistRegs::A1
volatile uint32_t A1
Definition: sdlr_pbist.h:88
SDL_pbistRegs::RF10L
volatile uint32_t RF10L
Definition: sdlr_pbist.h:64
SDL_pbistRegs::RF4U
volatile uint32_t RF4U
Definition: sdlr_pbist.h:74
SDL_pbistRegs::PID
volatile uint32_t PID
Definition: sdlr_pbist.h:118
SDL_pbistRegs::L0
volatile uint32_t L0
Definition: sdlr_pbist.h:91
SDL_pbistRegs::L2
volatile uint32_t L2
Definition: sdlr_pbist.h:93
SDL_pbistRegs::SCR
volatile uint64_t SCR
Definition: sdlr_pbist.h:114
SDL_pbistRegs::RF6L
volatile uint32_t RF6L
Definition: sdlr_pbist.h:60
SDL_pbistRegs::RF15L
volatile uint32_t RF15L
Definition: sdlr_pbist.h:69
SDL_pbistRegs::RF7U
volatile uint32_t RF7U
Definition: sdlr_pbist.h:77
SDL_pbistRegs::FSRA
volatile uint64_t FSRA
Definition: sdlr_pbist.h:123
SDL_pbistRegs::RF3L
volatile uint32_t RF3L
Definition: sdlr_pbist.h:57
SDL_pbistRegs::STR
volatile uint32_t STR
Definition: sdlr_pbist.h:113
SDL_pbistRegs::RF6U
volatile uint32_t RF6U
Definition: sdlr_pbist.h:76
SDL_pbistRegs::RF10U
volatile uint32_t RF10U
Definition: sdlr_pbist.h:80
SDL_pbistRegs::RF2L
volatile uint32_t RF2L
Definition: sdlr_pbist.h:56
SDL_pbistRegs::RAMT
volatile uint32_t RAMT
Definition: sdlr_pbist.h:110
SDL_pbistRegs::RF0L
volatile uint32_t RF0L
Definition: sdlr_pbist.h:54
SDL_pbistRegs::FSRDL1
volatile uint32_t FSRDL1
Definition: sdlr_pbist.h:126
SDL_pbistRegs::WRENZ
volatile uint32_t WRENZ
Definition: sdlr_pbist.h:128
SDL_pbistRegs::A3
volatile uint32_t A3
Definition: sdlr_pbist.h:90
SDL_pbistRegs::RF1L
volatile uint32_t RF1L
Definition: sdlr_pbist.h:55
SDL_pbistRegs::RF11U
volatile uint32_t RF11U
Definition: sdlr_pbist.h:81
SDL_pbistRegs::RF11L
volatile uint32_t RF11L
Definition: sdlr_pbist.h:65
SDL_pbistRegs::RF14L
volatile uint32_t RF14L
Definition: sdlr_pbist.h:68
SDL_pbistRegs::E
volatile uint32_t E
Definition: sdlr_pbist.h:96
SDL_pbistRegs::OVER
volatile uint32_t OVER
Definition: sdlr_pbist.h:119
SDL_pbistRegs::CSR
volatile uint32_t CSR
Definition: sdlr_pbist.h:115
SDL_pbistRegs::L3
volatile uint32_t L3
Definition: sdlr_pbist.h:94