AM261x MCU+ SDK: sipc_notify_cfg.h Source File

| AM261x MCU+ SDK 26.00.00 |

sipc_notify_cfg.h
Go to the documentation of this file.
1 /*
2 * Copyright (C) 2022-23 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 #ifndef SIPC_NOTIFY_CFG_H_
33 #define SIPC_NOTIFY_CFG_H_
34
35 #ifdef __cplusplus
36 extern "C"
37 {
38 #endif
39
40 #include <drivers/hw_include/am263x/cslr_soc.h>
41 #include <drivers/soc/am263x/soc.h>
42 #include <kernel/dpl/CpuIdP.h>
43
47 #define SIPC_MSG_SIZE (13u)
48
49 /* Max number of interrupt configs possible for AM263x */
50 #define INTR_CFG_NUM_MAX (1u)
51
52 /* If SIPC is compiled for R5 core then Max client ID = 32
53 * Else for HSM its 2 */
54
55
56
57 /* HSM specific register addresses defined here to remove the dependency on CSL files */
58 #define HSM_SOC_CTRL_U_BASE (0x40000000U)
59 #define HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK (0x00000048U)
60 #define HSM_SOC_CTRL_HSM_MBOX_READ_DONE (0x0000004CU)
61
62 /* R5 Register for sending and receiving IPC interrutps
63 * As write DONE interrupt line is being used by regular IPC communication we will use READ_DONE_ACK
64 * register to post the interrupt to receiving core and it will read READ_DONE register to process
65 * that interrupt */
66 #define R5FSS0_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK)
67 #define R5FSS0_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE)
68 #define R5FSS0_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK)
69 #define R5FSS0_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE)
70 #define R5FSS1_0_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK)
71 #define R5FSS1_0_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE)
72 #define R5FSS1_1_MBOX_READ_DONE_ACK (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK)
73 #define R5FSS1_1_MBOX_READ_DONE (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE)
74
75 /* HSM registers for sending and receiving IPC interrupts */
76 #define HSM0_0_MBOX_READ_DONE_ACK (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK)
77 #define HSM0_0_MBOX_READ_DONE (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE)
78
79 /* CPU bit positions within the HSM mailbox registers for sending interrupt
80 * HSM will write the READ_DONE_ACK register to raise an interrupt to R5 core */
81 #define R5FSS0_0_MBOX_WRITE_PROC_BIT_POS ( 0U)
82 #define R5FSS0_1_MBOX_WRITE_PROC_BIT_POS ( 4U)
83 #define R5FSS1_0_MBOX_WRITE_PROC_BIT_POS ( 8U)
84 #define R5FSS1_1_MBOX_WRITE_PROC_BIT_POS ( 12U)
85
86 /* Bitshift to raise an interrupt from R5 core to HSM */
87 #define HSM0_0_MBOX_WRITE_PROC_BIT_POS ( 6U)
88
89 /* CPU bit positions within the mailbox registers for receiving interrupts */
90 #define R5FSS0_0_MBOX_READ_PROC_BIT_POS ( 0U)
91 #define R5FSS0_1_MBOX_READ_PROC_BIT_POS ( 4U)
92 #define R5FSS1_0_MBOX_READ_PROC_BIT_POS ( 8U)
93 #define R5FSS1_1_MBOX_READ_PROC_BIT_POS (12U)
94 #define HSM0_0_MBOX_READ_PROC_BIT_POS (24U)
95
96 /* Mailbox interrupts numbers */
97 #define R5FSS0_0_MBOX_READ_ACK_INTR ( 137U)
98 #define R5FSS0_1_MBOX_READ_ACK_INTR ( 137U)
99 #define R5FSS1_0_MBOX_READ_ACK_INTR ( 137U)
100 #define R5FSS1_1_MBOX_READ_ACK_INTR ( 137U)
101 #define HSM0_0_MBOX_READ_ACK_INTR ( 56U )
102
109 typedef uint32_t SIPC_coreId;
110
111 #define CORE_ID_R5FSS0_0 (0U)
112 #define CORE_ID_R5FSS0_1 (1U)
113 #define CORE_ID_R5FSS1_0 (2U)
114 #define CORE_ID_R5FSS1_1 (3U)
115 #define CORE_ID_HSM0_0 (4U)
116 #define CORE_ID_MAX (5U)
117
118
125 typedef uint32_t SIPC_SecCoreId;
126
127 #define CORE_INDEX_SEC_MASTER_0 (0U)
128 #define CORE_INDEX_SEC_MASTER_1 (1U)
129 #define CORE_INDEX_HSM (2U)
130 #define MAX_SEC_CORES_WITH_HSM (3U)
131
132 #if defined(__ARM_ARCH_7R__)
133
134 /* If building for R5 then read selfcore ID from the Core Cluster register */
135 static uint32_t SIPC_readSelfCoreID(void)
136 {
137 uint32_t coreId ;
138 CSL_ArmR5CPUInfo cpuId = {0, 0};
139 CSL_armR5GetCpuID(&cpuId);
140 /* both cpuId and greId fields can be either 0 or 1
141 * ex for R5FSS1-0 core grpId = 1 and cpu id = 0 */
142 coreId = cpuId.cpuID | (cpuId.grpId) << 1 ;
143 return coreId;
144 }
145 #define SELF_CORE_ID (SIPC_readSelfCoreID())
146
153 #define SIPC_CLIENT_ID_MAX (5U)
154
155 #else
156 #define SIPC_CLIENT_ID_MAX (2U)
157 #define SELF_CORE_ID (CORE_ID_HSM0_0)
158 #endif
159
160 /*
161 * Client ID used by HSM server's boot notify message
162 */
163 #define SIPC_BOOT_NOTIFY_CLIENT_ID (0U)
164
165 #ifdef __cplusplus
166 }
167 #endif
168
169 #endif
CSL_ArmR5CPUInfo::grpId
uint32_t grpId
Definition: CpuIdP.h:62
CSL_ArmR5CPUInfo
Structure containing the CPU Info such as CPU ID and Cluster Group ID.
Definition: CpuIdP.h:57
CpuIdP.h
CSL_ArmR5CPUInfo::cpuID
uint32_t cpuID
Definition: CpuIdP.h:58
CSL_armR5GetCpuID
void CSL_armR5GetCpuID(CSL_ArmR5CPUInfo *cpuInfo)
Get the cluster group and CPU ID for current R5 Core.
SIPC_SecCoreId
uint32_t SIPC_SecCoreId
Secure host Id to identify different secure hosts. Max number of secure host on AM263x is 2.
Definition: sipc_notify_cfg.h:125
SIPC_coreId
uint32_t SIPC_coreId
Core Ids to identify different cores.
Definition: sipc_notify_cfg.h:109