AM261x MCU+ SDK: hw.h Source File

| AM261x MCU+ SDK 26.00.00 |

hw.h
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1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/DWC_usb3/driver/hw.h $
3 * $Revision: #60 $
4 * $Date: 2013/12/17 $
5 * $Change: 2392669 $
6 *
7 * Synopsys SS USB3 Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33
34 #ifndef _DWC_USB3_REGS_H_
35 #define _DWC_USB3_REGS_H_
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
58 /****************************************************************************/
59 /* Core Global Registers */
60
77 #define DWC_SBUSCFG0_HBURSTLEN_BITS 0x000000ffU
78 #define DWC_SBUSCFG0_HBURSTLEN_SHIFT 0U
80 #define DWC_SBUSCFG0_INT_DMA_BURST_SINGLE 0U
81 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR 1U
82 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR4 3U
83 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR8 7U
84 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR16 15U
85 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR32 31U
86 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR64 63U
87 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR128 127U
88 #define DWC_SBUSCFG0_INT_DMA_BURST_INCR256 255U
91 #define DWC_SBUSCFG0_DES_WR_POST_BIT 0x00000100U
92 #define DWC_SBUSCFG0_DES_WR_POST_SHIFT 8U
93
95 #define DWC_SBUSCFG0_DAT_WR_POST_BIT 0x00000200U
96 #define DWC_SBUSCFG0_DAT_WR_POST_SHIFT 9U
97
99 #define DWC_SBUSCFG0_DES_BIG_END_BIT 0x00000400U
100 #define DWC_SBUSCFG0_DES_BIG_END_SHIFT 10U
101
103 #define DWC_SBUSCFG0_DAT_BIG_END_BIT 0x00000800U
104 #define DWC_SBUSCFG0_DAT_BIG_END_SHIFT 11U
105
107 #define DWC_SBUSCFG0_STORE_AND_FORWARD_BIT 0x00001000U
108 #define DWC_SBUSCFG0_STORE_AND_FORWARD_SHIFT 12U
109
111 #define DWC_SBUSCFG0_SING_REQ_BIT 0x00004000U
112 #define DWC_SBUSCFG0_SING_REQ_SHIFT 14U
113
115 #define DWC_SBUSCFG0_READ_AFTER_WRITE_BIT 0x00008000U
116 #define DWC_SBUSCFG0_READ_AFTER_WRITE_SHIFT 15U
117
119 #define DWC_SBUSCFG0_DES_WR_REQ_INFO_BITS 0x000f0000U
120 #define DWC_SBUSCFG0_DES_WR_REQ_INFO_SHIFT 16U
121
123 #define DWC_SBUSCFG0_DAT_WR_REQ_INFO_BITS 0x00f00000U
124 #define DWC_SBUSCFG0_DAT_WR_REQ_INFO_SHIFT 20U
125
127 #define DWC_SBUSCFG0_DES_RD_REQ_INFO_BITS 0x0f000000U
128 #define DWC_SBUSCFG0_DES_RD_REQ_INFO_SHIFT 24U
129
131 #define DWC_SBUSCFG0_DAT_RD_REQ_INFO_BITS 0xf0000000U
132 #define DWC_SBUSCFG0_DAT_RD_REQ_INFO_SHIFT 28U
133
142 #define DWC_SBUSCFG1_DES_ADDR_SPC_BITS 0x0000000fU
143 #define DWC_SBUSCFG1_DES_ADDR_SPC_SHIFT 0U
144
146 #define DWC_SBUSCFG1_DAT_ADDR_SPC_BITS 0x000000f0U
147 #define DWC_SBUSCFG1_DAT_ADDR_SPC_SHIFT 4U
148
157 #define DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_BITS 0x00ff0000U
158 #define DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_SHIFT 16U
159
161 #define DWC_TXTHRCTL_USB_TX_PKT_CNT_BITS 0x1f000000U
162 #define DWC_TXTHRCTL_USB_TX_PKT_CNT_SHIFT 24U
163
165 #define DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_BIT 0x20000000U
166 #define DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_SHIFT 29U
167
177 #define DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_BITS 0x00f80000U
178 #define DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_SHIFT 19U
179
181 #define DWC_RXTHRCTL_USB_RX_PKT_CNT_BITS 0x0f000000U
182 #define DWC_RXTHRCTL_USB_RX_PKT_CNT_SHIFT 24U
183
185 #define DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_BIT 0x20000000U
186 #define DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_SHIFT 29U
187
196 #define DWC_GCTL_DSBL_CLCK_GTNG_BIT 0x00000001U
197 #define DWC_GCTL_DSBL_CLCK_GTNG_SHIFT 0U
198
200 #define DWC_GCTL_GBL_HIBER_EN_BIT 0x00000002U
201 #define DWC_GCTL_GBL_HIBER_EN_SHIFT 1U
202
204 #define DWC_GCTL_DIS_SCRAMBLE_BIT 0x00000008U
205 #define DWC_GCTL_DIS_SCRAMBLE_SHIFT 3U
206
208 #define DWC_GCTL_SCALE_DOWN_BITS 0x00000030U
209 #define DWC_GCTL_SCALE_DOWN_SHIFT 4U
210
212 #define DWC_GCTL_RAM_CLK_SEL_BITS 0x000000c0U
213 #define DWC_GCTL_RAM_CLK_SEL_SHIFT 6U
214
216 #define DWC_GCTL_DEBUG_ATTACH_BIT 0x00000100U
217 #define DWC_GCTL_DEBUG_ATTACH_SHIFT 8U
218
220 #define DWC_GCTL_U1U2_TIMER_SCALE_BIT 0x00000200U
221 #define DWC_GCTL_U1U2_TIMER_SCALE_SHIFT 9U
222
224 #define DWC_GCTL_SOFITPSYNC_BIT 0x00000400U
225 #define DWC_GCTL_SOFITPSYNC_SHIFT 10U
226
228 #define DWC_GCTL_CORE_SOFT_RST_BIT 0x00000800U
229 #define DWC_GCTL_CORE_SOFT_RST_SHIFT 11U
230
232 #define DWC_GCTL_PRT_CAP_DIR_BITS 0x00003000U
233 #define DWC_GCTL_PRT_CAP_DIR_SHIFT 12U
234
236 #define DWC_GCTL_PRT_CAP_HOST 1U
237 #define DWC_GCTL_PRT_CAP_DEVICE 2U
238 #define DWC_GCTL_PRT_CAP_OTG 3U
239
241 #define DWC_GCTL_FRMSCLDWN_BITS 0x0000c000U
242 #define DWC_GCTL_FRMSCLDWN_SHIFT 14U
243
245 #define DWC_GCTL_U2RSTECN_BIT 0x00010000U
246 #define DWC_GCTL_U2RSTECN_SHIFT 16U
247
249 #define DWC_GCTL_BYPSSETADDR_BIT 0x00020000U
250 #define DWC_GCTL_BYPSSETADDR_SHIFT 17U
251
253 #define DWC_GCTL_MASTERFILTBYPASS_BIT 0x00040000U
254 #define DWC_GCTL_MASTERFILTBYPASS_SHIFT 18U
255
257 #define DWC_GCTL_PWR_DN_SCALE_BITS 0xfff80000U
258 #define DWC_GCTL_PWR_DN_SCALE_SHIFT 19U
259
268 #define DWC_GEVTEN_ULPI_CK_EVT_EN_BIT 0x00000001U
269 #define DWC_GEVTEN_ULPI_CK_EVT_SHIFT 0U
270
272 #define DWC_GEVTEN_I2C_EVT_EN_BIT 0x00000002U
273 #define DWC_GEVTEN_I2C_EVT_EN_SHIFT 1U
274
287 #define DWC_GSTS_CURMODE_BITS 0x00000003U
288 #define DWC_GSTS_CURMODE_SHIFT 0U
289
290 #define DWC_GSTS_DEVICE_MODE 0U
291 #define DWC_GSTS_HOST_MODE 1U
292 #define DWC_GSTS_DRD_MODE 2U
293
295 #define DWC_GSTS_BUS_ERR_ADDR_VLD_BIT 0x00000010U
296 #define DWC_GSTS_BUS_ERR_ADDR_VLD_SHIFT 4U
297
299 #define DWC_GSTS_CSR_TIMEOUT_BIT 0x00000020U
300 #define DWC_GSTS_CSR_TIMEOUT_SHIFT 5U
301
303 #define DWC_GSTS_DEV_EVT_PENDING_BIT 0x00000040U
304 #define DWC_GSTS_DEV_EVT_PENDING_SHIFT 6U
305
307 #define DWC_GSTS_HOST_EVT_PENDING_BIT 0x00000080U
308 #define DWC_GSTS_HOST_EVT_PENDING_SHIFT 7U
309
311 #define DWC_GSTS_ADP_EVT_PENDING_BIT 0x00000100U
312 #define DWC_GSTS_ADP_EVT_PENDING_SHIFT 8U
313
315 #define DWC_GSTS_BC_EVT_PENDING_BIT 0x00000200U
316 #define DWC_GSTS_BC_EVT_PENDING_SHIFT 9U
317
319 #define DWC_GSTS_OTG_EVT_PENDING_BIT 0x00000400U
320 #define DWC_GSTS_OTG_EVT_PENDING_SHIFT 10U
321
323 #define DWC_GSTS_SSIC_IP_BIT 0x00000800U
324 #define DWC_GSTS_SSIC_IP_SHIFT 11U
325
327 #define DWC_GSTS_CBELT_BITS 0xfff00000U
328 #define DWC_GSTS_CBELT_SHIFT 20U
329
337 #define DWC_HWP0_MODE_BITS 0x00000007U
338 #define DWC_HWP0_MODE_SHIFT 0U
339
340 #define DWC_HWP0_MBUS_TYPE_BITS 0x00000038U
341 #define DWC_HWP0_MBUS_TYPE_SHIFT 3U
342
343 #define DWC_HWP0_SBUS_TYPE_BITS 0x000000c0U
344 #define DWC_HWP0_SBUS_TYPE_SHIFT 6U
345
346 #define DWC_HWP0_MDWIDTH_BITS 0x0000ff00U
347 #define DWC_HWP0_MDWIDTH_SHIFT 8U
348
349 #define DWC_HWP0_SDWIDTH_BITS 0x00ff0000U
350 #define DWC_HWP0_SDWIDTH_SHIFT 16U
351
352 #define DWC_HWP0_AWIDTH_BITS 0x3f000000U
353 #define DWC_HWP0_AWIDTH_SHIFT 24U
354
362 #define DWC_HWP1_IDWIDTH_M1_BITS 0x00000007U
363 #define DWC_HWP1_IDWIDTH_M1_SHIFT 0U
364
365 #define DWC_HWP1_BURSTWIDTH_M1_BITS 0x00000038U
366 #define DWC_HWP1_BURSTWIDTH_M1_SHIFT 3U
367
368 #define DWC_HWP1_DATAINFOWIDTH_BITS 0x000001c0U
369 #define DWC_HWP1_DATAINFOWIDTH_SHIFT 6U
370
371 #define DWC_HWP1_REQINFOWIDTH_BITS 0x00000e00U
372 #define DWC_HWP1_REQINFOWIDTH_SHIFT 9U
373
374 #define DWC_HWP1_ASPACEWIDTH_BITS 0x00007000U
375 #define DWC_HWP1_ASPACEWIDTH_SHIFT 12U
376
377 #define DWC_HWP1_DEV_NUM_INT_BITS 0x001f8000U
378 #define DWC_HWP1_DEV_NUM_INT_SHIFT 15U
379
380 #define DWC_HWP1_NUM_RAMS_BITS 0x00600000U
381 #define DWC_HWP1_NUM_RAMS_SHIFT 21U
382
383 #define DWC_HWP1_SPRAM_TYP_BIT 0x00800000U
384 #define DWC_HWP1_SPRAM_TYP_SHIFT 23U
385
386 #define DWC_HWP1_EN_PWROPT_BITS 0x03000000U
387 #define DWC_HWP1_EN_PWROPT_SHIFT 24U
388
389 #define DWC_EN_PWROPT_NONE 0U
390 #define DWC_EN_PWROPT_CLK_GATING_ONLY 1U
391 #define DWC_EN_PWROPT_HIBERNATION 2U
392
393 #define DWC_HWP1_MAC_PHY_CLKS_SYNC_BIT 0x04000000U
394 #define DWC_HWP1_MAC_PHY_CLKS_SYNC_SHIFT 26U
395
396 #define DWC_HWP1_MAC_RAM_CLKS_SYNC_BIT 0x08000000U
397 #define DWC_HWP1_MAC_RAM_CLKS_SYNC_SHIFT 27U
398
399 #define DWC_HWP1_RAM_BUS_CLKS_SYNC_BIT 0x10000000U
400 #define DWC_HWP1_RAM_BUS_CLKS_SYNC_SHIFT 28U
401
402 #define DWC_HWP1_RM_OPT_FEATURES_BIT 0x40000000U
403 #define DWC_HWP1_RM_OPT_FEATURES_SHIFT 30U
404
412 #define DWC_HWP2_USERID_BITS 0xffffffffU
413 #define DWC_HWP2_USERID_SHIFT 0U
414
422 #define DWC_HWP3_SSPHY_IFC_BITS 0x00000003U
423 #define DWC_HWP3_SSPHY_IFC_SHIFT 0U
424
425 #define DWC_HWP3_HSPHY_IFC_BITS 0x0000000cU
426 #define DWC_HWP3_HSPHY_IFC_SHIFT 2U
427
428 #define DWC_HWP3_FSPHY_IFC_BITS 0x00000030U
429 #define DWC_HWP3_FSPHY_IFC_SHIFT 4U
430
431 #define DWC_HWP3_HSPHY_DWIDTH_BITS 0x000000c0U
432 #define DWC_HWP3_HSPHY_DWIDTH_SHIFT 6U
433
434 #define DWC_HWP3_VEND_CTL_IFC_BIT 0x00000400U
435 #define DWC_HWP3_VEND_CTL_IFC_SHIFT 10U
436
437 #define DWC_HWP3_ULPI_CARKIT_BIT 0x00000800U
438 #define DWC_HWP3_ULPI_CARKIT_SHIFT 11U
439
440 #define DWC_HWP3_NUM_EPS_BITS 0x0003f000U
441 #define DWC_HWP3_NUM_EPS_SHIFT 12U
442
443 #define DWC_HWP3_NUM_IN_EPS_BITS 0x007c0000U
444 #define DWC_HWP3_NUM_IN_EPS_SHIFT 18U
445
446 #define DWC_HWP3_TOT_XFR_RSRC_BITS 0x7f800000U
447 #define DWC_HWP3_TOT_XFR_RSRC_SHIFT 23U
448
457 #define DWC_HWP4_TRBS_PER_XFER_BITS 0x0000003fU
458 #define DWC_HWP4_TRBS_PER_XFER_SHIFT 0U
459
460 #define DWC_HWP4_HIBER_SPAD_BITS 0x0001e000U
461 #define DWC_HWP4_HIBER_SPAD_SHIFT 13U
462
463 #define DWC_HWP4_NUM_SS_USB_INST_BITS 0x001e0000U
464 #define DWC_HWP4_NUM_SS_USB_INST_SHIFT 17U
465
466 #define DWC_HWP4_EN_ISOC_SUPT_BIT 0x00800000U
467 #define DWC_HWP4_EN_ISOC_SUPT_SHIFT 23U
468
469 #define DWC_HWP4_BMU_PTL_DEPTH_BITS 0x0f000000U
470 #define DWC_HWP4_BMU_PTL_DEPTH_SHIFT 24U
471
472 #define DWC_HWP4_BMU_LSP_DEPTH_BITS 0xf0000000U
473 #define DWC_HWP4_BMU_LSP_DEPTH_SHIFT 28U
474
482 #define DWC_HWP5_BMU_BUSGM_DEPTH_BITS 0x0000000fU
483 #define DWC_HWP5_BMU_BUSGM_DEPTH_SHIFT 0U
484
485 #define DWC_HWP5_RXQ_FIFO_DEPTH_BITS 0x000003f0U
486 #define DWC_HWP5_RXQ_FIFO_DEPTH_SHIFT 4U
487
488 #define DWC_HWP5_TXQ_FIFO_DEPTH_BITS 0x0000fc00U
489 #define DWC_HWP5_TXQ_FIFO_DEPTH_SHIFT 10U
490
491 #define DWC_HWP5_DWQ_FIFO_DEPTH_BITS 0x003f0000U
492 #define DWC_HWP5_DWQ_FIFO_DEPTH_SHIFT 16U
493
494 #define DWC_HWP5_DFQ_FIFO_DEPTH_BITS 0x0fc00000U
495 #define DWC_HWP5_DFQ_FIFO_DEPTH_SHIFT 22U
496
504 #define DWC_HWP6_PSQ_FIFO_DEPTH_BITS 0x0000003fU
505 #define DWC_HWP6_PSQ_FIFO_DEPTH_SHIFT 0U
506
507 #define DWC_HWP6_EN_DBG_PORTS_BIT 0x00000040U
508 #define DWC_HWP6_EN_DBG_PORTS_SHIFT 6U
509
510 #define DWC_HWP6_EN_FPGA_BIT 0x00000080U
511 #define DWC_HWP6_EN_FPGA_SHIFT 7U
512
513 #define DWC_HWP6_EN_SRP_BIT 0x00000400U
514 #define DWC_HWP6_EN_SRP_SHIFT 10U
515
516 #define DWC_HWP6_EN_HNP_BIT 0x00000800U
517 #define DWC_HWP6_EN_HNP_SHIFT 11U
518
519 #define DWC_HWP6_EN_ADP_BIT 0x00001000U
520 #define DWC_HWP6_EN_ADP_SHIFT 12U
521
522 #define DWC_HWP6_EN_OTG_BIT 0x00002000U
523 #define DWC_HWP6_EN_OTG_SHIFT 13U
524
525 #define DWC_HWP6_EN_BC_BIT 0x00004000U
526 #define DWC_HWP6_EN_BC_SHIFT 14U
527
528 #define DWC_HWP6_EN_BUS_FILTERS_BIT 0x00008000U
529 #define DWC_HWP6_EN_BUS_FILTERS_SHIFT 15U
530
531 #define DWC_HWP6_RAM0_DEPTH_BITS 0xffff0000U
532 #define DWC_HWP6_RAM0_DEPTH_SHIFT 16U
533
541 #define DWC_HWP7_RAM1_DEPTH_BITS 0x0000ffffU
542 #define DWC_HWP7_RAM1_DEPTH_SHIFT 0U
543
544 #define DWC_HWP7_RAM2_DEPTH_BITS 0xffff0000U
545 #define DWC_HWP7_RAM2_DEPTH_SHIFT 16U
546
554 #define DWC_HWP8_DCACHE_DEPTH_BITS 0xffffffffU
555 #define DWC_HWP8_DCACHE_DEPTH_SHIFT 0U
556
572 #define DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_BITS 0x000000ffU
573 #define DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_SHIFT 0U
574
576 #define DWC_DBGFIFOSPACE_SPACE_AVAIL_BITS 0xffff0000U
577 #define DWC_DBGFIFOSPACE_SPACE_AVAIL_SHIFT 16U
578
587 #define DWC_DBGLTSSM_PIPE_STATUS_BITS 0x0003ffffU
588 #define DWC_DBGLTSSM_PIPE_STATUS_SHIFT 0U
589
591 #define DWC_DBGLTSSM_LTDB_SUB_STATE_BITS 0x003c0000U
592 #define DWC_DBGLTSSM_LTDB_SUB_STATE_SHIFT 18U
593
595 #define DWC_DBGLTSSM_LTDB_STATE_BITS 0x03c00000U
596 #define DWC_DBGLTSSM_LTDB_STATE_SHIFT 22U
597
599 #define DWC_DBGLTSSM_LTDB_TIMEOUT_BIT 0x04000000U
600 #define DWC_DBGLTSSM_LTDB_TIMEOUT_SHIFT 26U
601
608 #define DWC_RMMICTL_MPHY_STATE_BITS 0x0e000000U
609 #define DWC_RMMICTL_MPHY_STATE_SHIFT 25U
610
611 #define DWC_MPHY_STATE_DISABLED 0U
612 #define DWC_MPHY_STATE_HIBERN8 1U
613 #define DWC_MPHY_STATE_SLEEP 2U
614 #define DWC_MPHY_STATE_STALL 3U
615 #define DWC_MPHY_STATE_PWM_BURST 4U
616 #define DWC_MPHY_STATE_HS_BURST 5U
617 #define DWC_MPHY_STATE_LINE_CFG 6U
618 #define DWC_MPHY_STATE_LINE_RESET 7U
619
620 #define DWC_RMMICTL_AUTO_EXIT_RRAP_BIT 0x10000000U
621 #define DWC_RMMICTL_AUTO_EXIT_RRAP_SHIFT 28U
622
623 #define DWC_RMMICTL_AUTO_ROM_RRAP_BIT 0x20000000U
624 #define DWC_RMMICTL_AUTO_ROM_RRAP_SHIFT 29U
625
626 #define DWC_RMMICTL_AUTO_EXIT_H8_BIT 0x40000000U
627 #define DWC_RMMICTL_AUTO_EXIT_H8_SHIFT 30U
628
629 #define DWC_RMMICTL_AUTO_ROM_H8_BIT 0x80000000U
630 #define DWC_RMMICTL_AUTO_ROM_H8_SHIFT 31U
631
639 #define DWC_USB2PHYCFG_TOUT_CAL_BITS 0x00000007U
640 #define DWC_USB2PHYCFG_TOUT_CAL_SHIFT 0U
641
643 #define DWC_USB2PHYCFG_16B_PHY_IF_BIT 0x00000008U
644 #define DWC_USB2PHYCFG_16B_PHY_IF_SHIFT 3U
645 /*--------*/
647 #define DWC_USB2PHYCFG_DDR_SEL_BIT 0x00000008U
648 #define DWC_USB2PHYCFG_DDR_SEL_SHIFT 3U
649
651 #define DWC_USB2PHYCFG_UTMI_ULPI_BIT 0x00000010U
652 #define DWC_USB2PHYCFG_UTMI_ULPI_SHIFT 4U
653
655 #define DWC_USB2PHYCFG_FSINTF_BIT 0x00000020U
656 #define DWC_USB2PHYCFG_FSINTF_SHIFT 5U
657
659 #define DWC_USB2PHYCFG_SUS_PHY_BIT 0x00000040U
660 #define DWC_USB2PHYCFG_SUS_PHY_SHIFT 6U
661
663 #define DWC_USB2PHYCFG_PHY_SEL_BIT 0x00000080U
664 #define DWC_USB2PHYCFG_PHY_SEL_SHIFT 7U
665
667 #define DWC_USB2PHYCFG_ENBL_SLP_M_BIT 0x00000100U
668 #define DWC_USB2PHYCFG_ENBL_SLP_M_SHIFT 8U
669
671 #define DWC_USB2PHYCFG_USB_TRD_TIM_BITS 0x00003c00U
672 #define DWC_USB2PHYCFG_USB_TRD_TIM_SHIFT 10U
673
675 #define DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_BIT 0x00004000U
676 #define DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_SHIFT 14U
677
679 #define DWC_USB2PHYCFG_ULPI_AUTO_RES_BIT 0x0000800U
680 #define DWC_USB2PHYCFG_ULPI_AUTO_RES_SHIFT 15U
681
683 #define DWC_USB2PHYCFG_ULPI_CLK_SUS_M_BIT 0x00010000U
684 #define DWC_USB2PHYCFG_ULPI_CLK_SUS_M_SHIFT 16U
685
687 #define DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_BIT 0x00020000U
688 #define DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_SHIFT 17U
689
691 #define DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_BIT 0x00040000U
692 #define DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_SHIFT 18U
693
695 #define DWC_USB2PHYCFG_PHY_INTR_NUM_BITS 0x01f80000U
696 #define DWC_USB2PHYCFG_PHY_INTR_NUM_SHIFT 19U
697
699 #define DWC_USB2PHYCFG_OTG_INTR_NUM_BITS 0x7e000000U
700 #define DWC_USB2PHYCFG_OTG_INTR_NUM_SHIFT 25U
701
703 #define DWC_USB2PHYCFG_PHY_SOFT_RST_BIT 0x80000000U
704 #define DWC_USB2PHYCFG_PHY_SOFT_RST_SHIFT 31U
705
713 #define DWC_USB2I2C_RSVD_BITS 0xffffffffU
714 #define DWC_USB2I2C_RSVD_SHIFT 0U
715
724 #define DWC_USB2PHY_REGDATA_BITS 0x000000ffU
725 #define DWC_USB2PHY_REGDATA_SHIFT 0U
726
728 #define DWC_USB2PHY_VCTRL_BITS 0x0000ff00U
729 #define DWC_USB2PHY_VCTRL_SHIFT 8U
730 /*--------*/
732 #define DWC_USB2PHY_EXTREGADDR_BITS 0x00003f00U
733 #define DWC_USB2PHY_EXTREGADDR_SHIFT 8U
734
736 #define DWC_USB2PHY_REGADDR_BITS 0x003f0000U
737 #define DWC_USB2PHY_REGADDR_SHIFT 16U
738
740 #define DWC_USB2PHY_REGWR_BIT 0x00400000U
741 #define DWC_USB2PHY_REGWR_SHIFT 22U
742
744 #define DWC_USB2PHY_VSTSBSY_BIT 0x00800000U
745 #define DWC_USB2PHY_VSTSBSY_SHIFT 23U
746
748 #define DWC_USB2PHY_VSTSDONE_BIT 0x01000000U
749 #define DWC_USB2PHY_VSTSDONE_SHIFT 24U
750
752 #define DWC_USB2PHY_NEWREGREQ_BIT 0x02000000U
753 #define DWC_USB2PHY_NEWREGREQ_SHIFT 25U
754
756 #define DWC_USB2PHY_DIS_ULPI_DRVR_BIT 0x04000000U
757 #define DWC_USB2PHY_DIS_ULPI_DRVR_SHIFT 26U
758
767 #define DWC_PIPECTL_ELAS_BUF_MODE_BIT 0x00000001U
768 #define DWC_PIPECTL_ELAS_BUF_MODE_SHIFT 0U
769
771 #define DWC_PIPECTL_TX_DEMPH_BITS 0x00000006U
772 #define DWC_PIPECTL_TX_DEMPH_SHIFT 1U
773
775 #define DWC_PIPECTL_TX_MARGIN_BITS 0x00000038U
776 #define DWC_PIPECTL_TX_MARGIN_SHIFT 3U
777
779 #define DWC_PIPECTL_TX_SWING_BIT 0x00000040U
780 #define DWC_PIPECTL_TX_SWING_SHIFT 6U
781
783 #define DWC_PIPECTL_SSIC_EN_BIT 0x00000080U
784 #define DWC_PIPECTL_SSIC_EN_SHIFT 7U
785
787 #define DWC_PIPECTL_LFPS_FILTER_BIT 0x00000200U
788 #define DWC_PIPECTL_LFPS_FILTER_SHIFT 9U
789
791 #define DWC_PIPECTL_P3_EX_SIG_P2_BIT 0x00000400U
792 #define DWC_PIPECTL_P3_EX_SIG_P2_SHIFT 10U
793
795 #define DWC_PIPECTL_P3_P2_TRAN_OK_BIT 0x00000800U
796 #define DWC_PIPECTL_P3_P2_TRAN_OK_SHIFT 11U
797
799 #define DWC_PIPECTL_LFPS_P0_ALGN_BIT 0x00001000U
800 #define DWC_PIPECTL_LFPS_P0_ALGN_SHIFT 12U
801
803 #define DWC_PIPECTL_DATA_WIDTH_BITS 0x00018000U
804 #define DWC_PIPECTL_DATA_WIDTH_SHIFT 15U
805
807 #define DWC_PIPECTL_SUS_PHY_BIT 0x00020000U
808 #define DWC_PIPECTL_SUS_PHY_SHIFT 17U
809
811 #define DWC_PIPECTL_PHY_SOFT_RST_BIT 0x80000000U
812 #define DWC_PIPECTL_PHY_SOFT_RST_SHIFT 31U
813
819 #define DWC_FIFOSZ_DEPTH_BITS 0x0000ffffU
820 #define DWC_FIFOSZ_DEPTH_SHIFT 0U
821
823 #define DWC_FIFOSZ_STARTADDR_BITS 0xffff0000U
824 #define DWC_FIFOSZ_STARTADDR_SHIFT 16U
825
833 #define DWC_EVENTSIZ_SIZ_BITS 0x0000ffffU
834 #define DWC_EVENTSIZ_SIZ_SHIFT 0U
835
837 #define DWC_EVENTSIZ_INT_MSK_BIT 0x80000000U
838 #define DWC_EVENTSIZ_INT_MSK_SHIFT 31U
839
848 #define DWC_EVENTCNT_CNT_BITS 0x0000ffffU
849 #define DWC_EVENTCNT_CNT_SHIFT 0U
850
855 #define DWC_EVENT_NON_EP_BIT 0x01U
856 #define DWC_EVENT_NON_EP_SHIFT 0U
857
859 #define DWC_EVENT_INTTYPE_BITS 0xfeU
860 #define DWC_EVENT_INTTYPE_SHIFT 1U
861
863 #define DWC_EVENT_DEV_INT 0U
864 #define DWC_EVENT_OTG_INT 1U
865 #define DWC_EVENT_CARKIT_INT 3U
866 #define DWC_EVENT_I2C_INT 4U
867
874 #define DWC_DEVT_BITS 0x00000f00U
875 #define DWC_DEVT_SHIFT 8U
876
878 #define DWC_DEVT_DISCONN 0U
879 #define DWC_DEVT_USBRESET 1U
880 #define DWC_DEVT_CONNDONE 2U
881 #define DWC_DEVT_ULST_CHNG 3U
882 #define DWC_DEVT_WKUP 4U
883 #define DWC_DEVT_HIBER_REQ 5U
884 #define DWC_DEVT_U3_L2L1_SUSP 6U
885 #define DWC_DEVT_SOF 7U
886 #define DWC_DEVT_ERRATICERR 9U
887 #define DWC_DEVT_CMD_CMPL 10U
888 #define DWC_DEVT_OVERFLOW 11U
889 #define DWC_DEVT_VNDR_DEV_TST_RCVD 12U
890 #define DWC_DEVT_INACT_TIMEOUT_RCVD 13U
891
893 #define DWC_DEVT_EVT_INFO_BITS 0xffff0000U
894 #define DWC_DEVT_EVT_INFO_SHIFT 16U
895
897 #define DWC_DEVT_ULST_STATE_BITS 0x000f0000U
898 #define DWC_DEVT_ULST_STATE_SHIFT 16U
899
901 #define DWC_LINK_STATE_U0 0U
902 #define DWC_LINK_STATE_U1 1U
903 #define DWC_LINK_STATE_U2 2U
904 #define DWC_LINK_STATE_U3 3U
905 #define DWC_LINK_STATE_SS_DIS 4U
906 #define DWC_LINK_STATE_RX_DET 5U
907 #define DWC_LINK_STATE_SS_INACT 6U
908 #define DWC_LINK_STATE_POLL 7U
909 #define DWC_LINK_STATE_RECOV 8U
910 #define DWC_LINK_STATE_HRESET 9U
911 #define DWC_LINK_STATE_CMPLY 10U
912 #define DWC_LINK_STATE_LPBK 11U
913 #define DWC_LINK_STATE_RESET 14U
914 #define DWC_LINK_STATE_RESUME 15U
915
917 #define DWC_LINK_STATE_ON 0U
918 #define DWC_LINK_STATE_SLEEP 2U
919 #define DWC_LINK_STATE_SUSPEND 3U
920 #define DWC_LINK_STATE_EARLY_SUSPEND 5U
921
922 #define DWC_DEVT_ULST_SS_BIT 0x00100000U
923 #define DWC_DEVT_ULST_SS_SHIFT 20U
924
925 #define DWC_DEVT_HIBER_STATE_BITS DWC_DEVT_ULST_STATE_BITS
926 #define DWC_DEVT_HIBER_STATE_SHIFT DWC_DEVT_ULST_STATE_SHIFT
927
928 #define DWC_DEVT_HIBER_SS_BIT DWC_DEVT_ULST_SS_BIT
929 #define DWC_DEVT_HIBER_SS_SHIFT DWC_DEVT_ULST_SS_SHIFT
930
931 #define DWC_DEVT_HIBER_HIRD_BITS 0x0f000000U
932 #define DWC_DEVT_HIBER_HIRD_SHIFT 24U
933
939 #define DWC_DEPEVT_EPNUM_BITS 0x0000003eU
940 #define DWC_DEPEVT_EPNUM_SHIFT 1U
941
943 #define DWC_DEPEVT_INTTYPE_BITS 0x000003c0U
944 #define DWC_DEPEVT_INTTYPE_SHIFT 6U
945
947 #define DWC_DEPEVT_XFER_CMPL 1U
948 #define DWC_DEPEVT_XFER_IN_PROG 2U
949 #define DWC_DEPEVT_XFER_NRDY 3U
950 #define DWC_DEPEVT_FIFOXRUN 4U
951 #define DWC_DEPEVT_STRM_EVT 6U
952 #define DWC_DEPEVT_EPCMD_CMPL 7U
953
955 #define DWC_DEPEVT_NO_MORE_RSCS_BIT 0x00001000U
956 #define DWC_DEPEVT_NO_MORE_RSCS_SHIFT 12U
957 #define DWC_DEPEVT_ISOC_TIME_PASSED_BIT 0x00002000U
958 #define DWC_DEPEVT_ISOC_TIME_PASSED_SHIFT 13U
959
961 #define DWC_DEPEVT_STRM_EVT_BITS 0x0000f000U
962 #define DWC_DEPEVT_STRM_EVT_SHIFT 12U
963
965 #define DWC_DEPEVT_STRM_FOUND 1U
966 #define DWC_DEPEVT_STRM_NOT_FOUND 2U
967
969 #define DWC_DEPEVT_BUS_ERR_BIT 0x00001000U
970 #define DWC_DEPEVT_BUS_ERR_SHIFT 12U
971 #define DWC_DEPEVT_SHORT_PKT_BIT 0x00002000U
972 #define DWC_DEPEVT_SHORT_PKT_SHIFT 13U
973 #define DWC_DEPEVT_IOC_BIT 0x00004000U
974 #define DWC_DEPEVT_IOC_SHIFT 14U
975 #define DWC_DEPEVT_LST_BIT 0x00008000U
976 #define DWC_DEPEVT_LST_SHIFT 15U
977 #define DWC_DEPEVT_MISSED_ISOC_BIT DWC_DEPEVT_LST_BIT
978 #define DWC_DEPEVT_MISSED_ISOC_SHIFT DWC_DEPEVT_LST_SHIFT
979
981 #define DWC_DEPEVT_CTRL_BITS 0x00003000U
982 #define DWC_DEPEVT_CTRL_SHIFT 12U
983 #define DWC_DEPEVT_XFER_ACTIVE_BIT 0x00008000U
984 #define DWC_DEPEVT_XFER_ACTIVE_SHIFT 15U
985
987 #define DWC_DEPEVT_CTRL_SETUP 0U
988 #define DWC_DEPEVT_CTRL_DATA 1U
989 #define DWC_DEPEVT_CTRL_STATUS 2U
990
992 #define DWC_DEPEVT_STRM_ID_BITS 0xffff0000U
993 #define DWC_DEPEVT_STRM_ID_SHIFT 16U
994
996 #define DWC_DEPEVT_ISOC_UFRAME_NUM_BITS 0xffff0000U
997 #define DWC_DEPEVT_ISOC_UFRAME_NUM_SHIFT 16U
998
1000 #define DWC_DEPEVT_XFER_RSC_IDX_BITS 0x007f0000U
1001 #define DWC_DEPEVT_XFER_RSC_IDX_SHIFT 16U
1002
1004 #define DWC_DEPEVT_CUR_DAT_SEQ_NUM_BITS 0x001f0000U
1005 #define DWC_DEPEVT_CUR_DAT_SEQ_NUM_SHIFT 16U
1006
1008 #define DWC_DEPEVT_FLOW_CTRL_BIT 0x00200000U
1009 #define DWC_DEPEVT_FLOW_CTRL_SHIFT 21U
1010
1016 #define DWC_GINT_PHY_PORT_BITS 0xf00U
1017 #define DWC_GINT_PHY_PORT_SHIFT 8U
1018
1023 typedef struct geventbuf_data {
1025 volatile u32 geventadr_lo;
1026
1028 volatile u32 geventadr_hi;
1029
1032 volatile u32 geventsiz;
1033
1036 volatile u32 geventcnt;
1037 } geventbuf_data_t;
1038
1045 typedef struct dwc_usb3_core_global_regs {
1046
1047 #define DWC_CORE_GLOBAL_REG_OFFSET 0x100U
1048
1051 volatile u32 gsbuscfg0;
1052
1055 volatile u32 gsbuscfg1;
1056
1059 volatile u32 gtxthrcfg;
1060
1063 volatile u32 grxthrcfg;
1064
1067 volatile u32 gctl;
1068
1071 volatile u32 gevten;
1072
1075 volatile u32 gsts;
1076
1078 volatile u32 reserved0;
1079
1081 volatile u32 gsnpsid;
1082
1084 volatile u32 ggpio;
1085
1087 volatile u32 guid;
1088
1090 volatile u32 reserved1;
1091
1093 volatile u32 gbuserraddrlo;
1094
1096 volatile u32 gbuserraddrhi;
1097
1099 volatile u32 gprtbimap_lo;
1100
1102 volatile u32 gprtbimap_hi;
1103
1106 volatile u32 ghwparams0;
1107
1110 volatile u32 ghwparams1;
1111
1114 volatile u32 ghwparams2;
1115
1118 volatile u32 ghwparams3;
1119
1122 volatile u32 ghwparams4;
1123
1126 volatile u32 ghwparams5;
1127
1130 volatile u32 ghwparams6;
1131
1134 volatile u32 ghwparams7;
1135
1138 volatile u32 gdbgfifospace;
1139
1142 volatile u32 gdbgltssm;
1143
1145 volatile u32 gdbglnmcc;
1146
1148 volatile u32 gdbgbmu;
1149
1151 volatile u32 gdbglspmux;
1152
1154 volatile u32 gdbglsp;
1155
1157 volatile u32 gdbgepinfo0;
1158
1160 volatile u32 gdbgepinfo1;
1161
1163 volatile u32 gprtbimap_hs_lo;
1164
1166 volatile u32 gprtbimap_hs_hi;
1167
1169 volatile u32 gprtbimap_fs_lo;
1170
1172 volatile u32 gprtbimap_fs_hi;
1173
1175 volatile u32 reserved4[12];
1176
1178 volatile u32 gusb3rmmictl[16];
1179
1182 volatile u32 gusb2phycfg[16];
1183
1186 volatile u32 gusb2i2cctl[16];
1187
1190 volatile u32 gusb2phyacc[16];
1191
1194 volatile u32 gusb3pipectl[16];
1195
1197 volatile u32 gtxfifosiz[32];
1198
1200 volatile u32 grxfifosiz[32];
1201
1204 struct geventbuf_data geventbuf[32];
1205
1208 volatile u32 ghwparams8;
1209 } dwc_usb3_core_global_regs_t;
1210
1211
1212 /****************************************************************************/
1213 /* Device Global Registers */
1214
1222 #define DWC_DCFG_DEVSPD_BITS 0x000007U
1223 #define DWC_DCFG_DEVSPD_SHIFT 0U
1224
1226 #define DWC_SPEED_HS_PHY_30MHZ_OR_60MHZ 0U
1227 #define DWC_SPEED_FS_PHY_30MHZ_OR_60MHZ 1U
1228 #define DWC_SPEED_LS_PHY_6MHZ 2U
1229 #define DWC_SPEED_FS_PHY_48MHZ 3U
1230 #define DWC_SPEED_SS_PHY_125MHZ_OR_250MHZ 4U
1231
1233 #define DWC_DCFG_DEVADDR_BITS 0x0003f8U
1234 #define DWC_DCFG_DEVADDR_SHIFT 3U
1235
1237 #define DWC_DCFG_PER_FR_INTVL_BITS 0x000c00U
1238 #define DWC_DCFG_PER_FR_INTVL_SHIFT 10U
1239
1241 #define DWC_DCFG_PER_FR_INTVL_80 0U
1242 #define DWC_DCFG_PER_FR_INTVL_85 1U
1243 #define DWC_DCFG_PER_FR_INTVL_90 2U
1244 #define DWC_DCFG_PER_FR_INTVL_95 3U
1245
1247 #define DWC_DCFG_DEV_INTR_NUM_BITS 0x01f000U
1248 #define DWC_DCFG_DEV_INTR_NUM_SHIFT 12U
1249
1251 #define DWC_DCFG_NUM_RCV_BUF_BITS 0x3e0000U
1252 #define DWC_DCFG_NUM_RCV_BUF_SHIFT 17U
1253
1255 #define DWC_DCFG_LPM_CAP_BIT 0x400000U
1256 #define DWC_DCFG_LPM_CAP_SHIFT 22U
1257
1266 #define DWC_DCTL_SFT_DISCONN_BIT 0x00000001U
1267 #define DWC_DCTL_SFT_DISCONN_SHIFT 0U
1268
1270 #define DWC_DCTL_TSTCTL_BITS 0x0000001eU
1271 #define DWC_DCTL_TSTCTL_SHIFT 1U
1272
1274 #define DWC_DCTL_ULST_CHNG_REQ_BITS 0x000001e0U
1275 #define DWC_DCTL_ULST_CHNG_REQ_SHIFT 5U
1276
1278 #define DWC_LINK_STATE_REQ_NO_ACTION 0U
1279 #define DWC_LINK_STATE_REQ_SS_DISABLED 4U
1280 #define DWC_LINK_STATE_REQ_RX_DETECT 5U
1281 #define DWC_LINK_STATE_REQ_INACTIVE 6U
1282 #define DWC_LINK_STATE_REQ_RECOVERY 8U
1283 #define DWC_LINK_STATE_REQ_COMPLIANCE 10U
1284 #define DWC_LINK_STATE_REQ_LOOPBACK 11U
1285 #define DWC_LINK_STATE_REQ_HOST_MODE_ONLY 15U
1286
1288 #define DWC_LINK_STATE_REQ_REMOTE_WAKEUP 8U
1289
1291 #define DWC_DCTL_ACCEPT_U1_EN_BIT 0x00000200U
1292 #define DWC_DCTL_ACCEPT_U1_EN_SHIFT 9U
1293 #define DWC_DCTL_INIT_U1_EN_BIT 0x00000400U
1294 #define DWC_DCTL_INIT_U1_EN_SHIFT 10U
1295 #define DWC_DCTL_ACCEPT_U2_EN_BIT 0x00000800U
1296 #define DWC_DCTL_ACCEPT_U2_EN_SHIFT 11U
1297 #define DWC_DCTL_INIT_U2_EN_BIT 0x00001000U
1298 #define DWC_DCTL_INIT_U2_EN_SHIFT 12U
1299
1301 #define DWC_DCTL_CSS_BIT 0x00010000U
1302 #define DWC_DCTL_CSS_SHIFT 16U
1303
1305 #define DWC_DCTL_CRS_BIT 0x00020000U
1306 #define DWC_DCTL_CRS_SHIFT 17U
1307
1309 #define DWC_DCTL_L1_HIBER_EN_BIT 0x00040000U
1310 #define DWC_DCTL_L1_HIBER_EN_RES_SHIFT 18U
1311
1313 #define DWC_DCTL_KEEP_CONNECT_BIT 0x00080000U
1314 #define DWC_DCTL_KEEP_CONNECT_SHIFT 19U
1315
1317 #define DWC_DCTL_LPM_NYET_THRESH_BITS 0x00f00000U
1318 #define DWC_DCTL_LPM_NYET_THRESH_SHIFT 20U
1319
1321 #define DWC_DCTL_APP_L1_RES_BIT 0x00800000U
1322 #define DWC_DCTL_APP_L1_RES_SHIFT 23U
1323
1324 /* HIRD Threshold <i>Access: R_W</i> */
1325 #define DWC_DCTL_HIRD_THR_BITS 0x1f000000U
1326 #define DWC_DCTL_HIRD_THR_SHIFT 24U
1327
1329 #define DWC_DCTL_LSFT_RST_BIT 0x20000000U
1330 #define DWC_DCTL_LSFT_RST_SHIFT 29U
1331
1333 #define DWC_DCTL_CSFT_RST_BIT 0x40000000U
1334 #define DWC_DCTL_CSFT_RST_SHIFT 30U
1335
1337 #define DWC_DCTL_RUN_STOP_BIT 0x80000000U
1338 #define DWC_DCTL_RUN_STOP_SHIFT 31U
1339
1348 #define DWC_DEVTEN_DISCONN_BIT 0x0001U
1349 #define DWC_DEVTEN_DISCONN_SHIFT 0U
1350
1352 #define DWC_DEVTEN_USBRESET_BIT 0x0002U
1353 #define DWC_DEVTEN_USBRESET_SHIFT 1U
1354
1356 #define DWC_DEVTEN_CONNDONE_BIT 0x0004U
1357 #define DWC_DEVTEN_CONNDONE_SHIFT 2U
1358
1360 #define DWC_DEVTEN_ULST_CHNG_BIT 0x0008U
1361 #define DWC_DEVTEN_ULST_CHNG_SHIFT 3U
1362
1364 #define DWC_DEVTEN_WKUP_BIT 0x0010U
1365 #define DWC_DEVTEN_WKUP_SHIFT 4U
1366
1368 #define DWC_DEVTEN_HIBER_REQ_BIT 0x0020U
1369 #define DWC_DEVTEN_HIBER_REQ_SHIFT 5U
1370
1372 #define DWC_DEVTEN_U3_L2L1_SUSP_BIT 0x0040U
1373 #define DWC_DEVTEN_U3_L2L1_SUSP_SHIFT 6U
1374
1376 #define DWC_DEVTEN_SOF_BIT 0x0080U
1377 #define DWC_DEVTEN_SOF_SHIFT 7U
1378
1380 #define DWC_DEVTEN_ERRATICERR_BIT 0x0200U
1381 #define DWC_DEVTEN_ERRATICERR_SHIFT 9U
1382
1384 #define DWC_DEVTEN_INACT_TIMEOUT_BIT 0x2000U
1385 #define DWC_DEVTEN_INACT_TIMEOUT_SHIFT 13U
1386
1396 #define DWC_DSTS_CONNSPD_BITS 0x00000007U
1397 #define DWC_DSTS_CONNSPD_SHIFT 0U
1398
1400 #define DWC_DSTS_SOF_FN_BITS 0x0001fff8U
1401 #define DWC_DSTS_SOF_FN_SHIFT 3U
1402
1404 #define DWC_DSTS_RXFIFO_EMPTY_BIT 0x00020000U
1405 #define DWC_DSTS_RXFIFO_EMPTY_SHIFT 17U
1406
1408 #define DWC_DSTS_USBLNK_STATE_BITS 0x003c0000U
1409 #define DWC_DSTS_USBLNK_STATE_SHIFT 18U
1410
1414 #define DWC_DSTS_DEV_CTRL_HLT_BIT 0x00400000U
1415 #define DWC_DSTS_DEV_CTRL_HLT_SHIFT 22U
1416
1418 #define DWC_DSTS_CORE_IDLE_BIT 0x00800000U
1419 #define DWC_DSTS_CORE_IDLE_SHIFT 23U
1420
1422 #define DWC_DSTS_SSS_BIT 0x01000000U
1423 #define DWC_DSTS_SSS_SHIFT 24U
1424
1426 #define DWC_DSTS_RSS_BIT 0x02000000U
1427 #define DWC_DSTS_RSS_SHIFT 25U
1428
1430 #define DWC_DSTS_SRE_BIT 0x10000000U
1431 #define DWC_DSTS_SRE_SHIFT 28U
1432
1434 #define DWC_DSTS_LNR_BIT 0x20000000U
1435 #define DWC_DSTS_LNR_SHIFT 29U
1436
1445 #define DWC_DGCMD_PER_PARAM_SEL_BITS 0x000003ffU
1446 #define DWC_DGCMD_PER_PARAM_SEL_SHIFT 0U
1447
1449 #define DWC_DGCMDPAR_HOST_ROLE_REQ_BITS 0x00000003U
1450 #define DWC_DGCMDPAR_HOST_ROLE_REQ_SHIFT 0U
1451
1454 #define DWC_DGCMDPAR_HOST_ROLE_REQ_INITIATE 1U
1455 #define DWC_DGCMDPAR_HOST_ROLE_REQ_CONFIRM 2U
1456
1458 #define DWC_DGCMDPAR_DEV_NOTIF_TYPE_BITS 0x0000000fU
1459 #define DWC_DGCMDPAR_DEV_NOTIF_TYPE_SHIFT 0U
1460
1462 #define DWC_DGCMD_FUNCTION_WAKE_DEV_NOTIF 1U
1463 #define DWC_DGCMD_LATENCY_TOL_DEV_NOTIF 2U
1464 #define DWC_DGCMD_BUS_INTVL_ADJ_DEV_NOTIF 3U
1465 #define DWC_DGCMD_HOST_ROLE_REQ_DEV_NOTIF 4U
1466
1468 #define DWC_DGCMDPAR_DEV_NOTIF_PARAM_BITS 0xfffffff0U
1469 #define DWC_DGCMDPAR_DEV_NOTIF_PARAM_SHIFT 4U
1470
1473 #define DWC_DGCMDPAR_BELT_VALUE_BITS 0x000003ffU
1474 #define DWC_DGCMDPAR_BELT_VALUE_SHIFT 0U
1475
1478 #define DWC_DGCMDPAR_BELT_SCALE_BITS 0x00000c00U
1479 #define DWC_DGCMDPAR_BELT_SCALE_SHIFT 10U
1480
1482 #define DWC_LATENCY_VALUE_MULT_1024 1U
1483 #define DWC_LATENCY_VALUE_MULT_32768 2U
1484 #define DWC_LATENCY_VALUE_MULT_1048576 3U
1485
1494 #define DWC_DGCMD_TYP_BITS 0x0ffU
1495 #define DWC_DGCMD_TYP_SHIFT 0U
1496
1498 #define DWC_DGCMD_SET_PERIODIC_PARAMS 2U
1499 #define DWC_DGCMD_XMIT_FUNC_WAKE_DEV_NOTIF 3U
1500 #define DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_LO 4U
1501 #define DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_HI 5U
1502 #define DWC_DGCMD_XMIT_HOST_ROLE_REQUEST 6U
1503 #define DWC_DGCMD_XMIT_DEV_NOTIF 7U
1504 #define DWC_DGCMD_SELECTED_FIFO_FLUSH 9U
1505 #define DWC_DGCMD_ALL_FIFO_FLUSH 10U
1506 #define DWC_DGCMD_SET_EP_NRDY 12U
1507 #define DWC_DGCMD_RUN_SOC_BUS_LOOPBK_TST 16U
1508
1510 #define DWC_DGCMD_IOC_BIT 0x100U
1511 #define DWC_DGCMD_IOC_SHIFT 8U
1512
1514 #define DWC_DGCMD_ACT_BIT 0x400U
1515 #define DWC_DGCMD_ACT_SHIFT 10U
1516
1518 #define DWC_DGCMD_STS_BITS 0xf000U
1519 #define DWC_DGCMD_STS_SHIFT 12U
1520
1522 #define DWC_DGCMD_STS_ERROR 15U
1523
1529 #define DWC_EPMAP_RES_NUM_BITS 0x1fU
1530 #define DWC_EPMAP_RES_NUM_SHIFT 0U
1531
1538 typedef struct dwc_usb3_dev_global_regs {
1539
1540 #define DWC_DEV_GLOBAL_REG_OFFSET 0x700U
1541
1544 volatile u32 dcfg;
1545
1548 volatile u32 dctl;
1549
1552 volatile u32 devten;
1553
1556 volatile u32 dsts;
1557
1560 volatile u32 dgcmdpar;
1561
1564 volatile u32 dgcmd;
1565
1567 volatile u32 reserved[2];
1568
1571 volatile u32 dalepena;
1572 } dwc_usb3_dev_global_regs_t;
1573
1574
1575 /****************************************************************************/
1576 /* Device Endpoint Specific Registers */
1577
1584 #define DWC_EPCFG1_INTRNUM_BITS 0x0000003fU
1585 #define DWC_EPCFG1_INTRNUM_SHIFT 0U
1586
1588 #define DWC_EPCFG1_XFER_CMPL_BIT 0x00000100U
1589 #define DWC_EPCFG1_XFER_CMPL_SHIFT 8U
1590
1592 #define DWC_EPCFG1_XFER_IN_PROG_BIT 0x00000200U
1593 #define DWC_EPCFG1_XFER_IN_PROG_SHIFT 9U
1594
1596 #define DWC_EPCFG1_XFER_NRDY_BIT 0x00000400U
1597 #define DWC_EPCFG1_XFER_NRDY_SHIFT 10U
1598
1600 #define DWC_EPCFG1_FIFOXRUN_BIT 0x00000800U
1601 #define DWC_EPCFG1_FIFOXRUN_SHIFT 11U
1602
1604 #define DWC_EPCFG1_SETUP_PNDG_BIT 0x00001000U
1605 #define DWC_EPCFG1_SETUP_PNDG_SHIFT 12U
1606
1608 #define DWC_EPCFG1_EPCMD_CMPL_BIT 0x00002000U
1609 #define DWC_EPCFG1_EPCMD_CMPL_SHIFT 13U
1610
1612 #define DWC_EPCFG1_BINTERVAL_BITS 0x00ff0000U
1613 #define DWC_EPCFG1_BINTERVAL_SHIFT 16U
1614
1616 #define DWC_EPCFG1_STRM_CAP_BIT 0x01000000U
1617 #define DWC_EPCFG1_STRM_CAP_SHIFT 24U
1618
1620 #define DWC_EPCFG1_EP_DIR_BIT 0x02000000U
1621 #define DWC_EPCFG1_EP_DIR_SHIFT 25U
1622
1624 #define DWC_EPCFG1_EP_NUM_BITS 0x3c000000U
1625 #define DWC_EPCFG1_EP_NUM_SHIFT 26
1626
1633 #define DWC_EPCFG0_EPTYPE_BITS 0x00000006U
1634 #define DWC_EPCFG0_EPTYPE_SHIFT 1U
1635
1637 #define DWC_USB3_EP_TYPE_CONTROL 0U
1638 #define DWC_USB3_EP_TYPE_ISOC 1U
1639 #define DWC_USB3_EP_TYPE_BULK 2U
1640 #define DWC_USB3_EP_TYPE_INTR 3U
1641
1643 #define DWC_EPCFG0_MPS_BITS 0x00003ff8U
1644 #define DWC_EPCFG0_MPS_SHIFT 3U
1645
1647 #define DWC_EPCFG0_FLOW_CTRL_STATE_BIT 0x00010000U
1648 #define DWC_EPCFG0_FLOW_CTRL_STATE_SHIFT 16U
1649
1651 #define DWC_EPCFG0_TXFNUM_BITS 0x003e0000U
1652 #define DWC_EPCFG0_TXFNUM_SHIFT 17U
1653
1655 #define DWC_EPCFG0_BRSTSIZ_BITS 0x03c00000U
1656 #define DWC_EPCFG0_BRSTSIZ_SHIFT 22U
1657
1659 #define DWC_EPCFG0_DSNUM_BITS 0x7c000000U
1660 #define DWC_EPCFG0_DSNUM_SHIFT 26U
1661
1663 #define DWC_EPCFG0_IGN_DSNUM_BIT 0x80000000U
1664 #define DWC_EPCFG0_IGN_DSNUM_SHIFT 31U
1665
1667 #define DWC_EPCFG0_CFG_ACTION_BITS 0xc0000000U
1668 #define DWC_EPCFG0_CFG_ACTION_SHIFT 30U
1669
1671 #define DWC_CFG_ACTION_INIT 0U
1672 #define DWC_CFG_ACTION_RESTORE 1U
1673 #define DWC_CFG_ACTION_MODIFY 2U
1674
1682 #define DWC_EPCMD_TYP_BITS 0x0ffU
1683 #define DWC_EPCMD_TYP_SHIFT 0U
1684
1686 #define DWC_EPCMD_SET_EP_CFG 1U
1687 #define DWC_EPCMD_SET_XFER_CFG 2U
1688 #define DWC_EPCMD_GET_EP_STATE 3U
1689 #define DWC_EPCMD_SET_STALL 4U
1690 #define DWC_EPCMD_CLR_STALL 5U
1691 #define DWC_EPCMD_START_XFER 6U
1692 #define DWC_EPCMD_UPDATE_XFER 7U
1693 #define DWC_EPCMD_END_XFER 8U
1694 #define DWC_EPCMD_START_NEW_CFG 9U
1695
1697 #define DWC_EPCMD_IOC_BIT 0x100U
1698 #define DWC_EPCMD_IOC_SHIFT 8U
1699
1701 #define DWC_EPCMD_ACT_BIT 0x400U
1702 #define DWC_EPCMD_ACT_SHIFT 10U
1703
1705 #define DWC_EPCMD_HP_FRM_BIT 0x800U
1706 #define DWC_EPCMD_HP_FRM_SHIFT 11U
1707
1709 #define DWC_EPCMD_CMPL_STS_BITS 0xf000U
1710 #define DWC_EPCMD_CMPL_STS_SHIFT 12U
1711
1713 #define DWC_EPCMD_STR_NUM_OR_UF_BITS 0xffff0000U
1714 #define DWC_EPCMD_STR_NUM_OR_UF_SHIFT 16U
1715
1717 #define DWC_EPCMD_XFER_RSRC_IDX_BITS 0x007f0000U
1718 #define DWC_EPCMD_XFER_RSRC_IDX_SHIFT 16U
1719
1727 typedef struct dwc_usb3_dev_ep_regs {
1728
1729 #define DWC_DEV_OUT_EP_REG_OFFSET 0x800U
1730 #define DWC_DEV_IN_EP_REG_OFFSET 0x810U
1731 #define DWC_EP_REG_OFFSET 0x20U
1732
1735 volatile u32 depcmdpar2;
1736
1739 volatile u32 depcmdpar1;
1740
1743 volatile u32 depcmdpar0;
1744
1748 volatile u32 depcmd;
1749
1752 volatile u32 reserved[4];
1753 } dwc_usb3_dev_ep_regs_t;
1754
1755
1756 /****************************************************************************/
1757 /* DMA Descriptor Specific Structures */
1758
1766 #define DWC_DSCSTS_XFRCNT_BITS 0x00ffffffU
1767 #define DWC_DSCSTS_XFRCNT_SHIFT 0U
1768
1770 #define DWC_DSCSTS_PCM1_BITS 0x03000000U
1771 #define DWC_DSCSTS_PCM1_SHIFT 24U
1772
1774 #define DWC_DSCSTS_TRBRSP_BITS 0xf0000000U
1775 #define DWC_DSCSTS_TRBRSP_SHIFT 28U
1776
1778 #define DWC_TRBRSP_MISSED_ISOC_IN 1U
1779 #define DWC_TRBRSP_SETUP_PEND 2U
1780 #define DWC_TRBRSP_XFER_IN_PROG 4U
1781
1790 #define DWC_DSCCTL_HWO_BIT 0x00000001U
1791 #define DWC_DSCCTL_HWO_SHIFT 0U
1792
1794 #define DWC_DSCCTL_LST_BIT 0x00000002U
1795 #define DWC_DSCCTL_LST_SHIFT 1U
1796
1798 #define DWC_DSCCTL_CHN_BIT 0x00000004U
1799 #define DWC_DSCCTL_CHN_SHIFT 2U
1800
1802 #define DWC_DSCCTL_CSP_BIT 0x00000008U
1803 #define DWC_DSCCTL_CSP_SHIFT 3U
1804
1806 #define DWC_DSCCTL_TRBCTL_BITS 0x000003f0U
1807 #define DWC_DSCCTL_TRBCTL_SHIFT 4U
1808
1810 #define DWC_DSCCTL_TRBCTL_NORMAL 1
1811 #define DWC_DSCCTL_TRBCTL_SETUP 2
1812 #define DWC_DSCCTL_TRBCTL_STATUS_2 3
1813 #define DWC_DSCCTL_TRBCTL_STATUS_3 4
1814 #define DWC_DSCCTL_TRBCTL_CTLDATA_1ST 5
1815 #define DWC_DSCCTL_TRBCTL_ISOC_1ST 6
1816 #define DWC_DSCCTL_TRBCTL_ISOC 7
1817 #define DWC_DSCCTL_TRBCTL_LINK 8
1818
1820 #define DWC_DSCCTL_ISP_BIT 0x00000400U
1821 #define DWC_DSCCTL_ISP_SHIFT 10U
1822 #define DWC_DSCCTL_IMI_BIT DWC_DSCCTL_ISP_BIT
1823 #define DWC_DSCCTL_IMI_SHIFT DWC_DSCCTL_ISP_SHIFT
1824
1826 #define DWC_DSCCTL_IOC_BIT 0x00000800U
1827 #define DWC_DSCCTL_IOC_SHIFT 11U
1828
1830 #define DWC_DSCCTL_STRMID_SOFN_BITS 0x3fffc000U
1831 #define DWC_DSCCTL_STRMID_SOFN_SHIFT 14U
1832
1840 typedef struct dwc_usb3_dma_desc {
1842 u32 bptl;
1843
1845 u32 bpth;
1846
1848 u32 status;
1849
1851 u32 control;
1852 } dwc_usb3_dma_desc_t;
1853
1854 #ifdef SSIC
1855
1856 /* SSIC Registers */
1857 typedef struct dwc_usb3_ssic_regs {
1858
1859 #define DWC_SSIC_REG_OFFSET 0xc40
1860
1861 volatile u32 sctl[16];
1862 volatile u32 sevt[16];
1863 volatile u32 sevten[16];
1864 volatile u32 gscfg;
1865 volatile u32 gsser;
1866 volatile u32 gsdbg;
1867 } dwc_usb3_ssic_regs_t;
1868
1869 #define DWC_SEVTEN_ROM_INIT_CMPLT_EN_BIT 0x00000001U
1870 #define DWC_SEVTEN_ROM_INIT_CMPLT_EN_SHIFT 0U
1871
1872 #define DWC_SEVTEN_LACC_CMPLT_EN_BIT 0x00000002U
1873 #define DWC_SEVTEN_LACC_CMPLT_EN_SHIFT 1U
1874
1875 #define DWC_SEVTEN_RCMD_RES_RCVD_EN_BIT 0x00000004U
1876 #define DWC_SEVTEN_RCMD_RES_RCVD_EN_SHIFT 2U
1877
1878 #define DWC_SEVTEN_RCMD_RES_SENT_EN_BIT 0x00000008U
1879 #define DWC_SEVTEN_RCMD_RES_SENT_EN_SHIFT 3U
1880
1881 #define DWC_SEVTEN_MPHY_ST_CHNGD_EN_BIT 0x00000010U
1882 #define DWC_SEVTEN_MPHY_ST_CHNGD_EN_SHIFT 4U
1883
1884 #define DWC_SEVTEN_OK_STRT_RRAP_EN_BIT 0x00000020U
1885 #define DWC_SEVTEN_OK_STRT_RRAP_EN_SHIFT 5U
1886
1887 #define DWC_SEVTEN_RRAP_ERROR_EN_BIT 0x00000040U
1888 #define DWC_SEVTEN_RRAP_ERROR_EN_SHIFT 6U
1889
1890 #define DWC_SEVT_ROM_INIT_CMPLT_BIT 0x00000001U
1891 #define DWC_SEVT_ROM_INIT_CMPLT_SHIFT 0U
1892
1893 #define DWC_SEVT_LACC_CMPLT_BIT 0x00000002U
1894 #define DWC_SEVT_LACC_CMPLT_SHIFT 1U
1895
1896 #define DWC_SEVT_RCMD_RES_RCVD_BIT 0x00000004U
1897 #define DWC_SEVT_RCMD_RES_RCVD_SHIFT 2U
1898
1899 #define DWC_SEVT_RCMD_RES_SENT_BIT 0x00000008U
1900 #define DWC_SEVT_RCMD_RES_SENT_SHIFT 3U
1901
1902 #define DWC_SEVT_MPHY_ST_CHNG_BIT 0x00000010U
1903 #define DWC_SEVT_MPHY_ST_CHNG_SHIFT 4U
1904
1905 #define DWC_SEVT_OK_STRT_RRAP_BIT 0x00000020U
1906 #define DWC_SEVT_OK_STRT_RRAP_SHIFT 5U
1907
1908 #define DWC_SEVT_RRAP_ERROR_BIT 0x00000040U
1909 #define DWC_SEVT_RRAP_ERROR_SHIFT 6U
1910
1911 #define DWC_SEVT_RACC_RESULT_BITS 0x00000300U
1912 #define DWC_SEVT_RACC_RESULT_SHIFT 8U
1913
1914 #define DWC_SEVT_LACC_RESULT_BIT 0x00000400U
1915 #define DWC_SEVT_LACC_RESULT_SHIFT 10U
1916
1917 #define DWC_SEVT_READ_RCVD_BIT 0x00000800U
1918 #define DWC_SEVT_READ_RCVD_SHIFT 11U
1919
1920 #define DWC_SEVT_RUADDR_RCVD_BITS 0x0000f000U
1921 #define DWC_SEVT_RUADDR_RCVD_SHIFT 12U
1922
1923 #define DWC_SEVT_RLADDR_RCVD_BITS 0x00ff0000U
1924 #define DWC_SEVT_RLADDR_RCVD_SHIFT 16U
1925
1926 #define DWC_SEVT_RDATA_RCVD_BITS 0xff000000U
1927 #define DWC_SEVT_RDATA_RCVD_SHIFT 24U
1928
1929 #define DWC_SCTL_GO_ACC_BIT 0x00000001U
1930 #define DWC_SCTL_GO_ACC_SHIFT 0U
1931
1932 #define DWC_SCTL_RACC_BIT 0x00000002U
1933 #define DWC_SCTL_RACC_SHIFT 1U
1934
1935 #define DWC_SCTL_RD_WR_N_BIT 0x00000004U
1936 #define DWC_SCTL_RD_WR_N_SHIFT 2U
1937
1938 #define DWC_SCTL_BCW_BIT 0x00000008U
1939 #define DWC_SCTL_BCW_SHIFT 3U
1940
1941 #define DWC_SCTL_IN_LN_CFG_BIT 0x00000010U
1942 #define DWC_SCTL_IN_LN_CFG_SHIFT 4U
1943
1944 #define DWC_SCTL_CFG_DONE_BIT 0x00000020U
1945 #define DWC_SCTL_CFG_DEON_SHIFT 5U
1946
1947 #define DWC_SCTL_CBS_ACC_BIT 0x00000040U
1948 #define DWC_SCTL_CBS_ACC_SHIFT 6U
1949
1950 #define DWC_SCTL_RXS_ACC_BIT 0x00000080U
1951 #define DWC_SCTL_RXS_ACC_SHIFT 7U
1952
1953 #define DWC_SCTL_EAID_BITS 0x0000f000U
1954 #define DWC_SCTL_EAID_SHIFT 12U
1955
1956 #define DWC_SCTL_AID_BITS 0x00ff0000U
1957 #define DWC_SCTL_AID_SHIFT 16U
1958
1959 #define DWC_SCTL_ADATA_BITS 0xff000000U
1960 #define DWC_SCTL_ADATA_SHIFT 24U
1961
1962 #endif /* SSIC */
1963
1964 #ifdef __cplusplus
1965 }
1966 #endif
1967
1968 #endif /* _DWC_USB3_REGS_H_ */
dwc_usb3_core_global_regs_t::ghwparams1
volatile u32 ghwparams1
Definition: hw.h:1110
dwc_usb3_core_global_regs_t::gprtbimap_hs_hi
volatile u32 gprtbimap_hs_hi
Definition: hw.h:1166
u32
unsigned int u32
Definition: os_defs.h:41
dwc_usb3_dev_global_regs_t::dcfg
volatile u32 dcfg
Definition: hw.h:1544
dwc_usb3_core_global_regs_t::ggpio
volatile u32 ggpio
Definition: hw.h:1084
dwc_usb3_core_global_regs_t::gdbglspmux
volatile u32 gdbglspmux
Definition: hw.h:1151
dwc_usb3_core_global_regs_t::gdbgepinfo0
volatile u32 gdbgepinfo0
Definition: hw.h:1157
dwc_usb3_core_global_regs_t::ghwparams8
volatile u32 ghwparams8
Definition: hw.h:1208
dwc_usb3_core_global_regs_t::gprtbimap_hi
volatile u32 gprtbimap_hi
Definition: hw.h:1102
dwc_usb3_core_global_regs_t::gbuserraddrlo
volatile u32 gbuserraddrlo
Definition: hw.h:1093
dwc_usb3_dma_desc_t::status
u32 status
Definition: hw.h:1848
dwc_usb3_core_global_regs_t::ghwparams5
volatile u32 ghwparams5
Definition: hw.h:1126
dwc_usb3_dma_desc_t::control
u32 control
Definition: hw.h:1851
dwc_usb3_dev_global_regs_t::dgcmdpar
volatile u32 dgcmdpar
Definition: hw.h:1560
dwc_usb3_dev_global_regs_t::dgcmd
volatile u32 dgcmd
Definition: hw.h:1564
dwc_usb3_core_global_regs_t::ghwparams3
volatile u32 ghwparams3
Definition: hw.h:1118
dwc_usb3_core_global_regs_t::ghwparams2
volatile u32 ghwparams2
Definition: hw.h:1114
geventbuf_data_t
Definition: hw.h:1023
dwc_usb3_core_global_regs_t::gtxthrcfg
volatile u32 gtxthrcfg
Definition: hw.h:1059
dwc_usb3_core_global_regs_t::gsnpsid
volatile u32 gsnpsid
Definition: hw.h:1081
dwc_usb3_core_global_regs_t::gprtbimap_hs_lo
volatile u32 gprtbimap_hs_lo
Definition: hw.h:1163
dwc_usb3_core_global_regs_t::gctl
volatile u32 gctl
Definition: hw.h:1067
geventbuf_data_t::geventadr_lo
volatile u32 geventadr_lo
Definition: hw.h:1025
dwc_usb3_core_global_regs_t::gdbgbmu
volatile u32 gdbgbmu
Definition: hw.h:1148
dwc_usb3_dma_desc_t::bpth
u32 bpth
Definition: hw.h:1845
dwc_usb3_core_global_regs_t::ghwparams4
volatile u32 ghwparams4
Definition: hw.h:1122
dwc_usb3_core_global_regs_t::gdbgltssm
volatile u32 gdbgltssm
Definition: hw.h:1142
dwc_usb3_dev_ep_regs_t::depcmdpar1
volatile u32 depcmdpar1
Definition: hw.h:1739
dwc_usb3_core_global_regs_t::gevten
volatile u32 gevten
Definition: hw.h:1071
geventbuf_data_t::geventadr_hi
volatile u32 geventadr_hi
Definition: hw.h:1028
dwc_usb3_dma_desc_t::bptl
u32 bptl
Definition: hw.h:1842
dwc_usb3_dev_ep_regs_t::depcmd
volatile u32 depcmd
Definition: hw.h:1748
dwc_usb3_core_global_regs_t::gdbglnmcc
volatile u32 gdbglnmcc
Definition: hw.h:1145
dwc_usb3_core_global_regs_t
Definition: hw.h:1045
dwc_usb3_core_global_regs_t::gdbgepinfo1
volatile u32 gdbgepinfo1
Definition: hw.h:1160
dwc_usb3_core_global_regs_t::gsts
volatile u32 gsts
Definition: hw.h:1075
dwc_usb3_dev_ep_regs_t
Definition: hw.h:1727
dwc_usb3_core_global_regs_t::gprtbimap_lo
volatile u32 gprtbimap_lo
Definition: hw.h:1099
dwc_usb3_dma_desc_t
DMA Descriptor structure.
Definition: hw.h:1840
dwc_usb3_core_global_regs_t::gbuserraddrhi
volatile u32 gbuserraddrhi
Definition: hw.h:1096
dwc_usb3_core_global_regs_t::gdbgfifospace
volatile u32 gdbgfifospace
Definition: hw.h:1138
dwc_usb3_core_global_regs_t::guid
volatile u32 guid
Definition: hw.h:1087
dwc_usb3_core_global_regs_t::reserved1
volatile u32 reserved1
Definition: hw.h:1090
dwc_usb3_core_global_regs_t::grxthrcfg
volatile u32 grxthrcfg
Definition: hw.h:1063
dwc_usb3_dev_global_regs_t
Definition: hw.h:1538
geventbuf_data_t::geventsiz
volatile u32 geventsiz
Definition: hw.h:1032
dwc_usb3_dev_ep_regs_t::depcmdpar2
volatile u32 depcmdpar2
Definition: hw.h:1735
geventbuf_data_t::geventcnt
volatile u32 geventcnt
Definition: hw.h:1036
dwc_usb3_core_global_regs_t::ghwparams6
volatile u32 ghwparams6
Definition: hw.h:1130
dwc_usb3_core_global_regs_t::gsbuscfg1
volatile u32 gsbuscfg1
Definition: hw.h:1055
dwc_usb3_core_global_regs_t::gdbglsp
volatile u32 gdbglsp
Definition: hw.h:1154
dwc_usb3_dev_global_regs_t::dalepena
volatile u32 dalepena
Definition: hw.h:1571
dwc_usb3_core_global_regs_t::gprtbimap_fs_hi
volatile u32 gprtbimap_fs_hi
Definition: hw.h:1172
dwc_usb3_core_global_regs_t::gsbuscfg0
volatile u32 gsbuscfg0
Definition: hw.h:1051
dwc_usb3_dev_global_regs_t::devten
volatile u32 devten
Definition: hw.h:1552
dwc_usb3_core_global_regs_t::ghwparams0
volatile u32 ghwparams0
Definition: hw.h:1106
dwc_usb3_dev_ep_regs_t::depcmdpar0
volatile u32 depcmdpar0
Definition: hw.h:1743
dwc_usb3_core_global_regs_t::ghwparams7
volatile u32 ghwparams7
Definition: hw.h:1134
dwc_usb3_dev_global_regs_t::dctl
volatile u32 dctl
Definition: hw.h:1548
dwc_usb3_core_global_regs_t::gprtbimap_fs_lo
volatile u32 gprtbimap_fs_lo
Definition: hw.h:1169
dwc_usb3_core_global_regs_t::reserved0
volatile u32 reserved0
Definition: hw.h:1078
dwc_usb3_dev_global_regs_t::dsts
volatile u32 dsts
Definition: hw.h:1556