AM261x MCU+ SDK: soc.h Source File

| AM261x MCU+ SDK 26.00.00 |

soc.h
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1 /*
2 * Copyright (C) 2021-2023 Texas Instruments Incorporated
3 *
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5 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 *
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13 * documentation and/or other materials provided with the
14 * distribution.
15 *
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef SOC_AM261X_H_
34 #define SOC_AM261X_H_
35
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40
50 #include <kernel/dpl/SystemP.h>
51 #include <drivers/hw_include/cslr_soc.h>
52 #include "soc_xbar.h"
53 #include "soc_rcm.h"
54
60 #define SOC_DOMAIN_ID_MAIN (0U)
61
63 /*Control MMRs partition*/
64 #define MSS_CTRL_PARTITION0 (1)
65 #define TOP_CTRL_PARTITION0 (2)
66 #define CONTROLSS_CTRL_PARTITION0 (3)
67
68 /*Clock and reset MMRs partition*/
69 #define MSS_RCM_PARTITION0 (4)
70 #define TOP_RCM_PARTITION0 (5)
71
72 /*Pinmux MMR*/
73 //#define IOMUX_PARTITION0 (6)
74
75
76 /* define the unlock and lock values for MSS_CTRL, TOP_CTRL, MSS_RCM, TOP_RCM*/
77 #define KICK_LOCK_VAL (0x00000000U)
78 #define KICK0_UNLOCK_VAL (0x01234567U)
79 #define KICK1_UNLOCK_VAL (0x0FEDCBA8U)
80
81 /* defines the Inputs to the SOC_selectAdcExtChXbarAPI for extChXbarIn param */
82 #define ADC0_EXTCHSEL_BIT0 (0U)
83 #define ADC0_EXTCHSEL_BIT1 (1U)
84 #define ADC1_EXTCHSEL_BIT0 (2U)
85 #define ADC1_EXTCHSEL_BIT1 (3U)
86 #define ADC2_EXTCHSEL_BIT0 (4U)
87 #define ADC2_EXTCHSEL_BIT1 (5U)
88
89 #define ADC_EXTCHSELCT_DELAY_3_CYCLES (0U)
90 #define ADC_EXTCHSELCT_DELAY_6_CYCLES (1U)
91
92 #define CMPSS_LOOP_BACK_INH (0U)
93 #define CMPSS_LOOP_BACK_INL (1U)
94
96 static inline int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
97 {
98 int32_t status = (int32_t)-3;
99
100 if ((baseAddr == CSL_MCSPI0_U_BASE) || \
101 (baseAddr == CSL_MCSPI1_U_BASE) || \
102 (baseAddr == CSL_MCSPI2_U_BASE) || \
103 (baseAddr == CSL_MCSPI3_U_BASE) )
104 {
105 status = 0;
106 }
107
108 return status;
109 }
110 #define IS_I2C_BASE_ADDR_VALID(baseAddr) ((baseAddr == CSL_I2C0_U_BASE) || \
111 (baseAddr == CSL_I2C1_U_BASE) || \
112 (baseAddr == CSL_I2C2_U_BASE))
113
115 #define IS_OSPI_BASE_ADDR_VALID(baseAddr) ((baseAddr == CSL_FLASH_CONFIG_REG8_U_BASE) || \
116 (baseAddr == CSL_FSS_UL_128_FSS_OF_UL_OSPI0_OSPI_CFG_VBUSP_VBP2APB_WRAP_OSPI_CFG_VBP_OSPI_FLASH_APB_U_BASE))
117
119 #define IS_OSPI_DATA_BASE_ADDR_VALID(baseAddr) ((baseAddr == CSL_FLASH_DATA_REG0_U_BASE) || \
120 (baseAddr == CSL_FLASH_DATA_REG1_U_BASE) || \
121 (baseAddr == CSL_FSS_UL_128_FSS_OF_UL_DAT_REG0_U_BASE))
122
123
133 int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
134
145 int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
146
154 const char *SOC_getCoreName(uint16_t coreId);
155
161 uint64_t SOC_getSelfCpuClk(void);
162
169 void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
170
177 void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
178
185 void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
186
193 void SOC_setMultipleEpwmTbClk(uint32_t epwmMask, uint32_t enable);
194
200 void SOC_enableAdcReference(uint32_t adcInstance);
201
208 void SOC_enableAdcInternalReference(uint32_t adcInstance, uint32_t enable);
209
216 void SOC_enableAdcReferenceMonitor(uint32_t adcInstance, uint32_t enable);
217
224 uint32_t SOC_getAdcReferenceStatus(uint32_t adcInstance);
225
233 void SOC_enableAdcOsdChannel(uint32_t adcInstance, uint32_t channel, uint32_t enable);
234
262 void SOC_setAdcOsdConfig(uint32_t adcInstance, uint32_t config);
263
270 void SOC_enableAdcGlobalForce(uint32_t adcInstance, uint32_t enable);
271
278 void SOC_adcSocGlobalForce(uint32_t socNumber);
291 void SOC_selectAdcExtChXbar(uint32_t extChXbarOut, uint32_t extChXbarIn);
292
301 void SOC_selextAdcExtChDelay(uint32_t delay);
302
308 void SOC_enableAdcDacLoopback(uint32_t enable);
309
320 void SOC_enableCmpssaDacLoopBack(uint32_t cmpssaInstance, uint32_t dacType, uint32_t enable);
321
332 void SOC_enableCmpssbDacLoopBack(uint32_t cmpssbInstance, uint32_t dacType, uint32_t enable);
333
340 void SOC_setEpwmGroup(uint32_t epwmInstance, uint32_t group);
341
347 void SOC_selectSdfm1Clk0Source(uint8_t source);
348
349
360 void SOC_sdfmClkLoopBackConfig(uint32_t sdfmInstance, uint32_t clkInstance, uint32_t defaultValue);
361
367 void SOC_gateEpwmClock(uint32_t epwmInstance);
368
374 void SOC_ungateEpwmClock(uint32_t epwmInstance);
375
381 void SOC_gateFsitxClock(uint32_t fsitxInstance);
382
388 void SOC_gateFsirxClock(uint32_t fsirxInstance);
389
395 void SOC_gateCmpssaClock(uint32_t cmpssaInstance);
396
402 void SOC_ungateCmpssaClock(uint32_t cmpssaInstance);
403
409 void SOC_gateCmpssbClock(uint32_t cmpssbInstance);
410
416 void SOC_ungateCmpssbClock(uint32_t cmpssbInstance);
417
423 void SOC_gateEcapClock(uint32_t ecapInstance);
424
430 void SOC_ungateEcapClock(uint32_t ecapInstance);
431
437 void SOC_gateEqepClock(uint32_t eqepInstance);
438
444 void SOC_ungateEqepClock(uint32_t eqepInstance);
445
451 void SOC_gateSdfmClock(uint32_t sdfmInstance);
452
458 void SOC_ungateSdfmClock(uint32_t sdfmInstance);
459
463 void SOC_gateDacClock(void);
464
468 void SOC_ungateDacClock(void);
469
475 void SOC_gateAdcClock(uint32_t adcInstance);
476
482 void SOC_ungateAdcClock(uint32_t adcInstance);
483
489 void SOC_gateRdcClock(uint32_t rdcInstance);
490
496 void SOC_gateOttoClock(uint32_t ottoInstance);
497
503 void SOC_ungateOttoClock(uint32_t ottoInstance);
504
510 void SOC_gateSdfmPllClock(uint32_t sdfmInstance);
511
517 void SOC_ungateSdfmPllClock(uint32_t sdfmInstance);
518
524 void SOC_gateFsiPllClock(uint32_t fsiInstance);
525
531 void SOC_generateEpwmReset(uint32_t ePWMInstance);
532
538 void SOC_generateFsiTxReset(uint32_t fsitxInstance);
539
545 void SOC_generateFsiRxReset(uint32_t fsirxInstance);
546
552 void SOC_generateCmpssaReset(uint32_t cmpssaInstance);
553
559 void SOC_generateEcapReset(uint32_t ecapInstance);
560
566 void SOC_generateEqepReset(uint32_t eqepInstance);
567
573 void SOC_generateSdfmReset(uint32_t sdfmInstance);
574
578 void SOC_generateDacReset(void);
579
585 void SOC_generateAdcReset(uint32_t adcInstance);
586
592 void SOC_generateRdcReset(uint32_t rdcInstance);
593
600 void Soc_enableEPWMHalt (uint32_t epwmInstance);
601
608 void Soc_disableEPWMHalt (uint32_t epwmInstance);
609
616 void Soc_enableECAPHalt (uint32_t ecapInstance);
617
624 void Soc_disableECAPHalt (uint32_t ecapInstance);
625
631 void SOC_generateOttoReset(uint32_t ottoInstance);
632
639 void SOC_selectIcssGpiMux(uint8_t pru_instance, uint32_t mask);
640
648 uint64_t SOC_virtToPhy(void *virtAddr);
649
657 void *SOC_phyToVirt(uint64_t phyAddr);
658
664 uint32_t SOC_getFlashDataBaseAddr(void);
665
671 void SOC_sendSoftwareInterrupt(uint16_t coreId);
672
674 static inline int32_t UART_IsBaseAddrValid(uint32_t baseAddr)
675 {
676 int32_t status = (int32_t)-3;
677
678 if(((baseAddr == CSL_UART0_U_BASE) ||
679 (baseAddr == CSL_UART1_U_BASE) ||
680 (baseAddr == CSL_UART2_U_BASE) ||
681 (baseAddr == CSL_UART3_U_BASE) ||
682 (baseAddr == CSL_UART4_U_BASE) ||
683 (baseAddr == CSL_UART5_U_BASE) ))
684 {
685 status = 0;
686 }
687
688 return status;
689 }
690
693 #ifdef __cplusplus
694 }
695 #endif
696
697 #endif
SOC_gateFsitxClock
void SOC_gateFsitxClock(uint32_t fsitxInstance)
Gate the FSI-TX clock.
SOC_enableAdcReferenceMonitor
void SOC_enableAdcReferenceMonitor(uint32_t adcInstance, uint32_t enable)
Enable ADC reference Monitors by writing to Control MMR.
SOC_moduleSetClockFrequency
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
Set module clock to specified frequency.
Soc_disableEPWMHalt
void Soc_disableEPWMHalt(uint32_t epwmInstance)
Halt EPWM with corresponding cPU.
SOC_generateEcapReset
void SOC_generateEcapReset(uint32_t ecapInstance)
Generate ECAP reset.
SOC_ungateSdfmPllClock
void SOC_ungateSdfmPllClock(uint32_t sdfmInstance)
Ungate the SDFM PLL clock.
SOC_gateEcapClock
void SOC_gateEcapClock(uint32_t ecapInstance)
Gate the ECAP clock.
SOC_controlModuleUnlockMMR
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)
Unlock control module partition to allow writes into control MMRs.
SOC_selectAdcExtChXbar
void SOC_selectAdcExtChXbar(uint32_t extChXbarOut, uint32_t extChXbarIn)
Selects the ADC External Channel Select bit for the output from each xbar out.
SOC_selectIcssGpiMux
void SOC_selectIcssGpiMux(uint8_t pru_instance, uint32_t mask)
Selection of ICSS GPI MUX.
SOC_virtToPhy
uint64_t SOC_virtToPhy(void *virtAddr)
SOC Virtual (CPU) to Physical address translation function.
SOC_gateFsirxClock
void SOC_gateFsirxClock(uint32_t fsirxInstance)
Gate the FSI-RX clock.
SOC_gateSdfmPllClock
void SOC_gateSdfmPllClock(uint32_t sdfmInstance)
Gate the SDFM PLL clock.
SOC_gateCmpssaClock
void SOC_gateCmpssaClock(uint32_t cmpssaInstance)
Gate the CMPSS-A clock.
SystemP.h
SOC_gateCmpssbClock
void SOC_gateCmpssbClock(uint32_t cmpssbInstance)
Gate the CMPSS-B clock.
SOC_getFlashDataBaseAddr
uint32_t SOC_getFlashDataBaseAddr(void)
This function gets the SOC mapped data base address of the flash.
SOC_enableCmpssbDacLoopBack
void SOC_enableCmpssbDacLoopBack(uint32_t cmpssbInstance, uint32_t dacType, uint32_t enable)
Enable or disable the CMPSS - DAC Loop Back configuration.
SOC_generateDacReset
void SOC_generateDacReset(void)
Generate DAC reset.
SOC_enableAdcReference
void SOC_enableAdcReference(uint32_t adcInstance)
Enable ADC references by writing to Control MMR.
Soc_enableECAPHalt
void Soc_enableECAPHalt(uint32_t ecapInstance)
Halt ECAP with corresponding cPU.
SOC_gateOttoClock
void SOC_gateOttoClock(uint32_t ottoInstance)
Gate the OTTO clock.
SOC_ungateDacClock
void SOC_ungateDacClock(void)
Ungate the DAC clock.
soc_rcm.h
SOC_setMultipleEpwmTbClk
void SOC_setMultipleEpwmTbClk(uint32_t epwmMask, uint32_t enable)
Enable or disable Multiple ePWM time base clock from Control MMR.
SOC_setAdcOsdConfig
void SOC_setAdcOsdConfig(uint32_t adcInstance, uint32_t config)
Sets the ADC OSD Configuration.
SOC_gateEqepClock
void SOC_gateEqepClock(uint32_t eqepInstance)
Gate the EQEP clock.
SOC_generateAdcReset
void SOC_generateAdcReset(uint32_t adcInstance)
Generate ADC reset.
SOC_generateEpwmReset
void SOC_generateEpwmReset(uint32_t ePWMInstance)
Generate ePWM reset.
SOC_phyToVirt
void * SOC_phyToVirt(uint64_t phyAddr)
Physical to Virtual (CPU) address translation function.
SOC_ungateEcapClock
void SOC_ungateEcapClock(uint32_t ecapInstance)
Ungate the ECAP clock.
SOC_sendSoftwareInterrupt
void SOC_sendSoftwareInterrupt(uint16_t coreId)
Send SOC level software triggered address.
SOC_gateDacClock
void SOC_gateDacClock(void)
Gate the DAC clock.
SOC_getSelfCpuClk
uint64_t SOC_getSelfCpuClk(void)
Get the clock frequency in Hz of the CPU on which the driver is running.
SOC_enableAdcGlobalForce
void SOC_enableAdcGlobalForce(uint32_t adcInstance, uint32_t enable)
Enable or Disable the ADC instnace for Gloabl SW force.
SOC_enableAdcOsdChannel
void SOC_enableAdcOsdChannel(uint32_t adcInstance, uint32_t channel, uint32_t enable)
Enable or disable the OSD circuit over the ADC channels.
SOC_generateRdcReset
void SOC_generateRdcReset(uint32_t rdcInstance)
Generate RDC reset.
SOC_selectSdfm1Clk0Source
void SOC_selectSdfm1Clk0Source(uint8_t source)
Select the SDFM1 CLK0 source.
SOC_selextAdcExtChDelay
void SOC_selextAdcExtChDelay(uint32_t delay)
Mux select to choose delay for ADC Extchsel.
UART_IsBaseAddrValid
static int32_t UART_IsBaseAddrValid(uint32_t baseAddr)
API to validate UART base address.
Definition: soc.h:674
SOC_gateFsiPllClock
void SOC_gateFsiPllClock(uint32_t fsiInstance)
Gate the FSI-TX PLL clock.
SOC_ungateOttoClock
void SOC_ungateOttoClock(uint32_t ottoInstance)
Ungate the OTTO clock.
SOC_ungateCmpssaClock
void SOC_ungateCmpssaClock(uint32_t cmpssaInstance)
Ungate the CMPSS-A clock.
SOC_enableAdcInternalReference
void SOC_enableAdcInternalReference(uint32_t adcInstance, uint32_t enable)
Enables the ADC internal reference.
SOC_gateAdcClock
void SOC_gateAdcClock(uint32_t adcInstance)
Gate the ADC clock.
MCSPI_lld_isBaseAddrValid
static int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
API to validate MCSPI base address.
Definition: soc.h:96
SOC_controlModuleLockMMR
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)
Lock control module partition to prevent writes into control MMRs.
SOC_ungateSdfmClock
void SOC_ungateSdfmClock(uint32_t sdfmInstance)
Ungate the SDFM clock.
SOC_ungateAdcClock
void SOC_ungateAdcClock(uint32_t adcInstance)
ungate the ADC clock
SOC_moduleClockEnable
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)
Enable clock to specified module.
SOC_generateCmpssaReset
void SOC_generateCmpssaReset(uint32_t cmpssaInstance)
Generate CMPSS-A reset.
SOC_generateSdfmReset
void SOC_generateSdfmReset(uint32_t sdfmInstance)
Generate SDFM reset.
SOC_gateEpwmClock
void SOC_gateEpwmClock(uint32_t epwmInstance)
Gate the ePWM clock.
SOC_ungateCmpssbClock
void SOC_ungateCmpssbClock(uint32_t cmpssbInstance)
Ungate the CMPSS-B clock.
Soc_disableECAPHalt
void Soc_disableECAPHalt(uint32_t ecapInstance)
Halt ECAP with corresponding cPU.
SOC_adcSocGlobalForce
void SOC_adcSocGlobalForce(uint32_t socNumber)
Triggers a global force for the SOC in enabled ADCs the ADCs may be enabled by using SOC_enableAdcGlo...
SOC_getCoreName
const char * SOC_getCoreName(uint16_t coreId)
Convert a core ID to a user readable name.
SOC_setEpwmTbClk
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)
Enable or disable ePWM time base clock from Control MMR.
SOC_setEpwmGroup
void SOC_setEpwmGroup(uint32_t epwmInstance, uint32_t group)
Configure the ePWM group.
SOC_ungateEpwmClock
void SOC_ungateEpwmClock(uint32_t epwmInstance)
Ungate the ePWM clock.
SOC_getAdcReferenceStatus
uint32_t SOC_getAdcReferenceStatus(uint32_t adcInstance)
Gets the Reference status.
SOC_ungateEqepClock
void SOC_ungateEqepClock(uint32_t eqepInstance)
Ungate the EQEP clock.
SOC_gateSdfmClock
void SOC_gateSdfmClock(uint32_t sdfmInstance)
Gate the SDFM clock.
SOC_generateFsiRxReset
void SOC_generateFsiRxReset(uint32_t fsirxInstance)
Generate FSI-RX reset.
Soc_enableEPWMHalt
void Soc_enableEPWMHalt(uint32_t epwmInstance)
Halt EPWM with corresponding cPU.
SOC_generateEqepReset
void SOC_generateEqepReset(uint32_t eqepInstance)
Generate EQEP reset.
soc_xbar.h
SOC_generateOttoReset
void SOC_generateOttoReset(uint32_t ottoInstance)
Generate OTTO reset.
SOC_sdfmClkLoopBackConfig
void SOC_sdfmClkLoopBackConfig(uint32_t sdfmInstance, uint32_t clkInstance, uint32_t defaultValue)
Sets the configuraion for the loopback control.
SOC_gateRdcClock
void SOC_gateRdcClock(uint32_t rdcInstance)
Gate the HW_RESOLVER clock.
SOC_generateFsiTxReset
void SOC_generateFsiTxReset(uint32_t fsitxInstance)
Generate FSI-TX reset.
SOC_enableCmpssaDacLoopBack
void SOC_enableCmpssaDacLoopBack(uint32_t cmpssaInstance, uint32_t dacType, uint32_t enable)
Enable or disable the CMPSS - DAC Loop Back configuration.
SOC_enableAdcDacLoopback
void SOC_enableAdcDacLoopback(uint32_t enable)
Enable or Disable the ADC CAL Pin to loopback with DAC.