AM261x MCU+ SDK: APIs for Cache

| AM261x MCU+ SDK 26.00.00 |

Data Structures | Functions | Macros
APIs for Cache
APIs for Driver Porting Layer

## Introduction

For more details and example usage, see Cache

## Data Structures
struct | CacheP_Config
| Cache config structure, this used by SysConfig and not to be used by end-users directly. More...

## Functions
void | CacheP_enable (uint32_t type)
| Cache enable. More...
void | CacheP_disable (uint32_t type)
| Cache disable. More...
uint32_t | CacheP_getEnabled (void)
| Get cache enabled bits. More...
void | CacheP_wbAll (uint32_t type)
| Cache writeback for full cache. More...
void | CacheP_wbInvAll (uint32_t type)
| Cache writeback and invalidate for full cache. More...
void | CacheP_wb (void *addr, uint32_t size, uint32_t type)
| Cache writeback for a specified region. More...
void | CacheP_inv (void *addr, uint32_t size, uint32_t type)
| Cache invalidate for a specified region. More...
void | CacheP_wbInv (void *addr, uint32_t size, uint32_t type)
| Cache writeback and invalidate for a specified region. More...
void | CacheP_init (void)
| Initialize Cache sub-system, called by SysConfig, not to be called by end users. More...

## Macros
#define | CacheP_CACHELINE_ALIGNMENT (128U)
| Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's. More...

## Cache Type
Values defined for CacheP types
#define | CacheP_TYPE_L1P (0x0001u)
#define | CacheP_TYPE_L1D (0x0002u)
#define | CacheP_TYPE_L2P (0x0004u)
#define | CacheP_TYPE_L2D (0x0008u)
#define | CacheP_TYPE_L1 ((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))
#define | CacheP_TYPE_L2 ((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D))
#define | CacheP_TYPE_ALLP ((CacheP_TYPE_L1P)|(CacheP_TYPE_L2P))
#define | CacheP_TYPE_ALLD ((CacheP_TYPE_L1D)|(CacheP_TYPE_L2D))
#define | CacheP_TYPE_ALL (((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))|((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D)))

## Macro Definition Documentation

## ◆ CacheP_CACHELINE_ALIGNMENT

#define CacheP_CACHELINE_ALIGNMENT (128U)

Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's.

## ◆ CacheP_TYPE_L1P

#define CacheP_TYPE_L1P (0x0001u)

L1 program cache

## ◆ CacheP_TYPE_L1D

#define CacheP_TYPE_L1D (0x0002u)

L1 data cache

## ◆ CacheP_TYPE_L2P

#define CacheP_TYPE_L2P (0x0004u)

L2 program cache

## ◆ CacheP_TYPE_L2D

#define CacheP_TYPE_L2D (0x0008u)

L2 data cache

## ◆ CacheP_TYPE_L1

#define CacheP_TYPE_L1 ((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))

All L1 cache's

## ◆ CacheP_TYPE_L2

#define CacheP_TYPE_L2 ((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D))

All L2 cache's

## ◆ CacheP_TYPE_ALLP

#define CacheP_TYPE_ALLP ((CacheP_TYPE_L1P)|(CacheP_TYPE_L2P))

All program cache's

## ◆ CacheP_TYPE_ALLD

#define CacheP_TYPE_ALLD ((CacheP_TYPE_L1D)|(CacheP_TYPE_L2D))

All data cache's

## ◆ CacheP_TYPE_ALL

#define CacheP_TYPE_ALL (((CacheP_TYPE_L1P)|(CacheP_TYPE_L1D))|((CacheP_TYPE_L2P)|(CacheP_TYPE_L2D)))

All cache's

## Function Documentation

## ◆ CacheP_enable()

void CacheP_enable | ( | uint32_t | type | ) |

Cache enable.

Parameters

  type | [in] cache type's to enable R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_disable()

void CacheP_disable | ( | uint32_t | type | ) |

Cache disable.

Parameters

  type | [in] cache type's to disable R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_getEnabled()

uint32_t CacheP_getEnabled | ( | void |  | ) |

Get cache enabled bits.

Returns
  cache type's that are enabled

## ◆ CacheP_wbAll()

void CacheP_wbAll | ( | uint32_t | type | ) |

Cache writeback for full cache.

Parameters

  type | [in] cache type's to writeback R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_wbInvAll()

void CacheP_wbInvAll | ( | uint32_t | type | ) |

Cache writeback and invalidate for full cache.

Parameters

  type | [in] cache type's to writeback and invalidate R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_wb()

void CacheP_wb | ( | void * | addr,
|  | uint32_t | size,
|  | uint32_t | type
| ) |  |

Cache writeback for a specified region.

Parameters

  addr | [in] region address. Recommend to specify address that is cache line aligned
  size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size
  type | [in] cache type's to writeback R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_inv()

void CacheP_inv | ( | void * | addr,
|  | uint32_t | size,
|  | uint32_t | type
| ) |  |

Cache invalidate for a specified region.

Parameters

  addr | [in] region address. Recommend to specify address that is cache line aligned
  size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size
  type | [in] cache type's to invalidate R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_wbInv()

void CacheP_wbInv | ( | void * | addr,
|  | uint32_t | size,
|  | uint32_t | type
| ) |  |

Cache writeback and invalidate for a specified region.

Parameters

  addr | [in] region address. Recommend to specify address that is cache line aligned
  size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size
  type | [in] cache type's to writeback and invalidate R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported

## ◆ CacheP_init()

void CacheP_init | ( | void |  | ) |

Initialize Cache sub-system, called by SysConfig, not to be called by end users.

## Variable Documentation

## ◆ gCacheConfig

const CacheP_Config gCacheConfig
| extern

Externally defined Cache configuration.