sipc_notify_mailbox.h

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/*
 *  Copyright (C) 2022 Texas Instruments Incorporated
 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef SIPC_NOTIFY_MAILBOX_H_
#define SIPC_NOTIFY_MAILBOX_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
 
/* this file has define's and inline function's to program the HW mailbox registers and SW queue structure */
#define MAILBOX_MAX_SW_QUEUE_STRUCT_SIZE      (sizeof(SIPC_SwQueue))
 
/* The HW mailbox only allows to trigger a interrupt on another core,
 * the SIPC Notify needs ability to pass x byte message along with a interrupt
 *
 * Basically this mimics the functionality of HW mailbox with HW FIFO in AM243x SOC
 *
 * This needs to be in sync with the addresses being set for SW queue memory in soc/{soc}/sipc_notify_cfg.c
 *
 * The new queue has two more parameters i.e EleSize = Size of 1 queue element in words
 * Qlength = total length of this Queue */
 
typedef struct SIPC_SwQueue_
{
    volatile uint32_t rdIdx; 
    volatile uint32_t wrIdx; 
    uint16_t EleSize ; 
    uint16_t Qlength ; 
    uint8_t *Qfifo; 
} SIPC_SwQueue;
 
#if defined(__aarch64__) || defined(__arm__)
static inline void asm_dsb_memory(void)
{
    __asm__ __volatile__( "dsb sy" "\n\t": : : "memory");
}
 
static inline void asm_isb_memory(void)
{
    __asm__ __volatile__( "isb" "\n\t": : : "memory");
}
#endif
 
/* Read from SW fifo within a mailbox  */
static inline int32_t SIPC_mailboxRead(SIPC_SwQueue *swQ, uint8_t *Buff)
{
    int32_t status = SystemP_FAILURE;
 
    uint32_t rdIdx = swQ->rdIdx;
    uint32_t wrIdx = swQ->wrIdx;
 
    if((rdIdx < swQ->Qlength) && (wrIdx < swQ->Qlength))
    {
        /* If this condition meets then it means there is something in the fifo*/
        if( rdIdx != wrIdx)
        {
            /* Copy EleSize bytes from Queue memory to the buffer */
            (void)memcpy(Buff, SOC_phyToVirt((uint64_t)(swQ->Qfifo + (swQ->EleSize*rdIdx))),swQ->EleSize);
 
            rdIdx = (rdIdx+1U)%swQ->Qlength;
 
            swQ->rdIdx = rdIdx;
 
            rdIdx = swQ->rdIdx; /* read back to ensure the update has reached the memory */
 
            if (rdIdx < swQ->rdIdx) /*To suppress MISRA warning*/
            {
                /*Do nothing*/
            }
            #if defined(__aarch64__) || defined(__arm__)
            asm_dsb_memory();
            asm_isb_memory();
            #endif
 
            status = SystemP_SUCCESS;
        }
    }
 
    return status;
}
 
/* Write to SW fifo and trigger HW interrupt using HW mailbox */
static inline int32_t SIPC_mailboxWrite(uint32_t mailboxBaseAddr, uint32_t wrIntrBitPos, SIPC_SwQueue *swQ, uint8_t *Buff)
{
    int32_t status = SystemP_FAILURE;
 
    volatile uint32_t rdIdx = swQ->rdIdx;
    volatile uint32_t wrIdx = swQ->wrIdx;
 
    if((rdIdx < swQ->Qlength) && (wrIdx < swQ->Qlength))
    {
        if( ( (wrIdx+1U)%swQ->Qlength ) != rdIdx )
        {
            volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
 
            /* There is some space in the FIFO */
 
            (void)memcpy(SOC_phyToVirt((uint64_t)(swQ->Qfifo + (swQ->EleSize*wrIdx))),Buff,swQ->EleSize);
 
            wrIdx = (wrIdx+1U)%swQ->Qlength;
 
            swQ->wrIdx = wrIdx;
 
            wrIdx = swQ->wrIdx; /* read back to ensure the update has reached the memory */
 
            #if defined(__aarch64__) || defined(__arm__)
            asm_dsb_memory();
            asm_isb_memory();
            #endif
 
            /* Trigger interrupt to other core */
            *addr = (1U << (wrIntrBitPos));
 
            status = SystemP_SUCCESS;
        }
    }
    return status;
}
 
static inline void SIPC_mailboxClearAllInt(uint32_t mailboxBaseAddr)
{
    volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
    *addr = 0x1111111;
}
 
static inline uint32_t SIPC_mailboxGetPendingIntr(uint32_t mailboxBaseAddr)
{
    volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
 
    return *addr;
}
 
static inline void SIPC_mailboxClearPendingIntr(uint32_t mailboxBaseAddr, uint32_t pendingIntr)
{
    volatile uint32_t *addr = ( uint32_t *)mailboxBaseAddr;
    *addr = pendingIntr;
}
 
static inline uint32_t SIPC_mailboxIsPendingIntr(uint32_t pendingIntr, uint32_t coreId)
{
    extern uint32_t gSIPCCoreIntrBitPos[];
 
    uint32_t isPending = 0;
    isPending = pendingIntr & (1U << gSIPCCoreIntrBitPos[coreId]);
    return isPending;
}
 
#ifdef __cplusplus
}
#endif
 
#endif /*SIPC_NOTIFY_MAILBOX_H_*/