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Macros
#define	SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE

#define	DWORD (0x20U)

#define	SDL_MSS_CTRL_MSS_CR5A0_AHB_BASE (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE)

#define	SDL_MSS_CTRL_MSS_CR5B0_AHB_BASE (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE)

#define	SDL_MSS_CTRL_MSS_CR5A0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)

#define	SDL_MSS_CTRL_MSS_CR5B0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)

#define	SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020U)

#define	SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020U)

#define	SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE)

#define	SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE)

#define	SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)

#define	SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)

#define	SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE+0x3FFFU)

#define	SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE+0X1FFCU-DWORD)

#define	SDL_CORE_VBUSP_START (0x50800000U)

#define	SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START+0X1FFCU)

#define	SDL_PERI_VBUSP_START (0x50200000U)

#define	SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START+0X7FFFFCU)

#define	SDL_L2OCRAM_BANK0 (SDL_L2OCRAM_U_BASE)

#define	SDL_L2OCRAM_BANK0_END (SDL_L2OCRAM_U_BASE + 0x7FFFFU)

#define	SDL_L2OCRAM_BANK1 (SDL_L2OCRAM_U_BASE + 0x80000U)

#define	SDL_L2OCRAM_BANK1_END (SDL_L2OCRAM_U_BASE + 0xFFFFFU)

#define	SDL_L2OCRAM_BANK2 (SDL_L2OCRAM_U_BASE + 0x100000U)

#define	SDL_L2OCRAM_BANK2_END (SDL_L2OCRAM_U_BASE + 0x17FFFFU)

#define	SDL_MSS_QSPI_U_BASE (SDL_QSPI0_U_BASE)

#define	SDL_MSS_QSPI_U_SIZE (0x000001D8U)

#define	SDL_MSS_QSPI_U_END (SDL_MSS_QSPI_U_BASE + SDL_MSS_QSPI_U_SIZE)

#define	SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)

#define	SDL_MSS_MCRC_U_SIZE (0x000001E4U)

#define	SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)

#define	SDL_MSS_CR5A_AXI_RD_START (0x35000000U)

#define	SDL_MSS_CR5A_AXI_RD_END (0x350003FFU-8U)

#define	SDL_MSS_CR5A_AXI_WR_START (0x35000000U)

#define	SDL_MSS_CR5A_AXI_WR_END (0x350003FFU-8U)

#define	SDL_MSS_CR5A_AXI_S_START (SDL_R5SS0_CORE0_TCMB_U_BASE)

#define	SDL_MSS_CR5A_AXI_S_END (SDL_R5SS0_CORE0_TCMB_U_BASE + 0xFFFFU)

#define	SDL_MSS_CR5B_AXI_RD_START (0x35000000U)

#define	SDL_MSS_CR5B_AXI_RD_END (0x350003FFU-8U)

#define	SDL_MSS_CR5B_AXI_WR_START (0x35000000U)

#define	SDL_MSS_CR5B_AXI_WR_END (0x350003FFU-8U)

#define	SDL_MSS_CR5B_AXI_S_START (SDL_R5SS0_CORE1_TCMB_U_BASE)

#define	SDL_MSS_CR5B_AXI_S_END (SDL_R5SS0_CORE1_TCMB_U_BASE + 0x7FFFU)

#define	SDL_MSS_CTRL_TPCC_A0_WR_BASE (0x52A40000U)

#define	SDL_MSS_CTRL_TPCC_A0_WR_END (0x52A40400U-8U)

#define	SDL_MSS_CTRL_TPCC_A1_WR_BASE (0x52A60000U)

#define	SDL_MSS_CTRL_TPCC_A1_WR_END (0x52A60400U-8U)

#define	SDL_MSS_CTRL_TPCC_A0_RD_BASE (0x52A40000U)

#define	SDL_MSS_CTRL_TPCC_A0_RD_END (0x52A40400U-8U)

#define	SDL_MSS_CTRL_TPCC_A1_RD_BASE (0x52A60000U)

#define	SDL_MSS_CTRL_TPCC_A1_RD_END (0x52A60400U-8U)

#define	SDL_MSS_VBUSP_BASE (0x35000000U)

#define	SDL_MSS_VBUSP_BASE_END (0x350003FFU-8U)

#define	SDL_MSS_VBUSP_PERI_BASE (0x35000000U)

#define	SDL_MSS_VBUSP_PERI_BASE_END (0x350003FFU-8U)

#define	SDL_MSS_CPSW_BASE (0x52800000U)

#define	SDL_MSS_CPSW_BASE_END (0x52800400U-8U)

#define	SDL_QSPI_U_BASE (0x48200000U)

#define	SDL_QSPI_U_BASE_END (0x482001FFU-8U)

#define	SDL_MCRC_U_BASE (0x35000000U)

#define	SDL_MCRC_U_BASE_END (0x350003FFU-8U)

#define	SDL_SCRP0_U_BASE (0x48000000U)

#define	SDL_SCRP0_U_BASE_END (0x4803FFFFU-8U)

#define	SDL_SCRP1_U_BASE (0x48000000U)

#define	SDL_SCRP1_U_BASE_END (0x4803FFFFU-8U)

#define	SDL_ICSSM0_PDSP0_U_BASE (SDL_ICSSM0_INTERNAL_U_BASE)

#define	SDL_ICSSM0_PDSP0_U_SIZE (0x000000FFU)

#define	SDL_ICSSM0_PDSP0_U_BASE_END (0x48038000U-8U)

#define	SDL_ICSSM0_PDSP1_U_BASE (SDL_ICSSM0_INTERNAL_U_BASE)

#define	SDL_ICSSM0_PDSP1_U_SIZE (0x000000FFU)

#define	SDL_ICSSM0_PDSP1_U_BASE_END (0x48038000U-8U)

#define	SDL_ICSSM0_S_BASE (SDL_ICSSM0_INTERNAL_U_BASE)

#define	SDL_ICSSM0_S_SIZE (0x000000FFU)

#define	SDL_ICSSM0_S_BASE_END (0x48038000U-8U)

#define	SDL_ICSSM1_PDSP0_U_BASE (SDL_ICSS_M_ICSSM_1_PR1_PDSP0_IRAM_U_BASE)

#define	SDL_ICSSM1_PDSP0_U_SIZE (0x000000FFU)

#define	SDL_ICSSM1_PDSP0_U_BASE_END (SDL_ICSS_M_ICSSM_1_PR1_PDSP0_IRAM_U_BASE+SDL_ICSSM1_PDSP0_U_SIZE)

#define	SDL_ICSSM1_PDSP1_U_BASE (SDL_ICSS_M_ICSSM_1_PR1_PDSP1_IRAM_U_BASE)

#define	SDL_ICSSM1_PDSP1_U_SIZE (0x000000FFU)

#define	SDL_ICSSM1_PDSP1_U_BASE_END (SDL_ICSS_M_ICSSM_1_PR1_PDSP1_IRAM_U_BASE+SDL_ICSSM1_PDSP1_U_SIZE)

#define	SDL_ICSSM1_S_BASE (SDL_ICSS_M_ICSSM_1_PR1_CFG_SLV_U_BASE)

#define	SDL_ICSSM1_S_SIZE (0x000000FFU)

#define	SDL_ICSSM1_S_BASE_END (SDL_ICSS_M_ICSSM_1_PR1_CFG_SLV_U_BASE+SDL_ICSSM1_S_SIZE)

#define	SDL_DAP_U_BASE (SDL_TOP_RCM_U_BASE)

#define	SDL_DAP_U_BASE_END (SDL_TOP_RCM_U_BASE + (0x1FFFU-8U))

#define	SDL_GPMC0_CFG_U_BASE_END (SDL_GPMC0_CFG_U_BASE+0X3FCU-DWORD)

#define	SDL_OSPI_U_BASE SDL_FLASH_CONFIG_REG6_U_BASE

#define	SDL_OSPI_U_BASE_END (SDL_FLASH_CONFIG_REG6_U_BASE+0x00001FFU)

#define	SDL_USB_RD_U_BASE (SDL_USB_RAM0_U_BASE)

#define	SDL_USB_RD_U_BASE_END (SDL_USB_RAM0_U_BASE + 0x00007FFCU)

#define	SDL_USB_WR_U_BASE (SDL_USB_RAM0_U_BASE)

#define	SDL_USB_WR_U_BASE_END (SDL_USB_RAM0_U_BASE + 0x00007FFCU)

#define	SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)

#define	SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)

#define	SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)

#define	SDL_ECC_BUS_SAFETY_MSS_READABLE_NODE 1U

#define	SDL_ECC_BUS_SAFETY_MSS_WRITABLE_NODE 0U

#define	SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE 4U

#define	SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE 32U

#define	SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG1_SIZE 16U

#define	SDL_MSS_CTRL_MSS_VBUSP_VBUSM_ERRAGG0_SIZE

#define	SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_1_MASK 0x01800030U

#define	SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_2_MASK 0x00002000U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 0U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 1U

#define	SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 2U

#define	SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 3U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 4U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 5U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 6U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 7U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 8U

#define	SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 9U

#define	SDL_ECC_BUS_SAFETY_DAP 16U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_VBUSM_ERRH 17U

#define	SDL_ECC_BUS_SAFETY_MSS_CPSW 18U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_A 19U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_B 20U

#define	SDL_ECC_BUS_SAFETY_MSS_L2_C 21U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 23U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 24U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 25U

#define	SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 26U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC0_RD 27U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC0_WR 28U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC1_RD 29U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_TPTC1_WR 30U

#define	SDL_ECC_BUS_SAFETY_MSS_ICSSM0_PDSP0 31U

#define	SDL_ECC_BUS_SAFETY_MSS_ICSSM0_PDSP1 32U

#define	SDL_ECC_BUS_SAFETY_MSS_OSPI 33U

#define	SDL_ECC_BUS_SAFETY_MSS_MCRC 34U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_DTHE 35U

#define	SDL_ECC_BUS_SAFETY_MSS_SCRP0 36U

#define	SDL_ECC_BUS_SAFETY_MSS_SCRP1 37U

#define	SDL_ECC_BUS_SAFETY_MSS_HSM_S 38U

#define	SDL_ECC_BUS_SAFETY_MSS_ICSSM0_S 39U

#define	SDL_ECC_BUS_SAFETY_MSS_MBOX 40U

#define	SDL_ECC_BUS_SAFETY_MSS_STM_STIM 41U

#define	SDL_ECC_BUS_SAFETY_MSS_MMC 42U

#define	SDL_ECC_BUS_SAFETY_MSS_GPMC 43U

#define	SDL_ECC_BUS_SAFETY_MSS_ICSSM1_PDSP0 46U

#define	SDL_ECC_BUS_SAFETY_MSS_ICSSM1_PDSP1 47U

#define	SDL_ECC_BUS_SAFETY_MSS_ICSSM1_S 48U

#define	SDL_ECC_BUS_SAFETY_MSS_OSPI1 49U

#define	SDL_ECC_BUS_SAFETY_MSS_USBSS_WR 50U

#define	SDL_ECC_BUS_SAFETY_MSS_USBSS_RD 51U

#define	SDL_ECC_BUS_SAFETY_SEC_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)

#define	SDL_ECC_BUS_SAFETY_SEC_END_NODE (SDL_ECC_BUS_SAFETY_MSS_USBSS_RD)

#define	SDL_ECC_BUS_SAFETY_DED_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)

#define	SDL_ECC_BUS_SAFETY_DED_END_NODE (SDL_ECC_BUS_SAFETY_MSS_USBSS_RD)

Macros