I2S

Instance: I2S
Component: I2S
Base address: 0x400C1000

I2S Audio DMA module supporting formats I2S, LJF, RJF and DSP

TOP:I2S Register Summary

Register Name	Type	Register Width (Bits)	Register Reset	Address Offset	Physical Address
WCLKSRC	RW	32	0x0000 0000	0x0000 0000	0x400C 1000
DMACFG	RW	32	0x0000 0000	0x0000 0004	0x400C 1004
DIRCFG	RW	32	0x0000 0000	0x0000 0008	0x400C 1008
FMTCFG	RW	32	0x0000 0170	0x0000 000C	0x400C 100C
WMASK0	RW	32	0x0000 0003	0x0000 0010	0x400C 1010
WMASK1	RW	32	0x0000 0003	0x0000 0014	0x400C 1014
INPTRNXT	RW	32	0x0000 0000	0x0000 0020	0x400C 1020
INPTR	RW	32	0x0000 0000	0x0000 0024	0x400C 1024
OUTPTRNXT	RW	32	0x0000 0000	0x0000 0028	0x400C 1028
OUTPTR	RW	32	0x0000 0000	0x0000 002C	0x400C 102C
STMPCTL	RW	32	0x0000 0000	0x0000 0034	0x400C 1034
STMPXCNTCAPT0	RO	32	0x0000 0000	0x0000 0038	0x400C 1038
STMPXPER	RO	32	0x0000 0000	0x0000 003C	0x400C 103C
STMPWCNTCAPT0	RO	32	0x0000 0000	0x0000 0040	0x400C 1040
STMPWPER	RW	32	0x0000 0000	0x0000 0044	0x400C 1044
STMPINTRIG	RW	32	0x0000 0000	0x0000 0048	0x400C 1048
STMPOUTTRIG	RW	32	0x0000 0000	0x0000 004C	0x400C 104C
STMPWSET	RW	32	0x0000 0000	0x0000 0050	0x400C 1050
STMPWADD	RW	32	0x0000 0000	0x0000 0054	0x400C 1054
STMPXPERMIN	RW	32	0x0000 FFFF	0x0000 0058	0x400C 1058
STMPWCNT	RO	32	0x0000 0000	0x0000 005C	0x400C 105C
STMPXCNT	RO	32	0x0000 0000	0x0000 0060	0x400C 1060
IRQMASK	RW	32	0x0000 0000	0x0000 0070	0x400C 1070
IRQFLAGS	RO	32	0x0000 0000	0x0000 0074	0x400C 1074
IRQSET	WO	32	0x0000 0000	0x0000 0078	0x400C 1078
IRQCLR	WO	32	0x0000 0000	0x0000 007C	0x400C 107C
MCLKDIV	RW	32	0x0000 0000	0x0000 0080	0x400C 1080
BCLKDIV	RW	32	0x0000 0000	0x0000 0084	0x400C 1084
WCLKDIV	RW	32	0x0000 0000	0x0000 0088	0x400C 1088
CLKCTL	RW	32	0x0000 0000	0x0000 008C	0x400C 108C
DTB	RW	32	0x0000 0000	0x0000 0090	0x400C 1090

TOP:I2S Register Descriptions

TOP:I2S:WCLKSRC

Address Offset	0x0000 0000
Physical Address	0x400C 1000	Instance	0x400C 1000
Description	This register configures the WCLK Source
Type	RW

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

WCLKINV

This field Inverts WCLK source (pad or internal).

Value	ENUM Name	Description
0x0	NOT_INTVERTED	Source is not intverted
0x1	INVERTED	Source is inverted

1:0

WBCLKSRC

This field selects WCLK/BCLK source for I2S.

Value	ENUM Name	Description
0x0	NONE	None ('0')
0x1	EXT	External WCLK generator, from pad
0x2	INT	Internal WCLK generator, from module PRCM
0x3	RESERVED	Not supported. Will give same WCLK as 'NONE' ('00')

0b00

TOP:I2S:DMACFG

Address Offset	0x0000 0004
Physical Address	0x400C 1004	Instance	0x400C 1004
Description	This register configures DMA buffer size
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	ENDFRMIDX	This field defines the length of the DMA buffer. Writing a non-zero value to this register field enables and initializes I2S. Note that before doing so, all other configuration must have been done, and INPTRNXT/OUTPTRNXT must have been loaded.	RW	0x00

TOP:I2S:DIRCFG

Address Offset	0x0000 0008
Physical Address	0x400C 1008	Instance	0x400C 1008
Description	This register configures the direction of data pins(AD0/AD1)
Type	RW

Bits

Field Name

Description

Type

Reset

31:6

RESERVED6

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000

5:4

AD1

The field configures the AD1 data pin direction

Value	ENUM Name	Description
0x0	DIS	Not in use (disabled)
0x1	IN	Input
0x2	OUT	Output
0x3	RESERVED	Reserved

0b00

3:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00

1:0

AD0

The field configures the AD0 data pin direction

Value	ENUM Name	Description
0x0	DIS	Not in use (disabled)
0x1	IN	Input
0x2	OUT	Output
0x3	RESERVED	Reserved

0b00

TOP:I2S:FMTCFG

Address Offset	0x0000 000C
Physical Address	0x400C 100C	Instance	0x400C 100C
Description	This register configures the serial interface format
Type	RW

Bits

Field Name

Description

Type

Reset

31:16

RESERVED16

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x0000

15:8

DATADLY

This field configures the number of BCLK periods between a WCLK edge and MSB of the first word in a phase

Note: When 0, MSB of the next word will be output in the idle period between LSB of the previous word and the start of the next word. Otherwise logical 0 will be output until the data delay has expired.

Value	ENUM Name	Description
0x0	ZERO	Zero BCLK periods - LJF and DSP formats
0x1	ONE	One BCLK periods - I2S and DSP formats
0x2	TWO	Two(Min) BCLK periods - RJF format
0xFF	MAX	Max(255) BCLK periods - RJF format

0x01

MEMLEN32

This register configures the size of each word stored to or loaded from memory

Value	ENUM Name	Description
0x0	DIS	16-bit (one 16 bit access per sample)
0x1	EN	32-bit(one 32-bit access per sample)

SMPLEDGE

This field configures the sample edge/ transfer edge of data (and WCLK) on BCLK

Value	ENUM Name	Description
0x0	NEGEDGE	Data is sampled on the negative edge and clocked out on the positive edge.
0x1	POSEDGE	Data is sampled on the positive edge and clocked out on the negative edge.

DUALPHASE

This field selects between dual-phase or single-phase format

Value	ENUM Name	Description
0x0	SINGLEPHASE	Single-phase: DSP format
0x1	DUALPHASE	Dual-phase: I2S, LJF and RJF formats

4:0

WORDLEN

Number of bits per word (8-24):
In single-phase format, this is the exact number of bits per word.
In dual-phase format, this is the maximum number of bits per word.

Values below 8 and above 24 give undefined behavior. Data written to memory is always aligned to 16 or 24 bits as defined by MEMLEN32. Bit widths that differ from this alignment will either be truncated or zero padded.

0b1 0000

TOP:I2S:WMASK0

Address Offset	0x0000 0010
Physical Address	0x400C 1010	Instance	0x400C 1010
Description	This register configures the word selection dit mask for data pin 0(AD0)
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RW	0x00 0000
7:0	MASK	Bit-mask indicating valid channels in a frame on AD0. In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins.	RW	0x03

TOP:I2S:WMASK1

Address Offset	0x0000 0014
Physical Address	0x400C 1014	Instance	0x400C 1014
Description	This register configures the word selection dit mask for data pin 1(AD1)
Type	RW

Bits	Field Name	Description	Type	Reset
31:8	RESERVED8	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x00 0000
7:0	MASK	Bit-mask indicating valid channels in a frame on AD1. In single-phase mode, each bit represents one channel, starting with LSB for the first word in the frame. A frame can contain up to 8 channels. Channels that are not included in the mask will not be sampled and stored in memory, and clocked out as '0'. In dual-phase mode, only the two LSBs are considered. For a stereo configuration, set both bits. For a mono configuration, set bit 0 only. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated when clocked out. In mono mode, only channel 0 will be sampled and stored to memory, and channel 0 will be repeated in the second phase when clocked out. If all bits are zero, no input words will be stored to memory, and the output data lines will be constant '0'. This can be utilized when PWM debug output is desired without any actively used output pins.	RW	0x03

TOP:I2S:INPTRNXT

Address Offset	0x0000 0020
Physical Address	0x400C 1020	Instance	0x400C 1020
Description	This register configures DMA input buffer next pointer
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	PTR	Pointer to the first byte in the next DMA input buffer. The read value equals the last written value until the currently used DMA input buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.DMAIN. At startup, the value must be written once before and once after configuring the DMA buffer size in DMACFG. The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTRERR will be raised and all input pins will be disabled.			RW	0x0000 0000

TOP:I2S:INPTR

Address Offset	0x0000 0024
Physical Address	0x400C 1024	Instance	0x400C 1024
Description	This register configures the DMA input buffer current pointer
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	PTR	Value of the DMA input buffer pointer currently used by the DMA controller. Incremented by 1 (byte) or 2 (word) for each AHB access.			RO	0x0000 0000

TOP:I2S:OUTPTRNXT

Address Offset	0x0000 0028
Physical Address	0x400C 1028	Instance	0x400C 1028
Description	This register configures DMA output buffer next pointer
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	PTR	Pointer to the first byte in the next DMA output buffer. The read value equals the last written value until the currently used DMA output buffer is completed, and then becomes null when the last written value is transferred to the DMA controller to start on the next buffer. This event is signalized by IRQFLAGS.DMAOUT. At startup, the value must be written once before and once after configuring the DMA buffer size in DMACFG. At this time, the first two samples will be fetched from memory. The next pointer must be written to this register while the DMA function uses the previously written pointer. If not written in time, IRQFLAGS.PTRERR will be raised and all output pins will be disabled.			RW	0x0000 0000

TOP:I2S:OUTPTR

Address Offset	0x0000 002C
Physical Address	0x400C 102C	Instance	0x400C 102C
Description	This register configures DMA output buffer current pointer
Type	RW

Bits	Field Name	Description			Type	Reset
31:0	PTR	Value of the DMA output buffer pointer currently used by the DMA controller Incremented by 1 (byte) or 2 (word) for each AHB access.			RO	0x0000 0000

TOP:I2S:STMPCTL

Address Offset	0x0000 0034
Physical Address	0x400C 1034	Instance	0x400C 1034
Description	This register controls the samplestamp generator.
Type	RW

Bits

Field Name

Description

Type

Reset

31:3

RESERVED3

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000 0000

OUTRDY

This field is low until the output pins are ready to be started by the samplestamp generator. When started (that is STMPOUTTRIG equals the WCLK counter) the bit goes back low.

INRDY

This field is low until the input pins are ready to be started by the samplestamp generator. When started (that is STMPINTRIG equals the WCLK counter) the bit goes back low.

STMPEN

This field configures the samplestamp generator. The samplestamp generator must only be enabled after it has been properly configured.
When cleared, all samplestamp generator counters and capture values are cleared.

Value	ENUM Name	Description
0x0	DIS	Disable the samplestamp generator
0x1	EN	Enable the samplestamp generator

TOP:I2S:STMPXCNTCAPT0

Address Offset	0x0000 0038
Physical Address	0x400C 1038	Instance	0x400C 1038
Description	This register gives the captured XOSC counter value, capture channel 0
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	RESERVED	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	CAPTVALUE	The value of the samplestamp XOSC counter (STMPXCNT.CURRVALUE) last time an event was pulsed. This number corresponds to the number of 24 MHz clock cycles since the last positive edge of the selected WCLK. The value is cleared when STMPCTL.STMPEN = 0. Note: Due to buffering and synchronization, WCLK is delayed by a small number of BCLK periods and clk periods. Note: When calculating the fractional part of the sample stamp, STMPXPER may be less than this bit field.	RO	0x0000

TOP:I2S:STMPXPER

Address Offset	0x0000 003C
Physical Address	0x400C 103C	Instance	0x400C 103C
Description	The register gives the XOSC period value
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	VALUE	The number of 24 MHz clock cycles in the previous WCLK period (that is - the next value of the XOSC counter at the positive WCLK edge, had it not been reset to 0). The value is cleared when STMPCTL.STMPEN = 0.	RO	0x0000

TOP:I2S:STMPWCNTCAPT0

Address Offset	0x0000 0040
Physical Address	0x400C 1040	Instance	0x400C 1040
Description	This register gives the captured WCLK counter value, capture channel 0
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	CAPT_VALUE	The value of the samplestamp WCLK counter (STMPWCNT.CURRVALUE) last time an event was pulsed. This number corresponds to the number of positive WCLK edges since the samplestamp generator was enabled (not taking modification through STMPWADD/STMPWSET into account). The value is cleared when STMPCTL.STMPEN = 0.	RO	0x0000

TOP:I2S:STMPWPER

Address Offset	0x0000 0044
Physical Address	0x400C 1044	Instance	0x400C 1044
Description	This register configures WCLK counter period value
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	VALUE	This field defines when STMPWCNT is to be reset so number of WCLK edges are found for the size of the sample buffer. This is thus a modulo value for the WCLK counter. This number must correspond to the size of the sample buffer used by the system (that is the index of the last sample plus 1).	RW	0x0000

TOP:I2S:STMPINTRIG

Address Offset	0x0000 0048
Physical Address	0x400C 1048	Instance	0x400C 1048
Description	This register configures WCLK counter trigger value for input pins
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	INSTARTWCNT	This field configures the compare value used to start the incoming audio streams. This bit field shall equal the WCLK counter value during the WCLK period in which the first input word(s) are sampled and stored to memory (that is the sample at the start of the very first DMA input buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as inputs in DIRCFG. - DMACFG has been configured for the correct buffer size, and at least 32 BCLK cycle ticks have happened. Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE.	RW	0x0000

TOP:I2S:STMPOUTTRIG

Address Offset	0x0000 004C
Physical Address	0x400C 104C	Instance	0x400C 104C
Description	This register configures WCLK counter trigger value for output pins
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	OUTSTARTWCNT	This field cofnigures the compare value used to start the outgoing audio streams. This bit field must equal the WCLK counter value during the WCLK period in which the first output word(s) read from memory are clocked out (that is the sample at the start of the very first DMA output buffer). The value of this register takes effect when the following conditions are met: - One or more pins are configured as outputs in DIRCFG. - DMACFG has been configured for the correct buffer size, and 32 BCLK cycle ticks have happened. - 2 samples have been preloaded from memory (examine the OUTPTR register if necessary). Note: The memory read access is only performed when required, that is channels 0/1 must be selected in WMASK0/WMASK1. Note: To avoid false triggers, this bit field should be set higher than STMPWPER.VALUE.	RW	0x0000

TOP:I2S:STMPWSET

Address Offset	0x0000 0050
Physical Address	0x400C 1050	Instance	0x400C 1050
Description	This register confiures WCLK counter set operation
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	VALUE	Sets the running WCLK counter equal to the written value.	WO	0x0000

TOP:I2S:STMPWADD

Address Offset	0x0000 0054
Physical Address	0x400C 1054	Instance	0x400C 1054
Description	This register configures WCLK counter add operation
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	VALUEINC	Adds the written value to the running WCLK counter. If a positive edge of WCLK occurs at the same time as the operation, this will be taken into account. To add a negative value, write "STMPWPER.VALUE - value".	WO	0x0000

TOP:I2S:STMPXPERMIN

Address Offset	0x0000 0058
Physical Address	0x400C 1058	Instance	0x400C 1058
Description	This register configures XOSC minimum period value Minimum Value of STMPXPER
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	VALUE	Each time STMPXPER is updated, the value is also loaded into this register, provided that the value is smaller than the current value in this register. When written, the register is reset to 0xFFFF (65535), regardless of the value written. The minimum value can be used to detect extra WCLK pulses (this registers value will be significantly smaller than STMPXPER.VALUE).	RW	0xFFFF

TOP:I2S:STMPWCNT

Address Offset	0x0000 005C
Physical Address	0x400C 105C	Instance	0x400C 105C
Description	This register gives the current value of WLCK counter
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	CURRVALUE	Current value of the WCLK counter	RO	0x0000

TOP:I2S:STMPXCNT

Address Offset	0x0000 0060
Physical Address	0x400C 1060	Instance	0x400C 1060
Description	This register gives the current value XOSC counter
Type	RO

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	CURRVALUE	Current value of the XOSC counter, latched when reading STMPWCNT.	RO	0x0000

TOP:I2S:IRQMASK

Address Offset	0x0000 0070
Physical Address	0x400C 1070	Instance	0x400C 1070
Description	Interrupt Mask Register Selects mask states of the flags in IRQFLAGS that contribute to the I2S_IRQ event.
Type	RW

Bits

Field Name

Description

Type

Reset

31:7

RESERVED7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000

XCNTCAPT

IRQFLAGS.XCNTCAPT interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

DMAIN

IRQFLAGS.DMAIN interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

DMAOUT

IRQFLAGS.DMAOUT interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

WCLKTIMEOUT

IRQFLAGS.WCLKTIMEOUT interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

BUSERR

IRQFLAGS.BUSERR interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

WCLKERR

IRQFLAGS.WCLKERR interrupt mask

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

PTRERR

IRQFLAGS.PTRERR interrupt mask.

Value	ENUM Name	Description
0x0	DIS	Disable the interrupt mask
0x1	EN	Enable the interrupt mask

TOP:I2S:IRQFLAGS

Address Offset	0x0000 0074
Physical Address	0x400C 1074	Instance	0x400C 1074
Description	This registers gives the raw interrupt status
Type	RO

Bits

Field Name

Description

Type

Reset

31:7

RESERVED7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000

XCNTCAPT

This interrupt is set when xcnt counter is captured either by events or software.
Needs to be cleared by software.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

DMAIN

This interrupt is set when condition for this bit field event occurs (auto cleared when input pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register for details.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

DMAOUT

This interrupt is set when condition for this bit field event occurs (auto cleared when output pointer is updated - OUTPTRNXT), see description of OUTPTRNXT register for details

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

WCLKTIMEOUT

Set when the sample stamp generator does not detect a positive WCLK edge for 65535 clk periods. This signalizes that the internal or external BCLK and WCLK generator source has been disabled.

The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLKTIMEOUT).

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

BUSERR

This interrupt set when a DMA operation is not completed in time (that is audio output buffer underflow, or audio input buffer overflow).
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.BUSERR).

Note that DMA initiated transactions to illegal addresses will not trigger an interrupt. The response to such transactions is undefined.

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

WCLKERR

This interrupt is set when:
- An unexpected WCLK edge occurs during the data delay period of a phase. Note unexpected WCLK edges during the word and idle periods of the phase are not detected.
- In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles apart.
- In single-phase mode, when a WCLK pulse occurs before the last channel.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.WCLKERR).

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

PTRERR

This interrupt set when INPTRNXT or OUTPTRNXT has not been loaded with the next block address in time.
This error requires a complete restart since word synchronization has been lost. The bit is sticky and may only be cleared by software (by writing '1' to IRQCLR.PTRERR).

Value	ENUM Name	Description
0x0	CLR	Interrupt did not occur
0x1	SET	Interrupt occured

TOP:I2S:IRQSET

Address Offset	0x0000 0078
Physical Address	0x400C 1078	Instance	0x400C 1078
Description	Interrupt Set Register. This register can be used by software for diagnostics and safety checking purposes.
Type	WO

Bits

Field Name

Description

Type

Reset

31:7

RESERVED7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000

XCNTCAPT

This field sets the interrupt IRQFLAGS.XCNTCAPT (unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

DMAIN

This field sets the interrupt IRQFLAGS.DMAIN (unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

DMAOUT

This field sets the interrupt IRQFLAGS.DMAOUT (unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

WCLKTIMEOUT

This field sets the interrupt IRQFLAGS.WCLKTIMEOUT(unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

BUSERR

1: Sets the interrupt of IRQFLAGS.BUSERR(unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

WCLKERR

This field sets the interrupt IRQFLAGS.WCLKERR(unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

PTRERR

This field sets the interrupt IRQFLAGS.PTRERR(unless a auto clear criteria was given at the same time, in which the set will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	SET	Set interrupt

TOP:I2S:IRQCLR

Address Offset	0x0000 007C
Physical Address	0x400C 107C	Instance	0x400C 107C
Description	Interrupt clear register. This register allows software to clear interrupts.
Type	WO

Bits

Field Name

Description

Type

Reset

31:7

RESERVED7

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b0 0000 0000 0000 0000 0000 0000

XCNTCAPT

Ths field clears the interrupt IRQFLAGS.XCNTCAPT (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

DMAIN

This field clears the interrupt of IRQFLAGS.DMAIN (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

DMAOUT

This field clears the interrupt IRQFLAGS.DMAOUT (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

WCLKTIMEOUT

1: Clears the interrupt of IRQFLAGS.WCLKTIMEOUT (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

BUSERR

This field clears the interrupt IRQFLAGS.BUSERR (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

WCLKERR

This field clears the interrupt IRQFLAGS.WCLKERR (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

PTRERR

This field clears the interrupt IRQFLAGS.PTRERR (unless a set criteria was given at the same time in which the clear will be ignored)

Value	ENUM Name	Description
0x0	NOEFF	Writing 0 has no effect
0x1	CLR	Clear interrupt

TOP:I2S:MCLKDIV

Address Offset	0x0000 0080
Physical Address	0x400C 1080	Instance	0x400C 1080
Description	This field configures MCLK division ratio
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000
9:0	MDIV	An unsigned factor of the division ratio used to generate MCLK [2-1024]: MCLK = MCUCLK/MDIV[Hz] MCUCLK is upto 96MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase.	RW	0b00 0000 0000

TOP:I2S:BCLKDIV

Address Offset	0x0000 0084
Physical Address	0x400C 1084	Instance	0x400C 1084
Description	This field configures BCLK division ratio
Type	RW

Bits	Field Name	Description	Type	Reset
31:10	RESERVED10	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0b00 0000 0000 0000 0000 0000
9:0	BDIV	An unsigned factor of the division ratio used to generate BCLK [2-1024]: BCLK = MCUCLK/BDIV[Hz] MCUCLK can be upto 96MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If BDIV is odd and FMTCFG.SMPLEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase. If BDIV is odd and FMTCFG.SMPLEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase.	RW	0b00 0000 0000

TOP:I2S:WCLKDIV

Address Offset	0x0000 0088
Physical Address	0x400C 1088	Instance	0x400C 1088
Description	This field configures WCLK division ratio
Type	RW

Bits	Field Name	Description	Type	Reset
31:16	RESERVED16	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.	RO	0x0000
15:0	WDIV	If CLKCTL.WCLKPHASE = 0, Single phase. WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV(WDIV[9:0] + 1) [Hz] MCUCLK upto 96MHz. If [CLKCTL.WCLKPHASE.] = 1, Dual phase. Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV(2WDIV[9:0]) [Hz] If [CLKCTL.WCLKPHASE.] = 2, User defined. WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods. WCLK = MCUCLK / (BDIV(WDIV[7:0] + WDIV[15:8]) [Hz]	RW	0x0000

TOP:I2S:CLKCTL

Address Offset	0x0000 008C
Physical Address	0x400C 108C	Instance	0x400C 108C
Description	This register controls internal audio clock
Type	RW

Bits

Field Name

Description

Type

Reset

31:4

RESERVED4

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0x000 0000

MEN

This field configures the MCLK generation

Value	ENUM Name	Description
0x0	DIS	Disable the generation
0x1	EN	Enable the generation

2:1

WCLKPHASE

The field configures how the WCLK division ratio is calculated and used to generate different duty cycles (See WCLKDIV.WDIV)

0b00

WBEN

This field configures WCLK/BCLK generation

Value	ENUM Name	Description
0x0	DIS	Disables the generation
0x1	EN	Enable the generation

TOP:I2S:DTB

Address Offset	0x0000 0090
Physical Address	0x400C 1090	Instance	0x400C 1090
Description	Digital test bus control
Type	RW

Bits

Field Name

Description

Type

Reset

31:2

RESERVED2

Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

0b00 0000 0000 0000 0000 0000 0000 0000

1:0

SEL

The field controls the select of DTB

Value	ENUM Name	Description
0x0	SEL_0	None is selected
0x1	SEL_1	Samplestamp WCNT(16 bits)
0x2	SEL_2	Samplestamp XCNT(16 bits)
0x3	SEL_3	{12{1'b0},aif_words_sampled, aif_word_loaded, aif_output_en, aif_input_en}

0b00