Instance: HSMCRYPTO
Component: HSMCRYPTO
Base address: 0x400F0000
HSM is a Root of Trust Engine that protects valuable assets, such as secret keys for embedded security sensitive applications in a Trusted Execution Environment
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x0000 0000 |
0x0000 0000 |
0x400F 0000 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0000 |
0x400F 0000 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0400 |
0x400F 0400 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 0400 |
0x400F 0400 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 3E00 |
0x400F 3E00 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 3E04 |
0x400F 3E04 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 3E08 |
0x400F 3E08 |
|
|
RO |
32 |
0x0000 001F |
0x0000 3E0C |
0x400F 3E0C |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3E0C |
0x400F 3E0C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3E10 |
0x400F 3E10 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3E10 |
0x400F 3E10 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3E14 |
0x400F 3E14 |
|
|
RO |
32 |
0x0000 0005 |
0x0000 3E18 |
0x400F 3E18 |
|
|
RO |
32 |
0x0140 36C9 |
0x0000 3E1C |
0x400F 3E1C |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F00 |
0x400F 3F00 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3F00 |
0x400F 3F00 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F04 |
0x400F 3F04 |
|
|
WO |
32 |
0x0000 0000 |
0x0000 3F04 |
0x400F 3F04 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F08 |
0x400F 3F08 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 3F0C |
0x400F 3F0C |
|
|
RW |
32 |
0x0000 0202 |
0x0000 3F10 |
0x400F 3F10 |
|
|
RW |
32 |
0x0000 0100 |
0x0000 3FE0 |
0x400F 3FE0 |
|
|
RO |
32 |
0x0020 007C |
0x0000 3FF4 |
0x400F 3FF4 |
|
|
RO |
32 |
0x0390 0312 |
0x0000 3FF8 |
0x400F 3FF8 |
|
|
RO |
32 |
0x0431 7D82 |
0x0000 3FFC |
0x400F 3FFC |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400F 0000 | Instance | 0x400F 0000 |
| Description | Input Mailbox 1 | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | Input Mailbox Memory | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400F 0000 | Instance | 0x400F 0000 |
| Description | Output Mailbox 1 | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | Output Mailbox Memory | WO | 0x0000 0000 | ||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0x400F 0400 | Instance | 0x400F 0400 |
| Description | Input Mailbox 2 | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | Input Mailbox Memory | RO | 0x0000 0000 | ||
| Address Offset | 0x0000 0400 | ||
| Physical Address | 0x400F 0400 | Instance | 0x400F 0400 |
| Description | Output Mailbox 2 | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | MEM | Output Mailbox Memory | WO | 0x0000 0000 | ||
| Address Offset | 0x0000 3E00 | ||
| Physical Address | 0x400F 3E00 | Instance | 0x400F 3E00 |
| Description | AIC Polarity Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Polarity
|
RW | 0 | |||||||||||
| 3 | MB2DONE | Mailbox 2 Token Done Interrupt Polarity
|
RW | 0 | |||||||||||
| 2 | MB2FREE | Mailbox 2 Free Interrupt Polarity
|
RW | 0 | |||||||||||
| 1 | MB1DONE | Mailbox 1 Token done Interrupt Polarity
|
RW | 0 | |||||||||||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Polarity
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 3E04 | ||
| Physical Address | 0x400F 3E04 | Instance | 0x400F 3E04 |
| Description | AIC Type Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Type
|
RW | 0 | |||||||||||
| 3 | MB2DONE | Mailbox 2 Token Done Interrupt Type
|
RW | 0 | |||||||||||
| 2 | MB2FREE | Mailbox 2 Free Interrupt Type
|
RW | 0 | |||||||||||
| 1 | MB1DONE | Mailbox 1 Token Done Interrupt Type
|
RW | 0 | |||||||||||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Type
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 3E08 | ||
| Physical Address | 0x400F 3E08 | Instance | 0x400F 3E08 |
| Description | AIC Enable Control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | |||||||||||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Enable. Indicates one or more mailbox can be linked
|
RW | 0 | |||||||||||
| 3 | MB2DONE | Mailbox 2 Token Done Interrupt Enable
|
RW | 0 | |||||||||||
| 2 | MB2FREE | Mailbox 2 Free Interrupt Enable
|
RW | 0 | |||||||||||
| 1 | MB1DONE | Mailbox 1 Token done Interrupt Enable
|
RW | 0 | |||||||||||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Enable
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 3E0C | ||
| Physical Address | 0x400F 3E0C | Instance | 0x400F 3E0C |
| Description | AIC Raw Source Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Status. Indicates one or more mailbox can be linked | RO | 1 | ||
| 3 | MB2DONE | Mailbox 2 Token Done Interrupt Status | RO | 1 | ||
| 2 | MB2FREE | Mailbox 2 Free Interrupt Status | RO | 1 | ||
| 1 | MB1DONE | Mailbox 1 Token done Interrupt Status | RO | 1 | ||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Status | RO | 1 | ||
| Address Offset | 0x0000 3E0C | ||
| Physical Address | 0x400F 3E0C | Instance | 0x400F 3E0C |
| Description | AIC Enable Set Registers | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||||||||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Enable Set
|
RW | 0 | ||||||||
| 3 | MB2DONE | MailBox 2 Token Done Interrupt Enable Set
|
RW | 0 | ||||||||
| 2 | MB2FREE | MailBox 2 Free Interrupt Enable Set
|
RW | 0 | ||||||||
| 1 | MB1DONE | MailBox 1 Token Done Interrupt Enable Set
|
RW | 0 | ||||||||
| 0 | MB1FREE | MailBox 1 Free Interrupt Enable Set
|
RW | 0 | ||||||||
| Address Offset | 0x0000 3E10 | ||
| Physical Address | 0x400F 3E10 | Instance | 0x400F 3E10 |
| Description | AIC Enabled Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Enable Status | RW | 0 | ||
| 3 | MB2DONE | Mailbox 2 Done Interrupt Enable Status | RW | 0 | ||
| 2 | MB2FREE | MailBox 2 Free Interrupt Enable Status | RW | 0 | ||
| 1 | MB1DONE | MailBox 1 Token Done Interrupt Enable Status | RW | 0 | ||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Enable Status | RW | 0 | ||
| Address Offset | 0x0000 3E10 | ||
| Physical Address | 0x400F 3E10 | Instance | 0x400F 3E10 |
| Description | AIC Acknowledge Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||||||||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Acknowledge
|
RW | 0 | ||||||||
| 3 | MB2DONE | Mailbox 2 Done Interrupt Acknowledge
|
RW | 0 | ||||||||
| 2 | MB2FREE | MailBox 2 Free Interrupt Acknowledge
|
RW | 0 | ||||||||
| 1 | MB1DONE | MailBox 1 Token Done Interrupt Acknowledge
|
RW | 0 | ||||||||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Acknowledge
|
RW | 0 | ||||||||
| Address Offset | 0x0000 3E14 | ||
| Physical Address | 0x400F 3E14 | Instance | 0x400F 3E14 |
| Description | AIC Enable Clear Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||||||||
| 31:5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 | ||||||||
| 4 | MBLNKABL | Mailbox Linkable Interrupt Enable Clear
|
RW | 0 | ||||||||
| 3 | MB2DONE | Mailbox 2 Done Interrupt Enable Clear
|
RW | 0 | ||||||||
| 2 | MB2FREE | MailBox 2 Free Interrupt Enable Clear
|
RW | 0 | ||||||||
| 1 | MB1DONE | MailBox 1 Token Done Interrupt Enable Clear
|
RW | 0 | ||||||||
| 0 | MB1FREE | Mailbox 1 Free Interrupt Enable Clear
|
RW | 0 | ||||||||
| Address Offset | 0x0000 3E18 | ||
| Physical Address | 0x400F 3E18 | Instance | 0x400F 3E18 |
| Description | AIC Options Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8 | MINRMAP | Mini register map. | RO | 0 | ||
| 7 | EXTRMAP | Extended register map. | RO | 0 | ||
| 6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 5:0 | INPUTS | The number of interrupt request inputs. | RO | 0b00 0101 | ||
| Address Offset | 0x0000 3E1C | ||
| Physical Address | 0x400F 3E1C | Instance | 0x400F 3E1C |
| Description | AIC Version Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | MAJORVER | These bits encode the major version number for the AIC module. | RO | 0x1 | ||
| 23:20 | MINORVER | These bits encode the minor version number for the AIC module. | RO | 0x4 | ||
| 19:16 | PATCHLVL | These bits encode the hardware patch level for the AIC module, starting at value 0 on the first release. | RO | 0x0 | ||
| 15:8 | NUMCMPL | These bits simply contain the complement of bits [7:0], used by a driver to ascertain that this version register is indeed read. | RO | 0x36 | ||
| 7:0 | NUM | These bits encode the AIC number. | RO | 0xC9 | ||
| Address Offset | 0x0000 3F00 | ||
| Physical Address | 0x400F 3F00 | Instance | 0x400F 3F00 |
| Description | Mailbox Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
| 7 | MB2AVAIL | Input Mailbox 2 available status
|
RO | 0 | |||||||||||
| 6 | MB2LNKD | Mailbox 2 Link Status
|
RO | 0 | |||||||||||
| 5 | MB2OUT | Output Mailbox 2 Status
|
RO | 0 | |||||||||||
| 4 | MB2IN | Input Mailbox 2 Status
|
RO | 0 | |||||||||||
| 3 | MB1AVAIL | Input Mailbox 1 available status
|
RO | 0 | |||||||||||
| 2 | MB1LNKD | Mailbox 1 Link Status
|
RO | 0 | |||||||||||
| 1 | MB1OUT | Output Mailbox 1 Status
|
RO | 0 | |||||||||||
| 0 | MB1IN | Input Mailbox 1 Status
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 3F00 | ||
| Physical Address | 0x400F 3F00 | Instance | 0x400F 3F00 |
| Description | Mailbox Control Register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||||||||
| 7 | MB2ULNK | Unlink the Mailbox from this host
|
WO | 0 | ||||||||
| 6 | MB2LNK | Link Mailbox to this Host. Host can link to a mailbox only if it is not filled and not linked to another host
|
WO | 0 | ||||||||
| 5 | MB2OUT | The Host for whom the token is in Output Mailbox 1 can clear the status
|
WO | 0 | ||||||||
| 4 | MB2IN | The Host linked to input mailbox 2 can set after placing a token into Input Mailbox 2
|
WO | 0 | ||||||||
| 3 | MB1UNLNK | Unlink the Mailbox from this host
|
WO | 0 | ||||||||
| 2 | MB1LNK | Link Mailbox to this Host. Host can link to a mailbox only if it is not filled and not linked to another host
|
WO | 0 | ||||||||
| 1 | MB1OUT | The Host for whom the token is in Output Mailbox 1 can clear the status
|
WO | 0 | ||||||||
| 0 | MB1IN | The Host linked to input mailbox 1 can set after placing a token into Input Mailbox 1
|
WO | 0 | ||||||||
| Address Offset | 0x0000 3F04 | ||
| Physical Address | 0x400F 3F04 | Instance | 0x400F 3F04 |
| Description | Raw Mailbox Status Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
| 6 | MB2LNKD | Mailbox 2 Linked Raw Status
|
RO | 0 | |||||||||||
| 5 | MB2OUT | Output Mailbox 2 Raw Status
|
RO | 0 | |||||||||||
| 4 | MB2IN | Input Mailbox 2 Raw Status
|
RO | 0 | |||||||||||
| 3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 2 | MB1LNKD | Mailbox 1 Linked Raw Status
|
RO | 0 | |||||||||||
| 1 | MB1OUT | Output Mailbox 1 Raw Status
|
RO | 0 | |||||||||||
| 0 | MB1IN | Input Mailbox 1 Raw Status
|
RO | 0 | |||||||||||
| Address Offset | 0x0000 3F04 | ||
| Physical Address | 0x400F 3F04 | Instance | 0x400F 3F04 |
| Description | Mailbox Reset Register. Only Master Host can write into this register | ||
| Type | WO | ||
| Bits | Field Name | Description | Type | Reset | ||||||||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||||||||
| 7 | MB2ULNK | Set only - Master Host can unlink mbx from current Host by writing 1b here.
|
WO | 0 | ||||||||
| 6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||
| 5 | MB2OUT | Set only - Master Host can clear mbx_out_full bit in MBSTA by writing 1b here.
|
WO | 0 | ||||||||
| 4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||
| 3 | MB1UNLNK | Set only - Master Host can unlink mbx from current Host by writing 1b here.
|
WO | 0 | ||||||||
| 2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||
| 1 | MB1OUT | Set only - Master Host can clear mbx_out_full bit in MBSTA by writing 1b here.
|
WO | 0 | ||||||||
| 0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||
| Address Offset | 0x0000 3F08 | ||
| Physical Address | 0x400F 3F08 | Instance | 0x400F 3F08 |
| Description | Mailbox Status - linked Host IDs Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MB2PACC | 0: Mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Mailbox 2 is only accessible if the Host uses protected access. | RO | 0 | ||
| 6:4 | MB2LNKID | Host cpu_id of the Host linked to the Mailbox 2 | RO | 0b000 | ||
| 3 | MB1PACC | 0: Mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Mailbox 1 is only accessible if the Host uses protected access. | RO | 0 | ||
| 2:0 | MB1LNKID | Host cpu_id of the Host linked to the Mailbox 1 | RO | 0b000 | ||
| Address Offset | 0x0000 3F0C | ||
| Physical Address | 0x400F 3F0C | Instance | 0x400F 3F0C |
| Description | Mailbox Status - output Host IDs Register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
| 7 | MB2PACC | 0: Output mailbox 2 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 2 is only accessible if the Host uses protected access. | RO | 0 | ||
| 6:4 | MB2ID | Host cpu_id of the Host allowed to read a result from the Mailbox 2 | RO | 0b000 | ||
| 3 | MB1PACC | 0: Output mailbox 1 can be accessed by the Host using protected or non-protected access. 1: Output mailbox 1 is only accessible if the Host uses protected access. | RO | 0 | ||
| 2:0 | MB1ID | HostID of the Host allowed to read a result from the Mailbox 1 | RO | 0b000 | ||
| Address Offset | 0x0000 3F10 | ||
| Physical Address | 0x400F 3F10 | Instance | 0x400F 3F10 |
| Description | Host or Mailbox lockout control Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
| 15:8 | MB2LKOUT | Bit map indicates which Hosts are blocked from accessing mailbox 2 | RW | 0x02 | ||
| 7:0 | MB1LKOUT | Bit map indicates which Hosts are blocked from accessing mailbox 1 | RW | 0x02 | ||
| Address Offset | 0x0000 3FE0 | ||
| Physical Address | 0x400F 3FE0 | Instance | 0x400F 3FE0 |
| Description | Module Status Register | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31 | FATAL | Set if fatal error occured | RO | 0 | ||
| 30:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
| 23 | FWACPTD | Set if firmware is to be executed | RO | 0 | ||
| 22 | FWCKDONE | Set if firmware checks complete | RO | 0 | ||
| 21:11 | RESERVED11 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 | ||
| 10 | CRC24ERR | Set if CRC on ProgramROM is fails | RO | 0 | ||
| 9 | CRC24OK | Set if CRC on ProgramROM is passes | RO | 0 | ||
| 8 | CRC24BSY | Set if CRC on ProgramROM is busy | RO | 1 | ||
| 7:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 | ||
| Address Offset | 0x0000 3FF4 | ||
| Physical Address | 0x400F 3FF4 | Instance | 0x400F 3FF4 |
| Description | Configured options(2) | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:26 | RESERVED26 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 | ||
| 25 | ADDCE10 | An additional crypto engine is available in hardware as custom engine10 | RO | 0 | ||
| 24 | ADDCE9 | An additional crypto engine is available in hardware as custom engine9 | RO | 0 | ||
| 23 | ADDCE8 | An additional crypto engine is available in hardware as custom engine8 | RO | 0 | ||
| 22 | ADDCE7 | An additional crypto engine is available in hardware as custom engine7 | RO | 0 | ||
| 21 | ADDCE6 | An additional crypto engine is available in hardware as custom engine6 | RO | 1 | ||
| 20 | ADDCE5 | An additional crypto engine is available in hardware as custom engine5 | RO | 0 | ||
| 19 | ADDCE4 | An additional crypto engine is available in hardware as custom engine4 | RO | 0 | ||
| 18 | ADDCE3 | An additional crypto engine is available in hardware as custom engine3 | RO | 0 | ||
| 17 | ADDCE2 | An additional crypto engine is available in hardware as custom engine2 | RO | 0 | ||
| 16 | ADDCE1 | An additional crypto engine is available in hardware as custom engine1 | RO | 0 | ||
| 15:13 | RESERVED13 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 | ||
| 12 | BUSIFC | Bus interface type, 0b = 32-bit AHB, 1b = 32-bit AXI | RO | 0 | ||
| 11:10 | RESERVED10 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| 9 | PROGRAM | Downloadable RAM based firmware program memory. | RO | 0 | ||
| 8 | CCPU | C capable local cpu available | RO | 0 | ||
| 7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 6 | CRNG | CRNG engine available | RO | 1 | ||
| 5 | PKCP | PKCP Engine available | RO | 1 | ||
| 4 | CRC | CRC calculation available | RO | 1 | ||
| 3 | TRNG | TRNG engine available | RO | 1 | ||
| 2 | SHA | SHA1/SHA2 combination core available | RO | 1 | ||
| 1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
| 0 | DESAES | DES/AES combination crypto core available | RO | 0 | ||
| Address Offset | 0x0000 3FF8 | ||
| Physical Address | 0x400F 3FF8 | Instance | 0x400F 3FF8 |
| Description | Configured options(1) | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||||||||
| 31:24 | SHOST | Bits to indicate which of the 8 possible HOSTID codes on the bus interface are active Hosts with secure access | RO | 0x03 | |||||||||||||||||
| 23 | MYIDSEC | Indicates the current protection bit values of the Host actually reading the register | RO | 1 | |||||||||||||||||
| 22:20 | MYID | Host ID code for the Host that is reading this register | RO | 0b001 | |||||||||||||||||
| 19 | RESERVED19 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||
| 18:16 | MASTERID | Value of the HOSTID that designates the Master Host | RO | 0b000 | |||||||||||||||||
| 15:8 | HOSTID | Bits to indicate which of the 8 possible HOSTID codes on the bus interface are active | RO | 0x03 | |||||||||||||||||
| 7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||
| 5:4 | MBSIZE | Mailbox pair Size
|
RO | 0b01 | |||||||||||||||||
| 3:0 | NMB | Number of Input/Output Mailbox pairs | RO | 0x2 | |||||||||||||||||
| Address Offset | 0x0000 3FFC | ||
| Physical Address | 0x400F 3FFC | Instance | 0x400F 3FFC |
| Description | Version register | ||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:28 | RESERVED28 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
| 27:24 | MAJOR | Major Version release number for this module | RO | 0x4 | ||
| 23:20 | MINOR | Minor Version release number for this module | RO | 0x3 | ||
| 19:16 | PATCHLVL | Hardware Patch Level for this module | RO | 0x1 | ||
| 15:8 | NUMCMPL | Bit by Bit compliment of IP Number | RO | 0x7D | ||
| 7:0 | NUM | IP number | RO | 0x82 | ||
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