Structure type to access the System Control Block (SCB). More...

#include <core_armv81mml.h>

Data Fields
__IM uint32_t	CPUID

__IOM uint32_t	ICSR

__IOM uint32_t	VTOR

__IOM uint32_t	AIRCR

__IOM uint32_t	SCR

__IOM uint32_t	CCR

__IOM uint8_t	SHPR [12U]

__IOM uint32_t	SHCSR

__IOM uint32_t	CFSR

__IOM uint32_t	HFSR

__IOM uint32_t	DFSR

__IOM uint32_t	MMFAR

__IOM uint32_t	BFAR

__IOM uint32_t	AFSR

__IM uint32_t	ID_PFR [2U]

__IM uint32_t	ID_DFR

__IM uint32_t	ID_AFR

__IM uint32_t	ID_MMFR [4U]

__IM uint32_t	ID_ISAR [6U]

__IM uint32_t	CLIDR

__IM uint32_t	CTR

__IM uint32_t	CCSIDR

__IOM uint32_t	CSSELR

__IOM uint32_t	CPACR

__IOM uint32_t	NSACR

uint32_t	RESERVED7 [21U]

__IOM uint32_t	SFSR

__IOM uint32_t	SFAR

uint32_t	RESERVED3 [69U]

__OM uint32_t	STIR

__IOM uint32_t	RFSR

uint32_t	RESERVED4 [14U]

__IM uint32_t	MVFR0

__IM uint32_t	MVFR1

__IM uint32_t	MVFR2

uint32_t	RESERVED5 [1U]

__OM uint32_t	ICIALLU

uint32_t	RESERVED6 [1U]

__OM uint32_t	ICIMVAU

__OM uint32_t	DCIMVAC

__OM uint32_t	DCISW

__OM uint32_t	DCCMVAU

__OM uint32_t	DCCMVAC

__OM uint32_t	DCCSW

__OM uint32_t	DCCIMVAC

__OM uint32_t	DCCISW

__OM uint32_t	BPIALL

uint32_t	RESERVED0

uint32_t	RESERVED1

__IOM uint32_t	SHPR [2U]

Detailed Description

Structure type to access the System Control Block (SCB).

Field Documentation

§ CPUID

__IM uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

§ ICSR

__IOM uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

§ VTOR

__IOM uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

§ AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

§ SCR

__IOM uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

§ CCR

__IOM uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

§ SHPR [1/2]

__IOM uint8_t SCB_Type::SHPR

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

§ SHCSR

__IOM uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

§ CFSR

__IOM uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

§ HFSR

__IOM uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

§ DFSR

__IOM uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

§ MMFAR

__IOM uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

§ BFAR

__IOM uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

§ AFSR

__IOM uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

§ ID_PFR

__IM uint32_t SCB_Type::ID_PFR

Offset: 0x040 (R/ ) Processor Feature Register

§ ID_DFR

__IM uint32_t SCB_Type::ID_DFR

Offset: 0x048 (R/ ) Debug Feature Register

§ ID_AFR

__IM uint32_t SCB_Type::ID_AFR

Offset: 0x04C (R/ ) Auxiliary Feature Register

§ ID_MMFR

__IM uint32_t SCB_Type::ID_MMFR

Offset: 0x050 (R/ ) Memory Model Feature Register

§ ID_ISAR

__IM uint32_t SCB_Type::ID_ISAR

Offset: 0x060 (R/ ) Instruction Set Attributes Register

§ CLIDR

__IM uint32_t SCB_Type::CLIDR

Offset: 0x078 (R/ ) Cache Level ID register

§ CTR

__IM uint32_t SCB_Type::CTR

Offset: 0x07C (R/ ) Cache Type register

§ CCSIDR

__IM uint32_t SCB_Type::CCSIDR

Offset: 0x080 (R/ ) Cache Size ID Register

§ CSSELR

__IOM uint32_t SCB_Type::CSSELR

Offset: 0x084 (R/W) Cache Size Selection Register

§ CPACR

__IOM uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

§ NSACR

__IOM uint32_t SCB_Type::NSACR

Offset: 0x08C (R/W) Non-Secure Access Control Register

§ RESERVED7

uint32_t SCB_Type::RESERVED7

§ SFSR

__IOM uint32_t SCB_Type::SFSR

Offset: 0x0E4 (R/W) Secure Fault Status Register

§ SFAR

__IOM uint32_t SCB_Type::SFAR

Offset: 0x0E8 (R/W) Secure Fault Address Register

§ RESERVED3

uint32_t SCB_Type::RESERVED3

§ STIR

__OM uint32_t SCB_Type::STIR

Offset: 0x200 ( /W) Software Triggered Interrupt Register

§ RFSR

__IOM uint32_t SCB_Type::RFSR

Offset: 0x204 (R/W) RAS Fault Status Register

§ RESERVED4

uint32_t SCB_Type::RESERVED4

§ MVFR0

__IM uint32_t SCB_Type::MVFR0

Offset: 0x240 (R/ ) Media and VFP Feature Register 0

§ MVFR1

__IM uint32_t SCB_Type::MVFR1

Offset: 0x244 (R/ ) Media and VFP Feature Register 1

§ MVFR2

__IM uint32_t SCB_Type::MVFR2

Offset: 0x248 (R/ ) Media and VFP Feature Register 2

§ RESERVED5

uint32_t SCB_Type::RESERVED5

§ ICIALLU

__OM uint32_t SCB_Type::ICIALLU

Offset: 0x250 ( /W) I-Cache Invalidate All to PoU

§ RESERVED6

uint32_t SCB_Type::RESERVED6

§ ICIMVAU

__OM uint32_t SCB_Type::ICIMVAU

Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU

§ DCIMVAC

__OM uint32_t SCB_Type::DCIMVAC

Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC

§ DCISW

__OM uint32_t SCB_Type::DCISW

Offset: 0x260 ( /W) D-Cache Invalidate by Set-way

§ DCCMVAU

__OM uint32_t SCB_Type::DCCMVAU

Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU

§ DCCMVAC

__OM uint32_t SCB_Type::DCCMVAC

Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC

§ DCCSW

__OM uint32_t SCB_Type::DCCSW

Offset: 0x26C ( /W) D-Cache Clean by Set-way

§ DCCIMVAC

__OM uint32_t SCB_Type::DCCIMVAC

Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC

§ DCCISW

__OM uint32_t SCB_Type::DCCISW

Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way

§ BPIALL

__OM uint32_t SCB_Type::BPIALL

Offset: 0x278 ( /W) Branch Predictor Invalidate All

§ RESERVED0

uint32_t SCB_Type::RESERVED0

§ RESERVED1

uint32_t SCB_Type::RESERVED1

§ SHPR [2/2]

__IOM uint32_t SCB_Type::SHPR[2U]

Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

The documentation for this struct was generated from the following files:

Data Fields