pmu_armv8.h File Reference

Go to the source code of this file.

Macros
#define	ARM_PMU_ARMV8_H
#define	ARM_PMU_SW_INCR   0x0000
	PMU Events. More...
#define	ARM_PMU_L1I_CACHE_REFILL   0x0001
#define	ARM_PMU_L1D_CACHE_REFILL   0x0003
#define	ARM_PMU_L1D_CACHE   0x0004
#define	ARM_PMU_LD_RETIRED   0x0006
#define	ARM_PMU_ST_RETIRED   0x0007
#define	ARM_PMU_INST_RETIRED   0x0008
#define	ARM_PMU_EXC_TAKEN   0x0009
#define	ARM_PMU_EXC_RETURN   0x000A
#define	ARM_PMU_PC_WRITE_RETIRED   0x000C
#define	ARM_PMU_BR_IMMED_RETIRED   0x000D
#define	ARM_PMU_BR_RETURN_RETIRED   0x000E
#define	ARM_PMU_UNALIGNED_LDST_RETIRED   0x000F
#define	ARM_PMU_BR_MIS_PRED   0x0010
#define	ARM_PMU_CPU_CYCLES   0x0011
#define	ARM_PMU_BR_PRED   0x0012
#define	ARM_PMU_MEM_ACCESS   0x0013
#define	ARM_PMU_L1I_CACHE   0x0014
#define	ARM_PMU_L1D_CACHE_WB   0x0015
#define	ARM_PMU_L2D_CACHE   0x0016
#define	ARM_PMU_L2D_CACHE_REFILL   0x0017
#define	ARM_PMU_L2D_CACHE_WB   0x0018
#define	ARM_PMU_BUS_ACCESS   0x0019
#define	ARM_PMU_MEMORY_ERROR   0x001A
#define	ARM_PMU_INST_SPEC   0x001B
#define	ARM_PMU_BUS_CYCLES   0x001D
#define	ARM_PMU_CHAIN   0x001E
#define	ARM_PMU_L1D_CACHE_ALLOCATE   0x001F
#define	ARM_PMU_L2D_CACHE_ALLOCATE   0x0020
#define	ARM_PMU_BR_RETIRED   0x0021
#define	ARM_PMU_BR_MIS_PRED_RETIRED   0x0022
#define	ARM_PMU_STALL_FRONTEND   0x0023
#define	ARM_PMU_STALL_BACKEND   0x0024
#define	ARM_PMU_L2I_CACHE   0x0027
#define	ARM_PMU_L2I_CACHE_REFILL   0x0028
#define	ARM_PMU_L3D_CACHE_ALLOCATE   0x0029
#define	ARM_PMU_L3D_CACHE_REFILL   0x002A
#define	ARM_PMU_L3D_CACHE   0x002B
#define	ARM_PMU_L3D_CACHE_WB   0x002C
#define	ARM_PMU_LL_CACHE_RD   0x0036
#define	ARM_PMU_LL_CACHE_MISS_RD   0x0037
#define	ARM_PMU_L1D_CACHE_MISS_RD   0x0039
#define	ARM_PMU_OP_COMPLETE   0x003A
#define	ARM_PMU_OP_SPEC   0x003B
#define	ARM_PMU_STALL   0x003C
#define	ARM_PMU_STALL_OP_BACKEND   0x003D
#define	ARM_PMU_STALL_OP_FRONTEND   0x003E
#define	ARM_PMU_STALL_OP   0x003F
#define	ARM_PMU_L1D_CACHE_RD   0x0040
#define	ARM_PMU_LE_RETIRED   0x0100
#define	ARM_PMU_LE_SPEC   0x0101
#define	ARM_PMU_BF_RETIRED   0x0104
#define	ARM_PMU_BF_SPEC   0x0105
#define	ARM_PMU_LE_CANCEL   0x0108
#define	ARM_PMU_BF_CANCEL   0x0109
#define	ARM_PMU_SE_CALL_S   0x0114
#define	ARM_PMU_SE_CALL_NS   0x0115
#define	ARM_PMU_DWT_CMPMATCH0   0x0118
#define	ARM_PMU_DWT_CMPMATCH1   0x0119
#define	ARM_PMU_DWT_CMPMATCH2   0x011A
#define	ARM_PMU_DWT_CMPMATCH3   0x011B
#define	ARM_PMU_MVE_INST_RETIRED   0x0200
#define	ARM_PMU_MVE_INST_SPEC   0x0201
#define	ARM_PMU_MVE_FP_RETIRED   0x0204
#define	ARM_PMU_MVE_FP_SPEC   0x0205
#define	ARM_PMU_MVE_FP_HP_RETIRED   0x0208
#define	ARM_PMU_MVE_FP_HP_SPEC   0x0209
#define	ARM_PMU_MVE_FP_SP_RETIRED   0x020C
#define	ARM_PMU_MVE_FP_SP_SPEC   0x020D
#define	ARM_PMU_MVE_FP_MAC_RETIRED   0x0214
#define	ARM_PMU_MVE_FP_MAC_SPEC   0x0215
#define	ARM_PMU_MVE_INT_RETIRED   0x0224
#define	ARM_PMU_MVE_INT_SPEC   0x0225
#define	ARM_PMU_MVE_INT_MAC_RETIRED   0x0228
#define	ARM_PMU_MVE_INT_MAC_SPEC   0x0229
#define	ARM_PMU_MVE_LDST_RETIRED   0x0238
#define	ARM_PMU_MVE_LDST_SPEC   0x0239
#define	ARM_PMU_MVE_LD_RETIRED   0x023C
#define	ARM_PMU_MVE_LD_SPEC   0x023D
#define	ARM_PMU_MVE_ST_RETIRED   0x0240
#define	ARM_PMU_MVE_ST_SPEC   0x0241
#define	ARM_PMU_MVE_LDST_CONTIG_RETIRED   0x0244
#define	ARM_PMU_MVE_LDST_CONTIG_SPEC   0x0245
#define	ARM_PMU_MVE_LD_CONTIG_RETIRED   0x0248
#define	ARM_PMU_MVE_LD_CONTIG_SPEC   0x0249
#define	ARM_PMU_MVE_ST_CONTIG_RETIRED   0x024C
#define	ARM_PMU_MVE_ST_CONTIG_SPEC   0x024D
#define	ARM_PMU_MVE_LDST_NONCONTIG_RETIRED   0x0250
#define	ARM_PMU_MVE_LDST_NONCONTIG_SPEC   0x0251
#define	ARM_PMU_MVE_LD_NONCONTIG_RETIRED   0x0254
#define	ARM_PMU_MVE_LD_NONCONTIG_SPEC   0x0255
#define	ARM_PMU_MVE_ST_NONCONTIG_RETIRED   0x0258
#define	ARM_PMU_MVE_ST_NONCONTIG_SPEC   0x0259
#define	ARM_PMU_MVE_LDST_MULTI_RETIRED   0x025C
#define	ARM_PMU_MVE_LDST_MULTI_SPEC   0x025D
#define	ARM_PMU_MVE_LD_MULTI_RETIRED   0x0260
#define	ARM_PMU_MVE_LD_MULTI_SPEC   0x0261
#define	ARM_PMU_MVE_ST_MULTI_RETIRED   0x0261
#define	ARM_PMU_MVE_ST_MULTI_SPEC   0x0265
#define	ARM_PMU_MVE_LDST_UNALIGNED_RETIRED   0x028C
#define	ARM_PMU_MVE_LDST_UNALIGNED_SPEC   0x028D
#define	ARM_PMU_MVE_LD_UNALIGNED_RETIRED   0x0290
#define	ARM_PMU_MVE_LD_UNALIGNED_SPEC   0x0291
#define	ARM_PMU_MVE_ST_UNALIGNED_RETIRED   0x0294
#define	ARM_PMU_MVE_ST_UNALIGNED_SPEC   0x0295
#define	ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED   0x0298
#define	ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC   0x0299
#define	ARM_PMU_MVE_VREDUCE_RETIRED   0x02A0
#define	ARM_PMU_MVE_VREDUCE_SPEC   0x02A1
#define	ARM_PMU_MVE_VREDUCE_FP_RETIRED   0x02A4
#define	ARM_PMU_MVE_VREDUCE_FP_SPEC   0x02A5
#define	ARM_PMU_MVE_VREDUCE_INT_RETIRED   0x02A8
#define	ARM_PMU_MVE_VREDUCE_INT_SPEC   0x02A9
#define	ARM_PMU_MVE_PRED   0x02B8
#define	ARM_PMU_MVE_STALL   0x02CC
#define	ARM_PMU_MVE_STALL_RESOURCE   0x02CD
#define	ARM_PMU_MVE_STALL_RESOURCE_MEM   0x02CE
#define	ARM_PMU_MVE_STALL_RESOURCE_FP   0x02CF
#define	ARM_PMU_MVE_STALL_RESOURCE_INT   0x02D0
#define	ARM_PMU_MVE_STALL_BREAK   0x02D3
#define	ARM_PMU_MVE_STALL_DEPENDENCY   0x02D4
#define	ARM_PMU_ITCM_ACCESS   0x4007
#define	ARM_PMU_DTCM_ACCESS   0x4008
#define	ARM_PMU_TRCEXTOUT0   0x4010
#define	ARM_PMU_TRCEXTOUT1   0x4011
#define	ARM_PMU_TRCEXTOUT2   0x4012
#define	ARM_PMU_TRCEXTOUT3   0x4013
#define	ARM_PMU_CTI_TRIGOUT4   0x4018
#define	ARM_PMU_CTI_TRIGOUT5   0x4019
#define	ARM_PMU_CTI_TRIGOUT6   0x401A
#define	ARM_PMU_CTI_TRIGOUT7   0x401B

Functions
__STATIC_INLINE void	ARM_PMU_Enable (void)
	PMU Functions. More...
__STATIC_INLINE void	ARM_PMU_Disable (void)
	Disable the PMU. More...
__STATIC_INLINE void	ARM_PMU_Set_EVTYPER (uint32_t num, uint32_t type)
	Set event to count for PMU eventer counter. More...
__STATIC_INLINE void	ARM_PMU_CYCCNT_Reset (void)
	Reset cycle counter. More...
__STATIC_INLINE void	ARM_PMU_EVCNTR_ALL_Reset (void)
	Reset all event counters. More...
__STATIC_INLINE void	ARM_PMU_CNTR_Enable (uint32_t mask)
	Enable counters. More...
__STATIC_INLINE void	ARM_PMU_CNTR_Disable (uint32_t mask)
	Disable counters. More...
__STATIC_INLINE uint32_t	ARM_PMU_Get_CCNTR (void)
	Read cycle counter. More...
__STATIC_INLINE uint32_t	ARM_PMU_Get_EVCNTR (uint32_t num)
	Read event counter. More...
__STATIC_INLINE uint32_t	ARM_PMU_Get_CNTR_OVS (void)
	Read counter overflow status. More...
__STATIC_INLINE void	ARM_PMU_Set_CNTR_OVS (uint32_t mask)
	Clear counter overflow status. More...
__STATIC_INLINE void	ARM_PMU_Set_CNTR_IRQ_Enable (uint32_t mask)
	Enable counter overflow interrupt request. More...
__STATIC_INLINE void	ARM_PMU_Set_CNTR_IRQ_Disable (uint32_t mask)
	Disable counter overflow interrupt request. More...
__STATIC_INLINE void	ARM_PMU_CNTR_Increment (uint32_t mask)
	Software increment event counter. More...

Macro Definition Documentation

ARM_PMU_ARMV8_H

#define ARM_PMU_ARMV8_H

ARM_PMU_SW_INCR

#define ARM_PMU_SW_INCR   0x0000

PMU Events.

Note

See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.Software update to the PMU_SWINC register, architecturally executed and condition code check pass

ARM_PMU_L1I_CACHE_REFILL

#define ARM_PMU_L1I_CACHE_REFILL   0x0001

L1 I-Cache refill

ARM_PMU_L1D_CACHE_REFILL

#define ARM_PMU_L1D_CACHE_REFILL   0x0003

L1 D-Cache refill

ARM_PMU_L1D_CACHE

#define ARM_PMU_L1D_CACHE   0x0004

L1 D-Cache access

ARM_PMU_LD_RETIRED

#define ARM_PMU_LD_RETIRED   0x0006

Memory-reading instruction architecturally executed and condition code check pass

ARM_PMU_ST_RETIRED

#define ARM_PMU_ST_RETIRED   0x0007

Memory-writing instruction architecturally executed and condition code check pass

ARM_PMU_INST_RETIRED

#define ARM_PMU_INST_RETIRED   0x0008

Instruction architecturally executed

ARM_PMU_EXC_TAKEN

#define ARM_PMU_EXC_TAKEN   0x0009

Exception entry

ARM_PMU_EXC_RETURN

#define ARM_PMU_EXC_RETURN   0x000A

Exception return instruction architecturally executed and the condition code check pass

ARM_PMU_PC_WRITE_RETIRED

#define ARM_PMU_PC_WRITE_RETIRED   0x000C

Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass

ARM_PMU_BR_IMMED_RETIRED

#define ARM_PMU_BR_IMMED_RETIRED   0x000D

Immediate branch architecturally executed

ARM_PMU_BR_RETURN_RETIRED

#define ARM_PMU_BR_RETURN_RETIRED   0x000E

Function return instruction architecturally executed and the condition code check pass

ARM_PMU_UNALIGNED_LDST_RETIRED

#define ARM_PMU_UNALIGNED_LDST_RETIRED   0x000F

Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass

ARM_PMU_BR_MIS_PRED

#define ARM_PMU_BR_MIS_PRED   0x0010

Mispredicted or not predicted branch speculatively executed

ARM_PMU_CPU_CYCLES

#define ARM_PMU_CPU_CYCLES   0x0011

Cycle

ARM_PMU_BR_PRED

#define ARM_PMU_BR_PRED   0x0012

Predictable branch speculatively executed

ARM_PMU_MEM_ACCESS

#define ARM_PMU_MEM_ACCESS   0x0013

Data memory access

ARM_PMU_L1I_CACHE

#define ARM_PMU_L1I_CACHE   0x0014

Level 1 instruction cache access

ARM_PMU_L1D_CACHE_WB

#define ARM_PMU_L1D_CACHE_WB   0x0015

Level 1 data cache write-back

ARM_PMU_L2D_CACHE

#define ARM_PMU_L2D_CACHE   0x0016

Level 2 data cache access

ARM_PMU_L2D_CACHE_REFILL

#define ARM_PMU_L2D_CACHE_REFILL   0x0017

Level 2 data cache refill

ARM_PMU_L2D_CACHE_WB

#define ARM_PMU_L2D_CACHE_WB   0x0018

Level 2 data cache write-back

ARM_PMU_BUS_ACCESS

#define ARM_PMU_BUS_ACCESS   0x0019

Bus access

ARM_PMU_MEMORY_ERROR

#define ARM_PMU_MEMORY_ERROR   0x001A

Local memory error

ARM_PMU_INST_SPEC

#define ARM_PMU_INST_SPEC   0x001B

Instruction speculatively executed

ARM_PMU_BUS_CYCLES

#define ARM_PMU_BUS_CYCLES   0x001D

Bus cycles

ARM_PMU_CHAIN

#define ARM_PMU_CHAIN   0x001E

For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE

ARM_PMU_L1D_CACHE_ALLOCATE

#define ARM_PMU_L1D_CACHE_ALLOCATE   0x001F

Level 1 data cache allocation without refill

ARM_PMU_L2D_CACHE_ALLOCATE

#define ARM_PMU_L2D_CACHE_ALLOCATE   0x0020

Level 2 data cache allocation without refill

ARM_PMU_BR_RETIRED

#define ARM_PMU_BR_RETIRED   0x0021

Branch instruction architecturally executed

ARM_PMU_BR_MIS_PRED_RETIRED

#define ARM_PMU_BR_MIS_PRED_RETIRED   0x0022

Mispredicted branch instruction architecturally executed

ARM_PMU_STALL_FRONTEND

#define ARM_PMU_STALL_FRONTEND   0x0023

No operation issued because of the frontend

ARM_PMU_STALL_BACKEND

#define ARM_PMU_STALL_BACKEND   0x0024

No operation issued because of the backend

ARM_PMU_L2I_CACHE

#define ARM_PMU_L2I_CACHE   0x0027

Level 2 instruction cache access

ARM_PMU_L2I_CACHE_REFILL

#define ARM_PMU_L2I_CACHE_REFILL   0x0028

Level 2 instruction cache refill

ARM_PMU_L3D_CACHE_ALLOCATE

#define ARM_PMU_L3D_CACHE_ALLOCATE   0x0029

Level 3 data cache allocation without refill

ARM_PMU_L3D_CACHE_REFILL

#define ARM_PMU_L3D_CACHE_REFILL   0x002A

Level 3 data cache refill

ARM_PMU_L3D_CACHE

#define ARM_PMU_L3D_CACHE   0x002B

Level 3 data cache access

ARM_PMU_L3D_CACHE_WB

#define ARM_PMU_L3D_CACHE_WB   0x002C

Level 3 data cache write-back

ARM_PMU_LL_CACHE_RD

#define ARM_PMU_LL_CACHE_RD   0x0036

Last level data cache read

ARM_PMU_LL_CACHE_MISS_RD

#define ARM_PMU_LL_CACHE_MISS_RD   0x0037

Last level data cache read miss

ARM_PMU_L1D_CACHE_MISS_RD

#define ARM_PMU_L1D_CACHE_MISS_RD   0x0039

Level 1 data cache read miss

ARM_PMU_OP_COMPLETE

#define ARM_PMU_OP_COMPLETE   0x003A

Operation retired

ARM_PMU_OP_SPEC

#define ARM_PMU_OP_SPEC   0x003B

Operation speculatively executed

ARM_PMU_STALL

#define ARM_PMU_STALL   0x003C

Stall cycle for instruction or operation not sent for execution

ARM_PMU_STALL_OP_BACKEND

#define ARM_PMU_STALL_OP_BACKEND   0x003D

Stall cycle for instruction or operation not sent for execution due to pipeline backend

ARM_PMU_STALL_OP_FRONTEND

#define ARM_PMU_STALL_OP_FRONTEND   0x003E

Stall cycle for instruction or operation not sent for execution due to pipeline frontend

ARM_PMU_STALL_OP

#define ARM_PMU_STALL_OP   0x003F

Instruction or operation slots not occupied each cycle

ARM_PMU_L1D_CACHE_RD

#define ARM_PMU_L1D_CACHE_RD   0x0040

Level 1 data cache read

ARM_PMU_LE_RETIRED

#define ARM_PMU_LE_RETIRED   0x0100

Loop end instruction executed

ARM_PMU_LE_SPEC

#define ARM_PMU_LE_SPEC   0x0101

Loop end instruction speculatively executed

ARM_PMU_BF_RETIRED

#define ARM_PMU_BF_RETIRED   0x0104

Branch future instruction architecturally executed and condition code check pass

ARM_PMU_BF_SPEC

#define ARM_PMU_BF_SPEC   0x0105

Branch future instruction speculatively executed and condition code check pass

ARM_PMU_LE_CANCEL

#define ARM_PMU_LE_CANCEL   0x0108

Loop end instruction not taken

ARM_PMU_BF_CANCEL

#define ARM_PMU_BF_CANCEL   0x0109

Branch future instruction not taken

ARM_PMU_SE_CALL_S

#define ARM_PMU_SE_CALL_S   0x0114

Call to secure function, resulting in Security state change

ARM_PMU_SE_CALL_NS

#define ARM_PMU_SE_CALL_NS   0x0115

Call to non-secure function, resulting in Security state change

ARM_PMU_DWT_CMPMATCH0

#define ARM_PMU_DWT_CMPMATCH0   0x0118

DWT comparator 0 match

ARM_PMU_DWT_CMPMATCH1

#define ARM_PMU_DWT_CMPMATCH1   0x0119

DWT comparator 1 match

ARM_PMU_DWT_CMPMATCH2

#define ARM_PMU_DWT_CMPMATCH2   0x011A

DWT comparator 2 match

ARM_PMU_DWT_CMPMATCH3

#define ARM_PMU_DWT_CMPMATCH3   0x011B

DWT comparator 3 match

ARM_PMU_MVE_INST_RETIRED

#define ARM_PMU_MVE_INST_RETIRED   0x0200

MVE instruction architecturally executed

ARM_PMU_MVE_INST_SPEC

#define ARM_PMU_MVE_INST_SPEC   0x0201

MVE instruction speculatively executed

ARM_PMU_MVE_FP_RETIRED

#define ARM_PMU_MVE_FP_RETIRED   0x0204

MVE floating-point instruction architecturally executed

ARM_PMU_MVE_FP_SPEC

#define ARM_PMU_MVE_FP_SPEC   0x0205

MVE floating-point instruction speculatively executed

ARM_PMU_MVE_FP_HP_RETIRED

#define ARM_PMU_MVE_FP_HP_RETIRED   0x0208

MVE half-precision floating-point instruction architecturally executed

ARM_PMU_MVE_FP_HP_SPEC

#define ARM_PMU_MVE_FP_HP_SPEC   0x0209

MVE half-precision floating-point instruction speculatively executed

ARM_PMU_MVE_FP_SP_RETIRED

#define ARM_PMU_MVE_FP_SP_RETIRED   0x020C

MVE single-precision floating-point instruction architecturally executed

ARM_PMU_MVE_FP_SP_SPEC

#define ARM_PMU_MVE_FP_SP_SPEC   0x020D

MVE single-precision floating-point instruction speculatively executed

ARM_PMU_MVE_FP_MAC_RETIRED

#define ARM_PMU_MVE_FP_MAC_RETIRED   0x0214

MVE floating-point multiply or multiply-accumulate instruction architecturally executed

ARM_PMU_MVE_FP_MAC_SPEC

#define ARM_PMU_MVE_FP_MAC_SPEC   0x0215

MVE floating-point multiply or multiply-accumulate instruction speculatively executed

ARM_PMU_MVE_INT_RETIRED

#define ARM_PMU_MVE_INT_RETIRED   0x0224

MVE integer instruction architecturally executed

ARM_PMU_MVE_INT_SPEC

#define ARM_PMU_MVE_INT_SPEC   0x0225

MVE integer instruction speculatively executed

ARM_PMU_MVE_INT_MAC_RETIRED

#define ARM_PMU_MVE_INT_MAC_RETIRED   0x0228

MVE multiply or multiply-accumulate instruction architecturally executed

ARM_PMU_MVE_INT_MAC_SPEC

#define ARM_PMU_MVE_INT_MAC_SPEC   0x0229

MVE multiply or multiply-accumulate instruction speculatively executed

ARM_PMU_MVE_LDST_RETIRED

#define ARM_PMU_MVE_LDST_RETIRED   0x0238

MVE load or store instruction architecturally executed

ARM_PMU_MVE_LDST_SPEC

#define ARM_PMU_MVE_LDST_SPEC   0x0239

MVE load or store instruction speculatively executed

ARM_PMU_MVE_LD_RETIRED

#define ARM_PMU_MVE_LD_RETIRED   0x023C

MVE load instruction architecturally executed

ARM_PMU_MVE_LD_SPEC

#define ARM_PMU_MVE_LD_SPEC   0x023D

MVE load instruction speculatively executed

ARM_PMU_MVE_ST_RETIRED

#define ARM_PMU_MVE_ST_RETIRED   0x0240

MVE store instruction architecturally executed

ARM_PMU_MVE_ST_SPEC

#define ARM_PMU_MVE_ST_SPEC   0x0241

MVE store instruction speculatively executed

ARM_PMU_MVE_LDST_CONTIG_RETIRED

#define ARM_PMU_MVE_LDST_CONTIG_RETIRED   0x0244

MVE contiguous load or store instruction architecturally executed

ARM_PMU_MVE_LDST_CONTIG_SPEC

#define ARM_PMU_MVE_LDST_CONTIG_SPEC   0x0245

MVE contiguous load or store instruction speculatively executed

ARM_PMU_MVE_LD_CONTIG_RETIRED

#define ARM_PMU_MVE_LD_CONTIG_RETIRED   0x0248

MVE contiguous load instruction architecturally executed

ARM_PMU_MVE_LD_CONTIG_SPEC

#define ARM_PMU_MVE_LD_CONTIG_SPEC   0x0249

MVE contiguous load instruction speculatively executed

ARM_PMU_MVE_ST_CONTIG_RETIRED

#define ARM_PMU_MVE_ST_CONTIG_RETIRED   0x024C

MVE contiguous store instruction architecturally executed

ARM_PMU_MVE_ST_CONTIG_SPEC

#define ARM_PMU_MVE_ST_CONTIG_SPEC   0x024D

MVE contiguous store instruction speculatively executed

ARM_PMU_MVE_LDST_NONCONTIG_RETIRED

#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED   0x0250

MVE non-contiguous load or store instruction architecturally executed

ARM_PMU_MVE_LDST_NONCONTIG_SPEC

#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC   0x0251

MVE non-contiguous load or store instruction speculatively executed

ARM_PMU_MVE_LD_NONCONTIG_RETIRED

#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED   0x0254

MVE non-contiguous load instruction architecturally executed

ARM_PMU_MVE_LD_NONCONTIG_SPEC

#define ARM_PMU_MVE_LD_NONCONTIG_SPEC   0x0255

MVE non-contiguous load instruction speculatively executed

ARM_PMU_MVE_ST_NONCONTIG_RETIRED

#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED   0x0258

MVE non-contiguous store instruction architecturally executed

ARM_PMU_MVE_ST_NONCONTIG_SPEC

#define ARM_PMU_MVE_ST_NONCONTIG_SPEC   0x0259

MVE non-contiguous store instruction speculatively executed

ARM_PMU_MVE_LDST_MULTI_RETIRED

#define ARM_PMU_MVE_LDST_MULTI_RETIRED   0x025C

MVE memory instruction targeting multiple registers architecturally executed

ARM_PMU_MVE_LDST_MULTI_SPEC

#define ARM_PMU_MVE_LDST_MULTI_SPEC   0x025D

MVE memory instruction targeting multiple registers speculatively executed

ARM_PMU_MVE_LD_MULTI_RETIRED

#define ARM_PMU_MVE_LD_MULTI_RETIRED   0x0260

MVE memory load instruction targeting multiple registers architecturally executed

ARM_PMU_MVE_LD_MULTI_SPEC

#define ARM_PMU_MVE_LD_MULTI_SPEC   0x0261

MVE memory load instruction targeting multiple registers speculatively executed

ARM_PMU_MVE_ST_MULTI_RETIRED

#define ARM_PMU_MVE_ST_MULTI_RETIRED   0x0261

MVE memory store instruction targeting multiple registers architecturally executed

ARM_PMU_MVE_ST_MULTI_SPEC

#define ARM_PMU_MVE_ST_MULTI_SPEC   0x0265

MVE memory store instruction targeting multiple registers speculatively executed

ARM_PMU_MVE_LDST_UNALIGNED_RETIRED

#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED   0x028C

MVE unaligned memory load or store instruction architecturally executed

ARM_PMU_MVE_LDST_UNALIGNED_SPEC

#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC   0x028D

MVE unaligned memory load or store instruction speculatively executed

ARM_PMU_MVE_LD_UNALIGNED_RETIRED

#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED   0x0290

MVE unaligned load instruction architecturally executed

ARM_PMU_MVE_LD_UNALIGNED_SPEC

#define ARM_PMU_MVE_LD_UNALIGNED_SPEC   0x0291

MVE unaligned load instruction speculatively executed

ARM_PMU_MVE_ST_UNALIGNED_RETIRED

#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED   0x0294

MVE unaligned store instruction architecturally executed

ARM_PMU_MVE_ST_UNALIGNED_SPEC

#define ARM_PMU_MVE_ST_UNALIGNED_SPEC   0x0295

MVE unaligned store instruction speculatively executed

ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED

#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED   0x0298

MVE unaligned noncontiguous load or store instruction architecturally executed

ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC

#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC   0x0299

MVE unaligned noncontiguous load or store instruction speculatively executed

ARM_PMU_MVE_VREDUCE_RETIRED

#define ARM_PMU_MVE_VREDUCE_RETIRED   0x02A0

MVE vector reduction instruction architecturally executed

ARM_PMU_MVE_VREDUCE_SPEC

#define ARM_PMU_MVE_VREDUCE_SPEC   0x02A1

MVE vector reduction instruction speculatively executed

ARM_PMU_MVE_VREDUCE_FP_RETIRED

#define ARM_PMU_MVE_VREDUCE_FP_RETIRED   0x02A4

MVE floating-point vector reduction instruction architecturally executed

ARM_PMU_MVE_VREDUCE_FP_SPEC

#define ARM_PMU_MVE_VREDUCE_FP_SPEC   0x02A5

MVE floating-point vector reduction instruction speculatively executed

ARM_PMU_MVE_VREDUCE_INT_RETIRED

#define ARM_PMU_MVE_VREDUCE_INT_RETIRED   0x02A8

MVE integer vector reduction instruction architecturally executed

ARM_PMU_MVE_VREDUCE_INT_SPEC

#define ARM_PMU_MVE_VREDUCE_INT_SPEC   0x02A9

MVE integer vector reduction instruction speculatively executed

ARM_PMU_MVE_PRED

#define ARM_PMU_MVE_PRED   0x02B8

Cycles where one or more predicated beats architecturally executed

ARM_PMU_MVE_STALL

#define ARM_PMU_MVE_STALL   0x02CC

Stall cycles caused by an MVE instruction

ARM_PMU_MVE_STALL_RESOURCE

#define ARM_PMU_MVE_STALL_RESOURCE   0x02CD

Stall cycles caused by an MVE instruction because of resource conflicts

ARM_PMU_MVE_STALL_RESOURCE_MEM

#define ARM_PMU_MVE_STALL_RESOURCE_MEM   0x02CE

Stall cycles caused by an MVE instruction because of memory resource conflicts

ARM_PMU_MVE_STALL_RESOURCE_FP

#define ARM_PMU_MVE_STALL_RESOURCE_FP   0x02CF

Stall cycles caused by an MVE instruction because of floating-point resource conflicts

ARM_PMU_MVE_STALL_RESOURCE_INT

#define ARM_PMU_MVE_STALL_RESOURCE_INT   0x02D0

Stall cycles caused by an MVE instruction because of integer resource conflicts

ARM_PMU_MVE_STALL_BREAK

#define ARM_PMU_MVE_STALL_BREAK   0x02D3

Stall cycles caused by an MVE chain break

ARM_PMU_MVE_STALL_DEPENDENCY

#define ARM_PMU_MVE_STALL_DEPENDENCY   0x02D4

Stall cycles caused by MVE register dependency

ARM_PMU_ITCM_ACCESS

#define ARM_PMU_ITCM_ACCESS   0x4007

Instruction TCM access

ARM_PMU_DTCM_ACCESS

#define ARM_PMU_DTCM_ACCESS   0x4008

Data TCM access

ARM_PMU_TRCEXTOUT0

#define ARM_PMU_TRCEXTOUT0   0x4010

ETM external output 0

ARM_PMU_TRCEXTOUT1

#define ARM_PMU_TRCEXTOUT1   0x4011

ETM external output 1

ARM_PMU_TRCEXTOUT2

#define ARM_PMU_TRCEXTOUT2   0x4012

ETM external output 2

ARM_PMU_TRCEXTOUT3

#define ARM_PMU_TRCEXTOUT3   0x4013

ETM external output 3

ARM_PMU_CTI_TRIGOUT4

#define ARM_PMU_CTI_TRIGOUT4   0x4018

Cross-trigger Interface output trigger 4

ARM_PMU_CTI_TRIGOUT5

#define ARM_PMU_CTI_TRIGOUT5   0x4019

Cross-trigger Interface output trigger 5

ARM_PMU_CTI_TRIGOUT6

#define ARM_PMU_CTI_TRIGOUT6   0x401A

Cross-trigger Interface output trigger 6

ARM_PMU_CTI_TRIGOUT7

#define ARM_PMU_CTI_TRIGOUT7   0x401B

Cross-trigger Interface output trigger 7

Function Documentation

ARM_PMU_Enable()

__STATIC_INLINE void ARM_PMU_Enable

(

void

)

PMU Functions.

Enable the PMU.

ARM_PMU_Disable()

__STATIC_INLINE void ARM_PMU_Disable

(

void

)

Disable the PMU.

ARM_PMU_Set_EVTYPER()

__STATIC_INLINE void ARM_PMU_Set_EVTYPER	(	uint32_t	num,
		uint32_t	type
	)

Set event to count for PMU eventer counter.

Parameters

[in]	num	Event counter (0-30) to configure
[in]	type	Event to count

ARM_PMU_CYCCNT_Reset()

__STATIC_INLINE void ARM_PMU_CYCCNT_Reset

(

void

)

Reset cycle counter.

ARM_PMU_EVCNTR_ALL_Reset()

__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset

(

void

)

Reset all event counters.

ARM_PMU_CNTR_Enable()

__STATIC_INLINE void ARM_PMU_CNTR_Enable

(

uint32_t

mask

)

Enable counters.

Parameters

[in]

mask

Counters to enable

Note

Enables one or more of the following:

• event counters (0-30)
• cycle counter

ARM_PMU_CNTR_Disable()

__STATIC_INLINE void ARM_PMU_CNTR_Disable

(

uint32_t

mask

)

Disable counters.

Parameters

[in]

mask

Counters to enable

Note

Disables one or more of the following:

• event counters (0-30)
• cycle counter

ARM_PMU_Get_CCNTR()

__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR

(

void

)

Read cycle counter.

Returns

Cycle count

ARM_PMU_Get_EVCNTR()

__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR

(

uint32_t

num

)

Read event counter.

Parameters

[in]

num

Event counter (0-30) to read

Returns

Event count

ARM_PMU_Get_CNTR_OVS()

__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS

(

void

)

Read counter overflow status.

Returns

Counter overflow status bits for the following:

• event counters (0-30)
• cycle counter

ARM_PMU_Set_CNTR_OVS()

__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS

(

uint32_t

mask

)

Clear counter overflow status.

Parameters

[in]

mask

Counter overflow status bits to clear

Note

Clears overflow status bits for one or more of the following:

• event counters (0-30)
• cycle counter

ARM_PMU_Set_CNTR_IRQ_Enable()

__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable

(

uint32_t

mask

)

Enable counter overflow interrupt request.

Parameters

[in]

mask

Counter overflow interrupt request bits to set

Note

Sets overflow interrupt request bits for one or more of the following:

• event counters (0-30)
• cycle counter

ARM_PMU_Set_CNTR_IRQ_Disable()

__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable

(

uint32_t

mask

)

Disable counter overflow interrupt request.

Parameters

[in]

mask

Counter overflow interrupt request bits to clear

Note

Clears overflow interrupt request bits for one or more of the following:

• event counters (0-30)
• cycle counter

ARM_PMU_CNTR_Increment()

__STATIC_INLINE void ARM_PMU_CNTR_Increment

(

uint32_t

mask

)

Software increment event counter.

Parameters

[in]

mask

Counters to increment

Note

Software increment bits for one or more event counters (0-30)