mpu_armv8.h File Reference

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures
struct	ARM_MPU_Region_t

Macros
#define	ARM_MPU_ARMV8_H
#define	ARM_MPU_ATTR_DEVICE   ( 0U )
	Attribute for device memory (outer only) More...
#define	ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )
	Attribute for non-cacheable, normal memory. More...
#define	ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)   ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
	Attribute for Normal memory, Outer and Inner cacheability. More...
#define	ARM_MPU_ATTR_DEVICE_nGnRnE   (0U)
	Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR_DEVICE_nGnRE   (1U)
	Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR_DEVICE_nGRE   (2U)
	Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR_DEVICE_GRE   (3U)
	Device memory type Gathering, Re-ordering, Early Write Acknowledgement. More...
#define	MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE   (0b0100)
	Normal memory outer-cacheable and inner-cacheable attributes WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate. More...
#define	MPU_ATTR_NORMAL_OUTER_WT_TR_RA   (0b0010)
#define	MPU_ATTR_NORMAL_OUTER_WT_TR_WA   (0b0001)
#define	MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA   (0b0011)
#define	MPU_ATTR_NORMAL_OUTER_WT_RA   (0b1010)
#define	MPU_ATTR_NORMAL_OUTER_WT_WA   (0b1001)
#define	MPU_ATTR_NORMAL_OUTER_WT_RA_WA   (0b1011)
#define	MPU_ATTR_NORMAL_OUTER_WB_TR_RA   (0b0101)
#define	MPU_ATTR_NORMAL_OUTER_WB_TR_WA   (0b0110)
#define	MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA   (0b0111)
#define	MPU_ATTR_NORMAL_OUTER_WB_RA   (0b1101)
#define	MPU_ATTR_NORMAL_OUTER_WB_WA   (0b1110)
#define	MPU_ATTR_NORMAL_OUTER_WB_RA_WA   (0b1111)
#define	MPU_ATTR_NORMAL_INNER_NON_CACHEABLE   (0b0100)
#define	MPU_ATTR_NORMAL_INNER_WT_TR_RA   (0b0010)
#define	MPU_ATTR_NORMAL_INNER_WT_TR_WA   (0b0001)
#define	MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   (0b0011)
#define	MPU_ATTR_NORMAL_INNER_WT_RA   (0b1010)
#define	MPU_ATTR_NORMAL_INNER_WT_WA   (0b1001)
#define	MPU_ATTR_NORMAL_INNER_WT_RA_WA   (0b1011)
#define	MPU_ATTR_NORMAL_INNER_WB_TR_RA   (0b0101)
#define	MPU_ATTR_NORMAL_INNER_WB_TR_WA   (0b0110)
#define	MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA   (0b0111)
#define	MPU_ATTR_NORMAL_INNER_WB_RA   (0b1101)
#define	MPU_ATTR_NORMAL_INNER_WB_WA   (0b1110)
#define	MPU_ATTR_NORMAL_INNER_WB_RA_WA   (0b1111)
#define	ARM_MPU_ATTR(O, I)   ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
	Memory Attribute. More...
#define	MAIR_ATTR(x)   ((x > 7 || x < 0) ? 0 : x)
#define	ARM_MPU_SH_NON   (0U)
	Normal memory, non-shareable. More...
#define	ARM_MPU_SH_OUTER   (2U)
	Normal memory, outer shareable. More...
#define	ARM_MPU_SH_INNER   (3U)
	Normal memory, inner shareable. More...
#define	ARM_MPU_AP_RW   (0U)
	Normal memory, read/write. More...
#define	ARM_MPU_AP_RO   (1U)
	Normal memory, read-only. More...
#define	ARM_MPU_AP_NP   (1U)
	Normal memory, any privilege level. More...
#define	ARM_MPU_AP_PO   (0U)
	Normal memory, privileged access only. More...
#define	ARM_MPU_XN   (1U)
	Normal memory, Execution only permitted if read permitted. More...
#define	ARM_MPU_EX   (0U)
	Normal memory, Execution only permitted if read permitted. More...
#define	ARM_MPU_AP_(RO, NP)   ((((RO) & 1U) << 1U) | ((NP) & 1U))
	Memory access permissions. More...
#define	ARM_MPU_RBAR(BASE, SH, RO, NP, XN)
	Region Base Address Register value. More...
#define	ARM_MPU_RLAR(LIMIT, IDX)
	Region Limit Address Register value. More...

Functions
__STATIC_INLINE uint32_t	ARM_MPU_TYPE ()
	Read MPU Type Register. More...
__STATIC_INLINE void	ARM_MPU_Enable (uint32_t MPU_Control)
__STATIC_INLINE void	ARM_MPU_Disable (void)
__STATIC_INLINE void	ARM_MPU_SetMemAttrEx (MPU_Type *mpu, uint8_t idx, uint8_t attr)
__STATIC_INLINE void	ARM_MPU_SetMemAttr (uint8_t idx, uint8_t attr)
__STATIC_INLINE void	ARM_MPU_ClrRegionEx (MPU_Type *mpu, uint32_t rnr)
__STATIC_INLINE void	ARM_MPU_ClrRegion (uint32_t rnr)
__STATIC_INLINE void	ARM_MPU_SetRegionEx (MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE void	ARM_MPU_SetRegion (uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE void	ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
__STATIC_INLINE void	ARM_MPU_LoadEx (MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
__STATIC_INLINE void	ARM_MPU_Load (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)

Macro Definition Documentation

ARM_MPU_ARMV8_H

#define ARM_MPU_ARMV8_H

ARM_MPU_ATTR_DEVICE

#define ARM_MPU_ATTR_DEVICE   ( 0U )

Attribute for device memory (outer only)

ARM_MPU_ATTR_NON_CACHEABLE

#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )

Attribute for non-cacheable, normal memory.

ARM_MPU_ATTR_MEMORY_

#define ARM_MPU_ATTR_MEMORY_	(		NT,
			WB,
			RA,
			WA
	)		((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))

Attribute for Normal memory, Outer and Inner cacheability.

Parameters

NT	Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
WB	Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
RA	Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
WA	Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.

ARM_MPU_ATTR_DEVICE_nGnRnE

#define ARM_MPU_ATTR_DEVICE_nGnRnE   (0U)

Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement.

ARM_MPU_ATTR_DEVICE_nGnRE

#define ARM_MPU_ATTR_DEVICE_nGnRE   (1U)

Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement.

ARM_MPU_ATTR_DEVICE_nGRE

#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)

Device memory type non Gathering, Re-ordering, Early Write Acknowledgement.

ARM_MPU_ATTR_DEVICE_GRE

#define ARM_MPU_ATTR_DEVICE_GRE   (3U)

Device memory type Gathering, Re-ordering, Early Write Acknowledgement.

MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE

#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE   (0b0100)

Normal memory outer-cacheable and inner-cacheable attributes WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate.

MPU_ATTR_NORMAL_OUTER_WT_TR_RA

#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA   (0b0010)

MPU_ATTR_NORMAL_OUTER_WT_TR_WA

#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA   (0b0001)

MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA   (0b0011)

MPU_ATTR_NORMAL_OUTER_WT_RA

#define MPU_ATTR_NORMAL_OUTER_WT_RA   (0b1010)

MPU_ATTR_NORMAL_OUTER_WT_WA

#define MPU_ATTR_NORMAL_OUTER_WT_WA   (0b1001)

MPU_ATTR_NORMAL_OUTER_WT_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA   (0b1011)

MPU_ATTR_NORMAL_OUTER_WB_TR_RA

#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA   (0b0101)

MPU_ATTR_NORMAL_OUTER_WB_TR_WA

#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA   (0b0110)

MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA   (0b0111)

MPU_ATTR_NORMAL_OUTER_WB_RA

#define MPU_ATTR_NORMAL_OUTER_WB_RA   (0b1101)

MPU_ATTR_NORMAL_OUTER_WB_WA

#define MPU_ATTR_NORMAL_OUTER_WB_WA   (0b1110)

MPU_ATTR_NORMAL_OUTER_WB_RA_WA

#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA   (0b1111)

MPU_ATTR_NORMAL_INNER_NON_CACHEABLE

#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE   (0b0100)

MPU_ATTR_NORMAL_INNER_WT_TR_RA

#define MPU_ATTR_NORMAL_INNER_WT_TR_RA   (0b0010)

MPU_ATTR_NORMAL_INNER_WT_TR_WA

#define MPU_ATTR_NORMAL_INNER_WT_TR_WA   (0b0001)

MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA

#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   (0b0011)

MPU_ATTR_NORMAL_INNER_WT_RA

#define MPU_ATTR_NORMAL_INNER_WT_RA   (0b1010)

MPU_ATTR_NORMAL_INNER_WT_WA

#define MPU_ATTR_NORMAL_INNER_WT_WA   (0b1001)

MPU_ATTR_NORMAL_INNER_WT_RA_WA

#define MPU_ATTR_NORMAL_INNER_WT_RA_WA   (0b1011)

MPU_ATTR_NORMAL_INNER_WB_TR_RA

#define MPU_ATTR_NORMAL_INNER_WB_TR_RA   (0b0101)

MPU_ATTR_NORMAL_INNER_WB_TR_WA

#define MPU_ATTR_NORMAL_INNER_WB_TR_WA   (0b0110)

MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA

#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA   (0b0111)

MPU_ATTR_NORMAL_INNER_WB_RA

#define MPU_ATTR_NORMAL_INNER_WB_RA   (0b1101)

MPU_ATTR_NORMAL_INNER_WB_WA

#define MPU_ATTR_NORMAL_INNER_WB_WA   (0b1110)

MPU_ATTR_NORMAL_INNER_WB_RA_WA

#define MPU_ATTR_NORMAL_INNER_WB_RA_WA   (0b1111)

ARM_MPU_ATTR

#define ARM_MPU_ATTR	(		O,
			I
	)		((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))

Memory Attribute.

Parameters

O	Outer memory attributes
I	O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes

MAIR_ATTR

#define MAIR_ATTR

(

x

)

((x > 7 || x < 0) ? 0 : x)

ARM_MPU_SH_NON

#define ARM_MPU_SH_NON   (0U)

Normal memory, non-shareable.

Shareability

ARM_MPU_SH_OUTER

#define ARM_MPU_SH_OUTER   (2U)

Normal memory, outer shareable.

ARM_MPU_SH_INNER

#define ARM_MPU_SH_INNER   (3U)

Normal memory, inner shareable.

ARM_MPU_AP_RW

#define ARM_MPU_AP_RW   (0U)

Normal memory, read/write.

Access permissions AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only

ARM_MPU_AP_RO

#define ARM_MPU_AP_RO   (1U)

Normal memory, read-only.

ARM_MPU_AP_NP

#define ARM_MPU_AP_NP   (1U)

Normal memory, any privilege level.

ARM_MPU_AP_PO

#define ARM_MPU_AP_PO   (0U)

Normal memory, privileged access only.

ARM_MPU_XN

#define ARM_MPU_XN   (1U)

Normal memory, Execution only permitted if read permitted.

ARM_MPU_EX

#define ARM_MPU_EX   (0U)

Normal memory, Execution only permitted if read permitted.

ARM_MPU_AP_

#define ARM_MPU_AP_	(		RO,
			NP
	)		((((RO) & 1U) << 1U) | ((NP) & 1U))

Memory access permissions.

Parameters

RO	Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
NP	Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.

ARM_MPU_RBAR

#define ARM_MPU_RBAR	(		BASE,
			SH,
			RO,
			NP,
			XN
	)

Value:

(((BASE) & MPU_RBAR_BASE_Msk) | \
  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))

Region Base Address Register value.

Parameters

BASE	The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
SH	Defines the Shareability domain for this memory region.
RO	Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
NP	Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
XN	eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.

ARM_MPU_RLAR

#define ARM_MPU_RLAR	(		LIMIT,
			IDX
	)

Value:

(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
  (MPU_RLAR_EN_Msk))

Region Limit Address Register value.

Parameters

LIMIT	The limit address bits [31:5] for this memory region. The value is one extended.
IDX	The attribute index to be associated with this memory region.

Function Documentation

ARM_MPU_TYPE()

__STATIC_INLINE uint32_t ARM_MPU_TYPE

(

)

Read MPU Type Register.

Returns

Number of MPU regions

ARM_MPU_Enable()

__STATIC_INLINE void ARM_MPU_Enable

(

uint32_t

MPU_Control

)

Enable the MPU.

Parameters

MPU_Control

Default access permissions for unconfigured regions.

References __DMB(), __DSB(), __ISB(), SCB, and SCB_SHCSR_MEMFAULTENA_Msk.

ARM_MPU_Disable()

__STATIC_INLINE void ARM_MPU_Disable

(

void

)

Disable the MPU.

References __DMB(), __DSB(), __ISB(), __STATIC_INLINE, SCB, and SCB_SHCSR_MEMFAULTENA_Msk.

ARM_MPU_SetMemAttrEx()

__STATIC_INLINE void ARM_MPU_SetMemAttrEx	(	MPU_Type *	mpu,
		uint8_t	idx,
		uint8_t	attr
	)

Set the memory attribute encoding to the given MPU.

Parameters

mpu	Pointer to the MPU to be configured.
idx	The attribute index to be set [0-7]
attr	The attribute value to be set.

Referenced by ARM_MPU_SetMemAttr().

ARM_MPU_SetMemAttr()

__STATIC_INLINE void ARM_MPU_SetMemAttr	(	uint8_t	idx,
		uint8_t	attr
	)

Set the memory attribute encoding.

Parameters

idx	The attribute index to be set [0-7]
attr	The attribute value to be set.

References __STATIC_INLINE, and ARM_MPU_SetMemAttrEx().

ARM_MPU_ClrRegionEx()

__STATIC_INLINE void ARM_MPU_ClrRegionEx	(	MPU_Type *	mpu,
		uint32_t	rnr
	)

Clear and disable the given MPU region of the given MPU.

Parameters

mpu	Pointer to MPU to be used.
rnr	Region number to be cleared.

Referenced by ARM_MPU_ClrRegion().

ARM_MPU_ClrRegion()

__STATIC_INLINE void ARM_MPU_ClrRegion

(

uint32_t

rnr

)

Clear and disable the given MPU region.

Parameters

rnr	Region number to be cleared.

References __STATIC_INLINE, and ARM_MPU_ClrRegionEx().

ARM_MPU_SetRegionEx()

__STATIC_INLINE void ARM_MPU_SetRegionEx	(	MPU_Type *	mpu,
		uint32_t	rnr,
		uint32_t	rbar,
		uint32_t	rlar
	)

Configure the given MPU region of the given MPU.

Parameters

mpu	Pointer to MPU to be used.
rnr	Region number to be configured.
rbar	Value for RBAR register.
rlar	Value for RLAR register.

Referenced by ARM_MPU_SetRegion().

ARM_MPU_SetRegion()

__STATIC_INLINE void ARM_MPU_SetRegion	(	uint32_t	rnr,
		uint32_t	rbar,
		uint32_t	rlar
	)

Configure the given MPU region.

Parameters

rnr	Region number to be configured.
rbar	Value for RBAR register.
rlar	Value for RLAR register.

References __STATIC_INLINE, and ARM_MPU_SetRegionEx().

ARM_MPU_OrderedMemcpy()

__STATIC_INLINE void ARM_MPU_OrderedMemcpy	(	volatile uint32_t *	dst,
		const uint32_t *__RESTRICT	src,
		uint32_t	len
	)

Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()

Parameters

dst	Destination data is copied to.
src	Source data is copied from.
len	Amount of data words to be copied.

Referenced by ARM_MPU_LoadEx().

ARM_MPU_LoadEx()

__STATIC_INLINE void ARM_MPU_LoadEx	(	MPU_Type *	mpu,
		uint32_t	rnr,
		ARM_MPU_Region_t const *	table,
		uint32_t	cnt
	)

Load the given number of MPU regions from a table to the given MPU.

Parameters

mpu	Pointer to the MPU registers to be used.
rnr	First region number to be configured.
table	Pointer to the MPU configuration table.
cnt	Amount of regions to be configured.

References ARM_MPU_OrderedMemcpy(), and ARM_MPU_Region_t::RBAR.

Referenced by ARM_MPU_Load().

ARM_MPU_Load()

__STATIC_INLINE void ARM_MPU_Load	(	uint32_t	rnr,
		ARM_MPU_Region_t const *	table,
		uint32_t	cnt
	)

Load the given number of MPU regions from a table.

Parameters

rnr	First region number to be configured.
table	Pointer to the MPU configuration table.
cnt	Amount of regions to be configured.

References __STATIC_INLINE, and ARM_MPU_LoadEx().