i2s.h

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/******************************************************************************
 *  Filename:       i2s.h
 *
 *  Description:    Prototypes and defines for the I2S API.
 *
 *  Copyright (c) 2023-2024 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1) Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *  2) Redistributions in binary form must reproduce the above copyright notice,
 *     this list of conditions and the following disclaimer in the documentation
 *     and/or other materials provided with the distribution.
 *
 *  3) Neither the name of the copyright holder nor the names of its
 *     contributors may be used to endorse or promote products derived from this
 *     software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 *  POSSIBILITY OF SUCH DAMAGE.
 *
 ******************************************************************************/

#ifndef __I2S_H__
#define __I2S_H__

//****************************************************************************
//
//
//****************************************************************************

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C" {
#endif

#include <stdbool.h>
#include <stdint.h>
#include "../inc/hw_types.h"
#include "../inc/hw_ints.h"
#include "../inc/hw_memmap.h"
#include "../inc/hw_i2s.h"
#include "debug.h"
#include "interrupt.h"

//*****************************************************************************
//
// Defines for selecting data pin usage.
//
//*****************************************************************************
#define I2S_SD0_DIS I2S_AIFDIRCFG_AD0_DIS 
#define I2S_SD0_IN  I2S_AIFDIRCFG_AD0_IN  
#define I2S_SD0_OUT I2S_AIFDIRCFG_AD0_OUT 
#define I2S_SD1_DIS I2S_AIFDIRCFG_AD1_DIS 
#define I2S_SD1_IN  I2S_AIFDIRCFG_AD1_IN  
#define I2S_SD1_OUT I2S_AIFDIRCFG_AD1_OUT 

//*****************************************************************************
//
// Defines for activating an audio channel.
//
//*****************************************************************************
#define I2S_CHAN0_MASK 0x00000001
#define I2S_CHAN1_MASK 0x00000002
#define I2S_CHAN2_MASK 0x00000004
#define I2S_CHAN3_MASK 0x00000008
#define I2S_CHAN4_MASK 0x00000010
#define I2S_CHAN5_MASK 0x00000020
#define I2S_CHAN6_MASK 0x00000040
#define I2S_CHAN7_MASK 0x00000080

//*****************************************************************************
//
// Defines for the audio format configuration
//
//*****************************************************************************
#define I2S_MEM_LENGTH_16 I2S_FMTCFG_MEMLEN32_DIS     
#define I2S_MEM_LENGTH_32 I2S_FMTCFG_MEMLEN32_EN      
#define I2S_POS_EDGE      I2S_FMTCFG_SMPLEDGE_POSEDGE 
#define I2S_NEG_EDGE      I2S_FMTCFG_SMPLEDGE_NEGEDGE 

//*****************************************************************************
//
// Defines for the sample stamp counters
//
//*****************************************************************************
#define I2S_STMP_SATURATION 0x0000FFFF 

//*****************************************************************************
//
// Defines for the interrupt
//
//*****************************************************************************
#define I2S_INT_XCNT_CAPTURE I2S_IRQFLAGS_XCNTCAPT    
#define I2S_INT_DMA_IN       I2S_IRQFLAGS_DMAIN       
#define I2S_INT_DMA_OUT      I2S_IRQFLAGS_DMAOUT      
#define I2S_INT_TIMEOUT      I2S_IRQFLAGS_WCLKTIMEOUT 
#define I2S_INT_BUS_ERR      I2S_IRQFLAGS_BUSERR      
#define I2S_INT_WCLK_ERR     I2S_IRQFLAGS_WCLKERR     
#define I2S_INT_PTR_ERR      I2S_IRQFLAGS_PTRERR      
#define I2S_INT_ALL                                                                                                   \
    (I2S_INT_XCNT_CAPTURE | I2S_INT_DMA_IN | I2S_INT_DMA_OUT | I2S_INT_TIMEOUT | I2S_INT_BUS_ERR | I2S_INT_WCLK_ERR | \
     I2S_INT_PTR_ERR) 

//*****************************************************************************
//
// API Functions and prototypes
//
//*****************************************************************************

#ifdef DRIVERLIB_DEBUG
//*****************************************************************************
//
//
//*****************************************************************************
static bool I2SBaseValid(uint32_t base)
{
    return (base == I2S_BASE);
}
#endif

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SEnableInt(uint32_t base, uint32_t intFlags)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Enable the specified interrupts
    HWREG(I2S_BASE + I2S_O_IRQMASK) |= intFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SDisableInt(uint32_t base, uint32_t intFlags)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Disable the specified interrupts
    HWREG(I2S_BASE + I2S_O_IRQMASK) &= ~intFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE uint32_t I2SIntStatus(uint32_t base, bool masked)
{
    uint32_t status;

    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Read the raw status
    status = HWREG(I2S_BASE + I2S_O_IRQFLAGS);

    // If the masked status is requested, mask the raw status with the interrupt
    // mask.
    if (masked)
    {
        status &= HWREG(I2S_BASE + I2S_O_IRQMASK);
    }

    return status;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SClearInt(uint32_t base, uint32_t intFlags)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Clear the requested interrupt sources
    HWREG(I2S_BASE + I2S_O_IRQCLR) = intFlags;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SEnableSampleStamp(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Set the enable bit
    HWREG(I2S_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMPEN_EN;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SDisableSampleStamp(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Clear the enable bit
    HWREG(I2S_BASE + I2S_O_STMPCTL) = 0;
}

//*****************************************************************************
//
//
//*****************************************************************************
extern uint32_t I2SGetSampleStamp(uint32_t base, uint32_t channel);

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SStart(uint32_t base, uint16_t dmaLength)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Enable the I2S module, by writting a non-zero value to AIFDMACFG.
    // AIFDMACFG expects the end frame index to be written, and the end index is
    // one less than the length.
    HWREG(I2S_BASE + I2S_O_DMACFG) = (dmaLength - 1) & I2S_DMACFG_ENDFRMIDX_M;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SStop(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Disable the I2S module
    HWREG(I2S_BASE + I2S_O_DMACFG) = 0x00;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SConfigureFormat(uint32_t base,
                                        uint8_t dataDelay,
                                        uint32_t memoryLength,
                                        uint32_t samplingEdge,
                                        bool dualPhase,
                                        uint8_t bitsPerSample)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));
    ASSERT(bitsPerSample <= 24); // Max. I2S_AIFFMTCFG_WORD_LEN
    ASSERT(bitsPerSample >= 8);  // Min. I2S_AIFFMTCFG_WORD_LEN

    // Setup register AIFFMTCFG Source
    HWREGH(I2S_BASE + I2S_O_FMTCFG) = (dataDelay << I2S_FMTCFG_DATADLY_S) | (memoryLength) | (samplingEdge) |
                                      (dualPhase << I2S_FMTCFG_DUALPHASE_S) | (bitsPerSample << I2S_FMTCFG_WORDLEN_S);
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE void I2SConfigureFrame(uint32_t base,
                                       uint8_t sd0Usage,
                                       uint8_t sd0Channels,
                                       uint8_t sd1Usage,
                                       uint8_t sd1Channels)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Configure input/output channels
    HWREGB(I2S_BASE + I2S_O_DIRCFG) = (sd0Usage | sd1Usage);

    // Configure the valid channel mask
    HWREGB(I2S_BASE + I2S_O_WMASK0) = sd0Channels;
    HWREGB(I2S_BASE + I2S_O_WMASK1) = sd1Channels;
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE void I2SConfigureClocks(uint32_t base,
                                        bool isController,
                                        bool invertWclk,
                                        bool dualPhase,
                                        uint32_t cclkDiv,
                                        uint32_t wclkDiv,
                                        uint32_t bclkDiv)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));
    ASSERT(cclkDiv <= 1024);
    ASSERT(cclkDiv >= 2);
    ASSERT(wclkDiv <= 1023);
    ASSERT(wclkDiv >= 1);
    ASSERT(bclkDiv <= 1024);
    ASSERT(bclkDiv >= 2);

    // Setup register WCLK and BCLK Source
    HWREGB(I2S_BASE + I2S_O_WCLKSRC) = ((isController ? I2S_WCLKSRC_WBCLKSRC_INT : I2S_WCLKSRC_WBCLKSRC_EXT) |
                                        (invertWclk ? I2S_WCLKSRC_WCLKINV : 0));

    // Configure internal clocks, if internal clocks are to be used
    if (isController)
    {

        // Make sure to compensate the WCLK division factor if using single
        // phase format.
        if (dualPhase == false)
        {
            wclkDiv -= 1;
        }

        // Write the clock division factors.
        // A value of 0 is interpreted as 1024 for CCLK and BCLK.
        HWREG(I2S_BASE + I2S_O_MCLKDIV) = (cclkDiv == 1024 ? 0 : cclkDiv);
        HWREG(I2S_BASE + I2S_O_WCLKDIV) = wclkDiv;
        HWREG(I2S_BASE + I2S_O_BCLKDIV) = (bclkDiv == 1024 ? 0 : bclkDiv);

        // Configure the WCLK format and disable CCLK, WCLK and BCLK
        HWREG(I2S_BASE + I2S_O_CLKCTL) = (dualPhase ? (1 << I2S_CLKCTL_WCLKPHASE_S) : (0 << I2S_CLKCTL_WCLKPHASE_S));
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SEnableControllerClocks(uint32_t base)
{
    // Enable CCLK, WCLK and BCLK
    HWREG(I2S_BASE + I2S_O_CLKCTL) |= I2S_CLKCTL_MEN | I2S_CLKCTL_WBEN;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SDisableControllerClocks(uint32_t base)
{
    // Disable CCLK, WCLK and BCLK
    HWREG(I2S_BASE + I2S_O_CLKCTL) &= ~(I2S_CLKCTL_MEN | I2S_CLKCTL_WBEN);
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE void I2SSetInPointer(uint32_t base, uint32_t nextPointer)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    HWREG(I2S_BASE + I2S_O_INPTRNXT) = nextPointer;
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE void I2SSetOutPointer(uint32_t base, uint32_t nextPointer)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    HWREG(I2S_BASE + I2S_O_OUTPTRNXT) = nextPointer;
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE uint32_t I2SGetInPointerNext(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    return (HWREG(I2S_BASE + I2S_O_INPTRNXT));
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE uint32_t I2SGetOutPointerNext(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    return (HWREG(I2S_BASE + I2S_O_OUTPTRNXT));
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE uint32_t I2SGetInPointer(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    return (HWREG(I2S_BASE + I2S_O_INPTR));
}

//****************************************************************************
//
//
//****************************************************************************
__STATIC_INLINE uint32_t I2SGetOutPointer(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    return (HWREG(I2S_BASE + I2S_O_OUTPTR));
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SConfigureInSampleStampTrigger(uint32_t base, uint16_t trigValue)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Setup the sample stamp trigger for input streams
    HWREGH(I2S_BASE + I2S_O_STMPINTRIG) = trigValue;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SConfigureOutSampleStampTrigger(uint32_t base, uint16_t trigValue)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Setup the sample stamp trigger for output streams
    HWREGH(I2S_BASE + I2S_O_STMPOUTTRIG) = trigValue;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SConfigureWclkCounterPeriod(uint32_t base, uint16_t period)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    // Configure the WCLK counter period
    HWREGH(I2S_BASE + I2S_O_STMPWPER) = period;
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SConfigureWclkCounter(uint32_t base, int16_t value)
{
    uint16_t minusValue;

    // Check the arguments
    ASSERT(I2SBaseValid(base));

    if (value >= 0)
    {
        HWREGH(I2S_BASE + I2S_O_STMPWADD) = value;
    }
    else
    {
        minusValue                        = (uint16_t)(-value);
        HWREGH(I2S_BASE + I2S_O_STMPWADD) = HWREGH(I2S_BASE + I2S_O_STMPWPER) - minusValue;
    }
}

//*****************************************************************************
//
//
//*****************************************************************************
__STATIC_INLINE void I2SResetWclkCounter(uint32_t base)
{
    // Check the arguments
    ASSERT(I2SBaseValid(base));

    HWREGH(I2S_BASE + I2S_O_STMPWSET) = 0;
}

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
//****************************************************************************
//
//
//****************************************************************************

#endif //  __I2S_H__