60 #include "../inc/hw_types.h" 61 #include "../inc/hw_ints.h" 62 #include "../inc/hw_memmap.h" 63 #include "../inc/hw_i2c.h" 73 #define I2C_CONTROLLER_CMD_SINGLE_SEND 0x00000007 74 #define I2C_CONTROLLER_CMD_SINGLE_RECEIVE 0x00000007 75 #define I2C_CONTROLLER_CMD_BURST_SEND_START 0x00000003 76 #define I2C_CONTROLLER_CMD_BURST_SEND_CONT 0x00000001 77 #define I2C_CONTROLLER_CMD_BURST_SEND_FINISH 0x00000005 78 #define I2C_CONTROLLER_CMD_BURST_SEND_ERROR_STOP 0x00000004 79 #define I2C_CONTROLLER_CMD_BURST_RECEIVE_START 0x0000000b 80 #define I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT 0x00000009 81 #define I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH 0x00000005 82 #define I2C_CONTROLLER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000004 89 #define I2C_CONTROLLER_ERR_NONE 0 90 #define I2C_CONTROLLER_ERR_ADDR_ACK 0x00000004 91 #define I2C_CONTROLLER_ERR_DATA_ACK 0x00000008 92 #define I2C_CONTROLLER_ERR_ARB_LOST 0x00000010 99 #define I2C_TARGET_ACT_NONE 0 100 #define I2C_TARGET_ACT_RREQ 0x00000001 // Controller has sent data 101 #define I2C_TARGET_ACT_TREQ 0x00000002 // Controller has requested data 102 #define I2C_TARGET_ACT_RREQ_FBR 0x00000005 // Controller has sent first byte 109 #define I2C_TARGET_INT_STOP 0x00000004 // Stop Condition Interrupt. 110 #define I2C_TARGET_INT_START 0x00000002 // Start Condition Interrupt. 111 #define I2C_TARGET_INT_DATA 0x00000001 // Data Interrupt. 118 #define I2C_CLK_FREQ 48000000 // Clock supplied to I2C periph in Hz 126 #ifdef DRIVERLIB_DEBUG 141 static bool I2CBaseValid(uint32_t base)
143 return (base == I2C0_BASE);
194 ASSERT(I2CBaseValid(base));
203 HWREG(base + I2C_O_CCTL) = cmd;
232 ASSERT(I2CBaseValid(base));
233 ASSERT(!(targetAddr & 0x80));
236 HWREG(base + I2C_O_CTA) = (targetAddr << 1) | receive;
253 ASSERT(I2CBaseValid(base));
256 HWREG(base + I2C_O_CCR) |= I2C_CCR_CFE_M;
259 HWREG(base + I2C_O_CCTL) = I2C_CCTL_RUN_EN;
276 ASSERT(I2CBaseValid(base));
279 HWREG(base + I2C_O_CCTL) = 0;
282 HWREG(base + I2C_O_CCR) &= ~I2C_CCR_CFE_M;
302 ASSERT(I2CBaseValid(base));
305 if (HWREG(base + I2C_O_CSTA) & I2C_CSTA_BUSY_M)
333 ASSERT(I2CBaseValid(base));
336 if (HWREG(base + I2C_O_CSTA) & I2C_CSTA_BUSBSY_M)
361 ASSERT(I2CBaseValid(base));
364 return (HWREG(base + I2C_O_CDR));
382 ASSERT(I2CBaseValid(base));
385 HWREG(base + I2C_O_CDR) = data;
420 ASSERT(I2CBaseValid(base));
423 HWREG(base + I2C_O_CIMR) = I2C_CIMR_IM;
440 ASSERT(I2CBaseValid(base));
443 HWREG(base + I2C_O_CIMR) = 0;
478 ASSERT(I2CBaseValid(base));
481 HWREG(base + I2C_O_CICR) = I2C_CICR_IC;
505 ASSERT(I2CBaseValid(base));
511 return ((HWREG(base + I2C_O_CMIS)) ?
true :
false);
515 return ((HWREG(base + I2C_O_CRIS)) ?
true :
false);
533 ASSERT(I2CBaseValid(base));
536 HWREG(base + I2C_O_CCR) |= I2C_CCR_TFE_M;
539 HWREG(base + I2C_O_TCTL) = I2C_TCTL_DA_EN;
562 ASSERT(I2CBaseValid(base));
563 ASSERT(!(targetAddr & 0x80));
569 HWREG(base + I2C_O_TOAR) = targetAddr;
587 ASSERT(I2CBaseValid(base));
588 ASSERT(!(targetAddr & 0x80));
591 HWREG(base + I2C_O_TOAR) = targetAddr;
608 ASSERT(I2CBaseValid(base));
611 HWREG(base + I2C_O_TCTL) = 0x0;
614 HWREG(base + I2C_O_CCR) &= ~I2C_CCR_TFE_M;
636 ASSERT(I2CBaseValid(base));
639 return (HWREG(base + I2C_O_TSTA));
657 ASSERT(I2CBaseValid(base));
660 return (HWREG(base + I2C_O_TDR));
678 ASSERT(I2CBaseValid(base));
681 HWREG(base + I2C_O_TDR) = data;
707 ASSERT(I2CBaseValid(base));
711 val = HWREG(base + I2C_O_TIMR);
713 HWREG(base + I2C_O_TIMR) = val;
739 ASSERT(I2CBaseValid(base));
743 val = HWREG(base + I2C_O_TIMR);
745 HWREG(base + I2C_O_TIMR) = val;
785 ASSERT(I2CBaseValid(base));
788 HWREG(base + I2C_O_TICR) = intFlags;
813 ASSERT(I2CBaseValid(base));
819 return (HWREG(base + I2C_O_TMIS));
823 return (HWREG(base + I2C_O_TRIS));
void CPUDelay(uint32_t count)
Provide a small non-zero delay using a simple loop counter.
#define I2C_CONTROLLER_CMD_BURST_SEND_CONT
Definition: i2c.h:76
__STATIC_INLINE void I2CControllerDisableInt(uint32_t base)
Disables the I2C Controller interrupt.
Definition: i2c.h:437
#define I2C_CONTROLLER_CMD_BURST_SEND_FINISH
Definition: i2c.h:77
__STATIC_INLINE void I2CTargetClearInt(uint32_t base, uint32_t intFlags)
Clears I2C Target interrupt sources.
Definition: i2c.h:782
__STATIC_INLINE void I2CTargetInit(uint32_t base, uint8_t targetAddr)
Initializes the I2C Target module.
Definition: i2c.h:559
#define I2C_CONTROLLER_CMD_BURST_SEND_ERROR_STOP
Definition: i2c.h:78
void I2CControllerInitExpClk(uint32_t base, bool fast)
Initializes the I2C Controller module.
Definition: i2c.c:43
__STATIC_INLINE void I2CControllerClearInt(uint32_t base)
Clears I2C Controller interrupt sources.
Definition: i2c.h:475
#define I2C_TARGET_INT_DATA
Definition: i2c.h:111
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_START
Definition: i2c.h:79
__STATIC_INLINE void I2CControllerCommand(uint32_t base, uint32_t cmd)
Controls the state of the I2C Controller module.
Definition: i2c.h:191
__STATIC_INLINE void I2CTargetEnable(uint32_t base)
Enables the I2C Target module.
Definition: i2c.h:530
__STATIC_INLINE uint32_t I2CTargetIntStatus(uint32_t base, bool masked)
Gets the current I2C Target interrupt status.
Definition: i2c.h:810
__STATIC_INLINE void I2CControllerDisable(uint32_t base)
Disables the I2C controller module.
Definition: i2c.h:273
__STATIC_INLINE bool I2CControllerIntStatus(uint32_t base, bool masked)
Gets the current I2C Controller interrupt status.
Definition: i2c.h:502
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_FINISH
Definition: i2c.h:81
__STATIC_INLINE void I2CTargetPutData(uint32_t base, uint8_t data)
Transmits a byte from the I2C Target.
Definition: i2c.h:675
#define I2C_CONTROLLER_CMD_BURST_SEND_START
Definition: i2c.h:75
__STATIC_INLINE void I2CControllerSetTargetAddr(uint32_t base, uint8_t targetAddr, bool receive)
Sets the address that the I2C Controller will place on the bus.
Definition: i2c.h:229
#define ASSERT(expr)
Definition: debug.h:71
__STATIC_INLINE uint32_t I2CTargetStatus(uint32_t base)
Gets the I2C Target module status.
Definition: i2c.h:633
__STATIC_INLINE void I2CControllerEnable(uint32_t base)
Enables the I2C Controller module.
Definition: i2c.h:250
__STATIC_INLINE uint32_t I2CControllerGetData(uint32_t base)
Receives a byte that has been sent to the I2C Controller.
Definition: i2c.h:358
__STATIC_INLINE void I2CTargetSetAddress(uint32_t base, uint8_t targetAddr)
Sets the I2C target address.
Definition: i2c.h:584
__STATIC_INLINE void I2CTargetEnableInt(uint32_t base, uint32_t intFlags)
Enables individual I2C Target interrupt sources.
Definition: i2c.h:702
__STATIC_INLINE void I2CTargetDisable(uint32_t base)
Disables the I2C target module.
Definition: i2c.h:605
__STATIC_INLINE void I2CTargetDisableInt(uint32_t base, uint32_t intFlags)
Disables individual I2C Target interrupt sources.
Definition: i2c.h:734
__STATIC_INLINE bool I2CControllerBusBusy(uint32_t base)
Indicates whether or not the I2C bus is busy.
Definition: i2c.h:330
__STATIC_INLINE void I2CControllerEnableInt(uint32_t base)
Enables the I2C Controller interrupt.
Definition: i2c.h:417
#define __STATIC_INLINE
Definition: cmsis_gcc.h:47
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_CONT
Definition: i2c.h:80
__STATIC_INLINE uint32_t I2CTargetGetData(uint32_t base)
Receives a byte that has been sent to the I2C Target.
Definition: i2c.h:654
#define I2C_TARGET_INT_STOP
Definition: i2c.h:109
__STATIC_INLINE void I2CControllerPutData(uint32_t base, uint8_t data)
Transmits a byte from the I2C Controller.
Definition: i2c.h:379
#define I2C_CONTROLLER_CMD_BURST_RECEIVE_ERROR_STOP
Definition: i2c.h:82
#define I2C_CONTROLLER_CMD_SINGLE_SEND
Definition: i2c.h:73
#define I2C_TARGET_INT_START
Definition: i2c.h:110
__STATIC_INLINE bool I2CControllerBusy(uint32_t base)
Indicates whether or not the I2C Controller is busy.
Definition: i2c.h:299
uint32_t I2CControllerError(uint32_t base)
Gets the error status of the I2C Controller module.
Definition: i2c.c:77