Collaboration diagram for [evtsvt.h] MCU Event Fabric:

Macros
#define	EVTSVT_SUB_CPUIRQ0 EVTSVT_O_CPUIRQ0SEL
	Subscriber ID for CPUIRQ0. More...

#define	EVTSVT_SUB_CPUIRQ1 EVTSVT_O_CPUIRQ1SEL
	Subscriber ID for CPUIRQ1. More...

#define	EVTSVT_SUB_CPUIRQ2 EVTSVT_O_CPUIRQ2SEL
	Subscriber ID for CPUIRQ2. More...

#define	EVTSVT_SUB_CPUIRQ3 EVTSVT_O_CPUIRQ3SEL
	Subscriber ID for CPUIRQ3. More...

#define	EVTSVT_SUB_CPUIRQ4 EVTSVT_O_CPUIRQ4SEL
	Subscriber ID for CPUIRQ4. More...

#define	EVTSVT_SUB_CPUIRQ16 EVTSVT_O_CPUIRQ16SEL
	Subscriber ID for CPUIRQ16. More...

#define	EVTSVT_SUB_CPUIRQ17 EVTSVT_O_CPUIRQ17SEL
	Subscriber ID for CPUIRQ17. More...

#define	EVTSVT_SUB_SYSTIMC1 EVTSVT_O_SYSTIMC1SEL
	Subscriber ID for SYSTIMC1. More...

#define	EVTSVT_SUB_SYSTIMC5 EVTSVT_O_SYSTIMC5SEL
	Subscriber ID for SYSTIMC5. More...

#define	EVTSVT_SUB_ADCTRG EVTSVT_O_ADCTRGSEL
	Subscriber ID for ADCTRG. More...

#define	EVTSVT_SUB_LGPTSYNC EVTSVT_O_LGPTSYNCSEL
	Subscriber ID for LGPTSYNC. More...

#define	EVTSVT_SUB_LGPT0IN0 EVTSVT_O_LGPT0IN0SEL
	Subscriber ID for LGPT0IN0. More...

#define	EVTSVT_SUB_LGPT0IN1 EVTSVT_O_LGPT0IN1SEL
	Subscriber ID for LGPT0IN1. More...

#define	EVTSVT_SUB_LGPT0IN2 EVTSVT_O_LGPT0IN2SEL
	Subscriber ID for LGPT0IN2. More...

#define	EVTSVT_SUB_LGPT0TEN EVTSVT_O_LGPT0TENSEL
	Subscriber ID for LGPT0TEN. More...

#define	EVTSVT_SUB_LGPT1IN0 EVTSVT_O_LGPT1IN0SEL
	Subscriber ID for LGPT1IN0. More...

#define	EVTSVT_SUB_LGPT1IN1 EVTSVT_O_LGPT1IN1SEL
	Subscriber ID for LGPT1IN1. More...

#define	EVTSVT_SUB_LGPT1IN2 EVTSVT_O_LGPT1IN2SEL
	Subscriber ID for LGPT1IN2. More...

#define	EVTSVT_SUB_LGPT1TEN EVTSVT_O_LGPT1TENSEL
	Subscriber ID for LGPT1TEN. More...

#define	EVTSVT_SUB_LGPT2IN0 EVTSVT_O_LGPT2IN0SEL
	Subscriber ID for LGPT2IN0. More...

#define	EVTSVT_SUB_LGPT2IN1 EVTSVT_O_LGPT2IN1SEL
	Subscriber ID for LGPT2IN1. More...

#define	EVTSVT_SUB_LGPT2IN2 EVTSVT_O_LGPT2IN2SEL
	Subscriber ID for LGPT2IN2. More...

#define	EVTSVT_SUB_LGPT2TEN EVTSVT_O_LGPT2TENSEL
	Subscriber ID for LGPT2TEN. More...

#define	EVTSVT_SUB_LGPT3IN0 EVTSVT_O_LGPT3IN0SEL
	Subscriber ID for LGPT3IN0. More...

#define	EVTSVT_SUB_LGPT3IN1 EVTSVT_O_LGPT3IN1SEL
	Subscriber ID for LGPT3IN1. More...

#define	EVTSVT_SUB_LGPT3IN2 EVTSVT_O_LGPT3IN2SEL
	Subscriber ID for LGPT3IN2. More...

#define	EVTSVT_SUB_LGPT3TEN EVTSVT_O_LGPT3TENSEL
	Subscriber ID for LGPT3TEN. More...

#define	EVTSVT_SUB_I2SSTMP EVTSVT_O_I2SSTMPSEL
	Subscriber ID for I2SSTMP. More...

#define	EVTSVT_DMA_CH0 EVTSVT_O_DMACH0SEL
	DMA channel 0 (DCH) More...

#define	EVTSVT_DMA_CH1 EVTSVT_O_DMACH1SEL
	DMA channel 1 (DCH) More...

#define	EVTSVT_DMA_CH2 EVTSVT_O_DMACH2SEL
	DMA channel 2 (DCH) More...

#define	EVTSVT_DMA_CH3 EVTSVT_O_DMACH3SEL
	DMA channel 3 (DCH) More...

#define	EVTSVT_DMA_CH4 EVTSVT_O_DMACH4SEL
	DMA channel 4 (DCH) More...

#define	EVTSVT_DMA_CH5 EVTSVT_O_DMACH5SEL
	DMA channel 5 (DCH) More...

#define	EVTSVT_DMA_CH6 EVTSVT_O_DMACH6SEL
	DMA channel 6 (DCH) More...

#define	EVTSVT_DMA_CH7 EVTSVT_O_DMACH7SEL
	DMA channel 7 (DCH) More...

#define	EVTSVT_DMA_CH8 EVTSVT_O_DMACH8SEL
	DMA channel 8 (ECH) More...

#define	EVTSVT_DMA_CH9 EVTSVT_O_DMACH9SEL
	DMA channel 9 (ECH) More...

#define	EVTSVT_DMA_CH10 EVTSVT_O_DMACH10SEL
	DMA channel 10 (ECH) More...

#define	EVTSVT_DMA_CH11 EVTSVT_O_DMACH11SEL
	DMA channel 11 (ECH) More...

#define	EVTSVT_DMA_TRIG_UART0TXTRG EVTSVT_DMACH2SEL_IPID_UART0TXTRG
	DMA trigger for UART0 TX. More...

#define	EVTSVT_DMA_TRIG_UART0RXTRG EVTSVT_DMACH3SEL_IPID_UART0RXTRG
	DMA trigger for UART0 RX. More...

#define	EVTSVT_DMA_TRIG_UART1TXTRG EVTSVT_DMACH1SEL_IPID_UART1TXTRG
	DMA trigger for UART1 TX. More...

#define	EVTSVT_DMA_TRIG_UART1RXTRG EVTSVT_DMACH0SEL_IPID_UART1RXTRG
	DMA trigger for UART1 RX. More...

#define	EVTSVT_DMA_TRIG_SPI0TXTRG EVTSVT_DMACH0SEL_IPID_SPI0TXTRG
	DMA trigger for SPI0 TX. More...

#define	EVTSVT_DMA_TRIG_SPI0RXTRG EVTSVT_DMACH1SEL_IPID_SPI0RXTRG
	DMA trigger for SPI0 RX. More...

#define	EVTSVT_DMA_TRIG_SPI1TXTRG EVTSVT_DMACH6SEL_IPID_SPI1TXTRG
	DMA trigger for SPI1 TX. More...

#define	EVTSVT_DMA_TRIG_SPI1RXTRG EVTSVT_DMACH7SEL_IPID_SPI1RXTRG
	DMA trigger for SPI1 RX. More...

#define	EVTSVT_DMA_TRIG_LRFDTRG EVTSVT_DMACH2SEL_IPID_LRFDTRG
	DMA trigger for LRFD. More...

#define	EVTSVT_DMA_TRIG_ADC0TRG EVTSVT_DMACH3SEL_IPID_ADC0TRG
	DMA trigger for ADC0. More...

#define	EVTSVT_DMA_TRIG_LAESTRGA EVTSVT_DMACH4SEL_IPID_LAESTRGA
	DMA trigger for LAES A. More...

#define	EVTSVT_DMA_TRIG_LAESTRGB EVTSVT_DMACH5SEL_IPID_LAESTRGB
	DMA trigger for LAES B. More...

#define	EVTSVT_DMA_TRIG_CANTRGA EVTSVT_DMACH6SEL_IPID_CANTRGA
	DMA trigger for CAN A. More...

#define	EVTSVT_DMA_TRIG_CANTRGB EVTSVT_DMACH7SEL_IPID_CANTRGB
	DMA trigger for CAN B. More...

#define	EVTSVT_PUB_SYSTIM5 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM5
	Publisher ID for System Timer 5. More...

#define	EVTSVT_PUB_GPIO_EVT1 EVTSVT_CPUIRQ0SEL_PUBID_GPIO_EVT1
	Publisher ID for GPIO Event 1. More...

#define	EVTSVT_PUB_APU_IRQ EVTSVT_CPUIRQ0SEL_PUBID_APU_IRQ
	Publisher ID for APU IRQ. More...

#define	EVTSVT_PUB_SPI1_COMB EVTSVT_CPUIRQ0SEL_PUBID_SPI1_COMB
	Publisher ID for SPI1 Combined event. More...

#define	EVTSVT_PUB_CAN_EVT EVTSVT_CPUIRQ0SEL_PUBID_CAN_EVT
	Publisher ID for CAN Event. More...

#define	EVTSVT_PUB_CAN_IRQ EVTSVT_CPUIRQ0SEL_PUBID_CAN_IRQ
	Publisher ID for CAN IRQ event. More...

#define	EVTSVT_PUB_I2S_IRQ EVTSVT_CPUIRQ0SEL_PUBID_I2S_IRQ
	Publisher ID for I2S IRQ event. More...

#define	EVTSVT_PUB_LGPT3_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_ADC
	Publisher ID for LGPT3 ADC event. More...

#define	EVTSVT_PUB_LGPT3_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_DMA
	Publisher ID for LGPT3 DMA event. More...

#define	EVTSVT_PUB_LGPT3_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_COMB
	Publisher ID for LGPT3 Combined event. More...

#define	EVTSVT_PUB_LGPT3C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C2
	Publisher ID for LGPT3 Channel 2 event. More...

#define	EVTSVT_PUB_LGPT3C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C1
	Publisher ID for LGPT3 Channel 1 event. More...

#define	EVTSVT_PUB_LGPT3C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C0
	Publisher ID for LGPT3 Channel 0 event. More...

#define	EVTSVT_PUB_LGPT2_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_ADC
	Publisher ID for LGPT2 ADC event. More...

#define	EVTSVT_PUB_LGPT2_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_DMA
	Publisher ID for LGPT2 DMA event. More...

#define	EVTSVT_PUB_LGPT2_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_COMB
	Publisher ID for LGPT2 Combined event. More...

#define	EVTSVT_PUB_LGPT2C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C2
	Publisher ID for LGPT2 Channel 2 event. More...

#define	EVTSVT_PUB_LGPT2C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C1
	Publisher ID for LGPT2 Channel 1 event. More...

#define	EVTSVT_PUB_LGPT2C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C0
	Publisher ID for LGPT2 Channel 0 event. More...

#define	EVTSVT_PUB_UART1_COMB EVTSVT_CPUIRQ0SEL_PUBID_UART1_COMB
	Publisher ID for UART1 Combined event. More...

#define	EVTSVT_PUB_LRFD_EVT2 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT2
	Publisher ID for LRFD Event 2. More...

#define	EVTSVT_PUB_LRFD_EVT1 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT1
	Publisher ID for LRFD Event 1. More...

#define	EVTSVT_PUB_LRFD_EVT0 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT0
	Publisher ID for LRFD Event 0. More...

#define	EVTSVT_PUB_LGPT1_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_ADC
	Publisher ID for LGPT1 ADC event. More...

#define	EVTSVT_PUB_LGPT1_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_DMA
	Publisher ID for LGPT1 DMA event. More...

#define	EVTSVT_PUB_LGPT1C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C2
	Publisher ID for LGPT1 Channel 2 event. More...

#define	EVTSVT_PUB_LGPT1C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C1
	Publisher ID for LGPT1 Channel 1 event. More...

#define	EVTSVT_PUB_LGPT1C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C0
	Publisher ID for LGPT1 Channel 0 event. More...

#define	EVTSVT_PUB_LGPT0_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_ADC
	Publisher ID for LGPT0 ADC event. More...

#define	EVTSVT_PUB_LGPT0_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_DMA
	Publisher ID for LGPT0 DMA event. More...

#define	EVTSVT_PUB_LGPT0C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C2
	Publisher ID for LGPT0 Channel 2 event. More...

#define	EVTSVT_PUB_LGPT0C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C1
	Publisher ID for LGPT0 Channel 1 event. More...

#define	EVTSVT_PUB_LGPT0C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C0
	Publisher ID for LGPT0 Channel 0 event. More...

#define	EVTSVT_PUB_SYSTIM4 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM4
	Publisher ID for System Timer 4. More...

#define	EVTSVT_PUB_SYSTIM3 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM3
	Publisher ID for System Timer 3. More...

#define	EVTSVT_PUB_SYSTIM2 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM2
	Publisher ID for System Timer 2. More...

#define	EVTSVT_PUB_SYSTIM1 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM1
	Publisher ID for System Timer 1. More...

#define	EVTSVT_PUB_SYSTIM0 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM0
	Publisher ID for System Timer 0. More...

#define	EVTSVT_PUB_SYSTIM_LT EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_LT
	Publisher ID for System Timer LT. More...

#define	EVTSVT_PUB_SYSTIM_HB EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_HB
	Publisher ID for System Timer HB. More...

#define	EVTSVT_PUB_I2C0_IRQ EVTSVT_CPUIRQ0SEL_PUBID_I2C0_IRQ
	Publisher ID for I2C0 IRQ. More...

#define	EVTSVT_PUB_UART0_COMB EVTSVT_CPUIRQ0SEL_PUBID_UART0_COMB
	Publisher ID for UART0 Combined event. More...

#define	EVTSVT_PUB_AES_COMB EVTSVT_CPUIRQ0SEL_PUBID_AES_COMB
	Publisher ID for AES Combined event. More...

#define	EVTSVT_PUB_DMA_ERR EVTSVT_CPUIRQ0SEL_PUBID_DMA_ERR
	Publisher ID for DMA Error. More...

#define	EVTSVT_PUB_DMA_DONE_COMB EVTSVT_CPUIRQ0SEL_PUBID_DMA_DONE_COMB
	Publisher ID for DMA Done Combined event. More...

#define	EVTSVT_PUB_LGPT1_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_COMB
	Publisher ID for LGPT1 Combined event. More...

#define	EVTSVT_PUB_LGPT0_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_COMB
	Publisher ID for LGPT0 Combined event. More...

#define	EVTSVT_PUB_ADC_EVT EVTSVT_CPUIRQ0SEL_PUBID_ADC_EVT
	Publisher ID for ADC Event. More...

#define	EVTSVT_PUB_ADC_COMB EVTSVT_CPUIRQ0SEL_PUBID_ADC_COMB
	Publisher ID for ADC Combined event. More...

#define	EVTSVT_PUB_SPI0_COMB EVTSVT_CPUIRQ0SEL_PUBID_SPI0_COMB
	Publisher ID for SPI0 Combined event. More...

#define	EVTSVT_PUB_LRFD_IRQ2 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ2
	Publisher ID for LRFD IRQ2. More...

#define	EVTSVT_PUB_LRFD_IRQ1 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ1
	Publisher ID for LRFD IRQ1. More...

#define	EVTSVT_PUB_LRFD_IRQ0 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ0
	Publisher ID for LRFD IRQ0. More...

#define	EVTSVT_PUB_FLASH_IRQ EVTSVT_CPUIRQ0SEL_PUBID_FLASH_IRQ
	Publisher ID for Flash IRQ. More...

#define	EVTSVT_PUB_GPIO_EVT EVTSVT_CPUIRQ0SEL_PUBID_GPIO_EVT
	Publisher ID for GPIO Event. More...

#define	EVTSVT_PUB_GPIO_COMB EVTSVT_CPUIRQ0SEL_PUBID_GPIO_COMB
	Publisher ID for GPIO Combined event. More...

#define	EVTSVT_PUB_SYSTIM_COMB EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_COMB
	Publisher ID for System Timer Combined event. More...

#define	EVTSVT_PUB_AON_IOC_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_IOC_COMB
	Publisher ID for AON IOC Combined event. More...

#define	EVTSVT_PUB_AON_LPMCMP_IRQ EVTSVT_CPUIRQ0SEL_PUBID_AON_LPMCMP_IRQ
	Publisher ID for AON Low Power Comparator IRQ. More...

#define	EVTSVT_PUB_AON_DBG_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_DBG_COMB
	Publisher ID for AON Debug Combined event. More...

#define	EVTSVT_PUB_AON_RTC_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_RTC_COMB
	Publisher ID for AON RTC Combined event. More...

#define	EVTSVT_PUB_AON_CKM_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_CKM_COMB
	Event ID for AON Clock Management Combined event. More...

#define	EVTSVT_PUB_AON_PMU_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB
	Event ID for AON Power Management Combined event. More...

#define	EVTSVT_PUB_NONE EVTSVT_CPUIRQ0SEL_PUBID_NONE
	No event (always inactive) More...

#define	EVTSVT_IPID_MAX_VAL EVTSVT_DMA_TRIG_UART1RXTRG
	Maximum allowed IPID value, used for range checking. More...

#define	EVTSVT_PUBID_MAX_VAL EVTSVT_PUB_SYSTIM5
	Maximum allowed PUBID value, used for range checking. More...

#define	EVTSVT_DMA_CH_MAX_VAL EVTSVT_DMA_CH9

#define	EVTSVT_DMA_CH_MIN_VAL EVTSVT_DMA_CH0
	Minimum allowed DMA channel parameter value, used for range checking. More...

#define	EVTSVT_SUB_MAX_VAL EVTSVT_SUB_I2SSTMP
	Maximum allowed subscriber parameter value, used for range checking. More...

#define	EVTSVT_SUB_MIN_VAL EVTSVT_SUB_CPUIRQ0
	Minimum allowed subscriber parameter value, used for range checking. More...

Functions
void	EVTSVTConfigureDma (uint32_t channel, uint32_t id)
	Configure DMA channel for the given trigger/publisher. More...

void	EVTSVTConfigureEvent (uint32_t subscriber, uint32_t pubId)
	Configure event publisher to be input to a subscriber. More...

Detailed Description

Macro Definition Documentation

§ EVTSVT_SUB_CPUIRQ0

#define EVTSVT_SUB_CPUIRQ0 EVTSVT_O_CPUIRQ0SEL

Subscriber ID for CPUIRQ0.

§ EVTSVT_SUB_CPUIRQ1

#define EVTSVT_SUB_CPUIRQ1 EVTSVT_O_CPUIRQ1SEL

Subscriber ID for CPUIRQ1.

§ EVTSVT_SUB_CPUIRQ2

#define EVTSVT_SUB_CPUIRQ2 EVTSVT_O_CPUIRQ2SEL

Subscriber ID for CPUIRQ2.

§ EVTSVT_SUB_CPUIRQ3

#define EVTSVT_SUB_CPUIRQ3 EVTSVT_O_CPUIRQ3SEL

Subscriber ID for CPUIRQ3.

§ EVTSVT_SUB_CPUIRQ4

#define EVTSVT_SUB_CPUIRQ4 EVTSVT_O_CPUIRQ4SEL

Subscriber ID for CPUIRQ4.

§ EVTSVT_SUB_CPUIRQ16

#define EVTSVT_SUB_CPUIRQ16 EVTSVT_O_CPUIRQ16SEL

Subscriber ID for CPUIRQ16.

§ EVTSVT_SUB_CPUIRQ17

#define EVTSVT_SUB_CPUIRQ17 EVTSVT_O_CPUIRQ17SEL

Subscriber ID for CPUIRQ17.

§ EVTSVT_SUB_SYSTIMC1

#define EVTSVT_SUB_SYSTIMC1 EVTSVT_O_SYSTIMC1SEL

Subscriber ID for SYSTIMC1.

§ EVTSVT_SUB_SYSTIMC5

#define EVTSVT_SUB_SYSTIMC5 EVTSVT_O_SYSTIMC5SEL

Subscriber ID for SYSTIMC5.

§ EVTSVT_SUB_ADCTRG

#define EVTSVT_SUB_ADCTRG EVTSVT_O_ADCTRGSEL

Subscriber ID for ADCTRG.

§ EVTSVT_SUB_LGPTSYNC

#define EVTSVT_SUB_LGPTSYNC EVTSVT_O_LGPTSYNCSEL

Subscriber ID for LGPTSYNC.

§ EVTSVT_SUB_LGPT0IN0

#define EVTSVT_SUB_LGPT0IN0 EVTSVT_O_LGPT0IN0SEL

Subscriber ID for LGPT0IN0.

§ EVTSVT_SUB_LGPT0IN1

#define EVTSVT_SUB_LGPT0IN1 EVTSVT_O_LGPT0IN1SEL

Subscriber ID for LGPT0IN1.

§ EVTSVT_SUB_LGPT0IN2

#define EVTSVT_SUB_LGPT0IN2 EVTSVT_O_LGPT0IN2SEL

Subscriber ID for LGPT0IN2.

§ EVTSVT_SUB_LGPT0TEN

#define EVTSVT_SUB_LGPT0TEN EVTSVT_O_LGPT0TENSEL

Subscriber ID for LGPT0TEN.

§ EVTSVT_SUB_LGPT1IN0

#define EVTSVT_SUB_LGPT1IN0 EVTSVT_O_LGPT1IN0SEL

Subscriber ID for LGPT1IN0.

§ EVTSVT_SUB_LGPT1IN1

#define EVTSVT_SUB_LGPT1IN1 EVTSVT_O_LGPT1IN1SEL

Subscriber ID for LGPT1IN1.

§ EVTSVT_SUB_LGPT1IN2

#define EVTSVT_SUB_LGPT1IN2 EVTSVT_O_LGPT1IN2SEL

Subscriber ID for LGPT1IN2.

§ EVTSVT_SUB_LGPT1TEN

#define EVTSVT_SUB_LGPT1TEN EVTSVT_O_LGPT1TENSEL

Subscriber ID for LGPT1TEN.

§ EVTSVT_SUB_LGPT2IN0

#define EVTSVT_SUB_LGPT2IN0 EVTSVT_O_LGPT2IN0SEL

Subscriber ID for LGPT2IN0.

§ EVTSVT_SUB_LGPT2IN1

#define EVTSVT_SUB_LGPT2IN1 EVTSVT_O_LGPT2IN1SEL

Subscriber ID for LGPT2IN1.

§ EVTSVT_SUB_LGPT2IN2

#define EVTSVT_SUB_LGPT2IN2 EVTSVT_O_LGPT2IN2SEL

Subscriber ID for LGPT2IN2.

§ EVTSVT_SUB_LGPT2TEN

#define EVTSVT_SUB_LGPT2TEN EVTSVT_O_LGPT2TENSEL

Subscriber ID for LGPT2TEN.

§ EVTSVT_SUB_LGPT3IN0

#define EVTSVT_SUB_LGPT3IN0 EVTSVT_O_LGPT3IN0SEL

Subscriber ID for LGPT3IN0.

§ EVTSVT_SUB_LGPT3IN1

#define EVTSVT_SUB_LGPT3IN1 EVTSVT_O_LGPT3IN1SEL

Subscriber ID for LGPT3IN1.

§ EVTSVT_SUB_LGPT3IN2

#define EVTSVT_SUB_LGPT3IN2 EVTSVT_O_LGPT3IN2SEL

Subscriber ID for LGPT3IN2.

§ EVTSVT_SUB_LGPT3TEN

#define EVTSVT_SUB_LGPT3TEN EVTSVT_O_LGPT3TENSEL

Subscriber ID for LGPT3TEN.

§ EVTSVT_SUB_I2SSTMP

#define EVTSVT_SUB_I2SSTMP EVTSVT_O_I2SSTMPSEL

Subscriber ID for I2SSTMP.

§ EVTSVT_DMA_CH0

#define EVTSVT_DMA_CH0 EVTSVT_O_DMACH0SEL

DMA channel 0 (DCH)

§ EVTSVT_DMA_CH1

#define EVTSVT_DMA_CH1 EVTSVT_O_DMACH1SEL

DMA channel 1 (DCH)

§ EVTSVT_DMA_CH2

#define EVTSVT_DMA_CH2 EVTSVT_O_DMACH2SEL

DMA channel 2 (DCH)

§ EVTSVT_DMA_CH3

#define EVTSVT_DMA_CH3 EVTSVT_O_DMACH3SEL

DMA channel 3 (DCH)

§ EVTSVT_DMA_CH4

#define EVTSVT_DMA_CH4 EVTSVT_O_DMACH4SEL

DMA channel 4 (DCH)

§ EVTSVT_DMA_CH5

#define EVTSVT_DMA_CH5 EVTSVT_O_DMACH5SEL

DMA channel 5 (DCH)

§ EVTSVT_DMA_CH6

#define EVTSVT_DMA_CH6 EVTSVT_O_DMACH6SEL

DMA channel 6 (DCH)

§ EVTSVT_DMA_CH7

#define EVTSVT_DMA_CH7 EVTSVT_O_DMACH7SEL

DMA channel 7 (DCH)

Referenced by EVTSVTConfigureDma(), and EVTSVTConfigureDma_veneer().

§ EVTSVT_DMA_CH8

#define EVTSVT_DMA_CH8 EVTSVT_O_DMACH8SEL

DMA channel 8 (ECH)

§ EVTSVT_DMA_CH9

#define EVTSVT_DMA_CH9 EVTSVT_O_DMACH9SEL

DMA channel 9 (ECH)

§ EVTSVT_DMA_CH10

#define EVTSVT_DMA_CH10 EVTSVT_O_DMACH10SEL

DMA channel 10 (ECH)

§ EVTSVT_DMA_CH11

#define EVTSVT_DMA_CH11 EVTSVT_O_DMACH11SEL

DMA channel 11 (ECH)

§ EVTSVT_DMA_TRIG_UART0TXTRG

#define EVTSVT_DMA_TRIG_UART0TXTRG EVTSVT_DMACH2SEL_IPID_UART0TXTRG

DMA trigger for UART0 TX.

§ EVTSVT_DMA_TRIG_UART0RXTRG

#define EVTSVT_DMA_TRIG_UART0RXTRG EVTSVT_DMACH3SEL_IPID_UART0RXTRG

DMA trigger for UART0 RX.

§ EVTSVT_DMA_TRIG_UART1TXTRG

#define EVTSVT_DMA_TRIG_UART1TXTRG EVTSVT_DMACH1SEL_IPID_UART1TXTRG

DMA trigger for UART1 TX.

§ EVTSVT_DMA_TRIG_UART1RXTRG

#define EVTSVT_DMA_TRIG_UART1RXTRG EVTSVT_DMACH0SEL_IPID_UART1RXTRG

DMA trigger for UART1 RX.

§ EVTSVT_DMA_TRIG_SPI0TXTRG

#define EVTSVT_DMA_TRIG_SPI0TXTRG EVTSVT_DMACH0SEL_IPID_SPI0TXTRG

DMA trigger for SPI0 TX.

§ EVTSVT_DMA_TRIG_SPI0RXTRG

#define EVTSVT_DMA_TRIG_SPI0RXTRG EVTSVT_DMACH1SEL_IPID_SPI0RXTRG

DMA trigger for SPI0 RX.

§ EVTSVT_DMA_TRIG_SPI1TXTRG

#define EVTSVT_DMA_TRIG_SPI1TXTRG EVTSVT_DMACH6SEL_IPID_SPI1TXTRG

DMA trigger for SPI1 TX.

§ EVTSVT_DMA_TRIG_SPI1RXTRG

#define EVTSVT_DMA_TRIG_SPI1RXTRG EVTSVT_DMACH7SEL_IPID_SPI1RXTRG

DMA trigger for SPI1 RX.

§ EVTSVT_DMA_TRIG_LRFDTRG

#define EVTSVT_DMA_TRIG_LRFDTRG EVTSVT_DMACH2SEL_IPID_LRFDTRG

DMA trigger for LRFD.

§ EVTSVT_DMA_TRIG_ADC0TRG

#define EVTSVT_DMA_TRIG_ADC0TRG EVTSVT_DMACH3SEL_IPID_ADC0TRG

DMA trigger for ADC0.

§ EVTSVT_DMA_TRIG_LAESTRGA

#define EVTSVT_DMA_TRIG_LAESTRGA EVTSVT_DMACH4SEL_IPID_LAESTRGA

DMA trigger for LAES A.

§ EVTSVT_DMA_TRIG_LAESTRGB

#define EVTSVT_DMA_TRIG_LAESTRGB EVTSVT_DMACH5SEL_IPID_LAESTRGB

DMA trigger for LAES B.

§ EVTSVT_DMA_TRIG_CANTRGA

#define EVTSVT_DMA_TRIG_CANTRGA EVTSVT_DMACH6SEL_IPID_CANTRGA

DMA trigger for CAN A.

§ EVTSVT_DMA_TRIG_CANTRGB

#define EVTSVT_DMA_TRIG_CANTRGB EVTSVT_DMACH7SEL_IPID_CANTRGB

DMA trigger for CAN B.

§ EVTSVT_PUB_SYSTIM5

#define EVTSVT_PUB_SYSTIM5 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM5

Publisher ID for System Timer 5.

§ EVTSVT_PUB_GPIO_EVT1

#define EVTSVT_PUB_GPIO_EVT1 EVTSVT_CPUIRQ0SEL_PUBID_GPIO_EVT1

Publisher ID for GPIO Event 1.

§ EVTSVT_PUB_APU_IRQ

#define EVTSVT_PUB_APU_IRQ EVTSVT_CPUIRQ0SEL_PUBID_APU_IRQ

Publisher ID for APU IRQ.

§ EVTSVT_PUB_SPI1_COMB

#define EVTSVT_PUB_SPI1_COMB EVTSVT_CPUIRQ0SEL_PUBID_SPI1_COMB

Publisher ID for SPI1 Combined event.

§ EVTSVT_PUB_CAN_EVT

#define EVTSVT_PUB_CAN_EVT EVTSVT_CPUIRQ0SEL_PUBID_CAN_EVT

Publisher ID for CAN Event.

§ EVTSVT_PUB_CAN_IRQ

#define EVTSVT_PUB_CAN_IRQ EVTSVT_CPUIRQ0SEL_PUBID_CAN_IRQ

Publisher ID for CAN IRQ event.

§ EVTSVT_PUB_I2S_IRQ

#define EVTSVT_PUB_I2S_IRQ EVTSVT_CPUIRQ0SEL_PUBID_I2S_IRQ

Publisher ID for I2S IRQ event.

§ EVTSVT_PUB_LGPT3_ADC

#define EVTSVT_PUB_LGPT3_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_ADC

Publisher ID for LGPT3 ADC event.

§ EVTSVT_PUB_LGPT3_DMA

#define EVTSVT_PUB_LGPT3_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_DMA

Publisher ID for LGPT3 DMA event.

§ EVTSVT_PUB_LGPT3_COMB

#define EVTSVT_PUB_LGPT3_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT3_COMB

Publisher ID for LGPT3 Combined event.

§ EVTSVT_PUB_LGPT3C2

#define EVTSVT_PUB_LGPT3C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C2

Publisher ID for LGPT3 Channel 2 event.

§ EVTSVT_PUB_LGPT3C1

#define EVTSVT_PUB_LGPT3C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C1

Publisher ID for LGPT3 Channel 1 event.

§ EVTSVT_PUB_LGPT3C0

#define EVTSVT_PUB_LGPT3C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT3C0

Publisher ID for LGPT3 Channel 0 event.

§ EVTSVT_PUB_LGPT2_ADC

#define EVTSVT_PUB_LGPT2_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_ADC

Publisher ID for LGPT2 ADC event.

§ EVTSVT_PUB_LGPT2_DMA

#define EVTSVT_PUB_LGPT2_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_DMA

Publisher ID for LGPT2 DMA event.

§ EVTSVT_PUB_LGPT2_COMB

#define EVTSVT_PUB_LGPT2_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT2_COMB

Publisher ID for LGPT2 Combined event.

§ EVTSVT_PUB_LGPT2C2

#define EVTSVT_PUB_LGPT2C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C2

Publisher ID for LGPT2 Channel 2 event.

§ EVTSVT_PUB_LGPT2C1

#define EVTSVT_PUB_LGPT2C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C1

Publisher ID for LGPT2 Channel 1 event.

§ EVTSVT_PUB_LGPT2C0

#define EVTSVT_PUB_LGPT2C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT2C0

Publisher ID for LGPT2 Channel 0 event.

§ EVTSVT_PUB_UART1_COMB

#define EVTSVT_PUB_UART1_COMB EVTSVT_CPUIRQ0SEL_PUBID_UART1_COMB

Publisher ID for UART1 Combined event.

§ EVTSVT_PUB_LRFD_EVT2

#define EVTSVT_PUB_LRFD_EVT2 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT2

Publisher ID for LRFD Event 2.

§ EVTSVT_PUB_LRFD_EVT1

#define EVTSVT_PUB_LRFD_EVT1 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT1

Publisher ID for LRFD Event 1.

§ EVTSVT_PUB_LRFD_EVT0

#define EVTSVT_PUB_LRFD_EVT0 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_EVT0

Publisher ID for LRFD Event 0.

§ EVTSVT_PUB_LGPT1_ADC

#define EVTSVT_PUB_LGPT1_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_ADC

Publisher ID for LGPT1 ADC event.

§ EVTSVT_PUB_LGPT1_DMA

#define EVTSVT_PUB_LGPT1_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_DMA

Publisher ID for LGPT1 DMA event.

§ EVTSVT_PUB_LGPT1C2

#define EVTSVT_PUB_LGPT1C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C2

Publisher ID for LGPT1 Channel 2 event.

§ EVTSVT_PUB_LGPT1C1

#define EVTSVT_PUB_LGPT1C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C1

Publisher ID for LGPT1 Channel 1 event.

§ EVTSVT_PUB_LGPT1C0

#define EVTSVT_PUB_LGPT1C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT1C0

Publisher ID for LGPT1 Channel 0 event.

§ EVTSVT_PUB_LGPT0_ADC

#define EVTSVT_PUB_LGPT0_ADC EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_ADC

Publisher ID for LGPT0 ADC event.

§ EVTSVT_PUB_LGPT0_DMA

#define EVTSVT_PUB_LGPT0_DMA EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_DMA

Publisher ID for LGPT0 DMA event.

§ EVTSVT_PUB_LGPT0C2

#define EVTSVT_PUB_LGPT0C2 EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C2

Publisher ID for LGPT0 Channel 2 event.

§ EVTSVT_PUB_LGPT0C1

#define EVTSVT_PUB_LGPT0C1 EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C1

Publisher ID for LGPT0 Channel 1 event.

§ EVTSVT_PUB_LGPT0C0

#define EVTSVT_PUB_LGPT0C0 EVTSVT_CPUIRQ0SEL_PUBID_LGPT0C0

Publisher ID for LGPT0 Channel 0 event.

§ EVTSVT_PUB_SYSTIM4

#define EVTSVT_PUB_SYSTIM4 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM4

Publisher ID for System Timer 4.

§ EVTSVT_PUB_SYSTIM3

#define EVTSVT_PUB_SYSTIM3 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM3

Publisher ID for System Timer 3.

§ EVTSVT_PUB_SYSTIM2

#define EVTSVT_PUB_SYSTIM2 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM2

Publisher ID for System Timer 2.

§ EVTSVT_PUB_SYSTIM1

#define EVTSVT_PUB_SYSTIM1 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM1

Publisher ID for System Timer 1.

§ EVTSVT_PUB_SYSTIM0

#define EVTSVT_PUB_SYSTIM0 EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM0

Publisher ID for System Timer 0.

§ EVTSVT_PUB_SYSTIM_LT

#define EVTSVT_PUB_SYSTIM_LT EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_LT

Publisher ID for System Timer LT.

§ EVTSVT_PUB_SYSTIM_HB

#define EVTSVT_PUB_SYSTIM_HB EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_HB

Publisher ID for System Timer HB.

§ EVTSVT_PUB_I2C0_IRQ

#define EVTSVT_PUB_I2C0_IRQ EVTSVT_CPUIRQ0SEL_PUBID_I2C0_IRQ

Publisher ID for I2C0 IRQ.

§ EVTSVT_PUB_UART0_COMB

#define EVTSVT_PUB_UART0_COMB EVTSVT_CPUIRQ0SEL_PUBID_UART0_COMB

Publisher ID for UART0 Combined event.

§ EVTSVT_PUB_AES_COMB

#define EVTSVT_PUB_AES_COMB EVTSVT_CPUIRQ0SEL_PUBID_AES_COMB

Publisher ID for AES Combined event.

§ EVTSVT_PUB_DMA_ERR

#define EVTSVT_PUB_DMA_ERR EVTSVT_CPUIRQ0SEL_PUBID_DMA_ERR

Publisher ID for DMA Error.

§ EVTSVT_PUB_DMA_DONE_COMB

#define EVTSVT_PUB_DMA_DONE_COMB EVTSVT_CPUIRQ0SEL_PUBID_DMA_DONE_COMB

Publisher ID for DMA Done Combined event.

§ EVTSVT_PUB_LGPT1_COMB

#define EVTSVT_PUB_LGPT1_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT1_COMB

Publisher ID for LGPT1 Combined event.

§ EVTSVT_PUB_LGPT0_COMB

#define EVTSVT_PUB_LGPT0_COMB EVTSVT_CPUIRQ0SEL_PUBID_LGPT0_COMB

Publisher ID for LGPT0 Combined event.

§ EVTSVT_PUB_ADC_EVT

#define EVTSVT_PUB_ADC_EVT EVTSVT_CPUIRQ0SEL_PUBID_ADC_EVT

Publisher ID for ADC Event.

§ EVTSVT_PUB_ADC_COMB

#define EVTSVT_PUB_ADC_COMB EVTSVT_CPUIRQ0SEL_PUBID_ADC_COMB

Publisher ID for ADC Combined event.

§ EVTSVT_PUB_SPI0_COMB

#define EVTSVT_PUB_SPI0_COMB EVTSVT_CPUIRQ0SEL_PUBID_SPI0_COMB

Publisher ID for SPI0 Combined event.

§ EVTSVT_PUB_LRFD_IRQ2

#define EVTSVT_PUB_LRFD_IRQ2 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ2

Publisher ID for LRFD IRQ2.

§ EVTSVT_PUB_LRFD_IRQ1

#define EVTSVT_PUB_LRFD_IRQ1 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ1

Publisher ID for LRFD IRQ1.

§ EVTSVT_PUB_LRFD_IRQ0

#define EVTSVT_PUB_LRFD_IRQ0 EVTSVT_CPUIRQ0SEL_PUBID_LRFD_IRQ0

Publisher ID for LRFD IRQ0.

§ EVTSVT_PUB_FLASH_IRQ

#define EVTSVT_PUB_FLASH_IRQ EVTSVT_CPUIRQ0SEL_PUBID_FLASH_IRQ

Publisher ID for Flash IRQ.

§ EVTSVT_PUB_GPIO_EVT

#define EVTSVT_PUB_GPIO_EVT EVTSVT_CPUIRQ0SEL_PUBID_GPIO_EVT

Publisher ID for GPIO Event.

§ EVTSVT_PUB_GPIO_COMB

#define EVTSVT_PUB_GPIO_COMB EVTSVT_CPUIRQ0SEL_PUBID_GPIO_COMB

Publisher ID for GPIO Combined event.

§ EVTSVT_PUB_SYSTIM_COMB

#define EVTSVT_PUB_SYSTIM_COMB EVTSVT_CPUIRQ0SEL_PUBID_SYSTIM_COMB

Publisher ID for System Timer Combined event.

§ EVTSVT_PUB_AON_IOC_COMB

#define EVTSVT_PUB_AON_IOC_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_IOC_COMB

Publisher ID for AON IOC Combined event.

§ EVTSVT_PUB_AON_LPMCMP_IRQ

#define EVTSVT_PUB_AON_LPMCMP_IRQ EVTSVT_CPUIRQ0SEL_PUBID_AON_LPMCMP_IRQ

Publisher ID for AON Low Power Comparator IRQ.

§ EVTSVT_PUB_AON_DBG_COMB

#define EVTSVT_PUB_AON_DBG_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_DBG_COMB

Publisher ID for AON Debug Combined event.

§ EVTSVT_PUB_AON_RTC_COMB

#define EVTSVT_PUB_AON_RTC_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_RTC_COMB

Publisher ID for AON RTC Combined event.

§ EVTSVT_PUB_AON_CKM_COMB

#define EVTSVT_PUB_AON_CKM_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_CKM_COMB

Event ID for AON Clock Management Combined event.

§ EVTSVT_PUB_AON_PMU_COMB

#define EVTSVT_PUB_AON_PMU_COMB EVTSVT_CPUIRQ0SEL_PUBID_AON_PMU_COMB

Event ID for AON Power Management Combined event.

§ EVTSVT_PUB_NONE

#define EVTSVT_PUB_NONE EVTSVT_CPUIRQ0SEL_PUBID_NONE

No event (always inactive)

§ EVTSVT_IPID_MAX_VAL

#define EVTSVT_IPID_MAX_VAL EVTSVT_DMA_TRIG_UART1RXTRG

Maximum allowed IPID value, used for range checking.

Referenced by EVTSVTConfigureDma(), and EVTSVTConfigureDma_veneer().

§ EVTSVT_PUBID_MAX_VAL

#define EVTSVT_PUBID_MAX_VAL EVTSVT_PUB_SYSTIM5

Maximum allowed PUBID value, used for range checking.

Referenced by EVTSVTConfigureDma(), EVTSVTConfigureEvent(), EVTSVTConfigureEvent_veneer(), and validatePubId().

§ EVTSVT_DMA_CH_MAX_VAL

#define EVTSVT_DMA_CH_MAX_VAL EVTSVT_DMA_CH9

Maximum allowed DMA channel parameter value, used for range checking.

Note: Channel address order is not always the same as the channel number.

Referenced by EVTSVTConfigureDma(), and EVTSVTConfigureDma_veneer().

§ EVTSVT_DMA_CH_MIN_VAL

#define EVTSVT_DMA_CH_MIN_VAL EVTSVT_DMA_CH0

Minimum allowed DMA channel parameter value, used for range checking.

Referenced by EVTSVTConfigureDma(), and EVTSVTConfigureDma_veneer().

§ EVTSVT_SUB_MAX_VAL

#define EVTSVT_SUB_MAX_VAL EVTSVT_SUB_I2SSTMP

Maximum allowed subscriber parameter value, used for range checking.

Referenced by EVTSVTConfigureEvent(), and EVTSVTConfigureEvent_veneer().

§ EVTSVT_SUB_MIN_VAL

#define EVTSVT_SUB_MIN_VAL EVTSVT_SUB_CPUIRQ0

Minimum allowed subscriber parameter value, used for range checking.

Referenced by EVTSVTConfigureEvent(), and EVTSVTConfigureEvent_veneer().

Function Documentation

§ EVTSVTConfigureDma()

void EVTSVTConfigureDma	(	uint32_t	channel,
		uint32_t	id
	)

Configure DMA channel for the given trigger/publisher.

This function configures the DMA channel channel to be triggered by the event publisher id. DMA channels 0-7 accept EVTSVT_DMA_TRIG_* defines, while channels 8-11 accept EVTSVT_PUB_* defines.

Note: Channel 0-7: Not all channels support all DMA triggers, please refer to the Technical Reference Manual for details.; Channel 8-11: These channels support edge detection and this function always enables it.

Parameters

channel	is the DMA channel to configure. The parameter can be ONE of the following values: EVTSVT_DMA_CH0 EVTSVT_DMA_CH1 EVTSVT_DMA_CH2 EVTSVT_DMA_CH3 EVTSVT_DMA_CH4 EVTSVT_DMA_CH5 EVTSVT_DMA_CH6 EVTSVT_DMA_CH7 EVTSVT_DMA_CH8 EVTSVT_DMA_CH9 EVTSVT_DMA_CH10 EVTSVT_DMA_CH11
id	is the `EVTSVT_DMA_TRIG_` or `EVTSVT_PUB_` define to configure the DMA channel with.

For DMA channels 0-7, id must be ONE of the following values:

For DMA channels 8-11, id must be ONE of the following values:

References ASSERT, EVTSVT_DMA_CH7, EVTSVT_DMA_CH_MAX_VAL, EVTSVT_DMA_CH_MIN_VAL, EVTSVT_IPID_MAX_VAL, and EVTSVT_PUBID_MAX_VAL.

Referenced by EVTSVTConfigureDma_veneer().

§ EVTSVTConfigureEvent()

void EVTSVTConfigureEvent	(	uint32_t	subscriber,
		uint32_t	pubId
	)

Configure event publisher to be input to a subscriber.

This function configures the pubId event publisher to be input of subscriber.

Note: Not all subscribers can select all publishers, please refer to the Technical Reference Manual for details.

Parameters

subscriber

is the subscriber ID. The parameter must be ONE of the following values:

pubId

is the publisher ID. The parameter must be ONE of the following values:

References ASSERT, EVTSVT_PUBID_MAX_VAL, EVTSVT_SUB_MAX_VAL, and EVTSVT_SUB_MIN_VAL.

Referenced by EVTSVTConfigureEvent_veneer().

Macros

Functions

Detailed Description

Macro Definition Documentation

§ EVTSVT_SUB_CPUIRQ0

§ EVTSVT_SUB_CPUIRQ1

§ EVTSVT_SUB_CPUIRQ2

§ EVTSVT_SUB_CPUIRQ3

§ EVTSVT_SUB_CPUIRQ4

§ EVTSVT_SUB_CPUIRQ16

§ EVTSVT_SUB_CPUIRQ17

§ EVTSVT_SUB_SYSTIMC1

§ EVTSVT_SUB_SYSTIMC5

§ EVTSVT_SUB_ADCTRG

§ EVTSVT_SUB_LGPTSYNC

§ EVTSVT_SUB_LGPT0IN0

§ EVTSVT_SUB_LGPT0IN1

§ EVTSVT_SUB_LGPT0IN2

§ EVTSVT_SUB_LGPT0TEN

§ EVTSVT_SUB_LGPT1IN0

§ EVTSVT_SUB_LGPT1IN1

§ EVTSVT_SUB_LGPT1IN2

§ EVTSVT_SUB_LGPT1TEN

§ EVTSVT_SUB_LGPT2IN0

§ EVTSVT_SUB_LGPT2IN1

§ EVTSVT_SUB_LGPT2IN2

§ EVTSVT_SUB_LGPT2TEN

§ EVTSVT_SUB_LGPT3IN0

§ EVTSVT_SUB_LGPT3IN1

§ EVTSVT_SUB_LGPT3IN2

§ EVTSVT_SUB_LGPT3TEN

§ EVTSVT_SUB_I2SSTMP

§ EVTSVT_DMA_CH0

§ EVTSVT_DMA_CH1

§ EVTSVT_DMA_CH2

§ EVTSVT_DMA_CH3

§ EVTSVT_DMA_CH4

§ EVTSVT_DMA_CH5

§ EVTSVT_DMA_CH6

§ EVTSVT_DMA_CH7

§ EVTSVT_DMA_CH8

§ EVTSVT_DMA_CH9

§ EVTSVT_DMA_CH10

§ EVTSVT_DMA_CH11

§ EVTSVT_DMA_TRIG_UART0TXTRG

§ EVTSVT_DMA_TRIG_UART0RXTRG

§ EVTSVT_DMA_TRIG_UART1TXTRG

§ EVTSVT_DMA_TRIG_UART1RXTRG

§ EVTSVT_DMA_TRIG_SPI0TXTRG

§ EVTSVT_DMA_TRIG_SPI0RXTRG

§ EVTSVT_DMA_TRIG_SPI1TXTRG

§ EVTSVT_DMA_TRIG_SPI1RXTRG

§ EVTSVT_DMA_TRIG_LRFDTRG

§ EVTSVT_DMA_TRIG_ADC0TRG

§ EVTSVT_DMA_TRIG_LAESTRGA

§ EVTSVT_DMA_TRIG_LAESTRGB

§ EVTSVT_DMA_TRIG_CANTRGA

§ EVTSVT_DMA_TRIG_CANTRGB

§ EVTSVT_PUB_SYSTIM5

§ EVTSVT_PUB_GPIO_EVT1

§ EVTSVT_PUB_APU_IRQ

§ EVTSVT_PUB_SPI1_COMB

§ EVTSVT_PUB_CAN_EVT

§ EVTSVT_PUB_CAN_IRQ

§ EVTSVT_PUB_I2S_IRQ

§ EVTSVT_PUB_LGPT3_ADC

§ EVTSVT_PUB_LGPT3_DMA

§ EVTSVT_PUB_LGPT3_COMB

§ EVTSVT_PUB_LGPT3C2

§ EVTSVT_PUB_LGPT3C1

§ EVTSVT_PUB_LGPT3C0

§ EVTSVT_PUB_LGPT2_ADC

§ EVTSVT_PUB_LGPT2_DMA

§ EVTSVT_PUB_LGPT2_COMB

§ EVTSVT_PUB_LGPT2C2

§ EVTSVT_PUB_LGPT2C1

§ EVTSVT_PUB_LGPT2C0

§ EVTSVT_PUB_UART1_COMB

§ EVTSVT_PUB_LRFD_EVT2

§ EVTSVT_PUB_LRFD_EVT1