Type definitions for the System Control Block Registers. More...

Collaboration diagram for System Control Block (SCB):

Data Structures
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...

Macros
#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_IESB_Pos 5U

#define	SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos)

#define	SCB_AIRCR_DIT_Pos 4U

#define	SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_TRD_Pos 20U

#define	SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos)

#define	SCB_CCR_LOB_Pos 19U

#define	SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_PMU_Pos 5U

#define	SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CP7_Pos 7U

#define	SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos)

#define	SCB_NSACR_CP6_Pos 6U

#define	SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos)

#define	SCB_NSACR_CP5_Pos 5U

#define	SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos)

#define	SCB_NSACR_CP4_Pos 4U

#define	SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos)

#define	SCB_NSACR_CP3_Pos 3U

#define	SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos)

#define	SCB_NSACR_CP2_Pos 2U

#define	SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos)

#define	SCB_NSACR_CP1_Pos 1U

#define	SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos)

#define	SCB_NSACR_CP0_Pos 0U

#define	SCB_NSACR_CP0_Msk (1UL /<< SCB_NSACR_CP0_Pos/)

#define	SCB_ID_DFR_UDE_Pos 28U

#define	SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos)

#define	SCB_ID_DFR_MProfDbg_Pos 20U

#define	SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_RFSR_V_Pos 31U

#define	SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos)

#define	SCB_RFSR_IS_Pos 16U

#define	SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos)

#define	SCB_RFSR_UET_Pos 0U

#define	SCB_RFSR_UET_Msk (3UL /<< SCB_RFSR_UET_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CPn_Pos 0U

#define	SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CPn_Pos 0U

#define	SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

§ SCB_CPUID_IMPLEMENTER_Pos [1/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

§ SCB_CPUID_IMPLEMENTER_Msk [1/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

§ SCB_CPUID_VARIANT_Pos [1/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

§ SCB_CPUID_VARIANT_Msk [1/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

§ SCB_CPUID_ARCHITECTURE_Pos [1/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

§ SCB_CPUID_ARCHITECTURE_Msk [1/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

§ SCB_CPUID_PARTNO_Pos [1/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

§ SCB_CPUID_PARTNO_Msk [1/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

§ SCB_CPUID_REVISION_Pos [1/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

§ SCB_CPUID_REVISION_Msk [1/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

§ SCB_ICSR_PENDNMISET_Pos [1/4]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

§ SCB_ICSR_PENDNMISET_Msk [1/4]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

§ SCB_ICSR_NMIPENDSET_Pos [1/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

§ SCB_ICSR_NMIPENDSET_Msk [1/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Referenced by IntSetPend().

§ SCB_ICSR_PENDNMICLR_Pos [1/4]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

§ SCB_ICSR_PENDNMICLR_Msk [1/4]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

§ SCB_ICSR_PENDSVSET_Pos [1/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

§ SCB_ICSR_PENDSVSET_Msk [1/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Referenced by IntSetPend().

§ SCB_ICSR_PENDSVCLR_Pos [1/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

§ SCB_ICSR_PENDSVCLR_Msk [1/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Referenced by IntClearPend().

§ SCB_ICSR_PENDSTSET_Pos [1/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

§ SCB_ICSR_PENDSTSET_Msk [1/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Referenced by IntSetPend().

§ SCB_ICSR_PENDSTCLR_Pos [1/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

§ SCB_ICSR_PENDSTCLR_Msk [1/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Referenced by IntClearPend().

§ SCB_ICSR_STTNS_Pos [1/4]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

§ SCB_ICSR_STTNS_Msk [1/4]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

§ SCB_ICSR_ISRPREEMPT_Pos [1/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

§ SCB_ICSR_ISRPREEMPT_Msk [1/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

§ SCB_ICSR_ISRPENDING_Pos [1/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

§ SCB_ICSR_ISRPENDING_Msk [1/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

§ SCB_ICSR_VECTPENDING_Pos [1/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

§ SCB_ICSR_VECTPENDING_Msk [1/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

§ SCB_ICSR_RETTOBASE_Pos [1/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

§ SCB_ICSR_RETTOBASE_Msk [1/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

§ SCB_ICSR_VECTACTIVE_Pos [1/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

§ SCB_ICSR_VECTACTIVE_Msk [1/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

§ SCB_VTOR_TBLOFF_Pos [1/3]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

§ SCB_VTOR_TBLOFF_Msk [1/3]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

§ SCB_AIRCR_VECTKEY_Pos [1/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Referenced by __NVIC_SetPriorityGrouping(), and __NVIC_SystemReset().

§ SCB_AIRCR_VECTKEY_Msk [1/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Referenced by __NVIC_SetPriorityGrouping(), and __NVIC_SystemReset().

§ SCB_AIRCR_VECTKEYSTAT_Pos [1/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

§ SCB_AIRCR_VECTKEYSTAT_Msk [1/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

§ SCB_AIRCR_ENDIANESS_Pos [1/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

§ SCB_AIRCR_ENDIANESS_Msk [1/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

§ SCB_AIRCR_PRIS_Pos [1/4]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

§ SCB_AIRCR_PRIS_Msk [1/4]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

§ SCB_AIRCR_BFHFNMINS_Pos [1/4]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

§ SCB_AIRCR_BFHFNMINS_Msk [1/4]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

§ SCB_AIRCR_PRIGROUP_Pos [1/3]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Referenced by __NVIC_GetPriorityGrouping(), __NVIC_SetPriorityGrouping(), and __NVIC_SystemReset().

§ SCB_AIRCR_PRIGROUP_Msk [1/3]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Referenced by __NVIC_GetPriorityGrouping(), __NVIC_SetPriorityGrouping(), and __NVIC_SystemReset().

§ SCB_AIRCR_IESB_Pos

#define SCB_AIRCR_IESB_Pos 5U

SCB AIRCR: Implicit ESB Enable Position

§ SCB_AIRCR_IESB_Msk

#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

§ SCB_AIRCR_DIT_Pos

#define SCB_AIRCR_DIT_Pos 4U

SCB AIRCR: Data Independent Timing Position

§ SCB_AIRCR_DIT_Msk

#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

§ SCB_AIRCR_SYSRESETREQS_Pos [1/4]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

§ SCB_AIRCR_SYSRESETREQS_Msk [1/4]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

§ SCB_AIRCR_SYSRESETREQ_Pos [1/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

§ SCB_AIRCR_SYSRESETREQ_Msk [1/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Referenced by __NVIC_SystemReset().

§ SCB_AIRCR_VECTCLRACTIVE_Pos [1/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

§ SCB_AIRCR_VECTCLRACTIVE_Msk [1/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

§ SCB_SCR_SEVONPEND_Pos [1/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

§ SCB_SCR_SEVONPEND_Msk [1/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

§ SCB_SCR_SLEEPDEEPS_Pos [1/4]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

§ SCB_SCR_SLEEPDEEPS_Msk [1/4]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

§ SCB_SCR_SLEEPDEEP_Pos [1/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

§ SCB_SCR_SLEEPDEEP_Msk [1/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

§ SCB_SCR_SLEEPONEXIT_Pos [1/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

§ SCB_SCR_SLEEPONEXIT_Msk [1/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

§ SCB_CCR_TRD_Pos

#define SCB_CCR_TRD_Pos 20U

SCB CCR: TRD Position

§ SCB_CCR_TRD_Msk

#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

§ SCB_CCR_LOB_Pos

#define SCB_CCR_LOB_Pos 19U

SCB CCR: LOB Position

§ SCB_CCR_LOB_Msk

#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

§ SCB_CCR_BP_Pos [1/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

§ SCB_CCR_BP_Msk [1/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

§ SCB_CCR_IC_Pos [1/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

§ SCB_CCR_IC_Msk [1/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

§ SCB_CCR_DC_Pos [1/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

§ SCB_CCR_DC_Msk [1/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

§ SCB_CCR_STKOFHFNMIGN_Pos [1/4]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

§ SCB_CCR_STKOFHFNMIGN_Msk [1/4]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

§ SCB_CCR_BFHFNMIGN_Pos [1/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

§ SCB_CCR_BFHFNMIGN_Msk [1/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

§ SCB_CCR_DIV_0_TRP_Pos [1/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

§ SCB_CCR_DIV_0_TRP_Msk [1/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

§ SCB_CCR_UNALIGN_TRP_Pos [1/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

§ SCB_CCR_UNALIGN_TRP_Msk [1/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

§ SCB_CCR_USERSETMPEND_Pos [1/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

§ SCB_CCR_USERSETMPEND_Msk [1/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

§ SCB_SHCSR_HARDFAULTPENDED_Pos [1/4]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

§ SCB_SHCSR_HARDFAULTPENDED_Msk [1/4]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

§ SCB_SHCSR_SECUREFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

§ SCB_SHCSR_SECUREFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

§ SCB_SHCSR_SECUREFAULTENA_Pos [1/3]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

§ SCB_SHCSR_SECUREFAULTENA_Msk [1/3]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

§ SCB_SHCSR_USGFAULTENA_Pos [1/3]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

§ SCB_SHCSR_USGFAULTENA_Msk [1/3]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

§ SCB_SHCSR_BUSFAULTENA_Pos [1/3]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

§ SCB_SHCSR_BUSFAULTENA_Msk [1/3]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

§ SCB_SHCSR_MEMFAULTENA_Pos [1/3]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

§ SCB_SHCSR_MEMFAULTENA_Msk [1/3]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Referenced by ARM_MPU_Disable(), and ARM_MPU_Enable().

§ SCB_SHCSR_SVCALLPENDED_Pos [1/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

§ SCB_SHCSR_SVCALLPENDED_Msk [1/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

§ SCB_SHCSR_BUSFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

§ SCB_SHCSR_BUSFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

§ SCB_SHCSR_MEMFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

§ SCB_SHCSR_MEMFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

§ SCB_SHCSR_USGFAULTPENDED_Pos [1/3]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

§ SCB_SHCSR_USGFAULTPENDED_Msk [1/3]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

§ SCB_SHCSR_SYSTICKACT_Pos [1/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

§ SCB_SHCSR_SYSTICKACT_Msk [1/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

§ SCB_SHCSR_PENDSVACT_Pos [1/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

§ SCB_SHCSR_PENDSVACT_Msk [1/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

§ SCB_SHCSR_MONITORACT_Pos [1/3]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

§ SCB_SHCSR_MONITORACT_Msk [1/3]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

§ SCB_SHCSR_SVCALLACT_Pos [1/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

§ SCB_SHCSR_SVCALLACT_Msk [1/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

§ SCB_SHCSR_NMIACT_Pos [1/4]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

§ SCB_SHCSR_NMIACT_Msk [1/4]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

§ SCB_SHCSR_SECUREFAULTACT_Pos [1/3]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

§ SCB_SHCSR_SECUREFAULTACT_Msk [1/3]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

§ SCB_SHCSR_USGFAULTACT_Pos [1/3]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

§ SCB_SHCSR_USGFAULTACT_Msk [1/3]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

§ SCB_SHCSR_HARDFAULTACT_Pos [1/4]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

§ SCB_SHCSR_HARDFAULTACT_Msk [1/4]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

§ SCB_SHCSR_BUSFAULTACT_Pos [1/3]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

§ SCB_SHCSR_BUSFAULTACT_Msk [1/3]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

§ SCB_SHCSR_MEMFAULTACT_Pos [1/3]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

§ SCB_SHCSR_MEMFAULTACT_Msk [1/3]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

§ SCB_CFSR_USGFAULTSR_Pos [1/3]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

§ SCB_CFSR_USGFAULTSR_Msk [1/3]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

§ SCB_CFSR_BUSFAULTSR_Pos [1/3]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

§ SCB_CFSR_BUSFAULTSR_Msk [1/3]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

§ SCB_CFSR_MEMFAULTSR_Pos [1/3]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

§ SCB_CFSR_MEMFAULTSR_Msk [1/3]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

§ SCB_CFSR_MMARVALID_Pos [1/3]

#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

§ SCB_CFSR_MMARVALID_Msk [1/3]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

§ SCB_CFSR_MLSPERR_Pos [1/3]

#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

§ SCB_CFSR_MLSPERR_Msk [1/3]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

§ SCB_CFSR_MSTKERR_Pos [1/3]

#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

§ SCB_CFSR_MSTKERR_Msk [1/3]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

§ SCB_CFSR_MUNSTKERR_Pos [1/3]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

§ SCB_CFSR_MUNSTKERR_Msk [1/3]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

§ SCB_CFSR_DACCVIOL_Pos [1/3]

#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

§ SCB_CFSR_DACCVIOL_Msk [1/3]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

§ SCB_CFSR_IACCVIOL_Pos [1/3]

#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

§ SCB_CFSR_IACCVIOL_Msk [1/3]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

§ SCB_CFSR_BFARVALID_Pos [1/3]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

§ SCB_CFSR_BFARVALID_Msk [1/3]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

§ SCB_CFSR_LSPERR_Pos [1/3]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

§ SCB_CFSR_LSPERR_Msk [1/3]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

§ SCB_CFSR_STKERR_Pos [1/3]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

§ SCB_CFSR_STKERR_Msk [1/3]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

§ SCB_CFSR_UNSTKERR_Pos [1/3]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

§ SCB_CFSR_UNSTKERR_Msk [1/3]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

§ SCB_CFSR_IMPRECISERR_Pos [1/3]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

§ SCB_CFSR_IMPRECISERR_Msk [1/3]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

§ SCB_CFSR_PRECISERR_Pos [1/3]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

§ SCB_CFSR_PRECISERR_Msk [1/3]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

§ SCB_CFSR_IBUSERR_Pos [1/3]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

§ SCB_CFSR_IBUSERR_Msk [1/3]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

§ SCB_CFSR_DIVBYZERO_Pos [1/3]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

§ SCB_CFSR_DIVBYZERO_Msk [1/3]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

§ SCB_CFSR_UNALIGNED_Pos [1/3]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

§ SCB_CFSR_UNALIGNED_Msk [1/3]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

§ SCB_CFSR_STKOF_Pos [1/3]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

§ SCB_CFSR_STKOF_Msk [1/3]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

§ SCB_CFSR_NOCP_Pos [1/3]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

§ SCB_CFSR_NOCP_Msk [1/3]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

§ SCB_CFSR_INVPC_Pos [1/3]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

§ SCB_CFSR_INVPC_Msk [1/3]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

§ SCB_CFSR_INVSTATE_Pos [1/3]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

§ SCB_CFSR_INVSTATE_Msk [1/3]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

§ SCB_CFSR_UNDEFINSTR_Pos [1/3]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

§ SCB_CFSR_UNDEFINSTR_Msk [1/3]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

§ SCB_HFSR_DEBUGEVT_Pos [1/3]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

§ SCB_HFSR_DEBUGEVT_Msk [1/3]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

§ SCB_HFSR_FORCED_Pos [1/3]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

§ SCB_HFSR_FORCED_Msk [1/3]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

§ SCB_HFSR_VECTTBL_Pos [1/3]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

§ SCB_HFSR_VECTTBL_Msk [1/3]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

§ SCB_DFSR_PMU_Pos

#define SCB_DFSR_PMU_Pos 5U

SCB DFSR: PMU Position

§ SCB_DFSR_PMU_Msk

#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

§ SCB_DFSR_EXTERNAL_Pos [1/3]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

§ SCB_DFSR_EXTERNAL_Msk [1/3]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

§ SCB_DFSR_VCATCH_Pos [1/3]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

§ SCB_DFSR_VCATCH_Msk [1/3]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

§ SCB_DFSR_DWTTRAP_Pos [1/3]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

§ SCB_DFSR_DWTTRAP_Msk [1/3]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

§ SCB_DFSR_BKPT_Pos [1/3]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

§ SCB_DFSR_BKPT_Msk [1/3]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

§ SCB_DFSR_HALTED_Pos [1/3]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

§ SCB_DFSR_HALTED_Msk [1/3]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

§ SCB_NSACR_CP11_Pos [1/3]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

§ SCB_NSACR_CP11_Msk [1/3]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

§ SCB_NSACR_CP10_Pos [1/3]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

§ SCB_NSACR_CP10_Msk [1/3]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

§ SCB_NSACR_CP7_Pos

#define SCB_NSACR_CP7_Pos 7U

SCB NSACR: CP7 Position

§ SCB_NSACR_CP7_Msk

#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

§ SCB_NSACR_CP6_Pos

#define SCB_NSACR_CP6_Pos 6U

SCB NSACR: CP6 Position

§ SCB_NSACR_CP6_Msk

#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

§ SCB_NSACR_CP5_Pos

#define SCB_NSACR_CP5_Pos 5U

SCB NSACR: CP5 Position

§ SCB_NSACR_CP5_Msk

#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

§ SCB_NSACR_CP4_Pos

#define SCB_NSACR_CP4_Pos 4U

SCB NSACR: CP4 Position

§ SCB_NSACR_CP4_Msk

#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

§ SCB_NSACR_CP3_Pos

#define SCB_NSACR_CP3_Pos 3U

SCB NSACR: CP3 Position

§ SCB_NSACR_CP3_Msk

#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

§ SCB_NSACR_CP2_Pos

#define SCB_NSACR_CP2_Pos 2U

SCB NSACR: CP2 Position

§ SCB_NSACR_CP2_Msk

#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

§ SCB_NSACR_CP1_Pos

#define SCB_NSACR_CP1_Pos 1U

SCB NSACR: CP1 Position

§ SCB_NSACR_CP1_Msk

#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

§ SCB_NSACR_CP0_Pos

#define SCB_NSACR_CP0_Pos 0U

SCB NSACR: CP0 Position

§ SCB_NSACR_CP0_Msk

#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

§ SCB_ID_DFR_UDE_Pos

#define SCB_ID_DFR_UDE_Pos 28U

SCB ID_DFR: UDE Position

§ SCB_ID_DFR_UDE_Msk

#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

§ SCB_ID_DFR_MProfDbg_Pos

#define SCB_ID_DFR_MProfDbg_Pos 20U

SCB ID_DFR: MProfDbg Position

§ SCB_ID_DFR_MProfDbg_Msk

#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

§ SCB_CLIDR_LOUU_Pos [1/3]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

§ SCB_CLIDR_LOUU_Msk [1/3]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

§ SCB_CLIDR_LOC_Pos [1/3]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

§ SCB_CLIDR_LOC_Msk [1/3]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

§ SCB_CTR_FORMAT_Pos [1/3]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

§ SCB_CTR_FORMAT_Msk [1/3]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

§ SCB_CTR_CWG_Pos [1/3]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

§ SCB_CTR_CWG_Msk [1/3]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

§ SCB_CTR_ERG_Pos [1/3]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

§ SCB_CTR_ERG_Msk [1/3]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

§ SCB_CTR_DMINLINE_Pos [1/3]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

§ SCB_CTR_DMINLINE_Msk [1/3]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

§ SCB_CTR_IMINLINE_Pos [1/3]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

§ SCB_CTR_IMINLINE_Msk [1/3]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

§ SCB_CCSIDR_WT_Pos [1/3]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

§ SCB_CCSIDR_WT_Msk [1/3]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

§ SCB_CCSIDR_WB_Pos [1/3]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

§ SCB_CCSIDR_WB_Msk [1/3]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

§ SCB_CCSIDR_RA_Pos [1/3]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

§ SCB_CCSIDR_RA_Msk [1/3]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

§ SCB_CCSIDR_WA_Pos [1/3]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

§ SCB_CCSIDR_WA_Msk [1/3]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

§ SCB_CCSIDR_NUMSETS_Pos [1/3]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

§ SCB_CCSIDR_NUMSETS_Msk [1/3]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

§ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

§ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

§ SCB_CCSIDR_LINESIZE_Pos [1/3]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

§ SCB_CCSIDR_LINESIZE_Msk [1/3]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

§ SCB_CSSELR_LEVEL_Pos [1/3]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

§ SCB_CSSELR_LEVEL_Msk [1/3]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

§ SCB_CSSELR_IND_Pos [1/3]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

§ SCB_CSSELR_IND_Msk [1/3]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

§ SCB_STIR_INTID_Pos [1/3]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

§ SCB_STIR_INTID_Msk [1/3]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

§ SCB_RFSR_V_Pos

#define SCB_RFSR_V_Pos 31U

SCB RFSR: V Position

§ SCB_RFSR_V_Msk

#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

§ SCB_RFSR_IS_Pos

#define SCB_RFSR_IS_Pos 16U

SCB RFSR: IS Position

§ SCB_RFSR_IS_Msk

#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

§ SCB_RFSR_UET_Pos

#define SCB_RFSR_UET_Pos 0U

SCB RFSR: UET Position

§ SCB_RFSR_UET_Msk

#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

§ SCB_DCISW_WAY_Pos [1/3]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

§ SCB_DCISW_WAY_Msk [1/3]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

§ SCB_DCISW_SET_Pos [1/3]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

§ SCB_DCISW_SET_Msk [1/3]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

§ SCB_DCCSW_WAY_Pos [1/3]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

§ SCB_DCCSW_WAY_Msk [1/3]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

§ SCB_DCCSW_SET_Pos [1/3]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

§ SCB_DCCSW_SET_Msk [1/3]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

§ SCB_DCCISW_WAY_Pos [1/3]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

§ SCB_DCCISW_WAY_Msk [1/3]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

§ SCB_DCCISW_SET_Pos [1/3]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

§ SCB_DCCISW_SET_Msk [1/3]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

§ SCB_CPUID_IMPLEMENTER_Pos [2/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

§ SCB_CPUID_IMPLEMENTER_Msk [2/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

§ SCB_CPUID_VARIANT_Pos [2/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

§ SCB_CPUID_VARIANT_Msk [2/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

§ SCB_CPUID_ARCHITECTURE_Pos [2/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

§ SCB_CPUID_ARCHITECTURE_Msk [2/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

§ SCB_CPUID_PARTNO_Pos [2/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

§ SCB_CPUID_PARTNO_Msk [2/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

§ SCB_CPUID_REVISION_Pos [2/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

§ SCB_CPUID_REVISION_Msk [2/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

§ SCB_ICSR_PENDNMISET_Pos [2/4]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

§ SCB_ICSR_PENDNMISET_Msk [2/4]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

§ SCB_ICSR_NMIPENDSET_Pos [2/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

§ SCB_ICSR_NMIPENDSET_Msk [2/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

§ SCB_ICSR_PENDNMICLR_Pos [2/4]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

§ SCB_ICSR_PENDNMICLR_Msk [2/4]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

§ SCB_ICSR_PENDSVSET_Pos [2/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

§ SCB_ICSR_PENDSVSET_Msk [2/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

§ SCB_ICSR_PENDSVCLR_Pos [2/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

§ SCB_ICSR_PENDSVCLR_Msk [2/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

§ SCB_ICSR_PENDSTSET_Pos [2/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

§ SCB_ICSR_PENDSTSET_Msk [2/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

§ SCB_ICSR_PENDSTCLR_Pos [2/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

§ SCB_ICSR_PENDSTCLR_Msk [2/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

§ SCB_ICSR_STTNS_Pos [2/4]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

§ SCB_ICSR_STTNS_Msk [2/4]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

§ SCB_ICSR_ISRPREEMPT_Pos [2/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

§ SCB_ICSR_ISRPREEMPT_Msk [2/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

§ SCB_ICSR_ISRPENDING_Pos [2/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

§ SCB_ICSR_ISRPENDING_Msk [2/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

§ SCB_ICSR_VECTPENDING_Pos [2/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

§ SCB_ICSR_VECTPENDING_Msk [2/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

§ SCB_ICSR_RETTOBASE_Pos [2/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

§ SCB_ICSR_RETTOBASE_Msk [2/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

§ SCB_ICSR_VECTACTIVE_Pos [2/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

§ SCB_ICSR_VECTACTIVE_Msk [2/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

§ SCB_AIRCR_VECTKEY_Pos [2/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

§ SCB_AIRCR_VECTKEY_Msk [2/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

§ SCB_AIRCR_VECTKEYSTAT_Pos [2/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

§ SCB_AIRCR_VECTKEYSTAT_Msk [2/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

§ SCB_AIRCR_ENDIANESS_Pos [2/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

§ SCB_AIRCR_ENDIANESS_Msk [2/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

§ SCB_AIRCR_PRIS_Pos [2/4]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

§ SCB_AIRCR_PRIS_Msk [2/4]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

§ SCB_AIRCR_BFHFNMINS_Pos [2/4]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

§ SCB_AIRCR_BFHFNMINS_Msk [2/4]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

§ SCB_AIRCR_SYSRESETREQS_Pos [2/4]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

§ SCB_AIRCR_SYSRESETREQS_Msk [2/4]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

§ SCB_AIRCR_SYSRESETREQ_Pos [2/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

§ SCB_AIRCR_SYSRESETREQ_Msk [2/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

§ SCB_AIRCR_VECTCLRACTIVE_Pos [2/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

§ SCB_AIRCR_VECTCLRACTIVE_Msk [2/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

§ SCB_SCR_SEVONPEND_Pos [2/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

§ SCB_SCR_SEVONPEND_Msk [2/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

§ SCB_SCR_SLEEPDEEPS_Pos [2/4]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

§ SCB_SCR_SLEEPDEEPS_Msk [2/4]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

§ SCB_SCR_SLEEPDEEP_Pos [2/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

§ SCB_SCR_SLEEPDEEP_Msk [2/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

§ SCB_SCR_SLEEPONEXIT_Pos [2/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

§ SCB_SCR_SLEEPONEXIT_Msk [2/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

§ SCB_CCR_BP_Pos [2/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

§ SCB_CCR_BP_Msk [2/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

§ SCB_CCR_IC_Pos [2/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

§ SCB_CCR_IC_Msk [2/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

§ SCB_CCR_DC_Pos [2/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

§ SCB_CCR_DC_Msk [2/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

§ SCB_CCR_STKOFHFNMIGN_Pos [2/4]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

§ SCB_CCR_STKOFHFNMIGN_Msk [2/4]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

§ SCB_CCR_BFHFNMIGN_Pos [2/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

§ SCB_CCR_BFHFNMIGN_Msk [2/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

§ SCB_CCR_DIV_0_TRP_Pos [2/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

§ SCB_CCR_DIV_0_TRP_Msk [2/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

§ SCB_CCR_UNALIGN_TRP_Pos [2/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

§ SCB_CCR_UNALIGN_TRP_Msk [2/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

§ SCB_CCR_USERSETMPEND_Pos [2/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

§ SCB_CCR_USERSETMPEND_Msk [2/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

§ SCB_SHCSR_HARDFAULTPENDED_Pos [2/4]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

§ SCB_SHCSR_HARDFAULTPENDED_Msk [2/4]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

§ SCB_SHCSR_SVCALLPENDED_Pos [2/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

§ SCB_SHCSR_SVCALLPENDED_Msk [2/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

§ SCB_SHCSR_SYSTICKACT_Pos [2/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

§ SCB_SHCSR_SYSTICKACT_Msk [2/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

§ SCB_SHCSR_PENDSVACT_Pos [2/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

§ SCB_SHCSR_PENDSVACT_Msk [2/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

§ SCB_SHCSR_SVCALLACT_Pos [2/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

§ SCB_SHCSR_SVCALLACT_Msk [2/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

§ SCB_SHCSR_NMIACT_Pos [2/4]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

§ SCB_SHCSR_NMIACT_Msk [2/4]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

§ SCB_SHCSR_HARDFAULTACT_Pos [2/4]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

§ SCB_SHCSR_HARDFAULTACT_Msk [2/4]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

§ SCB_CPUID_IMPLEMENTER_Pos [3/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

§ SCB_CPUID_IMPLEMENTER_Msk [3/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

§ SCB_CPUID_VARIANT_Pos [3/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

§ SCB_CPUID_VARIANT_Msk [3/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

§ SCB_CPUID_ARCHITECTURE_Pos [3/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

§ SCB_CPUID_ARCHITECTURE_Msk [3/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

§ SCB_CPUID_PARTNO_Pos [3/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

§ SCB_CPUID_PARTNO_Msk [3/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

§ SCB_CPUID_REVISION_Pos [3/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

§ SCB_CPUID_REVISION_Msk [3/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

§ SCB_ICSR_PENDNMISET_Pos [3/4]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

§ SCB_ICSR_PENDNMISET_Msk [3/4]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

§ SCB_ICSR_NMIPENDSET_Pos [3/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

§ SCB_ICSR_NMIPENDSET_Msk [3/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

§ SCB_ICSR_PENDNMICLR_Pos [3/4]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

§ SCB_ICSR_PENDNMICLR_Msk [3/4]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

§ SCB_ICSR_PENDSVSET_Pos [3/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

§ SCB_ICSR_PENDSVSET_Msk [3/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

§ SCB_ICSR_PENDSVCLR_Pos [3/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

§ SCB_ICSR_PENDSVCLR_Msk [3/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

§ SCB_ICSR_PENDSTSET_Pos [3/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

§ SCB_ICSR_PENDSTSET_Msk [3/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

§ SCB_ICSR_PENDSTCLR_Pos [3/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

§ SCB_ICSR_PENDSTCLR_Msk [3/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

§ SCB_ICSR_STTNS_Pos [3/4]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

§ SCB_ICSR_STTNS_Msk [3/4]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

§ SCB_ICSR_ISRPREEMPT_Pos [3/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

§ SCB_ICSR_ISRPREEMPT_Msk [3/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

§ SCB_ICSR_ISRPENDING_Pos [3/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

§ SCB_ICSR_ISRPENDING_Msk [3/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

§ SCB_ICSR_VECTPENDING_Pos [3/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

§ SCB_ICSR_VECTPENDING_Msk [3/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

§ SCB_ICSR_RETTOBASE_Pos [3/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

§ SCB_ICSR_RETTOBASE_Msk [3/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

§ SCB_ICSR_VECTACTIVE_Pos [3/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

§ SCB_ICSR_VECTACTIVE_Msk [3/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

§ SCB_VTOR_TBLOFF_Pos [2/3]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

§ SCB_VTOR_TBLOFF_Msk [2/3]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

§ SCB_AIRCR_VECTKEY_Pos [3/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

§ SCB_AIRCR_VECTKEY_Msk [3/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

§ SCB_AIRCR_VECTKEYSTAT_Pos [3/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

§ SCB_AIRCR_VECTKEYSTAT_Msk [3/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

§ SCB_AIRCR_ENDIANESS_Pos [3/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

§ SCB_AIRCR_ENDIANESS_Msk [3/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

§ SCB_AIRCR_PRIS_Pos [3/4]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

§ SCB_AIRCR_PRIS_Msk [3/4]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

§ SCB_AIRCR_BFHFNMINS_Pos [3/4]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

§ SCB_AIRCR_BFHFNMINS_Msk [3/4]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

§ SCB_AIRCR_PRIGROUP_Pos [2/3]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

§ SCB_AIRCR_PRIGROUP_Msk [2/3]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

§ SCB_AIRCR_SYSRESETREQS_Pos [3/4]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

§ SCB_AIRCR_SYSRESETREQS_Msk [3/4]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

§ SCB_AIRCR_SYSRESETREQ_Pos [3/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

§ SCB_AIRCR_SYSRESETREQ_Msk [3/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

§ SCB_AIRCR_VECTCLRACTIVE_Pos [3/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

§ SCB_AIRCR_VECTCLRACTIVE_Msk [3/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

§ SCB_SCR_SEVONPEND_Pos [3/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

§ SCB_SCR_SEVONPEND_Msk [3/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

§ SCB_SCR_SLEEPDEEPS_Pos [3/4]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

§ SCB_SCR_SLEEPDEEPS_Msk [3/4]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

§ SCB_SCR_SLEEPDEEP_Pos [3/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

§ SCB_SCR_SLEEPDEEP_Msk [3/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

§ SCB_SCR_SLEEPONEXIT_Pos [3/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

§ SCB_SCR_SLEEPONEXIT_Msk [3/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

§ SCB_CCR_BP_Pos [3/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

§ SCB_CCR_BP_Msk [3/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

§ SCB_CCR_IC_Pos [3/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

§ SCB_CCR_IC_Msk [3/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

§ SCB_CCR_DC_Pos [3/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

§ SCB_CCR_DC_Msk [3/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

§ SCB_CCR_STKOFHFNMIGN_Pos [3/4]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

§ SCB_CCR_STKOFHFNMIGN_Msk [3/4]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

§ SCB_CCR_BFHFNMIGN_Pos [3/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

§ SCB_CCR_BFHFNMIGN_Msk [3/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

§ SCB_CCR_DIV_0_TRP_Pos [3/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

§ SCB_CCR_DIV_0_TRP_Msk [3/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

§ SCB_CCR_UNALIGN_TRP_Pos [3/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

§ SCB_CCR_UNALIGN_TRP_Msk [3/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

§ SCB_CCR_USERSETMPEND_Pos [3/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

§ SCB_CCR_USERSETMPEND_Msk [3/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

§ SCB_SHCSR_HARDFAULTPENDED_Pos [3/4]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

§ SCB_SHCSR_HARDFAULTPENDED_Msk [3/4]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

§ SCB_SHCSR_SECUREFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

§ SCB_SHCSR_SECUREFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

§ SCB_SHCSR_SECUREFAULTENA_Pos [2/3]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

§ SCB_SHCSR_SECUREFAULTENA_Msk [2/3]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

§ SCB_SHCSR_USGFAULTENA_Pos [2/3]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

§ SCB_SHCSR_USGFAULTENA_Msk [2/3]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

§ SCB_SHCSR_BUSFAULTENA_Pos [2/3]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

§ SCB_SHCSR_BUSFAULTENA_Msk [2/3]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

§ SCB_SHCSR_MEMFAULTENA_Pos [2/3]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

§ SCB_SHCSR_MEMFAULTENA_Msk [2/3]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

§ SCB_SHCSR_SVCALLPENDED_Pos [3/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

§ SCB_SHCSR_SVCALLPENDED_Msk [3/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

§ SCB_SHCSR_BUSFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

§ SCB_SHCSR_BUSFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

§ SCB_SHCSR_MEMFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

§ SCB_SHCSR_MEMFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

§ SCB_SHCSR_USGFAULTPENDED_Pos [2/3]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

§ SCB_SHCSR_USGFAULTPENDED_Msk [2/3]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

§ SCB_SHCSR_SYSTICKACT_Pos [3/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

§ SCB_SHCSR_SYSTICKACT_Msk [3/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

§ SCB_SHCSR_PENDSVACT_Pos [3/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

§ SCB_SHCSR_PENDSVACT_Msk [3/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

§ SCB_SHCSR_MONITORACT_Pos [2/3]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

§ SCB_SHCSR_MONITORACT_Msk [2/3]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

§ SCB_SHCSR_SVCALLACT_Pos [3/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

§ SCB_SHCSR_SVCALLACT_Msk [3/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

§ SCB_SHCSR_NMIACT_Pos [3/4]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

§ SCB_SHCSR_NMIACT_Msk [3/4]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

§ SCB_SHCSR_SECUREFAULTACT_Pos [2/3]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

§ SCB_SHCSR_SECUREFAULTACT_Msk [2/3]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

§ SCB_SHCSR_USGFAULTACT_Pos [2/3]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

§ SCB_SHCSR_USGFAULTACT_Msk [2/3]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

§ SCB_SHCSR_HARDFAULTACT_Pos [3/4]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

§ SCB_SHCSR_HARDFAULTACT_Msk [3/4]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

§ SCB_SHCSR_BUSFAULTACT_Pos [2/3]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

§ SCB_SHCSR_BUSFAULTACT_Msk [2/3]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

§ SCB_SHCSR_MEMFAULTACT_Pos [2/3]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

§ SCB_SHCSR_MEMFAULTACT_Msk [2/3]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

§ SCB_CFSR_USGFAULTSR_Pos [2/3]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

§ SCB_CFSR_USGFAULTSR_Msk [2/3]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

§ SCB_CFSR_BUSFAULTSR_Pos [2/3]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

§ SCB_CFSR_BUSFAULTSR_Msk [2/3]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

§ SCB_CFSR_MEMFAULTSR_Pos [2/3]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

§ SCB_CFSR_MEMFAULTSR_Msk [2/3]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

§ SCB_CFSR_MMARVALID_Pos [2/3]

#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

§ SCB_CFSR_MMARVALID_Msk [2/3]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

§ SCB_CFSR_MLSPERR_Pos [2/3]

#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

§ SCB_CFSR_MLSPERR_Msk [2/3]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

§ SCB_CFSR_MSTKERR_Pos [2/3]

#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

§ SCB_CFSR_MSTKERR_Msk [2/3]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

§ SCB_CFSR_MUNSTKERR_Pos [2/3]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

§ SCB_CFSR_MUNSTKERR_Msk [2/3]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

§ SCB_CFSR_DACCVIOL_Pos [2/3]

#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

§ SCB_CFSR_DACCVIOL_Msk [2/3]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

§ SCB_CFSR_IACCVIOL_Pos [2/3]

#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

§ SCB_CFSR_IACCVIOL_Msk [2/3]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

§ SCB_CFSR_BFARVALID_Pos [2/3]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

§ SCB_CFSR_BFARVALID_Msk [2/3]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

§ SCB_CFSR_LSPERR_Pos [2/3]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

§ SCB_CFSR_LSPERR_Msk [2/3]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

§ SCB_CFSR_STKERR_Pos [2/3]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

§ SCB_CFSR_STKERR_Msk [2/3]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

§ SCB_CFSR_UNSTKERR_Pos [2/3]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

§ SCB_CFSR_UNSTKERR_Msk [2/3]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

§ SCB_CFSR_IMPRECISERR_Pos [2/3]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

§ SCB_CFSR_IMPRECISERR_Msk [2/3]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

§ SCB_CFSR_PRECISERR_Pos [2/3]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

§ SCB_CFSR_PRECISERR_Msk [2/3]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

§ SCB_CFSR_IBUSERR_Pos [2/3]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

§ SCB_CFSR_IBUSERR_Msk [2/3]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

§ SCB_CFSR_DIVBYZERO_Pos [2/3]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

§ SCB_CFSR_DIVBYZERO_Msk [2/3]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

§ SCB_CFSR_UNALIGNED_Pos [2/3]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

§ SCB_CFSR_UNALIGNED_Msk [2/3]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

§ SCB_CFSR_STKOF_Pos [2/3]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

§ SCB_CFSR_STKOF_Msk [2/3]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

§ SCB_CFSR_NOCP_Pos [2/3]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

§ SCB_CFSR_NOCP_Msk [2/3]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

§ SCB_CFSR_INVPC_Pos [2/3]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

§ SCB_CFSR_INVPC_Msk [2/3]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

§ SCB_CFSR_INVSTATE_Pos [2/3]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

§ SCB_CFSR_INVSTATE_Msk [2/3]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

§ SCB_CFSR_UNDEFINSTR_Pos [2/3]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

§ SCB_CFSR_UNDEFINSTR_Msk [2/3]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

§ SCB_HFSR_DEBUGEVT_Pos [2/3]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

§ SCB_HFSR_DEBUGEVT_Msk [2/3]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

§ SCB_HFSR_FORCED_Pos [2/3]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

§ SCB_HFSR_FORCED_Msk [2/3]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

§ SCB_HFSR_VECTTBL_Pos [2/3]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

§ SCB_HFSR_VECTTBL_Msk [2/3]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

§ SCB_DFSR_EXTERNAL_Pos [2/3]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

§ SCB_DFSR_EXTERNAL_Msk [2/3]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

§ SCB_DFSR_VCATCH_Pos [2/3]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

§ SCB_DFSR_VCATCH_Msk [2/3]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

§ SCB_DFSR_DWTTRAP_Pos [2/3]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

§ SCB_DFSR_DWTTRAP_Msk [2/3]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

§ SCB_DFSR_BKPT_Pos [2/3]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

§ SCB_DFSR_BKPT_Msk [2/3]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

§ SCB_DFSR_HALTED_Pos [2/3]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

§ SCB_DFSR_HALTED_Msk [2/3]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

§ SCB_NSACR_CP11_Pos [2/3]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

§ SCB_NSACR_CP11_Msk [2/3]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

§ SCB_NSACR_CP10_Pos [2/3]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

§ SCB_NSACR_CP10_Msk [2/3]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

§ SCB_NSACR_CPn_Pos [1/2]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

§ SCB_NSACR_CPn_Msk [1/2]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

§ SCB_CLIDR_LOUU_Pos [2/3]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

§ SCB_CLIDR_LOUU_Msk [2/3]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

§ SCB_CLIDR_LOC_Pos [2/3]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

§ SCB_CLIDR_LOC_Msk [2/3]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

§ SCB_CTR_FORMAT_Pos [2/3]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

§ SCB_CTR_FORMAT_Msk [2/3]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

§ SCB_CTR_CWG_Pos [2/3]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

§ SCB_CTR_CWG_Msk [2/3]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

§ SCB_CTR_ERG_Pos [2/3]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

§ SCB_CTR_ERG_Msk [2/3]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

§ SCB_CTR_DMINLINE_Pos [2/3]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

§ SCB_CTR_DMINLINE_Msk [2/3]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

§ SCB_CTR_IMINLINE_Pos [2/3]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

§ SCB_CTR_IMINLINE_Msk [2/3]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

§ SCB_CCSIDR_WT_Pos [2/3]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

§ SCB_CCSIDR_WT_Msk [2/3]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

§ SCB_CCSIDR_WB_Pos [2/3]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

§ SCB_CCSIDR_WB_Msk [2/3]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

§ SCB_CCSIDR_RA_Pos [2/3]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

§ SCB_CCSIDR_RA_Msk [2/3]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

§ SCB_CCSIDR_WA_Pos [2/3]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

§ SCB_CCSIDR_WA_Msk [2/3]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

§ SCB_CCSIDR_NUMSETS_Pos [2/3]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

§ SCB_CCSIDR_NUMSETS_Msk [2/3]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

§ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

§ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

§ SCB_CCSIDR_LINESIZE_Pos [2/3]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

§ SCB_CCSIDR_LINESIZE_Msk [2/3]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

§ SCB_CSSELR_LEVEL_Pos [2/3]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

§ SCB_CSSELR_LEVEL_Msk [2/3]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

§ SCB_CSSELR_IND_Pos [2/3]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

§ SCB_CSSELR_IND_Msk [2/3]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

§ SCB_STIR_INTID_Pos [2/3]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

§ SCB_STIR_INTID_Msk [2/3]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

§ SCB_DCISW_WAY_Pos [2/3]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

§ SCB_DCISW_WAY_Msk [2/3]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

§ SCB_DCISW_SET_Pos [2/3]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

§ SCB_DCISW_SET_Msk [2/3]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

§ SCB_DCCSW_WAY_Pos [2/3]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

§ SCB_DCCSW_WAY_Msk [2/3]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

§ SCB_DCCSW_SET_Pos [2/3]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

§ SCB_DCCSW_SET_Msk [2/3]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

§ SCB_DCCISW_WAY_Pos [2/3]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

§ SCB_DCCISW_WAY_Msk [2/3]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

§ SCB_DCCISW_SET_Pos [2/3]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

§ SCB_DCCISW_SET_Msk [2/3]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

§ SCB_CPUID_IMPLEMENTER_Pos [4/4]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

§ SCB_CPUID_IMPLEMENTER_Msk [4/4]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

§ SCB_CPUID_VARIANT_Pos [4/4]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

§ SCB_CPUID_VARIANT_Msk [4/4]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

§ SCB_CPUID_ARCHITECTURE_Pos [4/4]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

§ SCB_CPUID_ARCHITECTURE_Msk [4/4]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

§ SCB_CPUID_PARTNO_Pos [4/4]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

§ SCB_CPUID_PARTNO_Msk [4/4]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

§ SCB_CPUID_REVISION_Pos [4/4]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

§ SCB_CPUID_REVISION_Msk [4/4]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

§ SCB_ICSR_PENDNMISET_Pos [4/4]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

§ SCB_ICSR_PENDNMISET_Msk [4/4]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

§ SCB_ICSR_NMIPENDSET_Pos [4/4]

#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

§ SCB_ICSR_NMIPENDSET_Msk [4/4]

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

§ SCB_ICSR_PENDNMICLR_Pos [4/4]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

§ SCB_ICSR_PENDNMICLR_Msk [4/4]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

§ SCB_ICSR_PENDSVSET_Pos [4/4]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

§ SCB_ICSR_PENDSVSET_Msk [4/4]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

§ SCB_ICSR_PENDSVCLR_Pos [4/4]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

§ SCB_ICSR_PENDSVCLR_Msk [4/4]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

§ SCB_ICSR_PENDSTSET_Pos [4/4]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

§ SCB_ICSR_PENDSTSET_Msk [4/4]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

§ SCB_ICSR_PENDSTCLR_Pos [4/4]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

§ SCB_ICSR_PENDSTCLR_Msk [4/4]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

§ SCB_ICSR_STTNS_Pos [4/4]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

§ SCB_ICSR_STTNS_Msk [4/4]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

§ SCB_ICSR_ISRPREEMPT_Pos [4/4]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

§ SCB_ICSR_ISRPREEMPT_Msk [4/4]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

§ SCB_ICSR_ISRPENDING_Pos [4/4]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

§ SCB_ICSR_ISRPENDING_Msk [4/4]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

§ SCB_ICSR_VECTPENDING_Pos [4/4]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

§ SCB_ICSR_VECTPENDING_Msk [4/4]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

§ SCB_ICSR_RETTOBASE_Pos [4/4]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

§ SCB_ICSR_RETTOBASE_Msk [4/4]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

§ SCB_ICSR_VECTACTIVE_Pos [4/4]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

§ SCB_ICSR_VECTACTIVE_Msk [4/4]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

§ SCB_VTOR_TBLOFF_Pos [3/3]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

§ SCB_VTOR_TBLOFF_Msk [3/3]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

§ SCB_AIRCR_VECTKEY_Pos [4/4]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

§ SCB_AIRCR_VECTKEY_Msk [4/4]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

§ SCB_AIRCR_VECTKEYSTAT_Pos [4/4]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

§ SCB_AIRCR_VECTKEYSTAT_Msk [4/4]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

§ SCB_AIRCR_ENDIANESS_Pos [4/4]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

§ SCB_AIRCR_ENDIANESS_Msk [4/4]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

§ SCB_AIRCR_PRIS_Pos [4/4]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

§ SCB_AIRCR_PRIS_Msk [4/4]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

§ SCB_AIRCR_BFHFNMINS_Pos [4/4]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

§ SCB_AIRCR_BFHFNMINS_Msk [4/4]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

§ SCB_AIRCR_PRIGROUP_Pos [3/3]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

§ SCB_AIRCR_PRIGROUP_Msk [3/3]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

§ SCB_AIRCR_SYSRESETREQS_Pos [4/4]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

§ SCB_AIRCR_SYSRESETREQS_Msk [4/4]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

§ SCB_AIRCR_SYSRESETREQ_Pos [4/4]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

§ SCB_AIRCR_SYSRESETREQ_Msk [4/4]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

§ SCB_AIRCR_VECTCLRACTIVE_Pos [4/4]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

§ SCB_AIRCR_VECTCLRACTIVE_Msk [4/4]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

§ SCB_SCR_SEVONPEND_Pos [4/4]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

§ SCB_SCR_SEVONPEND_Msk [4/4]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

§ SCB_SCR_SLEEPDEEPS_Pos [4/4]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

§ SCB_SCR_SLEEPDEEPS_Msk [4/4]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

§ SCB_SCR_SLEEPDEEP_Pos [4/4]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

§ SCB_SCR_SLEEPDEEP_Msk [4/4]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

§ SCB_SCR_SLEEPONEXIT_Pos [4/4]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

§ SCB_SCR_SLEEPONEXIT_Msk [4/4]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

§ SCB_CCR_BP_Pos [4/4]

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

§ SCB_CCR_BP_Msk [4/4]

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

§ SCB_CCR_IC_Pos [4/4]

#define SCB_CCR_IC_Pos 17U

SCB CCR: IC Position

§ SCB_CCR_IC_Msk [4/4]

#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

§ SCB_CCR_DC_Pos [4/4]

#define SCB_CCR_DC_Pos 16U

SCB CCR: DC Position

§ SCB_CCR_DC_Msk [4/4]

#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

§ SCB_CCR_STKOFHFNMIGN_Pos [4/4]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

§ SCB_CCR_STKOFHFNMIGN_Msk [4/4]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

§ SCB_CCR_BFHFNMIGN_Pos [4/4]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

§ SCB_CCR_BFHFNMIGN_Msk [4/4]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

§ SCB_CCR_DIV_0_TRP_Pos [4/4]

#define SCB_CCR_DIV_0_TRP_Pos 4U

SCB CCR: DIV_0_TRP Position

§ SCB_CCR_DIV_0_TRP_Msk [4/4]

#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

§ SCB_CCR_UNALIGN_TRP_Pos [4/4]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

§ SCB_CCR_UNALIGN_TRP_Msk [4/4]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

§ SCB_CCR_USERSETMPEND_Pos [4/4]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

§ SCB_CCR_USERSETMPEND_Msk [4/4]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

§ SCB_SHCSR_HARDFAULTPENDED_Pos [4/4]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

§ SCB_SHCSR_HARDFAULTPENDED_Msk [4/4]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

§ SCB_SHCSR_SECUREFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

§ SCB_SHCSR_SECUREFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

§ SCB_SHCSR_SECUREFAULTENA_Pos [3/3]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

§ SCB_SHCSR_SECUREFAULTENA_Msk [3/3]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

§ SCB_SHCSR_USGFAULTENA_Pos [3/3]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

§ SCB_SHCSR_USGFAULTENA_Msk [3/3]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

§ SCB_SHCSR_BUSFAULTENA_Pos [3/3]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

§ SCB_SHCSR_BUSFAULTENA_Msk [3/3]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

§ SCB_SHCSR_MEMFAULTENA_Pos [3/3]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

§ SCB_SHCSR_MEMFAULTENA_Msk [3/3]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

§ SCB_SHCSR_SVCALLPENDED_Pos [4/4]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

§ SCB_SHCSR_SVCALLPENDED_Msk [4/4]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

§ SCB_SHCSR_BUSFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

§ SCB_SHCSR_BUSFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

§ SCB_SHCSR_MEMFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

§ SCB_SHCSR_MEMFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

§ SCB_SHCSR_USGFAULTPENDED_Pos [3/3]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

§ SCB_SHCSR_USGFAULTPENDED_Msk [3/3]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

§ SCB_SHCSR_SYSTICKACT_Pos [4/4]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

§ SCB_SHCSR_SYSTICKACT_Msk [4/4]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

§ SCB_SHCSR_PENDSVACT_Pos [4/4]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

§ SCB_SHCSR_PENDSVACT_Msk [4/4]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

§ SCB_SHCSR_MONITORACT_Pos [3/3]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

§ SCB_SHCSR_MONITORACT_Msk [3/3]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

§ SCB_SHCSR_SVCALLACT_Pos [4/4]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

§ SCB_SHCSR_SVCALLACT_Msk [4/4]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

§ SCB_SHCSR_NMIACT_Pos [4/4]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

§ SCB_SHCSR_NMIACT_Msk [4/4]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

§ SCB_SHCSR_SECUREFAULTACT_Pos [3/3]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

§ SCB_SHCSR_SECUREFAULTACT_Msk [3/3]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

§ SCB_SHCSR_USGFAULTACT_Pos [3/3]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

§ SCB_SHCSR_USGFAULTACT_Msk [3/3]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

§ SCB_SHCSR_HARDFAULTACT_Pos [4/4]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

§ SCB_SHCSR_HARDFAULTACT_Msk [4/4]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

§ SCB_SHCSR_BUSFAULTACT_Pos [3/3]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

§ SCB_SHCSR_BUSFAULTACT_Msk [3/3]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

§ SCB_SHCSR_MEMFAULTACT_Pos [3/3]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

§ SCB_SHCSR_MEMFAULTACT_Msk [3/3]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

§ SCB_CFSR_USGFAULTSR_Pos [3/3]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

§ SCB_CFSR_USGFAULTSR_Msk [3/3]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

§ SCB_CFSR_BUSFAULTSR_Pos [3/3]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

§ SCB_CFSR_BUSFAULTSR_Msk [3/3]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

§ SCB_CFSR_MEMFAULTSR_Pos [3/3]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

§ SCB_CFSR_MEMFAULTSR_Msk [3/3]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

§ SCB_CFSR_MMARVALID_Pos [3/3]

#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

§ SCB_CFSR_MMARVALID_Msk [3/3]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

§ SCB_CFSR_MLSPERR_Pos [3/3]

#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

§ SCB_CFSR_MLSPERR_Msk [3/3]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

§ SCB_CFSR_MSTKERR_Pos [3/3]

#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

§ SCB_CFSR_MSTKERR_Msk [3/3]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

§ SCB_CFSR_MUNSTKERR_Pos [3/3]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

§ SCB_CFSR_MUNSTKERR_Msk [3/3]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

§ SCB_CFSR_DACCVIOL_Pos [3/3]

#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

§ SCB_CFSR_DACCVIOL_Msk [3/3]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

§ SCB_CFSR_IACCVIOL_Pos [3/3]

#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

§ SCB_CFSR_IACCVIOL_Msk [3/3]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

§ SCB_CFSR_BFARVALID_Pos [3/3]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

§ SCB_CFSR_BFARVALID_Msk [3/3]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

§ SCB_CFSR_LSPERR_Pos [3/3]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

§ SCB_CFSR_LSPERR_Msk [3/3]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

§ SCB_CFSR_STKERR_Pos [3/3]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

§ SCB_CFSR_STKERR_Msk [3/3]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

§ SCB_CFSR_UNSTKERR_Pos [3/3]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

§ SCB_CFSR_UNSTKERR_Msk [3/3]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

§ SCB_CFSR_IMPRECISERR_Pos [3/3]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

§ SCB_CFSR_IMPRECISERR_Msk [3/3]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

§ SCB_CFSR_PRECISERR_Pos [3/3]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

§ SCB_CFSR_PRECISERR_Msk [3/3]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

§ SCB_CFSR_IBUSERR_Pos [3/3]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

§ SCB_CFSR_IBUSERR_Msk [3/3]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

§ SCB_CFSR_DIVBYZERO_Pos [3/3]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

§ SCB_CFSR_DIVBYZERO_Msk [3/3]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

§ SCB_CFSR_UNALIGNED_Pos [3/3]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

§ SCB_CFSR_UNALIGNED_Msk [3/3]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

§ SCB_CFSR_STKOF_Pos [3/3]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

§ SCB_CFSR_STKOF_Msk [3/3]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

§ SCB_CFSR_NOCP_Pos [3/3]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

§ SCB_CFSR_NOCP_Msk [3/3]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

§ SCB_CFSR_INVPC_Pos [3/3]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

§ SCB_CFSR_INVPC_Msk [3/3]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

§ SCB_CFSR_INVSTATE_Pos [3/3]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

§ SCB_CFSR_INVSTATE_Msk [3/3]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

§ SCB_CFSR_UNDEFINSTR_Pos [3/3]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

§ SCB_CFSR_UNDEFINSTR_Msk [3/3]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

§ SCB_HFSR_DEBUGEVT_Pos [3/3]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

§ SCB_HFSR_DEBUGEVT_Msk [3/3]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

§ SCB_HFSR_FORCED_Pos [3/3]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

§ SCB_HFSR_FORCED_Msk [3/3]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

§ SCB_HFSR_VECTTBL_Pos [3/3]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

§ SCB_HFSR_VECTTBL_Msk [3/3]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

§ SCB_DFSR_EXTERNAL_Pos [3/3]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

§ SCB_DFSR_EXTERNAL_Msk [3/3]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

§ SCB_DFSR_VCATCH_Pos [3/3]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

§ SCB_DFSR_VCATCH_Msk [3/3]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

§ SCB_DFSR_DWTTRAP_Pos [3/3]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

§ SCB_DFSR_DWTTRAP_Msk [3/3]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

§ SCB_DFSR_BKPT_Pos [3/3]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

§ SCB_DFSR_BKPT_Msk [3/3]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

§ SCB_DFSR_HALTED_Pos [3/3]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

§ SCB_DFSR_HALTED_Msk [3/3]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

§ SCB_NSACR_CP11_Pos [3/3]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

§ SCB_NSACR_CP11_Msk [3/3]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

§ SCB_NSACR_CP10_Pos [3/3]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

§ SCB_NSACR_CP10_Msk [3/3]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

§ SCB_NSACR_CPn_Pos [2/2]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

§ SCB_NSACR_CPn_Msk [2/2]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

§ SCB_CLIDR_LOUU_Pos [3/3]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

§ SCB_CLIDR_LOUU_Msk [3/3]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

§ SCB_CLIDR_LOC_Pos [3/3]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

§ SCB_CLIDR_LOC_Msk [3/3]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

§ SCB_CTR_FORMAT_Pos [3/3]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

§ SCB_CTR_FORMAT_Msk [3/3]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

§ SCB_CTR_CWG_Pos [3/3]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

§ SCB_CTR_CWG_Msk [3/3]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

§ SCB_CTR_ERG_Pos [3/3]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

§ SCB_CTR_ERG_Msk [3/3]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

§ SCB_CTR_DMINLINE_Pos [3/3]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

§ SCB_CTR_DMINLINE_Msk [3/3]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

§ SCB_CTR_IMINLINE_Pos [3/3]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

§ SCB_CTR_IMINLINE_Msk [3/3]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

§ SCB_CCSIDR_WT_Pos [3/3]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

§ SCB_CCSIDR_WT_Msk [3/3]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

§ SCB_CCSIDR_WB_Pos [3/3]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

§ SCB_CCSIDR_WB_Msk [3/3]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

§ SCB_CCSIDR_RA_Pos [3/3]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

§ SCB_CCSIDR_RA_Msk [3/3]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

§ SCB_CCSIDR_WA_Pos [3/3]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

§ SCB_CCSIDR_WA_Msk [3/3]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

§ SCB_CCSIDR_NUMSETS_Pos [3/3]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

§ SCB_CCSIDR_NUMSETS_Msk [3/3]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

§ SCB_CCSIDR_ASSOCIATIVITY_Pos [3/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

§ SCB_CCSIDR_ASSOCIATIVITY_Msk [3/3]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

§ SCB_CCSIDR_LINESIZE_Pos [3/3]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

§ SCB_CCSIDR_LINESIZE_Msk [3/3]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

§ SCB_CSSELR_LEVEL_Pos [3/3]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

§ SCB_CSSELR_LEVEL_Msk [3/3]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

§ SCB_CSSELR_IND_Pos [3/3]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

§ SCB_CSSELR_IND_Msk [3/3]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

§ SCB_STIR_INTID_Pos [3/3]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

§ SCB_STIR_INTID_Msk [3/3]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

§ SCB_DCISW_WAY_Pos [3/3]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

§ SCB_DCISW_WAY_Msk [3/3]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

§ SCB_DCISW_SET_Pos [3/3]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

§ SCB_DCISW_SET_Msk [3/3]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

§ SCB_DCCSW_WAY_Pos [3/3]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

§ SCB_DCCSW_WAY_Msk [3/3]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

§ SCB_DCCSW_SET_Pos [3/3]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

§ SCB_DCCSW_SET_Msk [3/3]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

§ SCB_DCCISW_WAY_Pos [3/3]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

§ SCB_DCCISW_WAY_Msk [3/3]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

§ SCB_DCCISW_SET_Pos [3/3]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

§ SCB_DCCISW_SET_Msk [3/3]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Data Structures

Macros

Detailed Description

Macro Definition Documentation

§ SCB_CPUID_IMPLEMENTER_Pos [1/4]

§ SCB_CPUID_IMPLEMENTER_Msk [1/4]

§ SCB_CPUID_VARIANT_Pos [1/4]

§ SCB_CPUID_VARIANT_Msk [1/4]

§ SCB_CPUID_ARCHITECTURE_Pos [1/4]

§ SCB_CPUID_ARCHITECTURE_Msk [1/4]

§ SCB_CPUID_PARTNO_Pos [1/4]

§ SCB_CPUID_PARTNO_Msk [1/4]

§ SCB_CPUID_REVISION_Pos [1/4]

§ SCB_CPUID_REVISION_Msk [1/4]

§ SCB_ICSR_PENDNMISET_Pos [1/4]

§ SCB_ICSR_PENDNMISET_Msk [1/4]

§ SCB_ICSR_NMIPENDSET_Pos [1/4]

§ SCB_ICSR_NMIPENDSET_Msk [1/4]

§ SCB_ICSR_PENDNMICLR_Pos [1/4]

§ SCB_ICSR_PENDNMICLR_Msk [1/4]

§ SCB_ICSR_PENDSVSET_Pos [1/4]

§ SCB_ICSR_PENDSVSET_Msk [1/4]

§ SCB_ICSR_PENDSVCLR_Pos [1/4]

§ SCB_ICSR_PENDSVCLR_Msk [1/4]

§ SCB_ICSR_PENDSTSET_Pos [1/4]

§ SCB_ICSR_PENDSTSET_Msk [1/4]

§ SCB_ICSR_PENDSTCLR_Pos [1/4]

§ SCB_ICSR_PENDSTCLR_Msk [1/4]

§ SCB_ICSR_STTNS_Pos [1/4]

§ SCB_ICSR_STTNS_Msk [1/4]

§ SCB_ICSR_ISRPREEMPT_Pos [1/4]

§ SCB_ICSR_ISRPREEMPT_Msk [1/4]

§ SCB_ICSR_ISRPENDING_Pos [1/4]

§ SCB_ICSR_ISRPENDING_Msk [1/4]

§ SCB_ICSR_VECTPENDING_Pos [1/4]

§ SCB_ICSR_VECTPENDING_Msk [1/4]

§ SCB_ICSR_RETTOBASE_Pos [1/4]

§ SCB_ICSR_RETTOBASE_Msk [1/4]

§ SCB_ICSR_VECTACTIVE_Pos [1/4]

§ SCB_ICSR_VECTACTIVE_Msk [1/4]

§ SCB_VTOR_TBLOFF_Pos [1/3]

§ SCB_VTOR_TBLOFF_Msk [1/3]

§ SCB_AIRCR_VECTKEY_Pos [1/4]

§ SCB_AIRCR_VECTKEY_Msk [1/4]

§ SCB_AIRCR_VECTKEYSTAT_Pos [1/4]

§ SCB_AIRCR_VECTKEYSTAT_Msk [1/4]

§ SCB_AIRCR_ENDIANESS_Pos [1/4]

§ SCB_AIRCR_ENDIANESS_Msk [1/4]

§ SCB_AIRCR_PRIS_Pos [1/4]

§ SCB_AIRCR_PRIS_Msk [1/4]

§ SCB_AIRCR_BFHFNMINS_Pos [1/4]

§ SCB_AIRCR_BFHFNMINS_Msk [1/4]

§ SCB_AIRCR_PRIGROUP_Pos [1/3]

§ SCB_AIRCR_PRIGROUP_Msk [1/3]

§ SCB_AIRCR_IESB_Pos

§ SCB_AIRCR_IESB_Msk

§ SCB_AIRCR_DIT_Pos

§ SCB_AIRCR_DIT_Msk

§ SCB_AIRCR_SYSRESETREQS_Pos [1/4]

§ SCB_AIRCR_SYSRESETREQS_Msk [1/4]

§ SCB_AIRCR_SYSRESETREQ_Pos [1/4]

§ SCB_AIRCR_SYSRESETREQ_Msk [1/4]

§ SCB_AIRCR_VECTCLRACTIVE_Pos [1/4]

§ SCB_AIRCR_VECTCLRACTIVE_Msk [1/4]

§ SCB_SCR_SEVONPEND_Pos [1/4]

§ SCB_SCR_SEVONPEND_Msk [1/4]

§ SCB_SCR_SLEEPDEEPS_Pos [1/4]

§ SCB_SCR_SLEEPDEEPS_Msk [1/4]

§ SCB_SCR_SLEEPDEEP_Pos [1/4]

§ SCB_SCR_SLEEPDEEP_Msk [1/4]

§ SCB_SCR_SLEEPONEXIT_Pos [1/4]

§ SCB_SCR_SLEEPONEXIT_Msk [1/4]

§ SCB_CCR_TRD_Pos

§ SCB_CCR_TRD_Msk

§ SCB_CCR_LOB_Pos

§ SCB_CCR_LOB_Msk

§ SCB_CCR_BP_Pos [1/4]

§ SCB_CCR_BP_Msk [1/4]

§ SCB_CCR_IC_Pos [1/4]

§ SCB_CCR_IC_Msk [1/4]