CC27xxDriverLibrary
Data Structures | Macros
Floating Point Unit (FPU)
Defines and Type Definitions

Type definitions for the Floating Point Unit (FPU) More...

Collaboration diagram for Floating Point Unit (FPU):

Data Structures

struct  FPU_Type
 Structure type to access the Floating Point Unit (FPU). More...
 

Macros

#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_LSPENS_Pos   29U
 
#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)
 
#define FPU_FPCCR_CLRONRET_Pos   28U
 
#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)
 
#define FPU_FPCCR_CLRONRETS_Pos   27U
 
#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)
 
#define FPU_FPCCR_TS_Pos   26U
 
#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)
 
#define FPU_FPCCR_UFRDY_Pos   10U
 
#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)
 
#define FPU_FPCCR_SPLIMVIOL_Pos   9U
 
#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_SFRDY_Pos   7U
 
#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_S_Pos   2U
 
#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define FPU_MVFR2_FPMisc_Pos   4U
 
#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)
 

Detailed Description

Type definitions for the Floating Point Unit (FPU)

Macro Definition Documentation

§ FPU_FPCCR_ASPEN_Pos [1/3]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

§ FPU_FPCCR_ASPEN_Msk [1/3]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

§ FPU_FPCCR_LSPEN_Pos [1/3]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

§ FPU_FPCCR_LSPEN_Msk [1/3]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

§ FPU_FPCCR_LSPENS_Pos [1/3]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

§ FPU_FPCCR_LSPENS_Msk [1/3]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

§ FPU_FPCCR_CLRONRET_Pos [1/3]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

§ FPU_FPCCR_CLRONRET_Msk [1/3]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

§ FPU_FPCCR_CLRONRETS_Pos [1/3]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

§ FPU_FPCCR_CLRONRETS_Msk [1/3]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

§ FPU_FPCCR_TS_Pos [1/3]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

§ FPU_FPCCR_TS_Msk [1/3]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

§ FPU_FPCCR_UFRDY_Pos [1/3]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

§ FPU_FPCCR_UFRDY_Msk [1/3]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

§ FPU_FPCCR_SPLIMVIOL_Pos [1/3]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

§ FPU_FPCCR_SPLIMVIOL_Msk [1/3]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

§ FPU_FPCCR_MONRDY_Pos [1/3]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

§ FPU_FPCCR_MONRDY_Msk [1/3]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

§ FPU_FPCCR_SFRDY_Pos [1/3]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

§ FPU_FPCCR_SFRDY_Msk [1/3]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

§ FPU_FPCCR_BFRDY_Pos [1/3]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

§ FPU_FPCCR_BFRDY_Msk [1/3]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

§ FPU_FPCCR_MMRDY_Pos [1/3]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

§ FPU_FPCCR_MMRDY_Msk [1/3]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

§ FPU_FPCCR_HFRDY_Pos [1/3]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

§ FPU_FPCCR_HFRDY_Msk [1/3]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

§ FPU_FPCCR_THREAD_Pos [1/3]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

§ FPU_FPCCR_THREAD_Msk [1/3]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

§ FPU_FPCCR_S_Pos [1/3]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

§ FPU_FPCCR_S_Msk [1/3]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

§ FPU_FPCCR_USER_Pos [1/3]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

§ FPU_FPCCR_USER_Msk [1/3]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

§ FPU_FPCCR_LSPACT_Pos [1/3]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

§ FPU_FPCCR_LSPACT_Msk [1/3]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

§ FPU_FPCAR_ADDRESS_Pos [1/3]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

§ FPU_FPCAR_ADDRESS_Msk [1/3]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

§ FPU_FPDSCR_AHP_Pos [1/3]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

§ FPU_FPDSCR_AHP_Msk [1/3]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

§ FPU_FPDSCR_DN_Pos [1/3]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

§ FPU_FPDSCR_DN_Msk [1/3]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

§ FPU_FPDSCR_FZ_Pos [1/3]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

§ FPU_FPDSCR_FZ_Msk [1/3]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

§ FPU_FPDSCR_RMode_Pos [1/3]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

§ FPU_FPDSCR_RMode_Msk [1/3]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

§ FPU_FPDSCR_FZ16_Pos

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

§ FPU_FPDSCR_FZ16_Msk

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

§ FPU_FPDSCR_LTPSIZE_Pos

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

§ FPU_FPDSCR_LTPSIZE_Msk

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

§ FPU_MVFR0_FPRound_Pos

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

§ FPU_MVFR0_FPRound_Msk

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

§ FPU_MVFR0_FPSqrt_Pos

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

§ FPU_MVFR0_FPSqrt_Msk

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

§ FPU_MVFR0_FPDivide_Pos

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

§ FPU_MVFR0_FPDivide_Msk

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

§ FPU_MVFR0_FPDP_Pos

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

§ FPU_MVFR0_FPDP_Msk

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Referenced by SCB_GetFPUType().

§ FPU_MVFR0_FPSP_Pos

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

§ FPU_MVFR0_FPSP_Msk

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Referenced by SCB_GetFPUType().

§ FPU_MVFR0_SIMDReg_Pos

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

§ FPU_MVFR0_SIMDReg_Msk

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

§ FPU_MVFR1_FMAC_Pos

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

§ FPU_MVFR1_FMAC_Msk

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

§ FPU_MVFR1_FPHP_Pos

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

§ FPU_MVFR1_FPHP_Msk

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

§ FPU_MVFR1_FP16_Pos

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

§ FPU_MVFR1_FP16_Msk

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

§ FPU_MVFR1_MVE_Pos

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Referenced by SCB_GetMVEType().

§ FPU_MVFR1_MVE_Msk

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Referenced by SCB_GetMVEType().

§ FPU_MVFR1_FPDNaN_Pos

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

§ FPU_MVFR1_FPDNaN_Msk

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

§ FPU_MVFR1_FPFtZ_Pos

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

§ FPU_MVFR1_FPFtZ_Msk

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

§ FPU_MVFR2_FPMisc_Pos [1/3]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

§ FPU_MVFR2_FPMisc_Msk [1/3]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

§ FPU_FPCCR_ASPEN_Pos [2/3]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

§ FPU_FPCCR_ASPEN_Msk [2/3]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

§ FPU_FPCCR_LSPEN_Pos [2/3]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

§ FPU_FPCCR_LSPEN_Msk [2/3]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

§ FPU_FPCCR_LSPENS_Pos [2/3]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

§ FPU_FPCCR_LSPENS_Msk [2/3]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

§ FPU_FPCCR_CLRONRET_Pos [2/3]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

§ FPU_FPCCR_CLRONRET_Msk [2/3]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

§ FPU_FPCCR_CLRONRETS_Pos [2/3]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

§ FPU_FPCCR_CLRONRETS_Msk [2/3]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

§ FPU_FPCCR_TS_Pos [2/3]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

§ FPU_FPCCR_TS_Msk [2/3]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

§ FPU_FPCCR_UFRDY_Pos [2/3]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

§ FPU_FPCCR_UFRDY_Msk [2/3]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

§ FPU_FPCCR_SPLIMVIOL_Pos [2/3]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

§ FPU_FPCCR_SPLIMVIOL_Msk [2/3]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

§ FPU_FPCCR_MONRDY_Pos [2/3]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

§ FPU_FPCCR_MONRDY_Msk [2/3]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

§ FPU_FPCCR_SFRDY_Pos [2/3]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

§ FPU_FPCCR_SFRDY_Msk [2/3]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

§ FPU_FPCCR_BFRDY_Pos [2/3]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

§ FPU_FPCCR_BFRDY_Msk [2/3]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

§ FPU_FPCCR_MMRDY_Pos [2/3]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

§ FPU_FPCCR_MMRDY_Msk [2/3]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

§ FPU_FPCCR_HFRDY_Pos [2/3]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

§ FPU_FPCCR_HFRDY_Msk [2/3]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

§ FPU_FPCCR_THREAD_Pos [2/3]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

§ FPU_FPCCR_THREAD_Msk [2/3]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

§ FPU_FPCCR_S_Pos [2/3]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

§ FPU_FPCCR_S_Msk [2/3]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

§ FPU_FPCCR_USER_Pos [2/3]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

§ FPU_FPCCR_USER_Msk [2/3]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

§ FPU_FPCCR_LSPACT_Pos [2/3]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

§ FPU_FPCCR_LSPACT_Msk [2/3]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

§ FPU_FPCAR_ADDRESS_Pos [2/3]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

§ FPU_FPCAR_ADDRESS_Msk [2/3]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

§ FPU_FPDSCR_AHP_Pos [2/3]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

§ FPU_FPDSCR_AHP_Msk [2/3]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

§ FPU_FPDSCR_DN_Pos [2/3]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

§ FPU_FPDSCR_DN_Msk [2/3]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

§ FPU_FPDSCR_FZ_Pos [2/3]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

§ FPU_FPDSCR_FZ_Msk [2/3]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

§ FPU_FPDSCR_RMode_Pos [2/3]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

§ FPU_FPDSCR_RMode_Msk [2/3]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

§ FPU_MVFR0_FP_rounding_modes_Pos [1/2]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

§ FPU_MVFR0_FP_rounding_modes_Msk [1/2]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

§ FPU_MVFR0_Short_vectors_Pos [1/2]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

§ FPU_MVFR0_Short_vectors_Msk [1/2]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

§ FPU_MVFR0_Square_root_Pos [1/2]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

§ FPU_MVFR0_Square_root_Msk [1/2]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

§ FPU_MVFR0_Divide_Pos [1/2]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

§ FPU_MVFR0_Divide_Msk [1/2]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

§ FPU_MVFR0_FP_excep_trapping_Pos [1/2]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

§ FPU_MVFR0_FP_excep_trapping_Msk [1/2]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

§ FPU_MVFR0_Double_precision_Pos [1/2]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

§ FPU_MVFR0_Double_precision_Msk [1/2]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

§ FPU_MVFR0_Single_precision_Pos [1/2]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

§ FPU_MVFR0_Single_precision_Msk [1/2]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

§ FPU_MVFR0_A_SIMD_registers_Pos [1/2]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

§ FPU_MVFR0_A_SIMD_registers_Msk [1/2]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

§ FPU_MVFR1_FP_fused_MAC_Pos [1/2]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

§ FPU_MVFR1_FP_fused_MAC_Msk [1/2]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

§ FPU_MVFR1_FP_HPFP_Pos [1/2]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

§ FPU_MVFR1_FP_HPFP_Msk [1/2]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

§ FPU_MVFR1_D_NaN_mode_Pos [1/2]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

§ FPU_MVFR1_D_NaN_mode_Msk [1/2]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

§ FPU_MVFR1_FtZ_mode_Pos [1/2]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

§ FPU_MVFR1_FtZ_mode_Msk [1/2]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

§ FPU_MVFR2_FPMisc_Pos [2/3]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

§ FPU_MVFR2_FPMisc_Msk [2/3]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask

§ FPU_FPCCR_ASPEN_Pos [3/3]

#define FPU_FPCCR_ASPEN_Pos   31U

FPCCR: ASPEN bit Position

§ FPU_FPCCR_ASPEN_Msk [3/3]

#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

§ FPU_FPCCR_LSPEN_Pos [3/3]

#define FPU_FPCCR_LSPEN_Pos   30U

FPCCR: LSPEN Position

§ FPU_FPCCR_LSPEN_Msk [3/3]

#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

§ FPU_FPCCR_LSPENS_Pos [3/3]

#define FPU_FPCCR_LSPENS_Pos   29U

FPCCR: LSPENS Position

§ FPU_FPCCR_LSPENS_Msk [3/3]

#define FPU_FPCCR_LSPENS_Msk   (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

§ FPU_FPCCR_CLRONRET_Pos [3/3]

#define FPU_FPCCR_CLRONRET_Pos   28U

FPCCR: CLRONRET Position

§ FPU_FPCCR_CLRONRET_Msk [3/3]

#define FPU_FPCCR_CLRONRET_Msk   (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

§ FPU_FPCCR_CLRONRETS_Pos [3/3]

#define FPU_FPCCR_CLRONRETS_Pos   27U

FPCCR: CLRONRETS Position

§ FPU_FPCCR_CLRONRETS_Msk [3/3]

#define FPU_FPCCR_CLRONRETS_Msk   (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

§ FPU_FPCCR_TS_Pos [3/3]

#define FPU_FPCCR_TS_Pos   26U

FPCCR: TS Position

§ FPU_FPCCR_TS_Msk [3/3]

#define FPU_FPCCR_TS_Msk   (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

§ FPU_FPCCR_UFRDY_Pos [3/3]

#define FPU_FPCCR_UFRDY_Pos   10U

FPCCR: UFRDY Position

§ FPU_FPCCR_UFRDY_Msk [3/3]

#define FPU_FPCCR_UFRDY_Msk   (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

§ FPU_FPCCR_SPLIMVIOL_Pos [3/3]

#define FPU_FPCCR_SPLIMVIOL_Pos   9U

FPCCR: SPLIMVIOL Position

§ FPU_FPCCR_SPLIMVIOL_Msk [3/3]

#define FPU_FPCCR_SPLIMVIOL_Msk   (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

§ FPU_FPCCR_MONRDY_Pos [3/3]

#define FPU_FPCCR_MONRDY_Pos   8U

FPCCR: MONRDY Position

§ FPU_FPCCR_MONRDY_Msk [3/3]

#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

§ FPU_FPCCR_SFRDY_Pos [3/3]

#define FPU_FPCCR_SFRDY_Pos   7U

FPCCR: SFRDY Position

§ FPU_FPCCR_SFRDY_Msk [3/3]

#define FPU_FPCCR_SFRDY_Msk   (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

§ FPU_FPCCR_BFRDY_Pos [3/3]

#define FPU_FPCCR_BFRDY_Pos   6U

FPCCR: BFRDY Position

§ FPU_FPCCR_BFRDY_Msk [3/3]

#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

§ FPU_FPCCR_MMRDY_Pos [3/3]

#define FPU_FPCCR_MMRDY_Pos   5U

FPCCR: MMRDY Position

§ FPU_FPCCR_MMRDY_Msk [3/3]

#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

§ FPU_FPCCR_HFRDY_Pos [3/3]

#define FPU_FPCCR_HFRDY_Pos   4U

FPCCR: HFRDY Position

§ FPU_FPCCR_HFRDY_Msk [3/3]

#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

§ FPU_FPCCR_THREAD_Pos [3/3]

#define FPU_FPCCR_THREAD_Pos   3U

FPCCR: processor mode bit Position

§ FPU_FPCCR_THREAD_Msk [3/3]

#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

§ FPU_FPCCR_S_Pos [3/3]

#define FPU_FPCCR_S_Pos   2U

FPCCR: Security status of the FP context bit Position

§ FPU_FPCCR_S_Msk [3/3]

#define FPU_FPCCR_S_Msk   (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

§ FPU_FPCCR_USER_Pos [3/3]

#define FPU_FPCCR_USER_Pos   1U

FPCCR: privilege level bit Position

§ FPU_FPCCR_USER_Msk [3/3]

#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

§ FPU_FPCCR_LSPACT_Pos [3/3]

#define FPU_FPCCR_LSPACT_Pos   0U

FPCCR: Lazy state preservation active bit Position

§ FPU_FPCCR_LSPACT_Msk [3/3]

#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

§ FPU_FPCAR_ADDRESS_Pos [3/3]

#define FPU_FPCAR_ADDRESS_Pos   3U

FPCAR: ADDRESS bit Position

§ FPU_FPCAR_ADDRESS_Msk [3/3]

#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

§ FPU_FPDSCR_AHP_Pos [3/3]

#define FPU_FPDSCR_AHP_Pos   26U

FPDSCR: AHP bit Position

§ FPU_FPDSCR_AHP_Msk [3/3]

#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

§ FPU_FPDSCR_DN_Pos [3/3]

#define FPU_FPDSCR_DN_Pos   25U

FPDSCR: DN bit Position

§ FPU_FPDSCR_DN_Msk [3/3]

#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

§ FPU_FPDSCR_FZ_Pos [3/3]

#define FPU_FPDSCR_FZ_Pos   24U

FPDSCR: FZ bit Position

§ FPU_FPDSCR_FZ_Msk [3/3]

#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

§ FPU_FPDSCR_RMode_Pos [3/3]

#define FPU_FPDSCR_RMode_Pos   22U

FPDSCR: RMode bit Position

§ FPU_FPDSCR_RMode_Msk [3/3]

#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

§ FPU_MVFR0_FP_rounding_modes_Pos [2/2]

#define FPU_MVFR0_FP_rounding_modes_Pos   28U

MVFR0: FP rounding modes bits Position

§ FPU_MVFR0_FP_rounding_modes_Msk [2/2]

#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

§ FPU_MVFR0_Short_vectors_Pos [2/2]

#define FPU_MVFR0_Short_vectors_Pos   24U

MVFR0: Short vectors bits Position

§ FPU_MVFR0_Short_vectors_Msk [2/2]

#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

§ FPU_MVFR0_Square_root_Pos [2/2]

#define FPU_MVFR0_Square_root_Pos   20U

MVFR0: Square root bits Position

§ FPU_MVFR0_Square_root_Msk [2/2]

#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

§ FPU_MVFR0_Divide_Pos [2/2]

#define FPU_MVFR0_Divide_Pos   16U

MVFR0: Divide bits Position

§ FPU_MVFR0_Divide_Msk [2/2]

#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

§ FPU_MVFR0_FP_excep_trapping_Pos [2/2]

#define FPU_MVFR0_FP_excep_trapping_Pos   12U

MVFR0: FP exception trapping bits Position

§ FPU_MVFR0_FP_excep_trapping_Msk [2/2]

#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

§ FPU_MVFR0_Double_precision_Pos [2/2]

#define FPU_MVFR0_Double_precision_Pos   8U

MVFR0: Double-precision bits Position

§ FPU_MVFR0_Double_precision_Msk [2/2]

#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

§ FPU_MVFR0_Single_precision_Pos [2/2]

#define FPU_MVFR0_Single_precision_Pos   4U

MVFR0: Single-precision bits Position

§ FPU_MVFR0_Single_precision_Msk [2/2]

#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

§ FPU_MVFR0_A_SIMD_registers_Pos [2/2]

#define FPU_MVFR0_A_SIMD_registers_Pos   0U

MVFR0: A_SIMD registers bits Position

§ FPU_MVFR0_A_SIMD_registers_Msk [2/2]

#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

§ FPU_MVFR1_FP_fused_MAC_Pos [2/2]

#define FPU_MVFR1_FP_fused_MAC_Pos   28U

MVFR1: FP fused MAC bits Position

§ FPU_MVFR1_FP_fused_MAC_Msk [2/2]

#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

§ FPU_MVFR1_FP_HPFP_Pos [2/2]

#define FPU_MVFR1_FP_HPFP_Pos   24U

MVFR1: FP HPFP bits Position

§ FPU_MVFR1_FP_HPFP_Msk [2/2]

#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

§ FPU_MVFR1_D_NaN_mode_Pos [2/2]

#define FPU_MVFR1_D_NaN_mode_Pos   4U

MVFR1: D_NaN mode bits Position

§ FPU_MVFR1_D_NaN_mode_Msk [2/2]

#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

§ FPU_MVFR1_FtZ_mode_Pos [2/2]

#define FPU_MVFR1_FtZ_mode_Pos   0U

MVFR1: FtZ mode bits Position

§ FPU_MVFR1_FtZ_mode_Msk [2/2]

#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

§ FPU_MVFR2_FPMisc_Pos [3/3]

#define FPU_MVFR2_FPMisc_Pos   4U

MVFR2: FPMisc bits Position

§ FPU_MVFR2_FPMisc_Msk [3/3]

#define FPU_MVFR2_FPMisc_Msk   (0xFUL << FPU_MVFR2_FPMisc_Pos)

MVFR2: FPMisc bits Mask