Type definitions for the Debug Control Block Registers. More...

Collaboration diagram for Debug Control Block:

Data Structures
struct	DCB_Type
	Structure type to access the Debug Control Block Registers (DCB). More...

Macros
#define	DCB_DHCSR_DBGKEY_Pos 16U

#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

#define	DCB_DHCSR_S_RESTART_ST_Pos 26U

#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

#define	DCB_DHCSR_S_RESET_ST_Pos 25U

#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U

#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

#define	DCB_DHCSR_S_FPD_Pos 23U

#define	DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)

#define	DCB_DHCSR_S_SUIDE_Pos 22U

#define	DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

#define	DCB_DHCSR_S_NSUIDE_Pos 21U

#define	DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

#define	DCB_DHCSR_S_SDE_Pos 20U

#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

#define	DCB_DHCSR_S_LOCKUP_Pos 19U

#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

#define	DCB_DHCSR_S_SLEEP_Pos 18U

#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

#define	DCB_DHCSR_S_HALT_Pos 17U

#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

#define	DCB_DHCSR_S_REGRDY_Pos 16U

#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

#define	DCB_DHCSR_C_PMOV_Pos 6U

#define	DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)

#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U

#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

#define	DCB_DHCSR_C_MASKINTS_Pos 3U

#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

#define	DCB_DHCSR_C_STEP_Pos 2U

#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

#define	DCB_DHCSR_C_HALT_Pos 1U

#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

#define	DCB_DHCSR_C_DEBUGEN_Pos 0U

#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)

#define	DCB_DCRSR_REGWnR_Pos 16U

#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

#define	DCB_DCRSR_REGSEL_Pos 0U

#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)

#define	DCB_DCRDR_DBGTMP_Pos 0U

#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)

#define	DCB_DEMCR_TRCENA_Pos 24U

#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

#define	DCB_DEMCR_MONPRKEY_Pos 23U

#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

#define	DCB_DEMCR_UMON_EN_Pos 21U

#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)

#define	DCB_DEMCR_SDME_Pos 20U

#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)

#define	DCB_DEMCR_MON_REQ_Pos 19U

#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)

#define	DCB_DEMCR_MON_STEP_Pos 18U

#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)

#define	DCB_DEMCR_MON_PEND_Pos 17U

#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)

#define	DCB_DEMCR_MON_EN_Pos 16U

#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)

#define	DCB_DEMCR_VC_SFERR_Pos 11U

#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

#define	DCB_DEMCR_VC_HARDERR_Pos 10U

#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

#define	DCB_DEMCR_VC_INTERR_Pos 9U

#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

#define	DCB_DEMCR_VC_BUSERR_Pos 8U

#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

#define	DCB_DEMCR_VC_STATERR_Pos 7U

#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

#define	DCB_DEMCR_VC_CHKERR_Pos 6U

#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

#define	DCB_DEMCR_VC_NOCPERR_Pos 5U

#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

#define	DCB_DEMCR_VC_MMERR_Pos 4U

#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

#define	DCB_DEMCR_VC_CORERESET_Pos 0U

#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)

#define	DCB_DSCEMCR_CLR_MON_REQ_Pos 19U

#define	DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

#define	DCB_DSCEMCR_CLR_MON_PEND_Pos 17U

#define	DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

#define	DCB_DSCEMCR_SET_MON_REQ_Pos 3U

#define	DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

#define	DCB_DSCEMCR_SET_MON_PEND_Pos 1U

#define	DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

#define	DCB_DAUTHCTRL_UIDEN_Pos 10U

#define	DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

#define	DCB_DAUTHCTRL_UIDAPEN_Pos 9U

#define	DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

#define	DCB_DAUTHCTRL_FSDMA_Pos 8U

#define	DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)

#define	DCB_DSCSR_CDSKEY_Pos 17U

#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

#define	DCB_DSCSR_CDS_Pos 16U

#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

#define	DCB_DSCSR_SBRSEL_Pos 1U

#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

#define	DCB_DSCSR_SBRSELEN_Pos 0U

#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)

#define	DCB_DHCSR_DBGKEY_Pos 16U

#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

#define	DCB_DHCSR_S_RESTART_ST_Pos 26U

#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

#define	DCB_DHCSR_S_RESET_ST_Pos 25U

#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U

#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

#define	DCB_DHCSR_S_SDE_Pos 20U

#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

#define	DCB_DHCSR_S_LOCKUP_Pos 19U

#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

#define	DCB_DHCSR_S_SLEEP_Pos 18U

#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

#define	DCB_DHCSR_S_HALT_Pos 17U

#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

#define	DCB_DHCSR_S_REGRDY_Pos 16U

#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

#define	DCB_DHCSR_C_MASKINTS_Pos 3U

#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

#define	DCB_DHCSR_C_STEP_Pos 2U

#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

#define	DCB_DHCSR_C_HALT_Pos 1U

#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

#define	DCB_DHCSR_C_DEBUGEN_Pos 0U

#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)

#define	DCB_DCRSR_REGWnR_Pos 16U

#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

#define	DCB_DCRSR_REGSEL_Pos 0U

#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)

#define	DCB_DCRDR_DBGTMP_Pos 0U

#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)

#define	DCB_DEMCR_TRCENA_Pos 24U

#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

#define	DCB_DEMCR_VC_HARDERR_Pos 10U

#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

#define	DCB_DEMCR_VC_CORERESET_Pos 0U

#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)

#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)

#define	DCB_DSCSR_CDSKEY_Pos 17U

#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

#define	DCB_DSCSR_CDS_Pos 16U

#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

#define	DCB_DSCSR_SBRSEL_Pos 1U

#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

#define	DCB_DSCSR_SBRSELEN_Pos 0U

#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)

#define	DCB_DHCSR_DBGKEY_Pos 16U

#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

#define	DCB_DHCSR_S_RESTART_ST_Pos 26U

#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

#define	DCB_DHCSR_S_RESET_ST_Pos 25U

#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U

#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

#define	DCB_DHCSR_S_SDE_Pos 20U

#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

#define	DCB_DHCSR_S_LOCKUP_Pos 19U

#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

#define	DCB_DHCSR_S_SLEEP_Pos 18U

#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

#define	DCB_DHCSR_S_HALT_Pos 17U

#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

#define	DCB_DHCSR_S_REGRDY_Pos 16U

#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U

#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

#define	DCB_DHCSR_C_MASKINTS_Pos 3U

#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

#define	DCB_DHCSR_C_STEP_Pos 2U

#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

#define	DCB_DHCSR_C_HALT_Pos 1U

#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

#define	DCB_DHCSR_C_DEBUGEN_Pos 0U

#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)

#define	DCB_DCRSR_REGWnR_Pos 16U

#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

#define	DCB_DCRSR_REGSEL_Pos 0U

#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)

#define	DCB_DCRDR_DBGTMP_Pos 0U

#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)

#define	DCB_DEMCR_TRCENA_Pos 24U

#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

#define	DCB_DEMCR_MONPRKEY_Pos 23U

#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

#define	DCB_DEMCR_UMON_EN_Pos 21U

#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)

#define	DCB_DEMCR_SDME_Pos 20U

#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)

#define	DCB_DEMCR_MON_REQ_Pos 19U

#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)

#define	DCB_DEMCR_MON_STEP_Pos 18U

#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)

#define	DCB_DEMCR_MON_PEND_Pos 17U

#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)

#define	DCB_DEMCR_MON_EN_Pos 16U

#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)

#define	DCB_DEMCR_VC_SFERR_Pos 11U

#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

#define	DCB_DEMCR_VC_HARDERR_Pos 10U

#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

#define	DCB_DEMCR_VC_INTERR_Pos 9U

#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

#define	DCB_DEMCR_VC_BUSERR_Pos 8U

#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

#define	DCB_DEMCR_VC_STATERR_Pos 7U

#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

#define	DCB_DEMCR_VC_CHKERR_Pos 6U

#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

#define	DCB_DEMCR_VC_NOCPERR_Pos 5U

#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

#define	DCB_DEMCR_VC_MMERR_Pos 4U

#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

#define	DCB_DEMCR_VC_CORERESET_Pos 0U

#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)

#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)

#define	DCB_DSCSR_CDSKEY_Pos 17U

#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

#define	DCB_DSCSR_CDS_Pos 16U

#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

#define	DCB_DSCSR_SBRSEL_Pos 1U

#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

#define	DCB_DSCSR_SBRSELEN_Pos 0U

#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)

#define	DCB_DHCSR_DBGKEY_Pos 16U

#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

#define	DCB_DHCSR_S_RESTART_ST_Pos 26U

#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

#define	DCB_DHCSR_S_RESET_ST_Pos 25U

#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U

#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

#define	DCB_DHCSR_S_SDE_Pos 20U

#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

#define	DCB_DHCSR_S_LOCKUP_Pos 19U

#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

#define	DCB_DHCSR_S_SLEEP_Pos 18U

#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

#define	DCB_DHCSR_S_HALT_Pos 17U

#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

#define	DCB_DHCSR_S_REGRDY_Pos 16U

#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U

#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

#define	DCB_DHCSR_C_MASKINTS_Pos 3U

#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

#define	DCB_DHCSR_C_STEP_Pos 2U

#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

#define	DCB_DHCSR_C_HALT_Pos 1U

#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

#define	DCB_DHCSR_C_DEBUGEN_Pos 0U

#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)

#define	DCB_DCRSR_REGWnR_Pos 16U

#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

#define	DCB_DCRSR_REGSEL_Pos 0U

#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)

#define	DCB_DCRDR_DBGTMP_Pos 0U

#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)

#define	DCB_DEMCR_TRCENA_Pos 24U

#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

#define	DCB_DEMCR_MONPRKEY_Pos 23U

#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

#define	DCB_DEMCR_UMON_EN_Pos 21U

#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)

#define	DCB_DEMCR_SDME_Pos 20U

#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)

#define	DCB_DEMCR_MON_REQ_Pos 19U

#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)

#define	DCB_DEMCR_MON_STEP_Pos 18U

#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)

#define	DCB_DEMCR_MON_PEND_Pos 17U

#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)

#define	DCB_DEMCR_MON_EN_Pos 16U

#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)

#define	DCB_DEMCR_VC_SFERR_Pos 11U

#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

#define	DCB_DEMCR_VC_HARDERR_Pos 10U

#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

#define	DCB_DEMCR_VC_INTERR_Pos 9U

#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

#define	DCB_DEMCR_VC_BUSERR_Pos 8U

#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

#define	DCB_DEMCR_VC_STATERR_Pos 7U

#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

#define	DCB_DEMCR_VC_CHKERR_Pos 6U

#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

#define	DCB_DEMCR_VC_NOCPERR_Pos 5U

#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

#define	DCB_DEMCR_VC_MMERR_Pos 4U

#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

#define	DCB_DEMCR_VC_CORERESET_Pos 0U

#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)

#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)

#define	DCB_DSCSR_CDSKEY_Pos 17U

#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

#define	DCB_DSCSR_CDS_Pos 16U

#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

#define	DCB_DSCSR_SBRSEL_Pos 1U

#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

#define	DCB_DSCSR_SBRSELEN_Pos 0U

#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)

Detailed Description

Type definitions for the Debug Control Block Registers.

Macro Definition Documentation

§ DCB_DHCSR_DBGKEY_Pos [1/4]

#define DCB_DHCSR_DBGKEY_Pos 16U

DCB DHCSR: Debug key Position

§ DCB_DHCSR_DBGKEY_Msk [1/4]

#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

§ DCB_DHCSR_S_RESTART_ST_Pos [1/4]

#define DCB_DHCSR_S_RESTART_ST_Pos 26U

DCB DHCSR: Restart sticky status Position

§ DCB_DHCSR_S_RESTART_ST_Msk [1/4]

#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

§ DCB_DHCSR_S_RESET_ST_Pos [1/4]

#define DCB_DHCSR_S_RESET_ST_Pos 25U

DCB DHCSR: Reset sticky status Position

§ DCB_DHCSR_S_RESET_ST_Msk [1/4]

#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

§ DCB_DHCSR_S_RETIRE_ST_Pos [1/4]

#define DCB_DHCSR_S_RETIRE_ST_Pos 24U

DCB DHCSR: Retire sticky status Position

§ DCB_DHCSR_S_RETIRE_ST_Msk [1/4]

#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

§ DCB_DHCSR_S_FPD_Pos

#define DCB_DHCSR_S_FPD_Pos 23U

DCB DHCSR: Floating-point registers Debuggable Position

§ DCB_DHCSR_S_FPD_Msk

#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

§ DCB_DHCSR_S_SUIDE_Pos

#define DCB_DHCSR_S_SUIDE_Pos 22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

§ DCB_DHCSR_S_SUIDE_Msk

#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

§ DCB_DHCSR_S_NSUIDE_Pos

#define DCB_DHCSR_S_NSUIDE_Pos 21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

§ DCB_DHCSR_S_NSUIDE_Msk

#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

§ DCB_DHCSR_S_SDE_Pos [1/4]

#define DCB_DHCSR_S_SDE_Pos 20U

DCB DHCSR: Secure debug enabled Position

§ DCB_DHCSR_S_SDE_Msk [1/4]

#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

§ DCB_DHCSR_S_LOCKUP_Pos [1/4]

#define DCB_DHCSR_S_LOCKUP_Pos 19U

DCB DHCSR: Lockup status Position

§ DCB_DHCSR_S_LOCKUP_Msk [1/4]

#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

§ DCB_DHCSR_S_SLEEP_Pos [1/4]

#define DCB_DHCSR_S_SLEEP_Pos 18U

DCB DHCSR: Sleeping status Position

§ DCB_DHCSR_S_SLEEP_Msk [1/4]

#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

§ DCB_DHCSR_S_HALT_Pos [1/4]

#define DCB_DHCSR_S_HALT_Pos 17U

DCB DHCSR: Halted status Position

§ DCB_DHCSR_S_HALT_Msk [1/4]

#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

§ DCB_DHCSR_S_REGRDY_Pos [1/4]

#define DCB_DHCSR_S_REGRDY_Pos 16U

DCB DHCSR: Register ready status Position

§ DCB_DHCSR_S_REGRDY_Msk [1/4]

#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

§ DCB_DHCSR_C_PMOV_Pos

#define DCB_DHCSR_C_PMOV_Pos 6U

DCB DHCSR: Halt on PMU overflow control Position

§ DCB_DHCSR_C_PMOV_Msk

#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

§ DCB_DHCSR_C_SNAPSTALL_Pos [1/3]

#define DCB_DHCSR_C_SNAPSTALL_Pos 5U

DCB DHCSR: Snap stall control Position

§ DCB_DHCSR_C_SNAPSTALL_Msk [1/3]

#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

§ DCB_DHCSR_C_MASKINTS_Pos [1/4]

#define DCB_DHCSR_C_MASKINTS_Pos 3U

DCB DHCSR: Mask interrupts control Position

§ DCB_DHCSR_C_MASKINTS_Msk [1/4]

#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

§ DCB_DHCSR_C_STEP_Pos [1/4]

#define DCB_DHCSR_C_STEP_Pos 2U

DCB DHCSR: Step control Position

§ DCB_DHCSR_C_STEP_Msk [1/4]

#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

§ DCB_DHCSR_C_HALT_Pos [1/4]

#define DCB_DHCSR_C_HALT_Pos 1U

DCB DHCSR: Halt control Position

§ DCB_DHCSR_C_HALT_Msk [1/4]

#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

§ DCB_DHCSR_C_DEBUGEN_Pos [1/4]

#define DCB_DHCSR_C_DEBUGEN_Pos 0U

DCB DHCSR: Debug enable control Position

§ DCB_DHCSR_C_DEBUGEN_Msk [1/4]

#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

§ DCB_DCRSR_REGWnR_Pos [1/4]

#define DCB_DCRSR_REGWnR_Pos 16U

DCB DCRSR: Register write/not-read Position

§ DCB_DCRSR_REGWnR_Msk [1/4]

#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

§ DCB_DCRSR_REGSEL_Pos [1/4]

#define DCB_DCRSR_REGSEL_Pos 0U

DCB DCRSR: Register selector Position

§ DCB_DCRSR_REGSEL_Msk [1/4]

#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

§ DCB_DCRDR_DBGTMP_Pos [1/4]

#define DCB_DCRDR_DBGTMP_Pos 0U

DCB DCRDR: Data temporary buffer Position

§ DCB_DCRDR_DBGTMP_Msk [1/4]

#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

§ DCB_DEMCR_TRCENA_Pos [1/4]

#define DCB_DEMCR_TRCENA_Pos 24U

DCB DEMCR: Trace enable Position

§ DCB_DEMCR_TRCENA_Msk [1/4]

#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

§ DCB_DEMCR_MONPRKEY_Pos [1/3]

#define DCB_DEMCR_MONPRKEY_Pos 23U

DCB DEMCR: Monitor pend req key Position

§ DCB_DEMCR_MONPRKEY_Msk [1/3]

#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

§ DCB_DEMCR_UMON_EN_Pos [1/3]

#define DCB_DEMCR_UMON_EN_Pos 21U

DCB DEMCR: Unprivileged monitor enable Position

§ DCB_DEMCR_UMON_EN_Msk [1/3]

#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

§ DCB_DEMCR_SDME_Pos [1/3]

#define DCB_DEMCR_SDME_Pos 20U

DCB DEMCR: Secure DebugMonitor enable Position

§ DCB_DEMCR_SDME_Msk [1/3]

#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

§ DCB_DEMCR_MON_REQ_Pos [1/3]

#define DCB_DEMCR_MON_REQ_Pos 19U

DCB DEMCR: Monitor request Position

§ DCB_DEMCR_MON_REQ_Msk [1/3]

#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

§ DCB_DEMCR_MON_STEP_Pos [1/3]

#define DCB_DEMCR_MON_STEP_Pos 18U

DCB DEMCR: Monitor step Position

§ DCB_DEMCR_MON_STEP_Msk [1/3]

#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

§ DCB_DEMCR_MON_PEND_Pos [1/3]

#define DCB_DEMCR_MON_PEND_Pos 17U

DCB DEMCR: Monitor pend Position

§ DCB_DEMCR_MON_PEND_Msk [1/3]

#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

§ DCB_DEMCR_MON_EN_Pos [1/3]

#define DCB_DEMCR_MON_EN_Pos 16U

DCB DEMCR: Monitor enable Position

§ DCB_DEMCR_MON_EN_Msk [1/3]

#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

§ DCB_DEMCR_VC_SFERR_Pos [1/3]

#define DCB_DEMCR_VC_SFERR_Pos 11U

DCB DEMCR: Vector Catch SecureFault Position

§ DCB_DEMCR_VC_SFERR_Msk [1/3]

#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

§ DCB_DEMCR_VC_HARDERR_Pos [1/4]

#define DCB_DEMCR_VC_HARDERR_Pos 10U

DCB DEMCR: Vector Catch HardFault errors Position

§ DCB_DEMCR_VC_HARDERR_Msk [1/4]

#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

§ DCB_DEMCR_VC_INTERR_Pos [1/3]

#define DCB_DEMCR_VC_INTERR_Pos 9U

DCB DEMCR: Vector Catch interrupt errors Position

§ DCB_DEMCR_VC_INTERR_Msk [1/3]

#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

§ DCB_DEMCR_VC_BUSERR_Pos [1/3]

#define DCB_DEMCR_VC_BUSERR_Pos 8U

DCB DEMCR: Vector Catch BusFault errors Position

§ DCB_DEMCR_VC_BUSERR_Msk [1/3]

#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

§ DCB_DEMCR_VC_STATERR_Pos [1/3]

#define DCB_DEMCR_VC_STATERR_Pos 7U

DCB DEMCR: Vector Catch state errors Position

§ DCB_DEMCR_VC_STATERR_Msk [1/3]

#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

§ DCB_DEMCR_VC_CHKERR_Pos [1/3]

#define DCB_DEMCR_VC_CHKERR_Pos 6U

DCB DEMCR: Vector Catch check errors Position

§ DCB_DEMCR_VC_CHKERR_Msk [1/3]

#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

§ DCB_DEMCR_VC_NOCPERR_Pos [1/3]

#define DCB_DEMCR_VC_NOCPERR_Pos 5U

DCB DEMCR: Vector Catch NOCP errors Position

§ DCB_DEMCR_VC_NOCPERR_Msk [1/3]

#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

§ DCB_DEMCR_VC_MMERR_Pos [1/3]

#define DCB_DEMCR_VC_MMERR_Pos 4U

DCB DEMCR: Vector Catch MemManage errors Position

§ DCB_DEMCR_VC_MMERR_Msk [1/3]

#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

§ DCB_DEMCR_VC_CORERESET_Pos [1/4]

#define DCB_DEMCR_VC_CORERESET_Pos 0U

DCB DEMCR: Vector Catch Core reset Position

§ DCB_DEMCR_VC_CORERESET_Msk [1/4]

#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

§ DCB_DSCEMCR_CLR_MON_REQ_Pos

#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U

DCB DSCEMCR: Clear monitor request Position

§ DCB_DSCEMCR_CLR_MON_REQ_Msk

#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

§ DCB_DSCEMCR_CLR_MON_PEND_Pos

#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U

DCB DSCEMCR: Clear monitor pend Position

§ DCB_DSCEMCR_CLR_MON_PEND_Msk

#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

§ DCB_DSCEMCR_SET_MON_REQ_Pos

#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U

DCB DSCEMCR: Set monitor request Position

§ DCB_DSCEMCR_SET_MON_REQ_Msk

#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

§ DCB_DSCEMCR_SET_MON_PEND_Pos

#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U

DCB DSCEMCR: Set monitor pend Position

§ DCB_DSCEMCR_SET_MON_PEND_Msk

#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

§ DCB_DAUTHCTRL_UIDEN_Pos

#define DCB_DAUTHCTRL_UIDEN_Pos 10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

§ DCB_DAUTHCTRL_UIDEN_Msk

#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

§ DCB_DAUTHCTRL_UIDAPEN_Pos

#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

§ DCB_DAUTHCTRL_UIDAPEN_Msk

#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

§ DCB_DAUTHCTRL_FSDMA_Pos

#define DCB_DAUTHCTRL_FSDMA_Pos 8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

§ DCB_DAUTHCTRL_FSDMA_Msk

#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

§ DCB_DAUTHCTRL_INTSPNIDEN_Pos [1/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPNIDEN_Msk [1/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

§ DCB_DAUTHCTRL_SPNIDENSEL_Pos [1/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

§ DCB_DAUTHCTRL_SPNIDENSEL_Msk [1/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

§ DCB_DAUTHCTRL_INTSPIDEN_Pos [1/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPIDEN_Msk [1/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

§ DCB_DAUTHCTRL_SPIDENSEL_Pos [1/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

§ DCB_DAUTHCTRL_SPIDENSEL_Msk [1/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

§ DCB_DSCSR_CDSKEY_Pos [1/4]

#define DCB_DSCSR_CDSKEY_Pos 17U

DCB DSCSR: CDS write-enable key Position

§ DCB_DSCSR_CDSKEY_Msk [1/4]

#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

§ DCB_DSCSR_CDS_Pos [1/4]

#define DCB_DSCSR_CDS_Pos 16U

DCB DSCSR: Current domain Secure Position

§ DCB_DSCSR_CDS_Msk [1/4]

#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

§ DCB_DSCSR_SBRSEL_Pos [1/4]

#define DCB_DSCSR_SBRSEL_Pos 1U

DCB DSCSR: Secure banked register select Position

§ DCB_DSCSR_SBRSEL_Msk [1/4]

#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

§ DCB_DSCSR_SBRSELEN_Pos [1/4]

#define DCB_DSCSR_SBRSELEN_Pos 0U

DCB DSCSR: Secure banked register select enable Position

§ DCB_DSCSR_SBRSELEN_Msk [1/4]

#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

§ DCB_DHCSR_DBGKEY_Pos [2/4]

#define DCB_DHCSR_DBGKEY_Pos 16U

DCB DHCSR: Debug key Position

§ DCB_DHCSR_DBGKEY_Msk [2/4]

#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

§ DCB_DHCSR_S_RESTART_ST_Pos [2/4]

#define DCB_DHCSR_S_RESTART_ST_Pos 26U

DCB DHCSR: Restart sticky status Position

§ DCB_DHCSR_S_RESTART_ST_Msk [2/4]

#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

§ DCB_DHCSR_S_RESET_ST_Pos [2/4]

#define DCB_DHCSR_S_RESET_ST_Pos 25U

DCB DHCSR: Reset sticky status Position

§ DCB_DHCSR_S_RESET_ST_Msk [2/4]

#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

§ DCB_DHCSR_S_RETIRE_ST_Pos [2/4]

#define DCB_DHCSR_S_RETIRE_ST_Pos 24U

DCB DHCSR: Retire sticky status Position

§ DCB_DHCSR_S_RETIRE_ST_Msk [2/4]

#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

§ DCB_DHCSR_S_SDE_Pos [2/4]

#define DCB_DHCSR_S_SDE_Pos 20U

DCB DHCSR: Secure debug enabled Position

§ DCB_DHCSR_S_SDE_Msk [2/4]

#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

§ DCB_DHCSR_S_LOCKUP_Pos [2/4]

#define DCB_DHCSR_S_LOCKUP_Pos 19U

DCB DHCSR: Lockup status Position

§ DCB_DHCSR_S_LOCKUP_Msk [2/4]

#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

§ DCB_DHCSR_S_SLEEP_Pos [2/4]

#define DCB_DHCSR_S_SLEEP_Pos 18U

DCB DHCSR: Sleeping status Position

§ DCB_DHCSR_S_SLEEP_Msk [2/4]

#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

§ DCB_DHCSR_S_HALT_Pos [2/4]

#define DCB_DHCSR_S_HALT_Pos 17U

DCB DHCSR: Halted status Position

§ DCB_DHCSR_S_HALT_Msk [2/4]

#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

§ DCB_DHCSR_S_REGRDY_Pos [2/4]

#define DCB_DHCSR_S_REGRDY_Pos 16U

DCB DHCSR: Register ready status Position

§ DCB_DHCSR_S_REGRDY_Msk [2/4]

#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

§ DCB_DHCSR_C_MASKINTS_Pos [2/4]

#define DCB_DHCSR_C_MASKINTS_Pos 3U

DCB DHCSR: Mask interrupts control Position

§ DCB_DHCSR_C_MASKINTS_Msk [2/4]

#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

§ DCB_DHCSR_C_STEP_Pos [2/4]

#define DCB_DHCSR_C_STEP_Pos 2U

DCB DHCSR: Step control Position

§ DCB_DHCSR_C_STEP_Msk [2/4]

#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

§ DCB_DHCSR_C_HALT_Pos [2/4]

#define DCB_DHCSR_C_HALT_Pos 1U

DCB DHCSR: Halt control Position

§ DCB_DHCSR_C_HALT_Msk [2/4]

#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

§ DCB_DHCSR_C_DEBUGEN_Pos [2/4]

#define DCB_DHCSR_C_DEBUGEN_Pos 0U

DCB DHCSR: Debug enable control Position

§ DCB_DHCSR_C_DEBUGEN_Msk [2/4]

#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

§ DCB_DCRSR_REGWnR_Pos [2/4]

#define DCB_DCRSR_REGWnR_Pos 16U

DCB DCRSR: Register write/not-read Position

§ DCB_DCRSR_REGWnR_Msk [2/4]

#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

§ DCB_DCRSR_REGSEL_Pos [2/4]

#define DCB_DCRSR_REGSEL_Pos 0U

DCB DCRSR: Register selector Position

§ DCB_DCRSR_REGSEL_Msk [2/4]

#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

§ DCB_DCRDR_DBGTMP_Pos [2/4]

#define DCB_DCRDR_DBGTMP_Pos 0U

DCB DCRDR: Data temporary buffer Position

§ DCB_DCRDR_DBGTMP_Msk [2/4]

#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

§ DCB_DEMCR_TRCENA_Pos [2/4]

#define DCB_DEMCR_TRCENA_Pos 24U

DCB DEMCR: Trace enable Position

§ DCB_DEMCR_TRCENA_Msk [2/4]

#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

§ DCB_DEMCR_VC_HARDERR_Pos [2/4]

#define DCB_DEMCR_VC_HARDERR_Pos 10U

DCB DEMCR: Vector Catch HardFault errors Position

§ DCB_DEMCR_VC_HARDERR_Msk [2/4]

#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

§ DCB_DEMCR_VC_CORERESET_Pos [2/4]

#define DCB_DEMCR_VC_CORERESET_Pos 0U

DCB DEMCR: Vector Catch Core reset Position

§ DCB_DEMCR_VC_CORERESET_Msk [2/4]

#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

§ DCB_DAUTHCTRL_INTSPNIDEN_Pos [2/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPNIDEN_Msk [2/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

§ DCB_DAUTHCTRL_SPNIDENSEL_Pos [2/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

§ DCB_DAUTHCTRL_SPNIDENSEL_Msk [2/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

§ DCB_DAUTHCTRL_INTSPIDEN_Pos [2/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPIDEN_Msk [2/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

§ DCB_DAUTHCTRL_SPIDENSEL_Pos [2/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

§ DCB_DAUTHCTRL_SPIDENSEL_Msk [2/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

§ DCB_DSCSR_CDSKEY_Pos [2/4]

#define DCB_DSCSR_CDSKEY_Pos 17U

DCB DSCSR: CDS write-enable key Position

§ DCB_DSCSR_CDSKEY_Msk [2/4]

#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

§ DCB_DSCSR_CDS_Pos [2/4]

#define DCB_DSCSR_CDS_Pos 16U

DCB DSCSR: Current domain Secure Position

§ DCB_DSCSR_CDS_Msk [2/4]

#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

§ DCB_DSCSR_SBRSEL_Pos [2/4]

#define DCB_DSCSR_SBRSEL_Pos 1U

DCB DSCSR: Secure banked register select Position

§ DCB_DSCSR_SBRSEL_Msk [2/4]

#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

§ DCB_DSCSR_SBRSELEN_Pos [2/4]

#define DCB_DSCSR_SBRSELEN_Pos 0U

DCB DSCSR: Secure banked register select enable Position

§ DCB_DSCSR_SBRSELEN_Msk [2/4]

#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

§ DCB_DHCSR_DBGKEY_Pos [3/4]

#define DCB_DHCSR_DBGKEY_Pos 16U

DCB DHCSR: Debug key Position

§ DCB_DHCSR_DBGKEY_Msk [3/4]

#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

§ DCB_DHCSR_S_RESTART_ST_Pos [3/4]

#define DCB_DHCSR_S_RESTART_ST_Pos 26U

DCB DHCSR: Restart sticky status Position

§ DCB_DHCSR_S_RESTART_ST_Msk [3/4]

#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

§ DCB_DHCSR_S_RESET_ST_Pos [3/4]

#define DCB_DHCSR_S_RESET_ST_Pos 25U

DCB DHCSR: Reset sticky status Position

§ DCB_DHCSR_S_RESET_ST_Msk [3/4]

#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

§ DCB_DHCSR_S_RETIRE_ST_Pos [3/4]

#define DCB_DHCSR_S_RETIRE_ST_Pos 24U

DCB DHCSR: Retire sticky status Position

§ DCB_DHCSR_S_RETIRE_ST_Msk [3/4]

#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

§ DCB_DHCSR_S_SDE_Pos [3/4]

#define DCB_DHCSR_S_SDE_Pos 20U

DCB DHCSR: Secure debug enabled Position

§ DCB_DHCSR_S_SDE_Msk [3/4]

#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

§ DCB_DHCSR_S_LOCKUP_Pos [3/4]

#define DCB_DHCSR_S_LOCKUP_Pos 19U

DCB DHCSR: Lockup status Position

§ DCB_DHCSR_S_LOCKUP_Msk [3/4]

#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

§ DCB_DHCSR_S_SLEEP_Pos [3/4]

#define DCB_DHCSR_S_SLEEP_Pos 18U

DCB DHCSR: Sleeping status Position

§ DCB_DHCSR_S_SLEEP_Msk [3/4]

#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

§ DCB_DHCSR_S_HALT_Pos [3/4]

#define DCB_DHCSR_S_HALT_Pos 17U

DCB DHCSR: Halted status Position

§ DCB_DHCSR_S_HALT_Msk [3/4]

#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

§ DCB_DHCSR_S_REGRDY_Pos [3/4]

#define DCB_DHCSR_S_REGRDY_Pos 16U

DCB DHCSR: Register ready status Position

§ DCB_DHCSR_S_REGRDY_Msk [3/4]

#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

§ DCB_DHCSR_C_SNAPSTALL_Pos [2/3]

#define DCB_DHCSR_C_SNAPSTALL_Pos 5U

DCB DHCSR: Snap stall control Position

§ DCB_DHCSR_C_SNAPSTALL_Msk [2/3]

#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

§ DCB_DHCSR_C_MASKINTS_Pos [3/4]

#define DCB_DHCSR_C_MASKINTS_Pos 3U

DCB DHCSR: Mask interrupts control Position

§ DCB_DHCSR_C_MASKINTS_Msk [3/4]

#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

§ DCB_DHCSR_C_STEP_Pos [3/4]

#define DCB_DHCSR_C_STEP_Pos 2U

DCB DHCSR: Step control Position

§ DCB_DHCSR_C_STEP_Msk [3/4]

#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

§ DCB_DHCSR_C_HALT_Pos [3/4]

#define DCB_DHCSR_C_HALT_Pos 1U

DCB DHCSR: Halt control Position

§ DCB_DHCSR_C_HALT_Msk [3/4]

#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

§ DCB_DHCSR_C_DEBUGEN_Pos [3/4]

#define DCB_DHCSR_C_DEBUGEN_Pos 0U

DCB DHCSR: Debug enable control Position

§ DCB_DHCSR_C_DEBUGEN_Msk [3/4]

#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

§ DCB_DCRSR_REGWnR_Pos [3/4]

#define DCB_DCRSR_REGWnR_Pos 16U

DCB DCRSR: Register write/not-read Position

§ DCB_DCRSR_REGWnR_Msk [3/4]

#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

§ DCB_DCRSR_REGSEL_Pos [3/4]

#define DCB_DCRSR_REGSEL_Pos 0U

DCB DCRSR: Register selector Position

§ DCB_DCRSR_REGSEL_Msk [3/4]

#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

§ DCB_DCRDR_DBGTMP_Pos [3/4]

#define DCB_DCRDR_DBGTMP_Pos 0U

DCB DCRDR: Data temporary buffer Position

§ DCB_DCRDR_DBGTMP_Msk [3/4]

#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

§ DCB_DEMCR_TRCENA_Pos [3/4]

#define DCB_DEMCR_TRCENA_Pos 24U

DCB DEMCR: Trace enable Position

§ DCB_DEMCR_TRCENA_Msk [3/4]

#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

§ DCB_DEMCR_MONPRKEY_Pos [2/3]

#define DCB_DEMCR_MONPRKEY_Pos 23U

DCB DEMCR: Monitor pend req key Position

§ DCB_DEMCR_MONPRKEY_Msk [2/3]

#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

§ DCB_DEMCR_UMON_EN_Pos [2/3]

#define DCB_DEMCR_UMON_EN_Pos 21U

DCB DEMCR: Unprivileged monitor enable Position

§ DCB_DEMCR_UMON_EN_Msk [2/3]

#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

§ DCB_DEMCR_SDME_Pos [2/3]

#define DCB_DEMCR_SDME_Pos 20U

DCB DEMCR: Secure DebugMonitor enable Position

§ DCB_DEMCR_SDME_Msk [2/3]

#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

§ DCB_DEMCR_MON_REQ_Pos [2/3]

#define DCB_DEMCR_MON_REQ_Pos 19U

DCB DEMCR: Monitor request Position

§ DCB_DEMCR_MON_REQ_Msk [2/3]

#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

§ DCB_DEMCR_MON_STEP_Pos [2/3]

#define DCB_DEMCR_MON_STEP_Pos 18U

DCB DEMCR: Monitor step Position

§ DCB_DEMCR_MON_STEP_Msk [2/3]

#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

§ DCB_DEMCR_MON_PEND_Pos [2/3]

#define DCB_DEMCR_MON_PEND_Pos 17U

DCB DEMCR: Monitor pend Position

§ DCB_DEMCR_MON_PEND_Msk [2/3]

#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

§ DCB_DEMCR_MON_EN_Pos [2/3]

#define DCB_DEMCR_MON_EN_Pos 16U

DCB DEMCR: Monitor enable Position

§ DCB_DEMCR_MON_EN_Msk [2/3]

#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

§ DCB_DEMCR_VC_SFERR_Pos [2/3]

#define DCB_DEMCR_VC_SFERR_Pos 11U

DCB DEMCR: Vector Catch SecureFault Position

§ DCB_DEMCR_VC_SFERR_Msk [2/3]

#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

§ DCB_DEMCR_VC_HARDERR_Pos [3/4]

#define DCB_DEMCR_VC_HARDERR_Pos 10U

DCB DEMCR: Vector Catch HardFault errors Position

§ DCB_DEMCR_VC_HARDERR_Msk [3/4]

#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

§ DCB_DEMCR_VC_INTERR_Pos [2/3]

#define DCB_DEMCR_VC_INTERR_Pos 9U

DCB DEMCR: Vector Catch interrupt errors Position

§ DCB_DEMCR_VC_INTERR_Msk [2/3]

#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

§ DCB_DEMCR_VC_BUSERR_Pos [2/3]

#define DCB_DEMCR_VC_BUSERR_Pos 8U

DCB DEMCR: Vector Catch BusFault errors Position

§ DCB_DEMCR_VC_BUSERR_Msk [2/3]

#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

§ DCB_DEMCR_VC_STATERR_Pos [2/3]

#define DCB_DEMCR_VC_STATERR_Pos 7U

DCB DEMCR: Vector Catch state errors Position

§ DCB_DEMCR_VC_STATERR_Msk [2/3]

#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

§ DCB_DEMCR_VC_CHKERR_Pos [2/3]

#define DCB_DEMCR_VC_CHKERR_Pos 6U

DCB DEMCR: Vector Catch check errors Position

§ DCB_DEMCR_VC_CHKERR_Msk [2/3]

#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

§ DCB_DEMCR_VC_NOCPERR_Pos [2/3]

#define DCB_DEMCR_VC_NOCPERR_Pos 5U

DCB DEMCR: Vector Catch NOCP errors Position

§ DCB_DEMCR_VC_NOCPERR_Msk [2/3]

#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

§ DCB_DEMCR_VC_MMERR_Pos [2/3]

#define DCB_DEMCR_VC_MMERR_Pos 4U

DCB DEMCR: Vector Catch MemManage errors Position

§ DCB_DEMCR_VC_MMERR_Msk [2/3]

#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

§ DCB_DEMCR_VC_CORERESET_Pos [3/4]

#define DCB_DEMCR_VC_CORERESET_Pos 0U

DCB DEMCR: Vector Catch Core reset Position

§ DCB_DEMCR_VC_CORERESET_Msk [3/4]

#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

§ DCB_DAUTHCTRL_INTSPNIDEN_Pos [3/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPNIDEN_Msk [3/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

§ DCB_DAUTHCTRL_SPNIDENSEL_Pos [3/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

§ DCB_DAUTHCTRL_SPNIDENSEL_Msk [3/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

§ DCB_DAUTHCTRL_INTSPIDEN_Pos [3/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPIDEN_Msk [3/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

§ DCB_DAUTHCTRL_SPIDENSEL_Pos [3/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

§ DCB_DAUTHCTRL_SPIDENSEL_Msk [3/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

§ DCB_DSCSR_CDSKEY_Pos [3/4]

#define DCB_DSCSR_CDSKEY_Pos 17U

DCB DSCSR: CDS write-enable key Position

§ DCB_DSCSR_CDSKEY_Msk [3/4]

#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

§ DCB_DSCSR_CDS_Pos [3/4]

#define DCB_DSCSR_CDS_Pos 16U

DCB DSCSR: Current domain Secure Position

§ DCB_DSCSR_CDS_Msk [3/4]

#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

§ DCB_DSCSR_SBRSEL_Pos [3/4]

#define DCB_DSCSR_SBRSEL_Pos 1U

DCB DSCSR: Secure banked register select Position

§ DCB_DSCSR_SBRSEL_Msk [3/4]

#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

§ DCB_DSCSR_SBRSELEN_Pos [3/4]

#define DCB_DSCSR_SBRSELEN_Pos 0U

DCB DSCSR: Secure banked register select enable Position

§ DCB_DSCSR_SBRSELEN_Msk [3/4]

#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

§ DCB_DHCSR_DBGKEY_Pos [4/4]

#define DCB_DHCSR_DBGKEY_Pos 16U

DCB DHCSR: Debug key Position

§ DCB_DHCSR_DBGKEY_Msk [4/4]

#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)

DCB DHCSR: Debug key Mask

§ DCB_DHCSR_S_RESTART_ST_Pos [4/4]

#define DCB_DHCSR_S_RESTART_ST_Pos 26U

DCB DHCSR: Restart sticky status Position

§ DCB_DHCSR_S_RESTART_ST_Msk [4/4]

#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)

DCB DHCSR: Restart sticky status Mask

§ DCB_DHCSR_S_RESET_ST_Pos [4/4]

#define DCB_DHCSR_S_RESET_ST_Pos 25U

DCB DHCSR: Reset sticky status Position

§ DCB_DHCSR_S_RESET_ST_Msk [4/4]

#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)

DCB DHCSR: Reset sticky status Mask

§ DCB_DHCSR_S_RETIRE_ST_Pos [4/4]

#define DCB_DHCSR_S_RETIRE_ST_Pos 24U

DCB DHCSR: Retire sticky status Position

§ DCB_DHCSR_S_RETIRE_ST_Msk [4/4]

#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)

DCB DHCSR: Retire sticky status Mask

§ DCB_DHCSR_S_SDE_Pos [4/4]

#define DCB_DHCSR_S_SDE_Pos 20U

DCB DHCSR: Secure debug enabled Position

§ DCB_DHCSR_S_SDE_Msk [4/4]

#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)

DCB DHCSR: Secure debug enabled Mask

§ DCB_DHCSR_S_LOCKUP_Pos [4/4]

#define DCB_DHCSR_S_LOCKUP_Pos 19U

DCB DHCSR: Lockup status Position

§ DCB_DHCSR_S_LOCKUP_Msk [4/4]

#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)

DCB DHCSR: Lockup status Mask

§ DCB_DHCSR_S_SLEEP_Pos [4/4]

#define DCB_DHCSR_S_SLEEP_Pos 18U

DCB DHCSR: Sleeping status Position

§ DCB_DHCSR_S_SLEEP_Msk [4/4]

#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)

DCB DHCSR: Sleeping status Mask

§ DCB_DHCSR_S_HALT_Pos [4/4]

#define DCB_DHCSR_S_HALT_Pos 17U

DCB DHCSR: Halted status Position

§ DCB_DHCSR_S_HALT_Msk [4/4]

#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)

DCB DHCSR: Halted status Mask

§ DCB_DHCSR_S_REGRDY_Pos [4/4]

#define DCB_DHCSR_S_REGRDY_Pos 16U

DCB DHCSR: Register ready status Position

§ DCB_DHCSR_S_REGRDY_Msk [4/4]

#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)

DCB DHCSR: Register ready status Mask

§ DCB_DHCSR_C_SNAPSTALL_Pos [3/3]

#define DCB_DHCSR_C_SNAPSTALL_Pos 5U

DCB DHCSR: Snap stall control Position

§ DCB_DHCSR_C_SNAPSTALL_Msk [3/3]

#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)

DCB DHCSR: Snap stall control Mask

§ DCB_DHCSR_C_MASKINTS_Pos [4/4]

#define DCB_DHCSR_C_MASKINTS_Pos 3U

DCB DHCSR: Mask interrupts control Position

§ DCB_DHCSR_C_MASKINTS_Msk [4/4]

#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)

DCB DHCSR: Mask interrupts control Mask

§ DCB_DHCSR_C_STEP_Pos [4/4]

#define DCB_DHCSR_C_STEP_Pos 2U

DCB DHCSR: Step control Position

§ DCB_DHCSR_C_STEP_Msk [4/4]

#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)

DCB DHCSR: Step control Mask

§ DCB_DHCSR_C_HALT_Pos [4/4]

#define DCB_DHCSR_C_HALT_Pos 1U

DCB DHCSR: Halt control Position

§ DCB_DHCSR_C_HALT_Msk [4/4]

#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)

DCB DHCSR: Halt control Mask

§ DCB_DHCSR_C_DEBUGEN_Pos [4/4]

#define DCB_DHCSR_C_DEBUGEN_Pos 0U

DCB DHCSR: Debug enable control Position

§ DCB_DHCSR_C_DEBUGEN_Msk [4/4]

#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)

DCB DHCSR: Debug enable control Mask

§ DCB_DCRSR_REGWnR_Pos [4/4]

#define DCB_DCRSR_REGWnR_Pos 16U

DCB DCRSR: Register write/not-read Position

§ DCB_DCRSR_REGWnR_Msk [4/4]

#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)

DCB DCRSR: Register write/not-read Mask

§ DCB_DCRSR_REGSEL_Pos [4/4]

#define DCB_DCRSR_REGSEL_Pos 0U

DCB DCRSR: Register selector Position

§ DCB_DCRSR_REGSEL_Msk [4/4]

#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)

DCB DCRSR: Register selector Mask

§ DCB_DCRDR_DBGTMP_Pos [4/4]

#define DCB_DCRDR_DBGTMP_Pos 0U

DCB DCRDR: Data temporary buffer Position

§ DCB_DCRDR_DBGTMP_Msk [4/4]

#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)

DCB DCRDR: Data temporary buffer Mask

§ DCB_DEMCR_TRCENA_Pos [4/4]

#define DCB_DEMCR_TRCENA_Pos 24U

DCB DEMCR: Trace enable Position

§ DCB_DEMCR_TRCENA_Msk [4/4]

#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)

DCB DEMCR: Trace enable Mask

§ DCB_DEMCR_MONPRKEY_Pos [3/3]

#define DCB_DEMCR_MONPRKEY_Pos 23U

DCB DEMCR: Monitor pend req key Position

§ DCB_DEMCR_MONPRKEY_Msk [3/3]

#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)

DCB DEMCR: Monitor pend req key Mask

§ DCB_DEMCR_UMON_EN_Pos [3/3]

#define DCB_DEMCR_UMON_EN_Pos 21U

DCB DEMCR: Unprivileged monitor enable Position

§ DCB_DEMCR_UMON_EN_Msk [3/3]

#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)

DCB DEMCR: Unprivileged monitor enable Mask

§ DCB_DEMCR_SDME_Pos [3/3]

#define DCB_DEMCR_SDME_Pos 20U

DCB DEMCR: Secure DebugMonitor enable Position

§ DCB_DEMCR_SDME_Msk [3/3]

#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)

DCB DEMCR: Secure DebugMonitor enable Mask

§ DCB_DEMCR_MON_REQ_Pos [3/3]

#define DCB_DEMCR_MON_REQ_Pos 19U

DCB DEMCR: Monitor request Position

§ DCB_DEMCR_MON_REQ_Msk [3/3]

#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)

DCB DEMCR: Monitor request Mask

§ DCB_DEMCR_MON_STEP_Pos [3/3]

#define DCB_DEMCR_MON_STEP_Pos 18U

DCB DEMCR: Monitor step Position

§ DCB_DEMCR_MON_STEP_Msk [3/3]

#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)

DCB DEMCR: Monitor step Mask

§ DCB_DEMCR_MON_PEND_Pos [3/3]

#define DCB_DEMCR_MON_PEND_Pos 17U

DCB DEMCR: Monitor pend Position

§ DCB_DEMCR_MON_PEND_Msk [3/3]

#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)

DCB DEMCR: Monitor pend Mask

§ DCB_DEMCR_MON_EN_Pos [3/3]

#define DCB_DEMCR_MON_EN_Pos 16U

DCB DEMCR: Monitor enable Position

§ DCB_DEMCR_MON_EN_Msk [3/3]

#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)

DCB DEMCR: Monitor enable Mask

§ DCB_DEMCR_VC_SFERR_Pos [3/3]

#define DCB_DEMCR_VC_SFERR_Pos 11U

DCB DEMCR: Vector Catch SecureFault Position

§ DCB_DEMCR_VC_SFERR_Msk [3/3]

#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)

DCB DEMCR: Vector Catch SecureFault Mask

§ DCB_DEMCR_VC_HARDERR_Pos [4/4]

#define DCB_DEMCR_VC_HARDERR_Pos 10U

DCB DEMCR: Vector Catch HardFault errors Position

§ DCB_DEMCR_VC_HARDERR_Msk [4/4]

#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)

DCB DEMCR: Vector Catch HardFault errors Mask

§ DCB_DEMCR_VC_INTERR_Pos [3/3]

#define DCB_DEMCR_VC_INTERR_Pos 9U

DCB DEMCR: Vector Catch interrupt errors Position

§ DCB_DEMCR_VC_INTERR_Msk [3/3]

#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)

DCB DEMCR: Vector Catch interrupt errors Mask

§ DCB_DEMCR_VC_BUSERR_Pos [3/3]

#define DCB_DEMCR_VC_BUSERR_Pos 8U

DCB DEMCR: Vector Catch BusFault errors Position

§ DCB_DEMCR_VC_BUSERR_Msk [3/3]

#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)

DCB DEMCR: Vector Catch BusFault errors Mask

§ DCB_DEMCR_VC_STATERR_Pos [3/3]

#define DCB_DEMCR_VC_STATERR_Pos 7U

DCB DEMCR: Vector Catch state errors Position

§ DCB_DEMCR_VC_STATERR_Msk [3/3]

#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)

DCB DEMCR: Vector Catch state errors Mask

§ DCB_DEMCR_VC_CHKERR_Pos [3/3]

#define DCB_DEMCR_VC_CHKERR_Pos 6U

DCB DEMCR: Vector Catch check errors Position

§ DCB_DEMCR_VC_CHKERR_Msk [3/3]

#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)

DCB DEMCR: Vector Catch check errors Mask

§ DCB_DEMCR_VC_NOCPERR_Pos [3/3]

#define DCB_DEMCR_VC_NOCPERR_Pos 5U

DCB DEMCR: Vector Catch NOCP errors Position

§ DCB_DEMCR_VC_NOCPERR_Msk [3/3]

#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)

DCB DEMCR: Vector Catch NOCP errors Mask

§ DCB_DEMCR_VC_MMERR_Pos [3/3]

#define DCB_DEMCR_VC_MMERR_Pos 4U

DCB DEMCR: Vector Catch MemManage errors Position

§ DCB_DEMCR_VC_MMERR_Msk [3/3]

#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)

DCB DEMCR: Vector Catch MemManage errors Mask

§ DCB_DEMCR_VC_CORERESET_Pos [4/4]

#define DCB_DEMCR_VC_CORERESET_Pos 0U

DCB DEMCR: Vector Catch Core reset Position

§ DCB_DEMCR_VC_CORERESET_Msk [4/4]

#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)

DCB DEMCR: Vector Catch Core reset Mask

§ DCB_DAUTHCTRL_INTSPNIDEN_Pos [4/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPNIDEN_Msk [4/4]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask

§ DCB_DAUTHCTRL_SPNIDENSEL_Pos [4/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position

§ DCB_DAUTHCTRL_SPNIDENSEL_Msk [4/4]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask

§ DCB_DAUTHCTRL_INTSPIDEN_Pos [4/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position

§ DCB_DAUTHCTRL_INTSPIDEN_Msk [4/4]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask

§ DCB_DAUTHCTRL_SPIDENSEL_Pos [4/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position

§ DCB_DAUTHCTRL_SPIDENSEL_Msk [4/4]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask

§ DCB_DSCSR_CDSKEY_Pos [4/4]

#define DCB_DSCSR_CDSKEY_Pos 17U

DCB DSCSR: CDS write-enable key Position

§ DCB_DSCSR_CDSKEY_Msk [4/4]

#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)

DCB DSCSR: CDS write-enable key Mask

§ DCB_DSCSR_CDS_Pos [4/4]

#define DCB_DSCSR_CDS_Pos 16U

DCB DSCSR: Current domain Secure Position

§ DCB_DSCSR_CDS_Msk [4/4]

#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)

DCB DSCSR: Current domain Secure Mask

§ DCB_DSCSR_SBRSEL_Pos [4/4]

#define DCB_DSCSR_SBRSEL_Pos 1U

DCB DSCSR: Secure banked register select Position

§ DCB_DSCSR_SBRSEL_Msk [4/4]

#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)

DCB DSCSR: Secure banked register select Mask

§ DCB_DSCSR_SBRSELEN_Pos [4/4]

#define DCB_DSCSR_SBRSELEN_Pos 0U

DCB DSCSR: Secure banked register select enable Position

§ DCB_DSCSR_SBRSELEN_Msk [4/4]

#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)

DCB DSCSR: Secure banked register select enable Mask

Data Structures

Macros

Detailed Description

Macro Definition Documentation

§ DCB_DHCSR_DBGKEY_Pos [1/4]

§ DCB_DHCSR_DBGKEY_Msk [1/4]

§ DCB_DHCSR_S_RESTART_ST_Pos [1/4]

§ DCB_DHCSR_S_RESTART_ST_Msk [1/4]

§ DCB_DHCSR_S_RESET_ST_Pos [1/4]

§ DCB_DHCSR_S_RESET_ST_Msk [1/4]

§ DCB_DHCSR_S_RETIRE_ST_Pos [1/4]

§ DCB_DHCSR_S_RETIRE_ST_Msk [1/4]

§ DCB_DHCSR_S_FPD_Pos

§ DCB_DHCSR_S_FPD_Msk

§ DCB_DHCSR_S_SUIDE_Pos

§ DCB_DHCSR_S_SUIDE_Msk

§ DCB_DHCSR_S_NSUIDE_Pos

§ DCB_DHCSR_S_NSUIDE_Msk

§ DCB_DHCSR_S_SDE_Pos [1/4]

§ DCB_DHCSR_S_SDE_Msk [1/4]

§ DCB_DHCSR_S_LOCKUP_Pos [1/4]

§ DCB_DHCSR_S_LOCKUP_Msk [1/4]

§ DCB_DHCSR_S_SLEEP_Pos [1/4]

§ DCB_DHCSR_S_SLEEP_Msk [1/4]

§ DCB_DHCSR_S_HALT_Pos [1/4]

§ DCB_DHCSR_S_HALT_Msk [1/4]

§ DCB_DHCSR_S_REGRDY_Pos [1/4]

§ DCB_DHCSR_S_REGRDY_Msk [1/4]

§ DCB_DHCSR_C_PMOV_Pos

§ DCB_DHCSR_C_PMOV_Msk

§ DCB_DHCSR_C_SNAPSTALL_Pos [1/3]

§ DCB_DHCSR_C_SNAPSTALL_Msk [1/3]

§ DCB_DHCSR_C_MASKINTS_Pos [1/4]

§ DCB_DHCSR_C_MASKINTS_Msk [1/4]

§ DCB_DHCSR_C_STEP_Pos [1/4]

§ DCB_DHCSR_C_STEP_Msk [1/4]

§ DCB_DHCSR_C_HALT_Pos [1/4]

§ DCB_DHCSR_C_HALT_Msk [1/4]

§ DCB_DHCSR_C_DEBUGEN_Pos [1/4]

§ DCB_DHCSR_C_DEBUGEN_Msk [1/4]

§ DCB_DCRSR_REGWnR_Pos [1/4]

§ DCB_DCRSR_REGWnR_Msk [1/4]

§ DCB_DCRSR_REGSEL_Pos [1/4]

§ DCB_DCRSR_REGSEL_Msk [1/4]

§ DCB_DCRDR_DBGTMP_Pos [1/4]

§ DCB_DCRDR_DBGTMP_Msk [1/4]

§ DCB_DEMCR_TRCENA_Pos [1/4]

§ DCB_DEMCR_TRCENA_Msk [1/4]

§ DCB_DEMCR_MONPRKEY_Pos [1/3]

§ DCB_DEMCR_MONPRKEY_Msk [1/3]

§ DCB_DEMCR_UMON_EN_Pos [1/3]

§ DCB_DEMCR_UMON_EN_Msk [1/3]

§ DCB_DEMCR_SDME_Pos [1/3]

§ DCB_DEMCR_SDME_Msk [1/3]

§ DCB_DEMCR_MON_REQ_Pos [1/3]

§ DCB_DEMCR_MON_REQ_Msk [1/3]

§ DCB_DEMCR_MON_STEP_Pos [1/3]

§ DCB_DEMCR_MON_STEP_Msk [1/3]

§ DCB_DEMCR_MON_PEND_Pos [1/3]

§ DCB_DEMCR_MON_PEND_Msk [1/3]

§ DCB_DEMCR_MON_EN_Pos [1/3]

§ DCB_DEMCR_MON_EN_Msk [1/3]

§ DCB_DEMCR_VC_SFERR_Pos [1/3]

§ DCB_DEMCR_VC_SFERR_Msk [1/3]

§ DCB_DEMCR_VC_HARDERR_Pos [1/4]

§ DCB_DEMCR_VC_HARDERR_Msk [1/4]

§ DCB_DEMCR_VC_INTERR_Pos [1/3]

§ DCB_DEMCR_VC_INTERR_Msk [1/3]

§ DCB_DEMCR_VC_BUSERR_Pos [1/3]

§ DCB_DEMCR_VC_BUSERR_Msk [1/3]

§ DCB_DEMCR_VC_STATERR_Pos [1/3]

§ DCB_DEMCR_VC_STATERR_Msk [1/3]

§ DCB_DEMCR_VC_CHKERR_Pos [1/3]

§ DCB_DEMCR_VC_CHKERR_Msk [1/3]

§ DCB_DEMCR_VC_NOCPERR_Pos [1/3]

§ DCB_DEMCR_VC_NOCPERR_Msk [1/3]

§ DCB_DEMCR_VC_MMERR_Pos [1/3]

§ DCB_DEMCR_VC_MMERR_Msk [1/3]

§ DCB_DEMCR_VC_CORERESET_Pos [1/4]

§ DCB_DEMCR_VC_CORERESET_Msk [1/4]