CC27xxDriverLibrary
core_armv8mml.h
Go to the documentation of this file.
1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30  #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32 
33 #ifndef __CORE_ARMV8MML_H_GENERIC
34 #define __CORE_ARMV8MML_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
57 /*******************************************************************************
58  * CMSIS definitions
59  ******************************************************************************/
65 #include "cmsis_version.h"
66 
67 /* CMSIS Armv8MML definitions */
68 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
71  __ARMv8MML_CMSIS_VERSION_SUB )
73 #define __CORTEX_M (80U)
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
81  #define __FPU_USED 1U
82  #else
83  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84  #define __FPU_USED 0U
85  #endif
86  #else
87  #define __FPU_USED 0U
88  #endif
89 
90  #if defined(__ARM_FEATURE_DSP)
91  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
92  #define __DSP_USED 1U
93  #else
94  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
95  #define __DSP_USED 0U
96  #endif
97  #else
98  #define __DSP_USED 0U
99  #endif
100 
101 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
102  #if defined __ARM_FP
103  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
104  #define __FPU_USED 1U
105  #else
106  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107  #define __FPU_USED 0U
108  #endif
109  #else
110  #define __FPU_USED 0U
111  #endif
112 
113  #if defined(__ARM_FEATURE_DSP)
114  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
115  #define __DSP_USED 1U
116  #else
117  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
118  #define __DSP_USED 0U
119  #endif
120  #else
121  #define __DSP_USED 0U
122  #endif
123 
124 #elif defined (__ti__)
125  #if defined (__ARM_FP)
126  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
137  #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
138  #define __DSP_USED 1U
139  #else
140  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
141  #define __DSP_USED 0U
142  #endif
143  #else
144  #define __DSP_USED 0U
145  #endif
146 
147 #elif defined ( __GNUC__ )
148  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
149  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
150  #define __FPU_USED 1U
151  #else
152  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
153  #define __FPU_USED 0U
154  #endif
155  #else
156  #define __FPU_USED 0U
157  #endif
158 
159  #if defined(__ARM_FEATURE_DSP)
160  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
161  #define __DSP_USED 1U
162  #else
163  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
164  #define __DSP_USED 0U
165  #endif
166  #else
167  #define __DSP_USED 0U
168  #endif
169 
170 #elif defined ( __ICCARM__ )
171  #if defined __ARMVFP__
172  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
173  #define __FPU_USED 1U
174  #else
175  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
176  #define __FPU_USED 0U
177  #endif
178  #else
179  #define __FPU_USED 0U
180  #endif
181 
182  #if defined(__ARM_FEATURE_DSP)
183  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
184  #define __DSP_USED 1U
185  #else
186  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
187  #define __DSP_USED 0U
188  #endif
189  #else
190  #define __DSP_USED 0U
191  #endif
192 
193 #elif defined ( __TI_ARM__ )
194  #if defined __TI_VFP_SUPPORT__
195  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
196  #define __FPU_USED 1U
197  #else
198  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
199  #define __FPU_USED 0U
200  #endif
201  #else
202  #define __FPU_USED 0U
203  #endif
204 
205 #elif defined ( __TASKING__ )
206  #if defined __FPU_VFP__
207  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
208  #define __FPU_USED 1U
209  #else
210  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
211  #define __FPU_USED 0U
212  #endif
213  #else
214  #define __FPU_USED 0U
215  #endif
216 
217 #elif defined ( __CSMC__ )
218  #if ( __CSMC__ & 0x400U)
219  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
220  #define __FPU_USED 1U
221  #else
222  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
223  #define __FPU_USED 0U
224  #endif
225  #else
226  #define __FPU_USED 0U
227  #endif
228 
229 #endif
230 
231 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
232 
233 
234 #ifdef __cplusplus
235 }
236 #endif
237 
238 #endif /* __CORE_ARMV8MML_H_GENERIC */
239 
240 #ifndef __CMSIS_GENERIC
241 
242 #ifndef __CORE_ARMV8MML_H_DEPENDANT
243 #define __CORE_ARMV8MML_H_DEPENDANT
244 
245 #ifdef __cplusplus
246  extern "C" {
247 #endif
248 
249 /* check device defines and use defaults */
250 #if defined __CHECK_DEVICE_DEFINES
251  #ifndef __ARMv8MML_REV
252  #define __ARMv8MML_REV 0x0000U
253  #warning "__ARMv8MML_REV not defined in device header file; using default!"
254  #endif
255 
256  #ifndef __FPU_PRESENT
257  #define __FPU_PRESENT 0U
258  #warning "__FPU_PRESENT not defined in device header file; using default!"
259  #endif
260 
261  #ifndef __MPU_PRESENT
262  #define __MPU_PRESENT 0U
263  #warning "__MPU_PRESENT not defined in device header file; using default!"
264  #endif
265 
266  #ifndef __SAUREGION_PRESENT
267  #define __SAUREGION_PRESENT 0U
268  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
269  #endif
270 
271  #ifndef __DSP_PRESENT
272  #define __DSP_PRESENT 0U
273  #warning "__DSP_PRESENT not defined in device header file; using default!"
274  #endif
275 
276  #ifndef __VTOR_PRESENT
277  #define __VTOR_PRESENT 1U
278  #warning "__VTOR_PRESENT not defined in device header file; using default!"
279  #endif
280 
281  #ifndef __NVIC_PRIO_BITS
282  #define __NVIC_PRIO_BITS 3U
283  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
284  #endif
285 
286  #ifndef __Vendor_SysTickConfig
287  #define __Vendor_SysTickConfig 0U
288  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
289  #endif
290 #endif
291 
292 /* IO definitions (access restrictions to peripheral registers) */
300 #ifdef __cplusplus
301  #define __I volatile
302 #else
303  #define __I volatile const
304 #endif
305 #define __O volatile
306 #define __IO volatile
308 /* following defines should be used for structure members */
309 #define __IM volatile const
310 #define __OM volatile
311 #define __IOM volatile
317 /*******************************************************************************
318  * Register Abstraction
319  Core Register contain:
320  - Core Register
321  - Core NVIC Register
322  - Core SCB Register
323  - Core SysTick Register
324  - Core Debug Register
325  - Core MPU Register
326  - Core SAU Register
327  - Core FPU Register
328  ******************************************************************************/
329 
344 typedef union
345 {
346  struct
347  {
348  uint32_t _reserved0:16;
349  uint32_t GE:4;
350  uint32_t _reserved1:7;
351  uint32_t Q:1;
352  uint32_t V:1;
353  uint32_t C:1;
354  uint32_t Z:1;
355  uint32_t N:1;
356  } b;
357  uint32_t w;
358 } APSR_Type;
359 
360 /* APSR Register Definitions */
361 #define APSR_N_Pos 31U
362 #define APSR_N_Msk (1UL << APSR_N_Pos)
364 #define APSR_Z_Pos 30U
365 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
367 #define APSR_C_Pos 29U
368 #define APSR_C_Msk (1UL << APSR_C_Pos)
370 #define APSR_V_Pos 28U
371 #define APSR_V_Msk (1UL << APSR_V_Pos)
373 #define APSR_Q_Pos 27U
374 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
376 #define APSR_GE_Pos 16U
377 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
383 typedef union
384 {
385  struct
386  {
387  uint32_t ISR:9;
388  uint32_t _reserved0:23;
389  } b;
390  uint32_t w;
391 } IPSR_Type;
392 
393 /* IPSR Register Definitions */
394 #define IPSR_ISR_Pos 0U
395 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
401 typedef union
402 {
403  struct
404  {
405  uint32_t ISR:9;
406  uint32_t _reserved0:7;
407  uint32_t GE:4;
408  uint32_t _reserved1:4;
409  uint32_t T:1;
410  uint32_t IT:2;
411  uint32_t Q:1;
412  uint32_t V:1;
413  uint32_t C:1;
414  uint32_t Z:1;
415  uint32_t N:1;
416  } b;
417  uint32_t w;
418 } xPSR_Type;
419 
420 /* xPSR Register Definitions */
421 #define xPSR_N_Pos 31U
422 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
424 #define xPSR_Z_Pos 30U
425 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
427 #define xPSR_C_Pos 29U
428 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
430 #define xPSR_V_Pos 28U
431 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
433 #define xPSR_Q_Pos 27U
434 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
436 #define xPSR_IT_Pos 25U
437 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
439 #define xPSR_T_Pos 24U
440 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
442 #define xPSR_GE_Pos 16U
443 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
445 #define xPSR_ISR_Pos 0U
446 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
452 typedef union
453 {
454  struct
455  {
456  uint32_t nPRIV:1;
457  uint32_t SPSEL:1;
458  uint32_t FPCA:1;
459  uint32_t SFPA:1;
460  uint32_t _reserved1:28;
461  } b;
462  uint32_t w;
463 } CONTROL_Type;
464 
465 /* CONTROL Register Definitions */
466 #define CONTROL_SFPA_Pos 3U
467 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
469 #define CONTROL_FPCA_Pos 2U
470 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
472 #define CONTROL_SPSEL_Pos 1U
473 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
475 #define CONTROL_nPRIV_Pos 0U
476 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
491 typedef struct
492 {
493  __IOM uint32_t ISER[16U];
494  uint32_t RESERVED0[16U];
495  __IOM uint32_t ICER[16U];
496  uint32_t RSERVED1[16U];
497  __IOM uint32_t ISPR[16U];
498  uint32_t RESERVED2[16U];
499  __IOM uint32_t ICPR[16U];
500  uint32_t RESERVED3[16U];
501  __IOM uint32_t IABR[16U];
502  uint32_t RESERVED4[16U];
503  __IOM uint32_t ITNS[16U];
504  uint32_t RESERVED5[16U];
505  __IOM uint8_t IPR[496U];
506  uint32_t RESERVED6[580U];
507  __OM uint32_t STIR;
508 } NVIC_Type;
509 
510 /* Software Triggered Interrupt Register Definitions */
511 #define NVIC_STIR_INTID_Pos 0U
512 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
527 typedef struct
528 {
529  __IM uint32_t CPUID;
530  __IOM uint32_t ICSR;
531  __IOM uint32_t VTOR;
532  __IOM uint32_t AIRCR;
533  __IOM uint32_t SCR;
534  __IOM uint32_t CCR;
535  __IOM uint8_t SHPR[12U];
536  __IOM uint32_t SHCSR;
537  __IOM uint32_t CFSR;
538  __IOM uint32_t HFSR;
539  __IOM uint32_t DFSR;
540  __IOM uint32_t MMFAR;
541  __IOM uint32_t BFAR;
542  __IOM uint32_t AFSR;
543  __IM uint32_t ID_PFR[2U];
544  __IM uint32_t ID_DFR;
545  __IM uint32_t ID_AFR;
546  __IM uint32_t ID_MMFR[4U];
547  __IM uint32_t ID_ISAR[6U];
548  __IM uint32_t CLIDR;
549  __IM uint32_t CTR;
550  __IM uint32_t CCSIDR;
551  __IOM uint32_t CSSELR;
552  __IOM uint32_t CPACR;
553  __IOM uint32_t NSACR;
554  uint32_t RESERVED7[21U];
555  __IOM uint32_t SFSR;
556  __IOM uint32_t SFAR;
557  uint32_t RESERVED3[69U];
558  __OM uint32_t STIR;
559  uint32_t RESERVED4[15U];
560  __IM uint32_t MVFR0;
561  __IM uint32_t MVFR1;
562  __IM uint32_t MVFR2;
563  uint32_t RESERVED5[1U];
564  __OM uint32_t ICIALLU;
565  uint32_t RESERVED6[1U];
566  __OM uint32_t ICIMVAU;
567  __OM uint32_t DCIMVAC;
568  __OM uint32_t DCISW;
569  __OM uint32_t DCCMVAU;
570  __OM uint32_t DCCMVAC;
571  __OM uint32_t DCCSW;
572  __OM uint32_t DCCIMVAC;
573  __OM uint32_t DCCISW;
574  __OM uint32_t BPIALL;
575 } SCB_Type;
576 
577 /* SCB CPUID Register Definitions */
578 #define SCB_CPUID_IMPLEMENTER_Pos 24U
579 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
581 #define SCB_CPUID_VARIANT_Pos 20U
582 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
584 #define SCB_CPUID_ARCHITECTURE_Pos 16U
585 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
587 #define SCB_CPUID_PARTNO_Pos 4U
588 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
590 #define SCB_CPUID_REVISION_Pos 0U
591 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
593 /* SCB Interrupt Control State Register Definitions */
594 #define SCB_ICSR_PENDNMISET_Pos 31U
595 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
597 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
598 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
600 #define SCB_ICSR_PENDNMICLR_Pos 30U
601 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
603 #define SCB_ICSR_PENDSVSET_Pos 28U
604 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
606 #define SCB_ICSR_PENDSVCLR_Pos 27U
607 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
609 #define SCB_ICSR_PENDSTSET_Pos 26U
610 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
612 #define SCB_ICSR_PENDSTCLR_Pos 25U
613 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
615 #define SCB_ICSR_STTNS_Pos 24U
616 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
618 #define SCB_ICSR_ISRPREEMPT_Pos 23U
619 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
621 #define SCB_ICSR_ISRPENDING_Pos 22U
622 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
624 #define SCB_ICSR_VECTPENDING_Pos 12U
625 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
627 #define SCB_ICSR_RETTOBASE_Pos 11U
628 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
630 #define SCB_ICSR_VECTACTIVE_Pos 0U
631 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
633 /* SCB Vector Table Offset Register Definitions */
634 #define SCB_VTOR_TBLOFF_Pos 7U
635 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
637 /* SCB Application Interrupt and Reset Control Register Definitions */
638 #define SCB_AIRCR_VECTKEY_Pos 16U
639 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
641 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
642 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
644 #define SCB_AIRCR_ENDIANESS_Pos 15U
645 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
647 #define SCB_AIRCR_PRIS_Pos 14U
648 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
650 #define SCB_AIRCR_BFHFNMINS_Pos 13U
651 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
653 #define SCB_AIRCR_PRIGROUP_Pos 8U
654 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
656 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
657 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
659 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
660 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
662 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
663 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
665 /* SCB System Control Register Definitions */
666 #define SCB_SCR_SEVONPEND_Pos 4U
667 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
669 #define SCB_SCR_SLEEPDEEPS_Pos 3U
670 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
672 #define SCB_SCR_SLEEPDEEP_Pos 2U
673 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
675 #define SCB_SCR_SLEEPONEXIT_Pos 1U
676 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
678 /* SCB Configuration Control Register Definitions */
679 #define SCB_CCR_BP_Pos 18U
680 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
682 #define SCB_CCR_IC_Pos 17U
683 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
685 #define SCB_CCR_DC_Pos 16U
686 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
688 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
689 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
691 #define SCB_CCR_BFHFNMIGN_Pos 8U
692 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
694 #define SCB_CCR_DIV_0_TRP_Pos 4U
695 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
697 #define SCB_CCR_UNALIGN_TRP_Pos 3U
698 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
700 #define SCB_CCR_USERSETMPEND_Pos 1U
701 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
703 /* SCB System Handler Control and State Register Definitions */
704 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
705 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
707 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
708 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
710 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
711 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
713 #define SCB_SHCSR_USGFAULTENA_Pos 18U
714 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
716 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
717 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
719 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
720 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
722 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
723 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
725 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
726 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
728 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
729 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
731 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
732 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
734 #define SCB_SHCSR_SYSTICKACT_Pos 11U
735 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
737 #define SCB_SHCSR_PENDSVACT_Pos 10U
738 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
740 #define SCB_SHCSR_MONITORACT_Pos 8U
741 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
743 #define SCB_SHCSR_SVCALLACT_Pos 7U
744 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
746 #define SCB_SHCSR_NMIACT_Pos 5U
747 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
749 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
750 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
752 #define SCB_SHCSR_USGFAULTACT_Pos 3U
753 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
755 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
756 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
758 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
759 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
761 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
762 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
764 /* SCB Configurable Fault Status Register Definitions */
765 #define SCB_CFSR_USGFAULTSR_Pos 16U
766 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
768 #define SCB_CFSR_BUSFAULTSR_Pos 8U
769 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
771 #define SCB_CFSR_MEMFAULTSR_Pos 0U
772 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
774 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
775 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
776 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
778 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
779 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
781 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
782 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
784 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
785 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
787 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
788 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
790 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
791 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
793 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
794 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
795 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
797 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
798 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
800 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
801 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
803 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
804 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
806 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
807 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
809 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
810 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
812 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
813 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
815 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
816 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
817 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
819 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
820 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
822 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
823 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
825 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
826 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
828 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
829 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
831 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
832 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
834 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
835 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
837 /* SCB Hard Fault Status Register Definitions */
838 #define SCB_HFSR_DEBUGEVT_Pos 31U
839 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
841 #define SCB_HFSR_FORCED_Pos 30U
842 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
844 #define SCB_HFSR_VECTTBL_Pos 1U
845 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
847 /* SCB Debug Fault Status Register Definitions */
848 #define SCB_DFSR_EXTERNAL_Pos 4U
849 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
851 #define SCB_DFSR_VCATCH_Pos 3U
852 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
854 #define SCB_DFSR_DWTTRAP_Pos 2U
855 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
857 #define SCB_DFSR_BKPT_Pos 1U
858 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
860 #define SCB_DFSR_HALTED_Pos 0U
861 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
863 /* SCB Non-Secure Access Control Register Definitions */
864 #define SCB_NSACR_CP11_Pos 11U
865 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
867 #define SCB_NSACR_CP10_Pos 10U
868 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
870 #define SCB_NSACR_CPn_Pos 0U
871 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
873 /* SCB Cache Level ID Register Definitions */
874 #define SCB_CLIDR_LOUU_Pos 27U
875 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
877 #define SCB_CLIDR_LOC_Pos 24U
878 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
880 /* SCB Cache Type Register Definitions */
881 #define SCB_CTR_FORMAT_Pos 29U
882 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
884 #define SCB_CTR_CWG_Pos 24U
885 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
887 #define SCB_CTR_ERG_Pos 20U
888 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
890 #define SCB_CTR_DMINLINE_Pos 16U
891 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
893 #define SCB_CTR_IMINLINE_Pos 0U
894 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
896 /* SCB Cache Size ID Register Definitions */
897 #define SCB_CCSIDR_WT_Pos 31U
898 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
900 #define SCB_CCSIDR_WB_Pos 30U
901 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
903 #define SCB_CCSIDR_RA_Pos 29U
904 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
906 #define SCB_CCSIDR_WA_Pos 28U
907 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
909 #define SCB_CCSIDR_NUMSETS_Pos 13U
910 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
912 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
913 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
915 #define SCB_CCSIDR_LINESIZE_Pos 0U
916 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
918 /* SCB Cache Size Selection Register Definitions */
919 #define SCB_CSSELR_LEVEL_Pos 1U
920 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
922 #define SCB_CSSELR_IND_Pos 0U
923 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
925 /* SCB Software Triggered Interrupt Register Definitions */
926 #define SCB_STIR_INTID_Pos 0U
927 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
929 /* SCB D-Cache Invalidate by Set-way Register Definitions */
930 #define SCB_DCISW_WAY_Pos 30U
931 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
933 #define SCB_DCISW_SET_Pos 5U
934 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
936 /* SCB D-Cache Clean by Set-way Register Definitions */
937 #define SCB_DCCSW_WAY_Pos 30U
938 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
940 #define SCB_DCCSW_SET_Pos 5U
941 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
943 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
944 #define SCB_DCCISW_WAY_Pos 30U
945 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
947 #define SCB_DCCISW_SET_Pos 5U
948 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
963 typedef struct
964 {
965  uint32_t RESERVED0[1U];
966  __IM uint32_t ICTR;
967  __IOM uint32_t ACTLR;
968  __IOM uint32_t CPPWR;
969 } SCnSCB_Type;
970 
971 /* Interrupt Controller Type Register Definitions */
972 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
973 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
988 typedef struct
989 {
990  __IOM uint32_t CTRL;
991  __IOM uint32_t LOAD;
992  __IOM uint32_t VAL;
993  __IM uint32_t CALIB;
994 } SysTick_Type;
995 
996 /* SysTick Control / Status Register Definitions */
997 #define SysTick_CTRL_COUNTFLAG_Pos 16U
998 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1000 #define SysTick_CTRL_CLKSOURCE_Pos 2U
1001 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1003 #define SysTick_CTRL_TICKINT_Pos 1U
1004 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1006 #define SysTick_CTRL_ENABLE_Pos 0U
1007 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1009 /* SysTick Reload Register Definitions */
1010 #define SysTick_LOAD_RELOAD_Pos 0U
1011 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1013 /* SysTick Current Register Definitions */
1014 #define SysTick_VAL_CURRENT_Pos 0U
1015 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1017 /* SysTick Calibration Register Definitions */
1018 #define SysTick_CALIB_NOREF_Pos 31U
1019 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1021 #define SysTick_CALIB_SKEW_Pos 30U
1022 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1024 #define SysTick_CALIB_TENMS_Pos 0U
1025 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1040 typedef struct
1041 {
1042  __OM union
1043  {
1044  __OM uint8_t u8;
1045  __OM uint16_t u16;
1046  __OM uint32_t u32;
1047  } PORT [32U];
1048  uint32_t RESERVED0[864U];
1049  __IOM uint32_t TER;
1050  uint32_t RESERVED1[15U];
1051  __IOM uint32_t TPR;
1052  uint32_t RESERVED2[15U];
1053  __IOM uint32_t TCR;
1054  uint32_t RESERVED3[32U];
1055  uint32_t RESERVED4[43U];
1056  __OM uint32_t LAR;
1057  __IM uint32_t LSR;
1058  uint32_t RESERVED5[1U];
1059  __IM uint32_t DEVARCH;
1060  uint32_t RESERVED6[4U];
1061  __IM uint32_t PID4;
1062  __IM uint32_t PID5;
1063  __IM uint32_t PID6;
1064  __IM uint32_t PID7;
1065  __IM uint32_t PID0;
1066  __IM uint32_t PID1;
1067  __IM uint32_t PID2;
1068  __IM uint32_t PID3;
1069  __IM uint32_t CID0;
1070  __IM uint32_t CID1;
1071  __IM uint32_t CID2;
1072  __IM uint32_t CID3;
1073 } ITM_Type;
1074 
1075 /* ITM Stimulus Port Register Definitions */
1076 #define ITM_STIM_DISABLED_Pos 1U
1077 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1079 #define ITM_STIM_FIFOREADY_Pos 0U
1080 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1082 /* ITM Trace Privilege Register Definitions */
1083 #define ITM_TPR_PRIVMASK_Pos 0U
1084 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1086 /* ITM Trace Control Register Definitions */
1087 #define ITM_TCR_BUSY_Pos 23U
1088 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1090 #define ITM_TCR_TRACEBUSID_Pos 16U
1091 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1093 #define ITM_TCR_GTSFREQ_Pos 10U
1094 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1096 #define ITM_TCR_TSPRESCALE_Pos 8U
1097 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1099 #define ITM_TCR_STALLENA_Pos 5U
1100 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1102 #define ITM_TCR_SWOENA_Pos 4U
1103 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1105 #define ITM_TCR_DWTENA_Pos 3U
1106 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1108 #define ITM_TCR_SYNCENA_Pos 2U
1109 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1111 #define ITM_TCR_TSENA_Pos 1U
1112 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1114 #define ITM_TCR_ITMENA_Pos 0U
1115 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1117 /* ITM Lock Status Register Definitions */
1118 #define ITM_LSR_ByteAcc_Pos 2U
1119 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1121 #define ITM_LSR_Access_Pos 1U
1122 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1124 #define ITM_LSR_Present_Pos 0U
1125 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /* end of group CMSIS_ITM */
1128 
1129 
1140 typedef struct
1141 {
1142  __IOM uint32_t CTRL;
1143  __IOM uint32_t CYCCNT;
1144  __IOM uint32_t CPICNT;
1145  __IOM uint32_t EXCCNT;
1146  __IOM uint32_t SLEEPCNT;
1147  __IOM uint32_t LSUCNT;
1148  __IOM uint32_t FOLDCNT;
1149  __IM uint32_t PCSR;
1150  __IOM uint32_t COMP0;
1151  uint32_t RESERVED1[1U];
1152  __IOM uint32_t FUNCTION0;
1153  uint32_t RESERVED2[1U];
1154  __IOM uint32_t COMP1;
1155  uint32_t RESERVED3[1U];
1156  __IOM uint32_t FUNCTION1;
1157  uint32_t RESERVED4[1U];
1158  __IOM uint32_t COMP2;
1159  uint32_t RESERVED5[1U];
1160  __IOM uint32_t FUNCTION2;
1161  uint32_t RESERVED6[1U];
1162  __IOM uint32_t COMP3;
1163  uint32_t RESERVED7[1U];
1164  __IOM uint32_t FUNCTION3;
1165  uint32_t RESERVED8[1U];
1166  __IOM uint32_t COMP4;
1167  uint32_t RESERVED9[1U];
1168  __IOM uint32_t FUNCTION4;
1169  uint32_t RESERVED10[1U];
1170  __IOM uint32_t COMP5;
1171  uint32_t RESERVED11[1U];
1172  __IOM uint32_t FUNCTION5;
1173  uint32_t RESERVED12[1U];
1174  __IOM uint32_t COMP6;
1175  uint32_t RESERVED13[1U];
1176  __IOM uint32_t FUNCTION6;
1177  uint32_t RESERVED14[1U];
1178  __IOM uint32_t COMP7;
1179  uint32_t RESERVED15[1U];
1180  __IOM uint32_t FUNCTION7;
1181  uint32_t RESERVED16[1U];
1182  __IOM uint32_t COMP8;
1183  uint32_t RESERVED17[1U];
1184  __IOM uint32_t FUNCTION8;
1185  uint32_t RESERVED18[1U];
1186  __IOM uint32_t COMP9;
1187  uint32_t RESERVED19[1U];
1188  __IOM uint32_t FUNCTION9;
1189  uint32_t RESERVED20[1U];
1190  __IOM uint32_t COMP10;
1191  uint32_t RESERVED21[1U];
1192  __IOM uint32_t FUNCTION10;
1193  uint32_t RESERVED22[1U];
1194  __IOM uint32_t COMP11;
1195  uint32_t RESERVED23[1U];
1196  __IOM uint32_t FUNCTION11;
1197  uint32_t RESERVED24[1U];
1198  __IOM uint32_t COMP12;
1199  uint32_t RESERVED25[1U];
1200  __IOM uint32_t FUNCTION12;
1201  uint32_t RESERVED26[1U];
1202  __IOM uint32_t COMP13;
1203  uint32_t RESERVED27[1U];
1204  __IOM uint32_t FUNCTION13;
1205  uint32_t RESERVED28[1U];
1206  __IOM uint32_t COMP14;
1207  uint32_t RESERVED29[1U];
1208  __IOM uint32_t FUNCTION14;
1209  uint32_t RESERVED30[1U];
1210  __IOM uint32_t COMP15;
1211  uint32_t RESERVED31[1U];
1212  __IOM uint32_t FUNCTION15;
1213  uint32_t RESERVED32[934U];
1214  __IM uint32_t LSR;
1215  uint32_t RESERVED33[1U];
1216  __IM uint32_t DEVARCH;
1217 } DWT_Type;
1218 
1219 /* DWT Control Register Definitions */
1220 #define DWT_CTRL_NUMCOMP_Pos 28U
1221 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1223 #define DWT_CTRL_NOTRCPKT_Pos 27U
1224 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1226 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1227 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1229 #define DWT_CTRL_NOCYCCNT_Pos 25U
1230 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1232 #define DWT_CTRL_NOPRFCNT_Pos 24U
1233 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1235 #define DWT_CTRL_CYCDISS_Pos 23U
1236 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1238 #define DWT_CTRL_CYCEVTENA_Pos 22U
1239 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1241 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1242 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1244 #define DWT_CTRL_LSUEVTENA_Pos 20U
1245 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1247 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1248 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1250 #define DWT_CTRL_EXCEVTENA_Pos 18U
1251 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1253 #define DWT_CTRL_CPIEVTENA_Pos 17U
1254 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1256 #define DWT_CTRL_EXCTRCENA_Pos 16U
1257 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1259 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1260 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1262 #define DWT_CTRL_SYNCTAP_Pos 10U
1263 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1265 #define DWT_CTRL_CYCTAP_Pos 9U
1266 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1268 #define DWT_CTRL_POSTINIT_Pos 5U
1269 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1271 #define DWT_CTRL_POSTPRESET_Pos 1U
1272 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1274 #define DWT_CTRL_CYCCNTENA_Pos 0U
1275 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1277 /* DWT CPI Count Register Definitions */
1278 #define DWT_CPICNT_CPICNT_Pos 0U
1279 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1281 /* DWT Exception Overhead Count Register Definitions */
1282 #define DWT_EXCCNT_EXCCNT_Pos 0U
1283 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1285 /* DWT Sleep Count Register Definitions */
1286 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1287 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1289 /* DWT LSU Count Register Definitions */
1290 #define DWT_LSUCNT_LSUCNT_Pos 0U
1291 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1293 /* DWT Folded-instruction Count Register Definitions */
1294 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1295 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1297 /* DWT Comparator Function Register Definitions */
1298 #define DWT_FUNCTION_ID_Pos 27U
1299 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1301 #define DWT_FUNCTION_MATCHED_Pos 24U
1302 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1304 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1305 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1307 #define DWT_FUNCTION_ACTION_Pos 4U
1308 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1310 #define DWT_FUNCTION_MATCH_Pos 0U
1311 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /* end of group CMSIS_DWT */
1314 
1315 
1326 typedef struct
1327 {
1328  __IM uint32_t SSPSR;
1329  __IOM uint32_t CSPSR;
1330  uint32_t RESERVED0[2U];
1331  __IOM uint32_t ACPR;
1332  uint32_t RESERVED1[55U];
1333  __IOM uint32_t SPPR;
1334  uint32_t RESERVED2[131U];
1335  __IM uint32_t FFSR;
1336  __IOM uint32_t FFCR;
1337  __IOM uint32_t PSCR;
1338  uint32_t RESERVED3[809U];
1339  __OM uint32_t LAR;
1340  __IM uint32_t LSR;
1341  uint32_t RESERVED4[4U];
1342  __IM uint32_t TYPE;
1343  __IM uint32_t DEVTYPE;
1344 } TPI_Type;
1345 
1346 /* TPI Asynchronous Clock Prescaler Register Definitions */
1347 #define TPI_ACPR_SWOSCALER_Pos 0U
1348 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
1350 /* TPI Selected Pin Protocol Register Definitions */
1351 #define TPI_SPPR_TXMODE_Pos 0U
1352 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1354 /* TPI Formatter and Flush Status Register Definitions */
1355 #define TPI_FFSR_FtNonStop_Pos 3U
1356 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1358 #define TPI_FFSR_TCPresent_Pos 2U
1359 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1361 #define TPI_FFSR_FtStopped_Pos 1U
1362 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1364 #define TPI_FFSR_FlInProg_Pos 0U
1365 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1367 /* TPI Formatter and Flush Control Register Definitions */
1368 #define TPI_FFCR_TrigIn_Pos 8U
1369 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1371 #define TPI_FFCR_FOnMan_Pos 6U
1372 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1374 #define TPI_FFCR_EnFCont_Pos 1U
1375 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1377 /* TPI Periodic Synchronization Control Register Definitions */
1378 #define TPI_PSCR_PSCount_Pos 0U
1379 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
1381 /* TPI Software Lock Status Register Definitions */
1382 #define TPI_LSR_nTT_Pos 1U
1383 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
1385 #define TPI_LSR_SLK_Pos 1U
1386 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
1388 #define TPI_LSR_SLI_Pos 0U
1389 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
1391 /* TPI DEVID Register Definitions */
1392 #define TPI_DEVID_NRZVALID_Pos 11U
1393 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1395 #define TPI_DEVID_MANCVALID_Pos 10U
1396 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1398 #define TPI_DEVID_PTINVALID_Pos 9U
1399 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1401 #define TPI_DEVID_FIFOSZ_Pos 6U
1402 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1404 /* TPI DEVTYPE Register Definitions */
1405 #define TPI_DEVTYPE_SubType_Pos 4U
1406 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1408 #define TPI_DEVTYPE_MajorType_Pos 0U
1409 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /* end of group CMSIS_TPI */
1412 
1413 
1414 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1415 
1425 typedef struct
1426 {
1427  __IM uint32_t TYPE;
1428  __IOM uint32_t CTRL;
1429  __IOM uint32_t RNR;
1430  __IOM uint32_t RBAR;
1431  __IOM uint32_t RLAR;
1432  __IOM uint32_t RBAR_A1;
1433  __IOM uint32_t RLAR_A1;
1434  __IOM uint32_t RBAR_A2;
1435  __IOM uint32_t RLAR_A2;
1436  __IOM uint32_t RBAR_A3;
1437  __IOM uint32_t RLAR_A3;
1438  uint32_t RESERVED0[1];
1439  union {
1440  __IOM uint32_t MAIR[2];
1441  struct {
1442  __IOM uint32_t MAIR0;
1443  __IOM uint32_t MAIR1;
1444  };
1445  };
1446 } MPU_Type;
1447 
1448 #define MPU_TYPE_RALIASES 4U
1449 
1450 /* MPU Type Register Definitions */
1451 #define MPU_TYPE_IREGION_Pos 16U
1452 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1454 #define MPU_TYPE_DREGION_Pos 8U
1455 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1457 #define MPU_TYPE_SEPARATE_Pos 0U
1458 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1460 /* MPU Control Register Definitions */
1461 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1462 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1464 #define MPU_CTRL_HFNMIENA_Pos 1U
1465 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1467 #define MPU_CTRL_ENABLE_Pos 0U
1468 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1470 /* MPU Region Number Register Definitions */
1471 #define MPU_RNR_REGION_Pos 0U
1472 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1474 /* MPU Region Base Address Register Definitions */
1475 #define MPU_RBAR_BASE_Pos 5U
1476 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1478 #define MPU_RBAR_SH_Pos 3U
1479 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1481 #define MPU_RBAR_AP_Pos 1U
1482 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1484 #define MPU_RBAR_XN_Pos 0U
1485 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1487 /* MPU Region Limit Address Register Definitions */
1488 #define MPU_RLAR_LIMIT_Pos 5U
1489 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1491 #define MPU_RLAR_AttrIndx_Pos 1U
1492 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1494 #define MPU_RLAR_EN_Pos 0U
1495 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1497 /* MPU Memory Attribute Indirection Register 0 Definitions */
1498 #define MPU_MAIR0_Attr3_Pos 24U
1499 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1501 #define MPU_MAIR0_Attr2_Pos 16U
1502 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1504 #define MPU_MAIR0_Attr1_Pos 8U
1505 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1507 #define MPU_MAIR0_Attr0_Pos 0U
1508 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1510 /* MPU Memory Attribute Indirection Register 1 Definitions */
1511 #define MPU_MAIR1_Attr7_Pos 24U
1512 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1514 #define MPU_MAIR1_Attr6_Pos 16U
1515 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1517 #define MPU_MAIR1_Attr5_Pos 8U
1518 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1520 #define MPU_MAIR1_Attr4_Pos 0U
1521 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1524 #endif
1525 
1526 
1527 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1528 
1538 typedef struct
1539 {
1540  __IOM uint32_t CTRL;
1541  __IM uint32_t TYPE;
1542 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1543  __IOM uint32_t RNR;
1544  __IOM uint32_t RBAR;
1545  __IOM uint32_t RLAR;
1546 #else
1547  uint32_t RESERVED0[3];
1548 #endif
1549  __IOM uint32_t SFSR;
1550  __IOM uint32_t SFAR;
1551 } SAU_Type;
1552 
1553 /* SAU Control Register Definitions */
1554 #define SAU_CTRL_ALLNS_Pos 1U
1555 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1557 #define SAU_CTRL_ENABLE_Pos 0U
1558 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1560 /* SAU Type Register Definitions */
1561 #define SAU_TYPE_SREGION_Pos 0U
1562 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1564 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1565 /* SAU Region Number Register Definitions */
1566 #define SAU_RNR_REGION_Pos 0U
1567 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1569 /* SAU Region Base Address Register Definitions */
1570 #define SAU_RBAR_BADDR_Pos 5U
1571 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1573 /* SAU Region Limit Address Register Definitions */
1574 #define SAU_RLAR_LADDR_Pos 5U
1575 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1577 #define SAU_RLAR_NSC_Pos 1U
1578 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1580 #define SAU_RLAR_ENABLE_Pos 0U
1581 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1583 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1584 
1585 /* Secure Fault Status Register Definitions */
1586 #define SAU_SFSR_LSERR_Pos 7U
1587 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1589 #define SAU_SFSR_SFARVALID_Pos 6U
1590 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1592 #define SAU_SFSR_LSPERR_Pos 5U
1593 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1595 #define SAU_SFSR_INVTRAN_Pos 4U
1596 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1598 #define SAU_SFSR_AUVIOL_Pos 3U
1599 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1601 #define SAU_SFSR_INVER_Pos 2U
1602 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1604 #define SAU_SFSR_INVIS_Pos 1U
1605 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1607 #define SAU_SFSR_INVEP_Pos 0U
1608 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1611 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1612 
1613 
1624 typedef struct
1625 {
1626  uint32_t RESERVED0[1U];
1627  __IOM uint32_t FPCCR;
1628  __IOM uint32_t FPCAR;
1629  __IOM uint32_t FPDSCR;
1630  __IM uint32_t MVFR0;
1631  __IM uint32_t MVFR1;
1632  __IM uint32_t MVFR2;
1633 } FPU_Type;
1634 
1635 /* Floating-Point Context Control Register Definitions */
1636 #define FPU_FPCCR_ASPEN_Pos 31U
1637 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1639 #define FPU_FPCCR_LSPEN_Pos 30U
1640 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1642 #define FPU_FPCCR_LSPENS_Pos 29U
1643 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1645 #define FPU_FPCCR_CLRONRET_Pos 28U
1646 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1648 #define FPU_FPCCR_CLRONRETS_Pos 27U
1649 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1651 #define FPU_FPCCR_TS_Pos 26U
1652 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1654 #define FPU_FPCCR_UFRDY_Pos 10U
1655 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1657 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
1658 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1660 #define FPU_FPCCR_MONRDY_Pos 8U
1661 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1663 #define FPU_FPCCR_SFRDY_Pos 7U
1664 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1666 #define FPU_FPCCR_BFRDY_Pos 6U
1667 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1669 #define FPU_FPCCR_MMRDY_Pos 5U
1670 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1672 #define FPU_FPCCR_HFRDY_Pos 4U
1673 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1675 #define FPU_FPCCR_THREAD_Pos 3U
1676 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1678 #define FPU_FPCCR_S_Pos 2U
1679 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1681 #define FPU_FPCCR_USER_Pos 1U
1682 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1684 #define FPU_FPCCR_LSPACT_Pos 0U
1685 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1687 /* Floating-Point Context Address Register Definitions */
1688 #define FPU_FPCAR_ADDRESS_Pos 3U
1689 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1691 /* Floating-Point Default Status Control Register Definitions */
1692 #define FPU_FPDSCR_AHP_Pos 26U
1693 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1695 #define FPU_FPDSCR_DN_Pos 25U
1696 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1698 #define FPU_FPDSCR_FZ_Pos 24U
1699 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1701 #define FPU_FPDSCR_RMode_Pos 22U
1702 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1704 /* Media and VFP Feature Register 0 Definitions */
1705 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1706 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1708 #define FPU_MVFR0_Short_vectors_Pos 24U
1709 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1711 #define FPU_MVFR0_Square_root_Pos 20U
1712 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1714 #define FPU_MVFR0_Divide_Pos 16U
1715 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1717 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1718 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1720 #define FPU_MVFR0_Double_precision_Pos 8U
1721 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1723 #define FPU_MVFR0_Single_precision_Pos 4U
1724 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1726 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1727 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1729 /* Media and VFP Feature Register 1 Definitions */
1730 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1731 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1733 #define FPU_MVFR1_FP_HPFP_Pos 24U
1734 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1736 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1737 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1739 #define FPU_MVFR1_FtZ_mode_Pos 0U
1740 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1742 /* Media and VFP Feature Register 2 Definitions */
1743 #define FPU_MVFR2_FPMisc_Pos 4U
1744 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
1748 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1749 
1759 typedef struct
1760 {
1761  __IOM uint32_t DHCSR;
1762  __OM uint32_t DCRSR;
1763  __IOM uint32_t DCRDR;
1764  __IOM uint32_t DEMCR;
1765  uint32_t RESERVED0[1U];
1766  __IOM uint32_t DAUTHCTRL;
1767  __IOM uint32_t DSCSR;
1768 } CoreDebug_Type;
1769 
1770 /* Debug Halting Control and Status Register Definitions */
1771 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1772 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1774 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1775 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1777 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1778 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1780 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1781 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1783 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1784 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1786 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1787 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1789 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1790 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1792 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1793 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1795 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1796 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1798 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1799 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1801 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1802 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1804 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1805 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1807 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1808 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1810 /* Debug Core Register Selector Register Definitions */
1811 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1812 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1814 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1815 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1817 /* Debug Exception and Monitor Control Register Definitions */
1818 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1819 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1821 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1822 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1824 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1825 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1827 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1828 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1830 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1831 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1833 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1834 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1836 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1837 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1839 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1840 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1842 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1843 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1845 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1846 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1848 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1849 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1851 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1852 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1854 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1855 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1857 /* Debug Authentication Control Register Definitions */
1858 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1859 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1861 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1862 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1864 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1865 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1867 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1868 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1870 /* Debug Security Control and Status Register Definitions */
1871 #define CoreDebug_DSCSR_CDS_Pos 16U
1872 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1874 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1875 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1877 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1878 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1893 typedef struct
1894 {
1895  __IOM uint32_t DHCSR;
1896  __OM uint32_t DCRSR;
1897  __IOM uint32_t DCRDR;
1898  __IOM uint32_t DEMCR;
1899  uint32_t RESERVED0[1U];
1900  __IOM uint32_t DAUTHCTRL;
1901  __IOM uint32_t DSCSR;
1902 } DCB_Type;
1903 
1904 /* DHCSR, Debug Halting Control and Status Register Definitions */
1905 #define DCB_DHCSR_DBGKEY_Pos 16U
1906 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1908 #define DCB_DHCSR_S_RESTART_ST_Pos 26U
1909 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1911 #define DCB_DHCSR_S_RESET_ST_Pos 25U
1912 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1914 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1915 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1917 #define DCB_DHCSR_S_SDE_Pos 20U
1918 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1920 #define DCB_DHCSR_S_LOCKUP_Pos 19U
1921 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
1923 #define DCB_DHCSR_S_SLEEP_Pos 18U
1924 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
1926 #define DCB_DHCSR_S_HALT_Pos 17U
1927 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
1929 #define DCB_DHCSR_S_REGRDY_Pos 16U
1930 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
1932 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U
1933 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
1935 #define DCB_DHCSR_C_MASKINTS_Pos 3U
1936 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
1938 #define DCB_DHCSR_C_STEP_Pos 2U
1939 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
1941 #define DCB_DHCSR_C_HALT_Pos 1U
1942 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
1944 #define DCB_DHCSR_C_DEBUGEN_Pos 0U
1945 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
1947 /* DCRSR, Debug Core Register Select Register Definitions */
1948 #define DCB_DCRSR_REGWnR_Pos 16U
1949 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
1951 #define DCB_DCRSR_REGSEL_Pos 0U
1952 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
1954 /* DCRDR, Debug Core Register Data Register Definitions */
1955 #define DCB_DCRDR_DBGTMP_Pos 0U
1956 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
1958 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1959 #define DCB_DEMCR_TRCENA_Pos 24U
1960 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
1962 #define DCB_DEMCR_MONPRKEY_Pos 23U
1963 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
1965 #define DCB_DEMCR_UMON_EN_Pos 21U
1966 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
1968 #define DCB_DEMCR_SDME_Pos 20U
1969 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
1971 #define DCB_DEMCR_MON_REQ_Pos 19U
1972 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
1974 #define DCB_DEMCR_MON_STEP_Pos 18U
1975 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
1977 #define DCB_DEMCR_MON_PEND_Pos 17U
1978 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
1980 #define DCB_DEMCR_MON_EN_Pos 16U
1981 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
1983 #define DCB_DEMCR_VC_SFERR_Pos 11U
1984 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
1986 #define DCB_DEMCR_VC_HARDERR_Pos 10U
1987 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
1989 #define DCB_DEMCR_VC_INTERR_Pos 9U
1990 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
1992 #define DCB_DEMCR_VC_BUSERR_Pos 8U
1993 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
1995 #define DCB_DEMCR_VC_STATERR_Pos 7U
1996 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
1998 #define DCB_DEMCR_VC_CHKERR_Pos 6U
1999 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
2001 #define DCB_DEMCR_VC_NOCPERR_Pos 5U
2002 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
2004 #define DCB_DEMCR_VC_MMERR_Pos 4U
2005 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
2007 #define DCB_DEMCR_VC_CORERESET_Pos 0U
2008 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
2010 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
2011 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
2012 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
2014 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
2015 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
2017 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
2018 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
2020 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
2021 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
2023 /* DSCSR, Debug Security Control and Status Register Definitions */
2024 #define DCB_DSCSR_CDSKEY_Pos 17U
2025 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2027 #define DCB_DSCSR_CDS_Pos 16U
2028 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2030 #define DCB_DSCSR_SBRSEL_Pos 1U
2031 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2033 #define DCB_DSCSR_SBRSELEN_Pos 0U
2034 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2050 typedef struct
2051 {
2052  __OM uint32_t DLAR;
2053  __IM uint32_t DLSR;
2054  __IM uint32_t DAUTHSTATUS;
2055  __IM uint32_t DDEVARCH;
2056  __IM uint32_t DDEVTYPE;
2057 } DIB_Type;
2058 
2059 /* DLAR, SCS Software Lock Access Register Definitions */
2060 #define DIB_DLAR_KEY_Pos 0U
2061 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
2063 /* DLSR, SCS Software Lock Status Register Definitions */
2064 #define DIB_DLSR_nTT_Pos 2U
2065 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
2067 #define DIB_DLSR_SLK_Pos 1U
2068 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
2070 #define DIB_DLSR_SLI_Pos 0U
2071 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
2073 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2074 #define DIB_DAUTHSTATUS_SNID_Pos 6U
2075 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
2077 #define DIB_DAUTHSTATUS_SID_Pos 4U
2078 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
2080 #define DIB_DAUTHSTATUS_NSNID_Pos 2U
2081 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
2083 #define DIB_DAUTHSTATUS_NSID_Pos 0U
2084 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
2086 /* DDEVARCH, SCS Device Architecture Register Definitions */
2087 #define DIB_DDEVARCH_ARCHITECT_Pos 21U
2088 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
2090 #define DIB_DDEVARCH_PRESENT_Pos 20U
2091 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
2093 #define DIB_DDEVARCH_REVISION_Pos 16U
2094 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
2096 #define DIB_DDEVARCH_ARCHVER_Pos 12U
2097 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
2099 #define DIB_DDEVARCH_ARCHPART_Pos 0U
2100 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
2102 /* DDEVTYPE, SCS Device Type Register Definitions */
2103 #define DIB_DDEVTYPE_SUB_Pos 4U
2104 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
2106 #define DIB_DDEVTYPE_MAJOR_Pos 0U
2107 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
2126 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2127 
2134 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2135 
2146 /* Memory mapping of Core Hardware */
2147  #define SCS_BASE (0xE000E000UL)
2148  #define ITM_BASE (0xE0000000UL)
2149  #define DWT_BASE (0xE0001000UL)
2150  #define TPI_BASE (0xE0040000UL)
2151  #define CoreDebug_BASE (0xE000EDF0UL)
2152  #define DCB_BASE (0xE000EDF0UL)
2153  #define DIB_BASE (0xE000EFB0UL)
2154  #define SysTick_BASE (SCS_BASE + 0x0010UL)
2155  #define NVIC_BASE (SCS_BASE + 0x0100UL)
2156  #define SCB_BASE (SCS_BASE + 0x0D00UL)
2158  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2159  #define SCB ((SCB_Type *) SCB_BASE )
2160  #define SysTick ((SysTick_Type *) SysTick_BASE )
2161  #define NVIC ((NVIC_Type *) NVIC_BASE )
2162  #define ITM ((ITM_Type *) ITM_BASE )
2163  #define DWT ((DWT_Type *) DWT_BASE )
2164  #define TPI ((TPI_Type *) TPI_BASE )
2165  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
2166  #define DCB ((DCB_Type *) DCB_BASE )
2167  #define DIB ((DIB_Type *) DIB_BASE )
2169  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2170  #define MPU_BASE (SCS_BASE + 0x0D90UL)
2171  #define MPU ((MPU_Type *) MPU_BASE )
2172  #endif
2173 
2174  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2175  #define SAU_BASE_CMSIS (SCS_BASE + 0x0DD0UL)
2176  #define SAU ((SAU_Type *) SAU_BASE_CMSIS )
2177  #endif
2178 
2179  #define FPU_BASE (SCS_BASE + 0x0F30UL)
2180  #define FPU ((FPU_Type *) FPU_BASE )
2182 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2183  #define SCS_BASE_NS (0xE002E000UL)
2184  #define CoreDebug_BASE_NS (0xE002EDF0UL)
2185  #define DCB_BASE_NS (0xE002EDF0UL)
2186  #define DIB_BASE_NS (0xE002EFB0UL)
2187  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2188  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2189  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2191  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2192  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2193  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2194  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2195  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2196  #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
2197  #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
2199  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2200  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2201  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2202  #endif
2203 
2204  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2205  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2207 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2208 
2217 #define ID_ADR (ID_AFR)
2218 
2221 /*******************************************************************************
2222  * Hardware Abstraction Layer
2223  Core Function Interface contains:
2224  - Core NVIC Functions
2225  - Core SysTick Functions
2226  - Core Debug Functions
2227  - Core Register Access Functions
2228  ******************************************************************************/
2229 
2235 /* ########################## NVIC functions #################################### */
2243 #ifdef CMSIS_NVIC_VIRTUAL
2244  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2245  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2246  #endif
2247  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2248 #else
2249  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2250  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2251  #define NVIC_EnableIRQ __NVIC_EnableIRQ
2252  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2253  #define NVIC_DisableIRQ __NVIC_DisableIRQ
2254  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2255  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2256  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2257  #define NVIC_GetActive __NVIC_GetActive
2258  #define NVIC_SetPriority __NVIC_SetPriority
2259  #define NVIC_GetPriority __NVIC_GetPriority
2260  #define NVIC_SystemReset __NVIC_SystemReset
2261 #endif /* CMSIS_NVIC_VIRTUAL */
2262 
2263 #ifdef CMSIS_VECTAB_VIRTUAL
2264  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2265  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2266  #endif
2267  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2268 #else
2269  #define NVIC_SetVector __NVIC_SetVector
2270  #define NVIC_GetVector __NVIC_GetVector
2271 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2272 
2273 #define NVIC_USER_IRQ_OFFSET 16
2274 
2275 
2276 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2277 
2278 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2279 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2280 
2281 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2282 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2283 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2284 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2285 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2286 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2287 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2288 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2289 
2290 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2291 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2292 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2293 #else
2294 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2295 #endif
2296 
2297 
2307 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2308 {
2309  uint32_t reg_value;
2310  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2311 
2312  reg_value = SCB->AIRCR; /* read old register configuration */
2313  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2314  reg_value = (reg_value |
2315  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2316  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2317  SCB->AIRCR = reg_value;
2318 }
2319 
2320 
2326 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2327 {
2328  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2329 }
2330 
2331 
2338 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2339 {
2340  if ((int32_t)(IRQn) >= 0)
2341  {
2342  __COMPILER_BARRIER();
2343  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2344  __COMPILER_BARRIER();
2345  }
2346 }
2347 
2348 
2357 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2358 {
2359  if ((int32_t)(IRQn) >= 0)
2360  {
2361  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2362  }
2363  else
2364  {
2365  return(0U);
2366  }
2367 }
2368 
2369 
2376 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2377 {
2378  if ((int32_t)(IRQn) >= 0)
2379  {
2380  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2381  __DSB();
2382  __ISB();
2383  }
2384 }
2385 
2386 
2395 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2396 {
2397  if ((int32_t)(IRQn) >= 0)
2398  {
2399  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2400  }
2401  else
2402  {
2403  return(0U);
2404  }
2405 }
2406 
2407 
2414 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2415 {
2416  if ((int32_t)(IRQn) >= 0)
2417  {
2418  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2419  }
2420 }
2421 
2422 
2429 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2430 {
2431  if ((int32_t)(IRQn) >= 0)
2432  {
2433  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2434  }
2435 }
2436 
2437 
2446 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2447 {
2448  if ((int32_t)(IRQn) >= 0)
2449  {
2450  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2451  }
2452  else
2453  {
2454  return(0U);
2455  }
2456 }
2457 
2458 
2459 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2460 
2468 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2469 {
2470  if ((int32_t)(IRQn) >= 0)
2471  {
2472  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2473  }
2474  else
2475  {
2476  return(0U);
2477  }
2478 }
2479 
2480 
2489 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2490 {
2491  if ((int32_t)(IRQn) >= 0)
2492  {
2493  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2494  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2495  }
2496  else
2497  {
2498  return(0U);
2499  }
2500 }
2501 
2502 
2511 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2512 {
2513  if ((int32_t)(IRQn) >= 0)
2514  {
2515  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2516  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2517  }
2518  else
2519  {
2520  return(0U);
2521  }
2522 }
2523 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2524 
2525 
2535 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2536 {
2537  if ((int32_t)(IRQn) >= 0)
2538  {
2539  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2540  }
2541  else
2542  {
2543  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2544  }
2545 }
2546 
2547 
2557 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2558 {
2559 
2560  if ((int32_t)(IRQn) >= 0)
2561  {
2562  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2563  }
2564  else
2565  {
2566  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2567  }
2568 }
2569 
2570 
2582 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2583 {
2584  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2585  uint32_t PreemptPriorityBits;
2586  uint32_t SubPriorityBits;
2587 
2588  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2589  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2590 
2591  return (
2592  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2593  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2594  );
2595 }
2596 
2597 
2609 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2610 {
2611  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2612  uint32_t PreemptPriorityBits;
2613  uint32_t SubPriorityBits;
2614 
2615  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2616  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2617 
2618  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2619  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2620 }
2621 
2622 
2632 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2633 {
2634  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2635  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2636  __DSB();
2637 }
2638 
2639 
2648 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2649 {
2650  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2651  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2652 }
2653 
2654 
2659 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2660 {
2661  __DSB(); /* Ensure all outstanding memory accesses included
2662  buffered write are completed before reset */
2663  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2664  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2665  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2666  __DSB(); /* Ensure completion of memory access */
2667 
2668  for(;;) /* wait until reset */
2669  {
2670  __NOP();
2671  }
2672 }
2673 
2674 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2675 
2684 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2685 {
2686  uint32_t reg_value;
2687  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2688 
2689  reg_value = SCB_NS->AIRCR; /* read old register configuration */
2690  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2691  reg_value = (reg_value |
2692  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2693  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2694  SCB_NS->AIRCR = reg_value;
2695 }
2696 
2697 
2703 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2704 {
2705  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2706 }
2707 
2708 
2715 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2716 {
2717  if ((int32_t)(IRQn) >= 0)
2718  {
2719  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2720  }
2721 }
2722 
2723 
2732 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2733 {
2734  if ((int32_t)(IRQn) >= 0)
2735  {
2736  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2737  }
2738  else
2739  {
2740  return(0U);
2741  }
2742 }
2743 
2744 
2751 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2752 {
2753  if ((int32_t)(IRQn) >= 0)
2754  {
2755  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2756  }
2757 }
2758 
2759 
2768 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2769 {
2770  if ((int32_t)(IRQn) >= 0)
2771  {
2772  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2773  }
2774  else
2775  {
2776  return(0U);
2777  }
2778 }
2779 
2780 
2787 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2788 {
2789  if ((int32_t)(IRQn) >= 0)
2790  {
2791  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2792  }
2793 }
2794 
2795 
2802 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2803 {
2804  if ((int32_t)(IRQn) >= 0)
2805  {
2806  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2807  }
2808 }
2809 
2810 
2819 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2820 {
2821  if ((int32_t)(IRQn) >= 0)
2822  {
2823  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2824  }
2825  else
2826  {
2827  return(0U);
2828  }
2829 }
2830 
2831 
2841 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2842 {
2843  if ((int32_t)(IRQn) >= 0)
2844  {
2845  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2846  }
2847  else
2848  {
2849  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2850  }
2851 }
2852 
2853 
2862 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2863 {
2864 
2865  if ((int32_t)(IRQn) >= 0)
2866  {
2867  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2868  }
2869  else
2870  {
2871  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2872  }
2873 }
2874 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2875 
2878 /* ########################## MPU functions #################################### */
2879 
2880 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2881 
2882 #include "mpu_armv8.h"
2883 
2884 #endif
2885 
2886 /* ########################## FPU functions #################################### */
2902 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2903 {
2904  uint32_t mvfr0;
2905 
2906  mvfr0 = FPU->MVFR0;
2907  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2908  {
2909  return 2U; /* Double + Single precision FPU */
2910  }
2911  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2912  {
2913  return 1U; /* Single precision FPU */
2914  }
2915  else
2916  {
2917  return 0U; /* No FPU */
2918  }
2919 }
2920 
2921 
2925 /* ########################## Cache functions #################################### */
2926 
2927 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2928  (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2929 #include "cachel1_armv7.h"
2930 #endif
2931 
2932 
2933 /* ########################## SAU functions #################################### */
2941 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2942 
2947 __STATIC_INLINE void TZ_SAU_Enable(void)
2948 {
2949  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2950 }
2951 
2952 
2953 
2958 __STATIC_INLINE void TZ_SAU_Disable(void)
2959 {
2960  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2961 }
2962 
2963 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2964 
2970 /* ################################## Debug Control function ############################################ */
2984 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2985 {
2986  __DSB();
2987  __ISB();
2988  DCB->DAUTHCTRL = value;
2989  __DSB();
2990  __ISB();
2991 }
2992 
2993 
2999 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3000 {
3001  return (DCB->DAUTHCTRL);
3002 }
3003 
3004 
3005 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3006 
3011 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3012 {
3013  __DSB();
3014  __ISB();
3015  DCB_NS->DAUTHCTRL = value;
3016  __DSB();
3017  __ISB();
3018 }
3019 
3020 
3026 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3027 {
3028  return (DCB_NS->DAUTHCTRL);
3029 }
3030 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3031 
3037 /* ################################## Debug Identification function ############################################ */
3051 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3052 {
3053  return (DIB->DAUTHSTATUS);
3054 }
3055 
3056 
3057 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3058 
3063 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3064 {
3065  return (DIB_NS->DAUTHSTATUS);
3066 }
3067 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3068 
3074 /* ################################## SysTick function ############################################ */
3082 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3083 
3095 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3096 {
3097  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3098  {
3099  return (1UL); /* Reload value impossible */
3100  }
3101 
3102  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3103  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3104  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3105  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3106  SysTick_CTRL_TICKINT_Msk |
3107  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3108  return (0UL); /* Function successful */
3109 }
3110 
3111 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3112 
3124 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3125 {
3126  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3127  {
3128  return (1UL); /* Reload value impossible */
3129  }
3130 
3131  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3132  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3133  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3134  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3135  SysTick_CTRL_TICKINT_Msk |
3136  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3137  return (0UL); /* Function successful */
3138 }
3139 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3140 
3141 #endif
3142 
3147 /* ##################################### Debug In/Output function ########################################### */
3155 extern volatile int32_t ITM_RxBuffer;
3156 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
3167 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3168 {
3169  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3170  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3171  {
3172  while (ITM->PORT[0U].u32 == 0UL)
3173  {
3174  __NOP();
3175  }
3176  ITM->PORT[0U].u8 = (uint8_t)ch;
3177  }
3178  return (ch);
3179 }
3180 
3181 
3188 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3189 {
3190  int32_t ch = -1; /* no character available */
3191 
3192  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3193  {
3194  ch = ITM_RxBuffer;
3195  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3196  }
3197 
3198  return (ch);
3199 }
3200 
3201 
3208 __STATIC_INLINE int32_t ITM_CheckChar (void)
3209 {
3210 
3211  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3212  {
3213  return (0); /* no character available */
3214  }
3215  else
3216  {
3217  return (1); /* character available */
3218  }
3219 }
3220 
3226 #ifdef __cplusplus
3227 }
3228 #endif
3229 
3230 #endif /* __CORE_ARMV8MML_H_DEPENDANT */
3231 
3232 #endif /* __CMSIS_GENERIC */
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv81mml.h:2505
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_armv8mml.h:1724
ITM
#define ITM
Definition: core_armv8mml.h:2162
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1202
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_armv81mml.h:3008
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_armv8mml.h:654
mpu_armv8.h
DCB
#define DCB
Definition: core_armv8mml.h:2166
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:3332
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:234
FPU
#define FPU
Definition: core_armv8mml.h:2180
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_armv8mml.h:639
SysTick
#define SysTick
Definition: core_armv8mml.h:2160
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_armv8mml.h:3156
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:3623
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:3313
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:3370
IRQn_Type
enum IRQn IRQn_Type
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv81mml.h:4207
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_armv81mml.h:4003
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_armv8mml.h:1721
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:3389
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:390
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1388
SysTick_IRQn
Definition: cc27xx.h:24
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv81mml.h:4227
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:3885
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:3584
NVIC
#define NVIC
Definition: core_armv8mml.h:2161
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:275
cmsis_version.h
CMSIS Core(M) Version definitions.
CoreDebug_Type
Definition: core_armv81mml.h:2646
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:534
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_armv8mml.h:1115
SCB
#define SCB
Definition: core_armv8mml.h:2159
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv81mml.h:1101
__IOM
#define __IOM
Definition: core_armv8mml.h:311
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:3607
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv81mml.h:3301
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:3351
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_armv8mml.h:653
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv81mml.h:1024
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:498
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1049
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mml.h:638
IRQn
IRQn
Definition: cc27xx.h:13
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:3421
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: cmsis_gcc.h:117
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_armv81mml.h:4070
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv8mml.h:2258
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:3510
DIB
#define DIB
Definition: core_armv8mml.h:2167
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mml.h:660
cmsis_compiler.h
CMSIS compiler generic header file.
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:351
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mml.h:1011
__OM
#define __OM
Definition: core_armv8mml.h:310
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:3404
__IM
#define __IM
Definition: core_armv8mml.h:309
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_armv81mml.h:2817
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:459
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mml.h:1001
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mml.h:1007
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mml.h:2273
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_gcc.h:47
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:3557
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:3634
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:408
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_armv81mml.h:4018
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:264
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:3532
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mml.h:1004
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv81mml.h:3282
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_gcc.h:53
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: cc27xx.h:106