CC27xxDriverLibrary
core_armv8mbl.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30  #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32 
33 #ifndef __CORE_ARMV8MBL_H_GENERIC
34 #define __CORE_ARMV8MBL_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
57 /*******************************************************************************
58  * CMSIS definitions
59  ******************************************************************************/
65 #include "cmsis_version.h"
66 
67 /* CMSIS definitions */
68 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
71  __ARMv8MBL_CMSIS_VERSION_SUB )
73 #define __CORTEX_M (2U)
78 #define __FPU_USED 0U
79 
80 #if defined ( __CC_ARM )
81  #if defined __TARGET_FPU_VFP
82  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83  #endif
84 
85 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
86  #if defined __ARM_FP
87  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88  #endif
89 
90 #elif defined (__ti__)
91  #if defined (__ARM_FP)
92  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93  #endif
94 
95 #elif defined ( __GNUC__ )
96  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
97  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98  #endif
99 
100 #elif defined ( __ICCARM__ )
101  #if defined __ARMVFP__
102  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103  #endif
104 
105 #elif defined ( __TI_ARM__ )
106  #if defined __TI_VFP_SUPPORT__
107  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108  #endif
109 
110 #elif defined ( __TASKING__ )
111  #if defined __FPU_VFP__
112  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113  #endif
114 
115 #elif defined ( __CSMC__ )
116  #if ( __CSMC__ & 0x400U)
117  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118  #endif
119 
120 #endif
121 
122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
123 
124 
125 #ifdef __cplusplus
126 }
127 #endif
128 
129 #endif /* __CORE_ARMV8MBL_H_GENERIC */
130 
131 #ifndef __CMSIS_GENERIC
132 
133 #ifndef __CORE_ARMV8MBL_H_DEPENDANT
134 #define __CORE_ARMV8MBL_H_DEPENDANT
135 
136 #ifdef __cplusplus
137  extern "C" {
138 #endif
139 
140 /* check device defines and use defaults */
141 #if defined __CHECK_DEVICE_DEFINES
142  #ifndef __ARMv8MBL_REV
143  #define __ARMv8MBL_REV 0x0000U
144  #warning "__ARMv8MBL_REV not defined in device header file; using default!"
145  #endif
146 
147  #ifndef __FPU_PRESENT
148  #define __FPU_PRESENT 0U
149  #warning "__FPU_PRESENT not defined in device header file; using default!"
150  #endif
151 
152  #ifndef __MPU_PRESENT
153  #define __MPU_PRESENT 0U
154  #warning "__MPU_PRESENT not defined in device header file; using default!"
155  #endif
156 
157  #ifndef __SAUREGION_PRESENT
158  #define __SAUREGION_PRESENT 0U
159  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
160  #endif
161 
162  #ifndef __VTOR_PRESENT
163  #define __VTOR_PRESENT 0U
164  #warning "__VTOR_PRESENT not defined in device header file; using default!"
165  #endif
166 
167  #ifndef __NVIC_PRIO_BITS
168  #define __NVIC_PRIO_BITS 2U
169  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
170  #endif
171 
172  #ifndef __Vendor_SysTickConfig
173  #define __Vendor_SysTickConfig 0U
174  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
175  #endif
176 
177  #ifndef __ETM_PRESENT
178  #define __ETM_PRESENT 0U
179  #warning "__ETM_PRESENT not defined in device header file; using default!"
180  #endif
181 
182  #ifndef __MTB_PRESENT
183  #define __MTB_PRESENT 0U
184  #warning "__MTB_PRESENT not defined in device header file; using default!"
185  #endif
186 
187 #endif
188 
189 /* IO definitions (access restrictions to peripheral registers) */
197 #ifdef __cplusplus
198  #define __I volatile
199 #else
200  #define __I volatile const
201 #endif
202 #define __O volatile
203 #define __IO volatile
205 /* following defines should be used for structure members */
206 #define __IM volatile const
207 #define __OM volatile
208 #define __IOM volatile
210 
214 /*******************************************************************************
215  * Register Abstraction
216  Core Register contain:
217  - Core Register
218  - Core NVIC Register
219  - Core SCB Register
220  - Core SysTick Register
221  - Core Debug Register
222  - Core MPU Register
223  - Core SAU Register
224  ******************************************************************************/
225 
240 typedef union
241 {
242  struct
243  {
244  uint32_t _reserved0:28;
245  uint32_t V:1;
246  uint32_t C:1;
247  uint32_t Z:1;
248  uint32_t N:1;
249  } b;
250  uint32_t w;
251 } APSR_Type;
252 
253 /* APSR Register Definitions */
254 #define APSR_N_Pos 31U
255 #define APSR_N_Msk (1UL << APSR_N_Pos)
257 #define APSR_Z_Pos 30U
258 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
260 #define APSR_C_Pos 29U
261 #define APSR_C_Msk (1UL << APSR_C_Pos)
263 #define APSR_V_Pos 28U
264 #define APSR_V_Msk (1UL << APSR_V_Pos)
270 typedef union
271 {
272  struct
273  {
274  uint32_t ISR:9;
275  uint32_t _reserved0:23;
276  } b;
277  uint32_t w;
278 } IPSR_Type;
279 
280 /* IPSR Register Definitions */
281 #define IPSR_ISR_Pos 0U
282 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
288 typedef union
289 {
290  struct
291  {
292  uint32_t ISR:9;
293  uint32_t _reserved0:15;
294  uint32_t T:1;
295  uint32_t _reserved1:3;
296  uint32_t V:1;
297  uint32_t C:1;
298  uint32_t Z:1;
299  uint32_t N:1;
300  } b;
301  uint32_t w;
302 } xPSR_Type;
303 
304 /* xPSR Register Definitions */
305 #define xPSR_N_Pos 31U
306 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
308 #define xPSR_Z_Pos 30U
309 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
311 #define xPSR_C_Pos 29U
312 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
314 #define xPSR_V_Pos 28U
315 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
317 #define xPSR_T_Pos 24U
318 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
320 #define xPSR_ISR_Pos 0U
321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
327 typedef union
328 {
329  struct
330  {
331  uint32_t nPRIV:1;
332  uint32_t SPSEL:1;
333  uint32_t _reserved1:30;
334  } b;
335  uint32_t w;
336 } CONTROL_Type;
337 
338 /* CONTROL Register Definitions */
339 #define CONTROL_SPSEL_Pos 1U
340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
342 #define CONTROL_nPRIV_Pos 0U
343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
345 
358 typedef struct
359 {
360  __IOM uint32_t ISER[16U];
361  uint32_t RESERVED0[16U];
362  __IOM uint32_t ICER[16U];
363  uint32_t RSERVED1[16U];
364  __IOM uint32_t ISPR[16U];
365  uint32_t RESERVED2[16U];
366  __IOM uint32_t ICPR[16U];
367  uint32_t RESERVED3[16U];
368  __IOM uint32_t IABR[16U];
369  uint32_t RESERVED4[16U];
370  __IOM uint32_t ITNS[16U];
371  uint32_t RESERVED5[16U];
372  __IOM uint32_t IPR[124U];
373 } NVIC_Type;
374 
388 typedef struct
389 {
390  __IM uint32_t CPUID;
391  __IOM uint32_t ICSR;
392 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
393  __IOM uint32_t VTOR;
394 #else
395  uint32_t RESERVED0;
396 #endif
397  __IOM uint32_t AIRCR;
398  __IOM uint32_t SCR;
399  __IOM uint32_t CCR;
400  uint32_t RESERVED1;
401  __IOM uint32_t SHPR[2U];
402  __IOM uint32_t SHCSR;
403 } SCB_Type;
404 
405 /* SCB CPUID Register Definitions */
406 #define SCB_CPUID_IMPLEMENTER_Pos 24U
407 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
409 #define SCB_CPUID_VARIANT_Pos 20U
410 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
412 #define SCB_CPUID_ARCHITECTURE_Pos 16U
413 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
415 #define SCB_CPUID_PARTNO_Pos 4U
416 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
418 #define SCB_CPUID_REVISION_Pos 0U
419 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
421 /* SCB Interrupt Control State Register Definitions */
422 #define SCB_ICSR_PENDNMISET_Pos 31U
423 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
425 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
426 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
428 #define SCB_ICSR_PENDNMICLR_Pos 30U
429 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
431 #define SCB_ICSR_PENDSVSET_Pos 28U
432 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
434 #define SCB_ICSR_PENDSVCLR_Pos 27U
435 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
437 #define SCB_ICSR_PENDSTSET_Pos 26U
438 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
440 #define SCB_ICSR_PENDSTCLR_Pos 25U
441 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
443 #define SCB_ICSR_STTNS_Pos 24U
444 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
446 #define SCB_ICSR_ISRPREEMPT_Pos 23U
447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
449 #define SCB_ICSR_ISRPENDING_Pos 22U
450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
452 #define SCB_ICSR_VECTPENDING_Pos 12U
453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
455 #define SCB_ICSR_RETTOBASE_Pos 11U
456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
458 #define SCB_ICSR_VECTACTIVE_Pos 0U
459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
461 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
462 /* SCB Vector Table Offset Register Definitions */
463 #define SCB_VTOR_TBLOFF_Pos 7U
464 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
465 #endif
466 
467 /* SCB Application Interrupt and Reset Control Register Definitions */
468 #define SCB_AIRCR_VECTKEY_Pos 16U
469 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
471 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
472 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
474 #define SCB_AIRCR_ENDIANESS_Pos 15U
475 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
477 #define SCB_AIRCR_PRIS_Pos 14U
478 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
480 #define SCB_AIRCR_BFHFNMINS_Pos 13U
481 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
483 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
484 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
486 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
487 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
489 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
490 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
492 /* SCB System Control Register Definitions */
493 #define SCB_SCR_SEVONPEND_Pos 4U
494 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
496 #define SCB_SCR_SLEEPDEEPS_Pos 3U
497 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
499 #define SCB_SCR_SLEEPDEEP_Pos 2U
500 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
502 #define SCB_SCR_SLEEPONEXIT_Pos 1U
503 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
505 /* SCB Configuration Control Register Definitions */
506 #define SCB_CCR_BP_Pos 18U
507 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
509 #define SCB_CCR_IC_Pos 17U
510 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
512 #define SCB_CCR_DC_Pos 16U
513 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
515 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
516 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
518 #define SCB_CCR_BFHFNMIGN_Pos 8U
519 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
521 #define SCB_CCR_DIV_0_TRP_Pos 4U
522 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
524 #define SCB_CCR_UNALIGN_TRP_Pos 3U
525 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
527 #define SCB_CCR_USERSETMPEND_Pos 1U
528 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
530 /* SCB System Handler Control and State Register Definitions */
531 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
532 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
534 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
535 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
537 #define SCB_SHCSR_SYSTICKACT_Pos 11U
538 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
540 #define SCB_SHCSR_PENDSVACT_Pos 10U
541 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
543 #define SCB_SHCSR_SVCALLACT_Pos 7U
544 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
546 #define SCB_SHCSR_NMIACT_Pos 5U
547 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
549 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
550 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
552 
565 typedef struct
566 {
567  __IOM uint32_t CTRL;
568  __IOM uint32_t LOAD;
569  __IOM uint32_t VAL;
570  __IM uint32_t CALIB;
571 } SysTick_Type;
572 
573 /* SysTick Control / Status Register Definitions */
574 #define SysTick_CTRL_COUNTFLAG_Pos 16U
575 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
577 #define SysTick_CTRL_CLKSOURCE_Pos 2U
578 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
580 #define SysTick_CTRL_TICKINT_Pos 1U
581 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
583 #define SysTick_CTRL_ENABLE_Pos 0U
584 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
586 /* SysTick Reload Register Definitions */
587 #define SysTick_LOAD_RELOAD_Pos 0U
588 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
590 /* SysTick Current Register Definitions */
591 #define SysTick_VAL_CURRENT_Pos 0U
592 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
594 /* SysTick Calibration Register Definitions */
595 #define SysTick_CALIB_NOREF_Pos 31U
596 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
598 #define SysTick_CALIB_SKEW_Pos 30U
599 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
601 #define SysTick_CALIB_TENMS_Pos 0U
602 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
604 
617 typedef struct
618 {
619  __IOM uint32_t CTRL;
620  uint32_t RESERVED0[6U];
621  __IM uint32_t PCSR;
622  __IOM uint32_t COMP0;
623  uint32_t RESERVED1[1U];
624  __IOM uint32_t FUNCTION0;
625  uint32_t RESERVED2[1U];
626  __IOM uint32_t COMP1;
627  uint32_t RESERVED3[1U];
628  __IOM uint32_t FUNCTION1;
629  uint32_t RESERVED4[1U];
630  __IOM uint32_t COMP2;
631  uint32_t RESERVED5[1U];
632  __IOM uint32_t FUNCTION2;
633  uint32_t RESERVED6[1U];
634  __IOM uint32_t COMP3;
635  uint32_t RESERVED7[1U];
636  __IOM uint32_t FUNCTION3;
637  uint32_t RESERVED8[1U];
638  __IOM uint32_t COMP4;
639  uint32_t RESERVED9[1U];
640  __IOM uint32_t FUNCTION4;
641  uint32_t RESERVED10[1U];
642  __IOM uint32_t COMP5;
643  uint32_t RESERVED11[1U];
644  __IOM uint32_t FUNCTION5;
645  uint32_t RESERVED12[1U];
646  __IOM uint32_t COMP6;
647  uint32_t RESERVED13[1U];
648  __IOM uint32_t FUNCTION6;
649  uint32_t RESERVED14[1U];
650  __IOM uint32_t COMP7;
651  uint32_t RESERVED15[1U];
652  __IOM uint32_t FUNCTION7;
653  uint32_t RESERVED16[1U];
654  __IOM uint32_t COMP8;
655  uint32_t RESERVED17[1U];
656  __IOM uint32_t FUNCTION8;
657  uint32_t RESERVED18[1U];
658  __IOM uint32_t COMP9;
659  uint32_t RESERVED19[1U];
660  __IOM uint32_t FUNCTION9;
661  uint32_t RESERVED20[1U];
662  __IOM uint32_t COMP10;
663  uint32_t RESERVED21[1U];
664  __IOM uint32_t FUNCTION10;
665  uint32_t RESERVED22[1U];
666  __IOM uint32_t COMP11;
667  uint32_t RESERVED23[1U];
668  __IOM uint32_t FUNCTION11;
669  uint32_t RESERVED24[1U];
670  __IOM uint32_t COMP12;
671  uint32_t RESERVED25[1U];
672  __IOM uint32_t FUNCTION12;
673  uint32_t RESERVED26[1U];
674  __IOM uint32_t COMP13;
675  uint32_t RESERVED27[1U];
676  __IOM uint32_t FUNCTION13;
677  uint32_t RESERVED28[1U];
678  __IOM uint32_t COMP14;
679  uint32_t RESERVED29[1U];
680  __IOM uint32_t FUNCTION14;
681  uint32_t RESERVED30[1U];
682  __IOM uint32_t COMP15;
683  uint32_t RESERVED31[1U];
684  __IOM uint32_t FUNCTION15;
685 } DWT_Type;
686 
687 /* DWT Control Register Definitions */
688 #define DWT_CTRL_NUMCOMP_Pos 28U
689 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
691 #define DWT_CTRL_NOTRCPKT_Pos 27U
692 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
694 #define DWT_CTRL_NOEXTTRIG_Pos 26U
695 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
697 #define DWT_CTRL_NOCYCCNT_Pos 25U
698 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
700 #define DWT_CTRL_NOPRFCNT_Pos 24U
701 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
703 /* DWT Comparator Function Register Definitions */
704 #define DWT_FUNCTION_ID_Pos 27U
705 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
707 #define DWT_FUNCTION_MATCHED_Pos 24U
708 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
710 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
711 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
713 #define DWT_FUNCTION_ACTION_Pos 4U
714 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)
716 #define DWT_FUNCTION_MATCH_Pos 0U
717 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
719  /* end of group CMSIS_DWT */
720 
721 
732 typedef struct
733 {
734  __IM uint32_t SSPSR;
735  __IOM uint32_t CSPSR;
736  uint32_t RESERVED0[2U];
737  __IOM uint32_t ACPR;
738  uint32_t RESERVED1[55U];
739  __IOM uint32_t SPPR;
740  uint32_t RESERVED2[131U];
741  __IM uint32_t FFSR;
742  __IOM uint32_t FFCR;
743  __IOM uint32_t PSCR;
744  uint32_t RESERVED3[809U];
745  __OM uint32_t LAR;
746  __IM uint32_t LSR;
747  uint32_t RESERVED4[4U];
748  __IM uint32_t TYPE;
749  __IM uint32_t DEVTYPE;
750 } TPI_Type;
751 
752 /* TPI Asynchronous Clock Prescaler Register Definitions */
753 #define TPI_ACPR_SWOSCALER_Pos 0U
754 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
756 /* TPI Selected Pin Protocol Register Definitions */
757 #define TPI_SPPR_TXMODE_Pos 0U
758 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
760 /* TPI Formatter and Flush Status Register Definitions */
761 #define TPI_FFSR_FtNonStop_Pos 3U
762 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
764 #define TPI_FFSR_TCPresent_Pos 2U
765 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
767 #define TPI_FFSR_FtStopped_Pos 1U
768 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
770 #define TPI_FFSR_FlInProg_Pos 0U
771 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
773 /* TPI Formatter and Flush Control Register Definitions */
774 #define TPI_FFCR_TrigIn_Pos 8U
775 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
777 #define TPI_FFCR_FOnMan_Pos 6U
778 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
780 #define TPI_FFCR_EnFCont_Pos 1U
781 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
783 /* TPI Periodic Synchronization Control Register Definitions */
784 #define TPI_PSCR_PSCount_Pos 0U
785 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
787 /* TPI Software Lock Status Register Definitions */
788 #define TPI_LSR_nTT_Pos 1U
789 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
791 #define TPI_LSR_SLK_Pos 1U
792 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
794 #define TPI_LSR_SLI_Pos 0U
795 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
797 /* TPI DEVID Register Definitions */
798 #define TPI_DEVID_NRZVALID_Pos 11U
799 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
801 #define TPI_DEVID_MANCVALID_Pos 10U
802 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
804 #define TPI_DEVID_PTINVALID_Pos 9U
805 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
807 #define TPI_DEVID_FIFOSZ_Pos 6U
808 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
810 /* TPI DEVTYPE Register Definitions */
811 #define TPI_DEVTYPE_SubType_Pos 4U
812 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
814 #define TPI_DEVTYPE_MajorType_Pos 0U
815 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
817  /* end of group CMSIS_TPI */
818 
819 
820 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
821 
831 typedef struct
832 {
833  __IM uint32_t TYPE;
834  __IOM uint32_t CTRL;
835  __IOM uint32_t RNR;
836  __IOM uint32_t RBAR;
837  __IOM uint32_t RLAR;
838  uint32_t RESERVED0[7U];
839  union {
840  __IOM uint32_t MAIR[2];
841  struct {
842  __IOM uint32_t MAIR0;
843  __IOM uint32_t MAIR1;
844  };
845  };
846 } MPU_Type;
847 
848 #define MPU_TYPE_RALIASES 1U
849 
850 /* MPU Type Register Definitions */
851 #define MPU_TYPE_IREGION_Pos 16U
852 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
854 #define MPU_TYPE_DREGION_Pos 8U
855 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
857 #define MPU_TYPE_SEPARATE_Pos 0U
858 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
860 /* MPU Control Register Definitions */
861 #define MPU_CTRL_PRIVDEFENA_Pos 2U
862 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
864 #define MPU_CTRL_HFNMIENA_Pos 1U
865 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
867 #define MPU_CTRL_ENABLE_Pos 0U
868 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
870 /* MPU Region Number Register Definitions */
871 #define MPU_RNR_REGION_Pos 0U
872 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
874 /* MPU Region Base Address Register Definitions */
875 #define MPU_RBAR_BASE_Pos 5U
876 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
878 #define MPU_RBAR_SH_Pos 3U
879 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
881 #define MPU_RBAR_AP_Pos 1U
882 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
884 #define MPU_RBAR_XN_Pos 0U
885 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
887 /* MPU Region Limit Address Register Definitions */
888 #define MPU_RLAR_LIMIT_Pos 5U
889 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
891 #define MPU_RLAR_AttrIndx_Pos 1U
892 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
894 #define MPU_RLAR_EN_Pos 0U
895 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
897 /* MPU Memory Attribute Indirection Register 0 Definitions */
898 #define MPU_MAIR0_Attr3_Pos 24U
899 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
901 #define MPU_MAIR0_Attr2_Pos 16U
902 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
904 #define MPU_MAIR0_Attr1_Pos 8U
905 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
907 #define MPU_MAIR0_Attr0_Pos 0U
908 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
910 /* MPU Memory Attribute Indirection Register 1 Definitions */
911 #define MPU_MAIR1_Attr7_Pos 24U
912 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
914 #define MPU_MAIR1_Attr6_Pos 16U
915 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
917 #define MPU_MAIR1_Attr5_Pos 8U
918 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
920 #define MPU_MAIR1_Attr4_Pos 0U
921 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
923 
924 #endif
925 
926 
927 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
928 
938 typedef struct
939 {
940  __IOM uint32_t CTRL;
941  __IM uint32_t TYPE;
942 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
943  __IOM uint32_t RNR;
944  __IOM uint32_t RBAR;
945  __IOM uint32_t RLAR;
946 #endif
947 } SAU_Type;
948 
949 /* SAU Control Register Definitions */
950 #define SAU_CTRL_ALLNS_Pos 1U
951 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
953 #define SAU_CTRL_ENABLE_Pos 0U
954 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
956 /* SAU Type Register Definitions */
957 #define SAU_TYPE_SREGION_Pos 0U
958 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
960 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
961 /* SAU Region Number Register Definitions */
962 #define SAU_RNR_REGION_Pos 0U
963 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
965 /* SAU Region Base Address Register Definitions */
966 #define SAU_RBAR_BADDR_Pos 5U
967 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
969 /* SAU Region Limit Address Register Definitions */
970 #define SAU_RLAR_LADDR_Pos 5U
971 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
973 #define SAU_RLAR_NSC_Pos 1U
974 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
976 #define SAU_RLAR_ENABLE_Pos 0U
977 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
979 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
980 
982 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
983 
984 
985 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
996 typedef struct
997 {
998  __IOM uint32_t DHCSR;
999  __OM uint32_t DCRSR;
1000  __IOM uint32_t DCRDR;
1001  __IOM uint32_t DEMCR;
1002  uint32_t RESERVED0[1U];
1003  __IOM uint32_t DAUTHCTRL;
1004  __IOM uint32_t DSCSR;
1005 } CoreDebug_Type;
1006 
1007 /* Debug Halting Control and Status Register Definitions */
1008 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1009 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1011 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1012 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1014 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1015 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1017 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1018 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1020 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1021 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1023 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1024 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1026 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1027 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1029 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1030 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1032 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1033 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1035 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1036 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1038 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1039 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1041 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1042 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1044 /* Debug Core Register Selector Register Definitions */
1045 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1046 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1048 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1049 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1051 /* Debug Exception and Monitor Control Register Definitions */
1052 #define CoreDebug_DEMCR_DWTENA_Pos 24U
1053 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos)
1055 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1056 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1058 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1059 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1061 /* Debug Authentication Control Register Definitions */
1062 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1063 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1065 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1066 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1068 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1069 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1071 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1072 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
1074 /* Debug Security Control and Status Register Definitions */
1075 #define CoreDebug_DSCSR_CDS_Pos 16U
1076 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
1078 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
1079 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
1081 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
1082 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
1084 
1097 typedef struct
1098 {
1099  __IOM uint32_t DHCSR;
1100  __OM uint32_t DCRSR;
1101  __IOM uint32_t DCRDR;
1102  __IOM uint32_t DEMCR;
1103  uint32_t RESERVED0[1U];
1104  __IOM uint32_t DAUTHCTRL;
1105  __IOM uint32_t DSCSR;
1106 } DCB_Type;
1107 
1108 /* DHCSR, Debug Halting Control and Status Register Definitions */
1109 #define DCB_DHCSR_DBGKEY_Pos 16U
1110 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
1112 #define DCB_DHCSR_S_RESTART_ST_Pos 26U
1113 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
1115 #define DCB_DHCSR_S_RESET_ST_Pos 25U
1116 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
1118 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U
1119 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
1121 #define DCB_DHCSR_S_SDE_Pos 20U
1122 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
1124 #define DCB_DHCSR_S_LOCKUP_Pos 19U
1125 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
1127 #define DCB_DHCSR_S_SLEEP_Pos 18U
1128 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
1130 #define DCB_DHCSR_S_HALT_Pos 17U
1131 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
1133 #define DCB_DHCSR_S_REGRDY_Pos 16U
1134 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
1136 #define DCB_DHCSR_C_MASKINTS_Pos 3U
1137 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
1139 #define DCB_DHCSR_C_STEP_Pos 2U
1140 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
1142 #define DCB_DHCSR_C_HALT_Pos 1U
1143 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
1145 #define DCB_DHCSR_C_DEBUGEN_Pos 0U
1146 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
1148 /* DCRSR, Debug Core Register Select Register Definitions */
1149 #define DCB_DCRSR_REGWnR_Pos 16U
1150 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
1152 #define DCB_DCRSR_REGSEL_Pos 0U
1153 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
1155 /* DCRDR, Debug Core Register Data Register Definitions */
1156 #define DCB_DCRDR_DBGTMP_Pos 0U
1157 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
1159 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1160 #define DCB_DEMCR_TRCENA_Pos 24U
1161 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
1163 #define DCB_DEMCR_VC_HARDERR_Pos 10U
1164 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
1166 #define DCB_DEMCR_VC_CORERESET_Pos 0U
1167 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
1169 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
1170 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
1171 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
1173 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
1174 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
1176 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
1177 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
1179 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
1180 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
1182 /* DSCSR, Debug Security Control and Status Register Definitions */
1183 #define DCB_DSCSR_CDSKEY_Pos 17U
1184 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
1186 #define DCB_DSCSR_CDS_Pos 16U
1187 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
1189 #define DCB_DSCSR_SBRSEL_Pos 1U
1190 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
1192 #define DCB_DSCSR_SBRSELEN_Pos 0U
1193 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
1195 
1209 typedef struct
1210 {
1211  __OM uint32_t DLAR;
1212  __IM uint32_t DLSR;
1213  __IM uint32_t DAUTHSTATUS;
1214  __IM uint32_t DDEVARCH;
1215  __IM uint32_t DDEVTYPE;
1216 } DIB_Type;
1217 
1218 /* DLAR, SCS Software Lock Access Register Definitions */
1219 #define DIB_DLAR_KEY_Pos 0U
1220 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
1222 /* DLSR, SCS Software Lock Status Register Definitions */
1223 #define DIB_DLSR_nTT_Pos 2U
1224 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
1226 #define DIB_DLSR_SLK_Pos 1U
1227 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
1229 #define DIB_DLSR_SLI_Pos 0U
1230 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
1232 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
1233 #define DIB_DAUTHSTATUS_SNID_Pos 6U
1234 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
1236 #define DIB_DAUTHSTATUS_SID_Pos 4U
1237 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
1239 #define DIB_DAUTHSTATUS_NSNID_Pos 2U
1240 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
1242 #define DIB_DAUTHSTATUS_NSID_Pos 0U
1243 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
1245 /* DDEVARCH, SCS Device Architecture Register Definitions */
1246 #define DIB_DDEVARCH_ARCHITECT_Pos 21U
1247 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
1249 #define DIB_DDEVARCH_PRESENT_Pos 20U
1250 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
1252 #define DIB_DDEVARCH_REVISION_Pos 16U
1253 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
1255 #define DIB_DDEVARCH_ARCHVER_Pos 12U
1256 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
1258 #define DIB_DDEVARCH_ARCHPART_Pos 0U
1259 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
1261 /* DDEVTYPE, SCS Device Type Register Definitions */
1262 #define DIB_DDEVTYPE_SUB_Pos 4U
1263 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
1265 #define DIB_DDEVTYPE_MAJOR_Pos 0U
1266 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
1269 
1285 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1286 
1293 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1294 
1305 /* Memory mapping of Core Hardware */
1306  #define SCS_BASE (0xE000E000UL)
1307  #define DWT_BASE (0xE0001000UL)
1308  #define TPI_BASE (0xE0040000UL)
1309  #define CoreDebug_BASE (0xE000EDF0UL)
1310  #define DCB_BASE (0xE000EDF0UL)
1311  #define DIB_BASE (0xE000EFB0UL)
1312  #define SysTick_BASE (SCS_BASE + 0x0010UL)
1313  #define NVIC_BASE (SCS_BASE + 0x0100UL)
1314  #define SCB_BASE (SCS_BASE + 0x0D00UL)
1317  #define SCB ((SCB_Type *) SCB_BASE )
1318  #define SysTick ((SysTick_Type *) SysTick_BASE )
1319  #define NVIC ((NVIC_Type *) NVIC_BASE )
1320  #define DWT ((DWT_Type *) DWT_BASE )
1321  #define TPI ((TPI_Type *) TPI_BASE )
1322  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
1323  #define DCB ((DCB_Type *) DCB_BASE )
1324  #define DIB ((DIB_Type *) DIB_BASE )
1326  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1327  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1328  #define MPU ((MPU_Type *) MPU_BASE )
1329  #endif
1330 
1331  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1332  #define SAU_BASE_CMSIS (SCS_BASE + 0x0DD0UL)
1333  #define SAU ((SAU_Type *) SAU_BASE_CMSIS )
1334  #endif
1335 
1336 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1337  #define SCS_BASE_NS (0xE002E000UL)
1338  #define CoreDebug_BASE_NS (0xE002EDF0UL)
1339  #define DCB_BASE_NS (0xE002EDF0UL)
1340  #define DIB_BASE_NS (0xE002EFB0UL)
1341  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
1342  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
1343  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
1345  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
1346  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
1347  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
1348  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
1349  #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
1350  #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
1352  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1353  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
1354  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
1355  #endif
1356 
1357 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1358 
1362 /*******************************************************************************
1363  * Hardware Abstraction Layer
1364  Core Function Interface contains:
1365  - Core NVIC Functions
1366  - Core SysTick Functions
1367  - Core Debug Functions
1368  - Core Register Access Functions
1369  ******************************************************************************/
1376 /* ########################## NVIC functions #################################### */
1384 #ifdef CMSIS_NVIC_VIRTUAL
1385  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1386  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1387  #endif
1388  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1389 #else
1390  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1391  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1392  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1393  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1394  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1395  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1396  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1397  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1398  #define NVIC_GetActive __NVIC_GetActive
1399  #define NVIC_SetPriority __NVIC_SetPriority
1400  #define NVIC_GetPriority __NVIC_GetPriority
1401  #define NVIC_SystemReset __NVIC_SystemReset
1402 #endif /* CMSIS_NVIC_VIRTUAL */
1403 
1404 #ifdef CMSIS_VECTAB_VIRTUAL
1405  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1406  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1407  #endif
1408  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1409 #else
1410  #define NVIC_SetVector __NVIC_SetVector
1411  #define NVIC_GetVector __NVIC_GetVector
1412 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1413 
1414 #define NVIC_USER_IRQ_OFFSET 16
1415 
1416 
1417 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1418 
1419 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1420 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1421 
1422 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1423 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1424 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1425 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1426 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1427 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1428 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1429 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1430 
1431 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1432 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1433 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1434 #else
1435 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1436 #endif
1437 
1438 
1439 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1440 /* The following MACROS handle generation of the register offset and byte masks */
1441 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1442 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1443 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1444 
1445 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1446 #define __NVIC_GetPriorityGrouping() (0U)
1447 
1454 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1455 {
1456  if ((int32_t)(IRQn) >= 0)
1457  {
1458  __COMPILER_BARRIER();
1459  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1460  __COMPILER_BARRIER();
1461  }
1462 }
1463 
1464 
1473 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1474 {
1475  if ((int32_t)(IRQn) >= 0)
1476  {
1477  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1478  }
1479  else
1480  {
1481  return(0U);
1482  }
1483 }
1484 
1485 
1492 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1493 {
1494  if ((int32_t)(IRQn) >= 0)
1495  {
1496  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1497  __DSB();
1498  __ISB();
1499  }
1500 }
1501 
1502 
1511 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1512 {
1513  if ((int32_t)(IRQn) >= 0)
1514  {
1515  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1516  }
1517  else
1518  {
1519  return(0U);
1520  }
1521 }
1522 
1523 
1530 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1531 {
1532  if ((int32_t)(IRQn) >= 0)
1533  {
1534  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1535  }
1536 }
1537 
1538 
1545 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1546 {
1547  if ((int32_t)(IRQn) >= 0)
1548  {
1549  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1550  }
1551 }
1552 
1553 
1562 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1563 {
1564  if ((int32_t)(IRQn) >= 0)
1565  {
1566  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1567  }
1568  else
1569  {
1570  return(0U);
1571  }
1572 }
1573 
1574 
1575 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1576 
1584 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1585 {
1586  if ((int32_t)(IRQn) >= 0)
1587  {
1588  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1589  }
1590  else
1591  {
1592  return(0U);
1593  }
1594 }
1595 
1596 
1605 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1606 {
1607  if ((int32_t)(IRQn) >= 0)
1608  {
1609  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1610  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1611  }
1612  else
1613  {
1614  return(0U);
1615  }
1616 }
1617 
1618 
1627 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1628 {
1629  if ((int32_t)(IRQn) >= 0)
1630  {
1631  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1632  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1633  }
1634  else
1635  {
1636  return(0U);
1637  }
1638 }
1639 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1640 
1641 
1651 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1652 {
1653  if ((int32_t)(IRQn) >= 0)
1654  {
1655  NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1656  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1657  }
1658  else
1659  {
1660  SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1661  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1662  }
1663 }
1664 
1665 
1675 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1676 {
1677 
1678  if ((int32_t)(IRQn) >= 0)
1679  {
1680  return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1681  }
1682  else
1683  {
1684  return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1685  }
1686 }
1687 
1688 
1700 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1701 {
1702  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1703  uint32_t PreemptPriorityBits;
1704  uint32_t SubPriorityBits;
1705 
1706  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1707  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1708 
1709  return (
1710  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1711  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1712  );
1713 }
1714 
1715 
1727 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1728 {
1729  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1730  uint32_t PreemptPriorityBits;
1731  uint32_t SubPriorityBits;
1732 
1733  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1734  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1735 
1736  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1737  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1738 }
1739 
1740 
1751 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1752 {
1753 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1754  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1755 #else
1756  uint32_t *vectors = (uint32_t *)0x0U;
1757 #endif
1758  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1759  __DSB();
1760 }
1761 
1762 
1771 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1772 {
1773 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1774  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1775 #else
1776  uint32_t *vectors = (uint32_t *)0x0U;
1777 #endif
1778  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1779 }
1780 
1781 
1786 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1787 {
1788  __DSB(); /* Ensure all outstanding memory accesses included
1789  buffered write are completed before reset */
1790  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1791  SCB_AIRCR_SYSRESETREQ_Msk);
1792  __DSB(); /* Ensure completion of memory access */
1793 
1794  for(;;) /* wait until reset */
1795  {
1796  __NOP();
1797  }
1798 }
1799 
1800 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1801 
1807 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1808 {
1809  if ((int32_t)(IRQn) >= 0)
1810  {
1811  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1812  }
1813 }
1814 
1815 
1824 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1825 {
1826  if ((int32_t)(IRQn) >= 0)
1827  {
1828  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1829  }
1830  else
1831  {
1832  return(0U);
1833  }
1834 }
1835 
1836 
1843 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1844 {
1845  if ((int32_t)(IRQn) >= 0)
1846  {
1847  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1848  }
1849 }
1850 
1851 
1860 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1861 {
1862  if ((int32_t)(IRQn) >= 0)
1863  {
1864  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1865  }
1866  else
1867  {
1868  return(0U);
1869  }
1870 }
1871 
1872 
1879 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1880 {
1881  if ((int32_t)(IRQn) >= 0)
1882  {
1883  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1884  }
1885 }
1886 
1887 
1894 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1895 {
1896  if ((int32_t)(IRQn) >= 0)
1897  {
1898  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1899  }
1900 }
1901 
1902 
1911 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1912 {
1913  if ((int32_t)(IRQn) >= 0)
1914  {
1915  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1916  }
1917  else
1918  {
1919  return(0U);
1920  }
1921 }
1922 
1923 
1933 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
1934 {
1935  if ((int32_t)(IRQn) >= 0)
1936  {
1937  NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1938  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1939  }
1940  else
1941  {
1942  SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1943  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1944  }
1945 }
1946 
1947 
1956 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
1957 {
1958 
1959  if ((int32_t)(IRQn) >= 0)
1960  {
1961  return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1962  }
1963  else
1964  {
1965  return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1966  }
1967 }
1968 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
1969 
1972 /* ########################## MPU functions #################################### */
1973 
1974 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1975 
1976 #include "mpu_armv8.h"
1977 
1978 #endif
1979 
1980 /* ########################## FPU functions #################################### */
1996 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1997 {
1998  return 0U; /* No FPU */
1999 }
2000 
2001 
2006 /* ########################## SAU functions #################################### */
2014 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2015 
2020 __STATIC_INLINE void TZ_SAU_Enable(void)
2021 {
2022  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2023 }
2024 
2025 
2026 
2031 __STATIC_INLINE void TZ_SAU_Disable(void)
2032 {
2033  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2034 }
2035 
2036 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2037 
2043 /* ################################## Debug Control function ############################################ */
2057 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2058 {
2059  __DSB();
2060  __ISB();
2061  DCB->DAUTHCTRL = value;
2062  __DSB();
2063  __ISB();
2064 }
2065 
2066 
2072 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2073 {
2074  return (DCB->DAUTHCTRL);
2075 }
2076 
2077 
2078 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2079 
2084 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2085 {
2086  __DSB();
2087  __ISB();
2088  DCB_NS->DAUTHCTRL = value;
2089  __DSB();
2090  __ISB();
2091 }
2092 
2093 
2099 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2100 {
2101  return (DCB_NS->DAUTHCTRL);
2102 }
2103 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2104 
2110 /* ################################## Debug Identification function ############################################ */
2124 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
2125 {
2126  return (DIB->DAUTHSTATUS);
2127 }
2128 
2129 
2130 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2131 
2136 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
2137 {
2138  return (DIB_NS->DAUTHSTATUS);
2139 }
2140 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2141 
2147 /* ################################## SysTick function ############################################ */
2155 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2156 
2168 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2169 {
2170  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2171  {
2172  return (1UL); /* Reload value impossible */
2173  }
2174 
2175  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2176  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2177  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2178  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2179  SysTick_CTRL_TICKINT_Msk |
2180  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2181  return (0UL); /* Function successful */
2182 }
2183 
2184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2185 
2197 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2198 {
2199  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2200  {
2201  return (1UL); /* Reload value impossible */
2202  }
2203 
2204  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2205  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2206  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2207  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2208  SysTick_CTRL_TICKINT_Msk |
2209  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2210  return (0UL); /* Function successful */
2211 }
2212 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2213 
2214 #endif
2215 
2221 #ifdef __cplusplus
2222 }
2223 #endif
2224 
2225 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */
2226 
2227 #endif /* __CMSIS_GENERIC */
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1202
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_armv81mml.h:3008
mpu_armv8.h
DCB
#define DCB
Definition: core_armv8mbl.h:1323
SCB_Type::RESERVED0
uint32_t RESERVED0
Definition: core_armv8mbl.h:395
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:3332
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:234
SysTick
#define SysTick
Definition: core_armv8mbl.h:1318
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:3623
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:3313
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:3370
IRQn_Type
enum IRQn IRQn_Type
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_armv81mml.h:4003
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:3389
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:390
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1388
SysTick_IRQn
Definition: cc27xx.h:24
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:3885
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:3584
_BIT_SHIFT
#define _BIT_SHIFT(IRQn)
Definition: core_armv8mbl.h:1441
NVIC
#define NVIC
Definition: core_armv8mbl.h:1319
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:275
cmsis_version.h
CMSIS Core(M) Version definitions.
CoreDebug_Type
Definition: core_armv81mml.h:2646
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:534
SCB
#define SCB
Definition: core_armv8mbl.h:1317
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:3607
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:3351
__IOM
#define __IOM
Definition: core_armv8mbl.h:208
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:498
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1049
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv8mbl.h:468
SCB_Type::RESERVED1
uint32_t RESERVED1
Definition: core_armv8mbl.h:400
IRQn
IRQn
Definition: cc27xx.h:13
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:3421
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: cmsis_gcc.h:117
_IP_IDX
#define _IP_IDX(IRQn)
Definition: core_armv8mbl.h:1443
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_armv81mml.h:4070
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv8mbl.h:1399
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:3510
DIB
#define DIB
Definition: core_armv8mbl.h:1324
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv8mbl.h:487
cmsis_compiler.h
CMSIS compiler generic header file.
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:351
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv8mbl.h:588
__IM
#define __IM
Definition: core_armv8mbl.h:206
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:3404
__OM
#define __OM
Definition: core_armv8mbl.h:207
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_armv81mml.h:2817
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:459
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv8mbl.h:578
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv8mbl.h:584
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv8mbl.h:1414
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_gcc.h:47
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:3557
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:3634
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:408
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_armv81mml.h:4018
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:264
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:3532
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv8mbl.h:581
_SHP_IDX
#define _SHP_IDX(IRQn)
Definition: core_armv8mbl.h:1442
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_gcc.h:53
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: cc27xx.h:106