CC27xxDriverLibrary
core_armv81mml.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2018-2023 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30  #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32 
33 #ifndef __CORE_ARMV81MML_H_GENERIC
34 #define __CORE_ARMV81MML_H_GENERIC
35 
36 #include <stdint.h>
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
57 /*******************************************************************************
58  * CMSIS definitions
59  ******************************************************************************/
65 #include "cmsis_version.h"
66 
67 /* CMSIS ARMV81MML definitions */
68 #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
69 #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
70 #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
71  __ARMv81MML_CMSIS_VERSION_SUB )
73 #define __CORTEX_M (81U)
75 #if defined ( __CC_ARM )
76  #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
77 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
78  #if defined __ARM_FP
79  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
80  #define __FPU_USED 1U
81  #else
82  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83  #define __FPU_USED 0U
84  #endif
85  #else
86  #define __FPU_USED 0U
87  #endif
88 
89  #if defined(__ARM_FEATURE_DSP)
90  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
91  #define __DSP_USED 1U
92  #else
93  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
94  #define __DSP_USED 0U
95  #endif
96  #else
97  #define __DSP_USED 0U
98  #endif
99 
100 #elif defined (__ti__)
101  #if defined (__ARM_FP)
102  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103  #define __FPU_USED 1U
104  #else
105  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #define __FPU_USED 0U
107  #endif
108  #else
109  #define __FPU_USED 0U
110  #endif
111 
112  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
113  #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
114  #define __DSP_USED 1U
115  #else
116  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
117  #define __DSP_USED 0U
118  #endif
119  #else
120  #define __DSP_USED 0U
121  #endif
122 
123 #elif defined ( __GNUC__ )
124  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
125  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
126  #define __FPU_USED 1U
127  #else
128  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129  #define __FPU_USED 0U
130  #endif
131  #else
132  #define __FPU_USED 0U
133  #endif
134 
135  #if defined(__ARM_FEATURE_DSP)
136  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
137  #define __DSP_USED 1U
138  #else
139  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
140  #define __DSP_USED 0U
141  #endif
142  #else
143  #define __DSP_USED 0U
144  #endif
145 
146 #elif defined ( __ICCARM__ )
147  #if defined __ARMVFP__
148  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
149  #define __FPU_USED 1U
150  #else
151  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
152  #define __FPU_USED 0U
153  #endif
154  #else
155  #define __FPU_USED 0U
156  #endif
157 
158  #if defined(__ARM_FEATURE_DSP)
159  #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
160  #define __DSP_USED 1U
161  #else
162  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
163  #define __DSP_USED 0U
164  #endif
165  #else
166  #define __DSP_USED 0U
167  #endif
168 
169 #elif defined ( __TI_ARM__ )
170  #if defined __TI_VFP_SUPPORT__
171  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
172  #define __FPU_USED 1U
173  #else
174  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
175  #define __FPU_USED 0U
176  #endif
177  #else
178  #define __FPU_USED 0U
179  #endif
180 
181 #elif defined ( __TASKING__ )
182  #if defined __FPU_VFP__
183  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
184  #define __FPU_USED 1U
185  #else
186  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
187  #define __FPU_USED 0U
188  #endif
189  #else
190  #define __FPU_USED 0U
191  #endif
192 
193 #elif defined ( __CSMC__ )
194  #if ( __CSMC__ & 0x400U)
195  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
196  #define __FPU_USED 1U
197  #else
198  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
199  #define __FPU_USED 0U
200  #endif
201  #else
202  #define __FPU_USED 0U
203  #endif
204 
205 #endif
206 
207 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
208 
209 
210 #ifdef __cplusplus
211 }
212 #endif
213 
214 #endif /* __CORE_ARMV81MML_H_GENERIC */
215 
216 #ifndef __CMSIS_GENERIC
217 
218 #ifndef __CORE_ARMV81MML_H_DEPENDANT
219 #define __CORE_ARMV81MML_H_DEPENDANT
220 
221 #ifdef __cplusplus
222  extern "C" {
223 #endif
224 
225 /* check device defines and use defaults */
226 #if defined __CHECK_DEVICE_DEFINES
227  #ifndef __ARMv81MML_REV
228  #define __ARMv81MML_REV 0x0000U
229  #warning "__ARMv81MML_REV not defined in device header file; using default!"
230  #endif
231 
232  #ifndef __FPU_PRESENT
233  #define __FPU_PRESENT 0U
234  #warning "__FPU_PRESENT not defined in device header file; using default!"
235  #endif
236 
237  #if __FPU_PRESENT != 0U
238  #ifndef __FPU_DP
239  #define __FPU_DP 0U
240  #warning "__FPU_DP not defined in device header file; using default!"
241  #endif
242  #endif
243 
244  #ifndef __MPU_PRESENT
245  #define __MPU_PRESENT 0U
246  #warning "__MPU_PRESENT not defined in device header file; using default!"
247  #endif
248 
249  #ifndef __ICACHE_PRESENT
250  #define __ICACHE_PRESENT 0U
251  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
252  #endif
253 
254  #ifndef __DCACHE_PRESENT
255  #define __DCACHE_PRESENT 0U
256  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
257  #endif
258 
259  #ifndef __PMU_PRESENT
260  #define __PMU_PRESENT 0U
261  #warning "__PMU_PRESENT not defined in device header file; using default!"
262  #endif
263 
264  #if __PMU_PRESENT != 0U
265  #ifndef __PMU_NUM_EVENTCNT
266  #define __PMU_NUM_EVENTCNT 2U
267  #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
268  #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2)
269  #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
270  #endif
271  #endif
272 
273  #ifndef __SAUREGION_PRESENT
274  #define __SAUREGION_PRESENT 0U
275  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
276  #endif
277 
278  #ifndef __DSP_PRESENT
279  #define __DSP_PRESENT 0U
280  #warning "__DSP_PRESENT not defined in device header file; using default!"
281  #endif
282 
283  #ifndef __VTOR_PRESENT
284  #define __VTOR_PRESENT 1U
285  #warning "__VTOR_PRESENT not defined in device header file; using default!"
286  #endif
287 
288  #ifndef __NVIC_PRIO_BITS
289  #define __NVIC_PRIO_BITS 3U
290  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
291  #endif
292 
293  #ifndef __Vendor_SysTickConfig
294  #define __Vendor_SysTickConfig 0U
295  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
296  #endif
297 #endif
298 
299 /* IO definitions (access restrictions to peripheral registers) */
307 #ifdef __cplusplus
308  #define __I volatile
309 #else
310  #define __I volatile const
311 #endif
312 #define __O volatile
313 #define __IO volatile
315 /* following defines should be used for structure members */
316 #define __IM volatile const
317 #define __OM volatile
318 #define __IOM volatile
320 
324 /*******************************************************************************
325  * Register Abstraction
326  Core Register contain:
327  - Core Register
328  - Core NVIC Register
329  - Core SCB Register
330  - Core SysTick Register
331  - Core Debug Register
332  - Core MPU Register
333  - Core SAU Register
334  - Core FPU Register
335  ******************************************************************************/
336 
351 typedef union
352 {
353  struct
354  {
355  uint32_t _reserved0:16;
356  uint32_t GE:4;
357  uint32_t _reserved1:7;
358  uint32_t Q:1;
359  uint32_t V:1;
360  uint32_t C:1;
361  uint32_t Z:1;
362  uint32_t N:1;
363  } b;
364  uint32_t w;
365 } APSR_Type;
366 
367 /* APSR Register Definitions */
368 #define APSR_N_Pos 31U
369 #define APSR_N_Msk (1UL << APSR_N_Pos)
371 #define APSR_Z_Pos 30U
372 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
374 #define APSR_C_Pos 29U
375 #define APSR_C_Msk (1UL << APSR_C_Pos)
377 #define APSR_V_Pos 28U
378 #define APSR_V_Msk (1UL << APSR_V_Pos)
380 #define APSR_Q_Pos 27U
381 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
383 #define APSR_GE_Pos 16U
384 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
390 typedef union
391 {
392  struct
393  {
394  uint32_t ISR:9;
395  uint32_t _reserved0:23;
396  } b;
397  uint32_t w;
398 } IPSR_Type;
399 
400 /* IPSR Register Definitions */
401 #define IPSR_ISR_Pos 0U
402 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
408 typedef union
409 {
410  struct
411  {
412  uint32_t ISR:9;
413  uint32_t _reserved0:7;
414  uint32_t GE:4;
415  uint32_t _reserved1:4;
416  uint32_t T:1;
417  uint32_t IT:2;
418  uint32_t Q:1;
419  uint32_t V:1;
420  uint32_t C:1;
421  uint32_t Z:1;
422  uint32_t N:1;
423  } b;
424  uint32_t w;
425 } xPSR_Type;
426 
427 /* xPSR Register Definitions */
428 #define xPSR_N_Pos 31U
429 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
431 #define xPSR_Z_Pos 30U
432 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
434 #define xPSR_C_Pos 29U
435 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
437 #define xPSR_V_Pos 28U
438 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
440 #define xPSR_Q_Pos 27U
441 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
443 #define xPSR_IT_Pos 25U
444 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
446 #define xPSR_T_Pos 24U
447 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
449 #define xPSR_GE_Pos 16U
450 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
452 #define xPSR_ISR_Pos 0U
453 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
459 typedef union
460 {
461  struct
462  {
463  uint32_t nPRIV:1;
464  uint32_t SPSEL:1;
465  uint32_t FPCA:1;
466  uint32_t SFPA:1;
467  uint32_t _reserved1:28;
468  } b;
469  uint32_t w;
470 } CONTROL_Type;
471 
472 /* CONTROL Register Definitions */
473 #define CONTROL_SFPA_Pos 3U
474 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
476 #define CONTROL_FPCA_Pos 2U
477 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
479 #define CONTROL_SPSEL_Pos 1U
480 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
482 #define CONTROL_nPRIV_Pos 0U
483 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
485 
498 typedef struct
499 {
500  __IOM uint32_t ISER[16U];
501  uint32_t RESERVED0[16U];
502  __IOM uint32_t ICER[16U];
503  uint32_t RSERVED1[16U];
504  __IOM uint32_t ISPR[16U];
505  uint32_t RESERVED2[16U];
506  __IOM uint32_t ICPR[16U];
507  uint32_t RESERVED3[16U];
508  __IOM uint32_t IABR[16U];
509  uint32_t RESERVED4[16U];
510  __IOM uint32_t ITNS[16U];
511  uint32_t RESERVED5[16U];
512  __IOM uint8_t IPR[496U];
513  uint32_t RESERVED6[580U];
514  __OM uint32_t STIR;
515 } NVIC_Type;
516 
517 /* Software Triggered Interrupt Register Definitions */
518 #define NVIC_STIR_INTID_Pos 0U
519 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
521 
534 typedef struct
535 {
536  __IM uint32_t CPUID;
537  __IOM uint32_t ICSR;
538  __IOM uint32_t VTOR;
539  __IOM uint32_t AIRCR;
540  __IOM uint32_t SCR;
541  __IOM uint32_t CCR;
542  __IOM uint8_t SHPR[12U];
543  __IOM uint32_t SHCSR;
544  __IOM uint32_t CFSR;
545  __IOM uint32_t HFSR;
546  __IOM uint32_t DFSR;
547  __IOM uint32_t MMFAR;
548  __IOM uint32_t BFAR;
549  __IOM uint32_t AFSR;
550  __IM uint32_t ID_PFR[2U];
551  __IM uint32_t ID_DFR;
552  __IM uint32_t ID_AFR;
553  __IM uint32_t ID_MMFR[4U];
554  __IM uint32_t ID_ISAR[6U];
555  __IM uint32_t CLIDR;
556  __IM uint32_t CTR;
557  __IM uint32_t CCSIDR;
558  __IOM uint32_t CSSELR;
559  __IOM uint32_t CPACR;
560  __IOM uint32_t NSACR;
561  uint32_t RESERVED7[21U];
562  __IOM uint32_t SFSR;
563  __IOM uint32_t SFAR;
564  uint32_t RESERVED3[69U];
565  __OM uint32_t STIR;
566  __IOM uint32_t RFSR;
567  uint32_t RESERVED4[14U];
568  __IM uint32_t MVFR0;
569  __IM uint32_t MVFR1;
570  __IM uint32_t MVFR2;
571  uint32_t RESERVED5[1U];
572  __OM uint32_t ICIALLU;
573  uint32_t RESERVED6[1U];
574  __OM uint32_t ICIMVAU;
575  __OM uint32_t DCIMVAC;
576  __OM uint32_t DCISW;
577  __OM uint32_t DCCMVAU;
578  __OM uint32_t DCCMVAC;
579  __OM uint32_t DCCSW;
580  __OM uint32_t DCCIMVAC;
581  __OM uint32_t DCCISW;
582  __OM uint32_t BPIALL;
583 } SCB_Type;
584 
585 /* SCB CPUID Register Definitions */
586 #define SCB_CPUID_IMPLEMENTER_Pos 24U
587 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
589 #define SCB_CPUID_VARIANT_Pos 20U
590 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
592 #define SCB_CPUID_ARCHITECTURE_Pos 16U
593 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
595 #define SCB_CPUID_PARTNO_Pos 4U
596 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
598 #define SCB_CPUID_REVISION_Pos 0U
599 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
601 /* SCB Interrupt Control State Register Definitions */
602 #define SCB_ICSR_PENDNMISET_Pos 31U
603 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
605 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
606 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
608 #define SCB_ICSR_PENDNMICLR_Pos 30U
609 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
611 #define SCB_ICSR_PENDSVSET_Pos 28U
612 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
614 #define SCB_ICSR_PENDSVCLR_Pos 27U
615 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
617 #define SCB_ICSR_PENDSTSET_Pos 26U
618 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
620 #define SCB_ICSR_PENDSTCLR_Pos 25U
621 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
623 #define SCB_ICSR_STTNS_Pos 24U
624 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
626 #define SCB_ICSR_ISRPREEMPT_Pos 23U
627 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
629 #define SCB_ICSR_ISRPENDING_Pos 22U
630 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
632 #define SCB_ICSR_VECTPENDING_Pos 12U
633 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
635 #define SCB_ICSR_RETTOBASE_Pos 11U
636 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
638 #define SCB_ICSR_VECTACTIVE_Pos 0U
639 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
641 /* SCB Vector Table Offset Register Definitions */
642 #define SCB_VTOR_TBLOFF_Pos 7U
643 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
645 /* SCB Application Interrupt and Reset Control Register Definitions */
646 #define SCB_AIRCR_VECTKEY_Pos 16U
647 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
649 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
650 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
652 #define SCB_AIRCR_ENDIANESS_Pos 15U
653 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
655 #define SCB_AIRCR_PRIS_Pos 14U
656 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
658 #define SCB_AIRCR_BFHFNMINS_Pos 13U
659 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
661 #define SCB_AIRCR_PRIGROUP_Pos 8U
662 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
664 #define SCB_AIRCR_IESB_Pos 5U
665 #define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos)
667 #define SCB_AIRCR_DIT_Pos 4U
668 #define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos)
670 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
671 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
673 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
674 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
676 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
677 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
679 /* SCB System Control Register Definitions */
680 #define SCB_SCR_SEVONPEND_Pos 4U
681 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
683 #define SCB_SCR_SLEEPDEEPS_Pos 3U
684 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
686 #define SCB_SCR_SLEEPDEEP_Pos 2U
687 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
689 #define SCB_SCR_SLEEPONEXIT_Pos 1U
690 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
692 /* SCB Configuration Control Register Definitions */
693 #define SCB_CCR_TRD_Pos 20U
694 #define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos)
696 #define SCB_CCR_LOB_Pos 19U
697 #define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos)
699 #define SCB_CCR_BP_Pos 18U
700 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
702 #define SCB_CCR_IC_Pos 17U
703 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
705 #define SCB_CCR_DC_Pos 16U
706 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
708 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
709 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
711 #define SCB_CCR_BFHFNMIGN_Pos 8U
712 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
714 #define SCB_CCR_DIV_0_TRP_Pos 4U
715 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
717 #define SCB_CCR_UNALIGN_TRP_Pos 3U
718 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
720 #define SCB_CCR_USERSETMPEND_Pos 1U
721 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
723 /* SCB System Handler Control and State Register Definitions */
724 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
725 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
727 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
728 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
730 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
731 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
733 #define SCB_SHCSR_USGFAULTENA_Pos 18U
734 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
736 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
737 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
739 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
740 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
742 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
743 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
745 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
746 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
748 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
749 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
751 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
752 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
754 #define SCB_SHCSR_SYSTICKACT_Pos 11U
755 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
757 #define SCB_SHCSR_PENDSVACT_Pos 10U
758 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
760 #define SCB_SHCSR_MONITORACT_Pos 8U
761 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
763 #define SCB_SHCSR_SVCALLACT_Pos 7U
764 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
766 #define SCB_SHCSR_NMIACT_Pos 5U
767 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
769 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
770 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
772 #define SCB_SHCSR_USGFAULTACT_Pos 3U
773 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
775 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
776 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
778 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
779 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
781 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
782 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
784 /* SCB Configurable Fault Status Register Definitions */
785 #define SCB_CFSR_USGFAULTSR_Pos 16U
786 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
788 #define SCB_CFSR_BUSFAULTSR_Pos 8U
789 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
791 #define SCB_CFSR_MEMFAULTSR_Pos 0U
792 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
794 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
795 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
796 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
798 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
799 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
801 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
802 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
804 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
805 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
807 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
808 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
810 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
811 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
813 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
814 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
815 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
817 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
818 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
820 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
821 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
823 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
824 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
826 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
827 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
829 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
830 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
832 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
833 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
835 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
836 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
837 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
839 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
840 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
842 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
843 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
845 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
846 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
848 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
849 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
851 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
852 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
854 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
855 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
857 /* SCB Hard Fault Status Register Definitions */
858 #define SCB_HFSR_DEBUGEVT_Pos 31U
859 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
861 #define SCB_HFSR_FORCED_Pos 30U
862 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
864 #define SCB_HFSR_VECTTBL_Pos 1U
865 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
867 /* SCB Debug Fault Status Register Definitions */
868 #define SCB_DFSR_PMU_Pos 5U
869 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos)
871 #define SCB_DFSR_EXTERNAL_Pos 4U
872 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
874 #define SCB_DFSR_VCATCH_Pos 3U
875 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
877 #define SCB_DFSR_DWTTRAP_Pos 2U
878 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
880 #define SCB_DFSR_BKPT_Pos 1U
881 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
883 #define SCB_DFSR_HALTED_Pos 0U
884 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
886 /* SCB Non-Secure Access Control Register Definitions */
887 #define SCB_NSACR_CP11_Pos 11U
888 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
890 #define SCB_NSACR_CP10_Pos 10U
891 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
893 #define SCB_NSACR_CP7_Pos 7U
894 #define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos)
896 #define SCB_NSACR_CP6_Pos 6U
897 #define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos)
899 #define SCB_NSACR_CP5_Pos 5U
900 #define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos)
902 #define SCB_NSACR_CP4_Pos 4U
903 #define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos)
905 #define SCB_NSACR_CP3_Pos 3U
906 #define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos)
908 #define SCB_NSACR_CP2_Pos 2U
909 #define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos)
911 #define SCB_NSACR_CP1_Pos 1U
912 #define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos)
914 #define SCB_NSACR_CP0_Pos 0U
915 #define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/)
917 /* SCB Debug Feature Register 0 Definitions */
918 #define SCB_ID_DFR_UDE_Pos 28U
919 #define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos)
921 #define SCB_ID_DFR_MProfDbg_Pos 20U
922 #define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
924 /* SCB Cache Level ID Register Definitions */
925 #define SCB_CLIDR_LOUU_Pos 27U
926 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
928 #define SCB_CLIDR_LOC_Pos 24U
929 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
931 /* SCB Cache Type Register Definitions */
932 #define SCB_CTR_FORMAT_Pos 29U
933 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
935 #define SCB_CTR_CWG_Pos 24U
936 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
938 #define SCB_CTR_ERG_Pos 20U
939 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
941 #define SCB_CTR_DMINLINE_Pos 16U
942 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
944 #define SCB_CTR_IMINLINE_Pos 0U
945 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
947 /* SCB Cache Size ID Register Definitions */
948 #define SCB_CCSIDR_WT_Pos 31U
949 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
951 #define SCB_CCSIDR_WB_Pos 30U
952 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
954 #define SCB_CCSIDR_RA_Pos 29U
955 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
957 #define SCB_CCSIDR_WA_Pos 28U
958 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
960 #define SCB_CCSIDR_NUMSETS_Pos 13U
961 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
963 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
964 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
966 #define SCB_CCSIDR_LINESIZE_Pos 0U
967 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
969 /* SCB Cache Size Selection Register Definitions */
970 #define SCB_CSSELR_LEVEL_Pos 1U
971 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
973 #define SCB_CSSELR_IND_Pos 0U
974 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
976 /* SCB Software Triggered Interrupt Register Definitions */
977 #define SCB_STIR_INTID_Pos 0U
978 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
980 /* SCB RAS Fault Status Register Definitions */
981 #define SCB_RFSR_V_Pos 31U
982 #define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos)
984 #define SCB_RFSR_IS_Pos 16U
985 #define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos)
987 #define SCB_RFSR_UET_Pos 0U
988 #define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/)
990 /* SCB D-Cache Invalidate by Set-way Register Definitions */
991 #define SCB_DCISW_WAY_Pos 30U
992 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
994 #define SCB_DCISW_SET_Pos 5U
995 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
997 /* SCB D-Cache Clean by Set-way Register Definitions */
998 #define SCB_DCCSW_WAY_Pos 30U
999 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
1001 #define SCB_DCCSW_SET_Pos 5U
1002 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
1004 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
1005 #define SCB_DCCISW_WAY_Pos 30U
1006 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
1008 #define SCB_DCCISW_SET_Pos 5U
1009 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
1011 
1024 typedef struct
1025 {
1026  uint32_t RESERVED0[1U];
1027  __IM uint32_t ICTR;
1028  __IOM uint32_t ACTLR;
1029  __IOM uint32_t CPPWR;
1030 } SCnSCB_Type;
1031 
1032 /* Interrupt Controller Type Register Definitions */
1033 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
1034 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
1036 
1049 typedef struct
1050 {
1051  __IOM uint32_t CTRL;
1052  __IOM uint32_t LOAD;
1053  __IOM uint32_t VAL;
1054  __IM uint32_t CALIB;
1055 } SysTick_Type;
1056 
1057 /* SysTick Control / Status Register Definitions */
1058 #define SysTick_CTRL_COUNTFLAG_Pos 16U
1059 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1061 #define SysTick_CTRL_CLKSOURCE_Pos 2U
1062 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1064 #define SysTick_CTRL_TICKINT_Pos 1U
1065 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1067 #define SysTick_CTRL_ENABLE_Pos 0U
1068 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1070 /* SysTick Reload Register Definitions */
1071 #define SysTick_LOAD_RELOAD_Pos 0U
1072 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1074 /* SysTick Current Register Definitions */
1075 #define SysTick_VAL_CURRENT_Pos 0U
1076 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1078 /* SysTick Calibration Register Definitions */
1079 #define SysTick_CALIB_NOREF_Pos 31U
1080 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1082 #define SysTick_CALIB_SKEW_Pos 30U
1083 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1085 #define SysTick_CALIB_TENMS_Pos 0U
1086 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1088 
1101 typedef struct
1102 {
1103  __OM union
1104  {
1105  __OM uint8_t u8;
1106  __OM uint16_t u16;
1107  __OM uint32_t u32;
1108  } PORT [32U];
1109  uint32_t RESERVED0[864U];
1110  __IOM uint32_t TER;
1111  uint32_t RESERVED1[15U];
1112  __IOM uint32_t TPR;
1113  uint32_t RESERVED2[15U];
1114  __IOM uint32_t TCR;
1115  uint32_t RESERVED3[32U];
1116  uint32_t RESERVED4[43U];
1117  __OM uint32_t LAR;
1118  __IM uint32_t LSR;
1119  uint32_t RESERVED5[1U];
1120  __IM uint32_t DEVARCH;
1121  uint32_t RESERVED6[3U];
1122  __IM uint32_t DEVTYPE;
1123  __IM uint32_t PID4;
1124  __IM uint32_t PID5;
1125  __IM uint32_t PID6;
1126  __IM uint32_t PID7;
1127  __IM uint32_t PID0;
1128  __IM uint32_t PID1;
1129  __IM uint32_t PID2;
1130  __IM uint32_t PID3;
1131  __IM uint32_t CID0;
1132  __IM uint32_t CID1;
1133  __IM uint32_t CID2;
1134  __IM uint32_t CID3;
1135 } ITM_Type;
1136 
1137 /* ITM Stimulus Port Register Definitions */
1138 #define ITM_STIM_DISABLED_Pos 1U
1139 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1141 #define ITM_STIM_FIFOREADY_Pos 0U
1142 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1144 /* ITM Trace Privilege Register Definitions */
1145 #define ITM_TPR_PRIVMASK_Pos 0U
1146 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1148 /* ITM Trace Control Register Definitions */
1149 #define ITM_TCR_BUSY_Pos 23U
1150 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1152 #define ITM_TCR_TRACEBUSID_Pos 16U
1153 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1155 #define ITM_TCR_GTSFREQ_Pos 10U
1156 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1158 #define ITM_TCR_TSPRESCALE_Pos 8U
1159 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1161 #define ITM_TCR_STALLENA_Pos 5U
1162 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1164 #define ITM_TCR_SWOENA_Pos 4U
1165 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1167 #define ITM_TCR_DWTENA_Pos 3U
1168 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1170 #define ITM_TCR_SYNCENA_Pos 2U
1171 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1173 #define ITM_TCR_TSENA_Pos 1U
1174 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1176 #define ITM_TCR_ITMENA_Pos 0U
1177 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1179 /* ITM Lock Status Register Definitions */
1180 #define ITM_LSR_ByteAcc_Pos 2U
1181 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1183 #define ITM_LSR_Access_Pos 1U
1184 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1186 #define ITM_LSR_Present_Pos 0U
1187 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1189  /* end of group CMSIS_ITM */
1190 
1191 
1202 typedef struct
1203 {
1204  __IOM uint32_t CTRL;
1205  __IOM uint32_t CYCCNT;
1206  __IOM uint32_t CPICNT;
1207  __IOM uint32_t EXCCNT;
1208  __IOM uint32_t SLEEPCNT;
1209  __IOM uint32_t LSUCNT;
1210  __IOM uint32_t FOLDCNT;
1211  __IM uint32_t PCSR;
1212  __IOM uint32_t COMP0;
1213  uint32_t RESERVED1[1U];
1214  __IOM uint32_t FUNCTION0;
1215  uint32_t RESERVED2[1U];
1216  __IOM uint32_t COMP1;
1217  uint32_t RESERVED3[1U];
1218  __IOM uint32_t FUNCTION1;
1219  uint32_t RESERVED4[1U];
1220  __IOM uint32_t COMP2;
1221  uint32_t RESERVED5[1U];
1222  __IOM uint32_t FUNCTION2;
1223  uint32_t RESERVED6[1U];
1224  __IOM uint32_t COMP3;
1225  uint32_t RESERVED7[1U];
1226  __IOM uint32_t FUNCTION3;
1227  uint32_t RESERVED8[1U];
1228  __IOM uint32_t COMP4;
1229  uint32_t RESERVED9[1U];
1230  __IOM uint32_t FUNCTION4;
1231  uint32_t RESERVED10[1U];
1232  __IOM uint32_t COMP5;
1233  uint32_t RESERVED11[1U];
1234  __IOM uint32_t FUNCTION5;
1235  uint32_t RESERVED12[1U];
1236  __IOM uint32_t COMP6;
1237  uint32_t RESERVED13[1U];
1238  __IOM uint32_t FUNCTION6;
1239  uint32_t RESERVED14[1U];
1240  __IOM uint32_t COMP7;
1241  uint32_t RESERVED15[1U];
1242  __IOM uint32_t FUNCTION7;
1243  uint32_t RESERVED16[1U];
1244  __IOM uint32_t COMP8;
1245  uint32_t RESERVED17[1U];
1246  __IOM uint32_t FUNCTION8;
1247  uint32_t RESERVED18[1U];
1248  __IOM uint32_t COMP9;
1249  uint32_t RESERVED19[1U];
1250  __IOM uint32_t FUNCTION9;
1251  uint32_t RESERVED20[1U];
1252  __IOM uint32_t COMP10;
1253  uint32_t RESERVED21[1U];
1254  __IOM uint32_t FUNCTION10;
1255  uint32_t RESERVED22[1U];
1256  __IOM uint32_t COMP11;
1257  uint32_t RESERVED23[1U];
1258  __IOM uint32_t FUNCTION11;
1259  uint32_t RESERVED24[1U];
1260  __IOM uint32_t COMP12;
1261  uint32_t RESERVED25[1U];
1262  __IOM uint32_t FUNCTION12;
1263  uint32_t RESERVED26[1U];
1264  __IOM uint32_t COMP13;
1265  uint32_t RESERVED27[1U];
1266  __IOM uint32_t FUNCTION13;
1267  uint32_t RESERVED28[1U];
1268  __IOM uint32_t COMP14;
1269  uint32_t RESERVED29[1U];
1270  __IOM uint32_t FUNCTION14;
1271  uint32_t RESERVED30[1U];
1272  __IOM uint32_t COMP15;
1273  uint32_t RESERVED31[1U];
1274  __IOM uint32_t FUNCTION15;
1275  uint32_t RESERVED32[934U];
1276  __IM uint32_t LSR;
1277  uint32_t RESERVED33[1U];
1278  __IM uint32_t DEVARCH;
1279 } DWT_Type;
1280 
1281 /* DWT Control Register Definitions */
1282 #define DWT_CTRL_NUMCOMP_Pos 28U
1283 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1285 #define DWT_CTRL_NOTRCPKT_Pos 27U
1286 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1288 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1289 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1291 #define DWT_CTRL_NOCYCCNT_Pos 25U
1292 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1294 #define DWT_CTRL_NOPRFCNT_Pos 24U
1295 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1297 #define DWT_CTRL_CYCDISS_Pos 23U
1298 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1300 #define DWT_CTRL_CYCEVTENA_Pos 22U
1301 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1303 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1304 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1306 #define DWT_CTRL_LSUEVTENA_Pos 20U
1307 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1309 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1310 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1312 #define DWT_CTRL_EXCEVTENA_Pos 18U
1313 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1315 #define DWT_CTRL_CPIEVTENA_Pos 17U
1316 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1318 #define DWT_CTRL_EXCTRCENA_Pos 16U
1319 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1321 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1322 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1324 #define DWT_CTRL_SYNCTAP_Pos 10U
1325 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1327 #define DWT_CTRL_CYCTAP_Pos 9U
1328 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1330 #define DWT_CTRL_POSTINIT_Pos 5U
1331 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1333 #define DWT_CTRL_POSTPRESET_Pos 1U
1334 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1336 #define DWT_CTRL_CYCCNTENA_Pos 0U
1337 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1339 /* DWT CPI Count Register Definitions */
1340 #define DWT_CPICNT_CPICNT_Pos 0U
1341 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1343 /* DWT Exception Overhead Count Register Definitions */
1344 #define DWT_EXCCNT_EXCCNT_Pos 0U
1345 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1347 /* DWT Sleep Count Register Definitions */
1348 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1349 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1351 /* DWT LSU Count Register Definitions */
1352 #define DWT_LSUCNT_LSUCNT_Pos 0U
1353 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1355 /* DWT Folded-instruction Count Register Definitions */
1356 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1357 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1359 /* DWT Comparator Function Register Definitions */
1360 #define DWT_FUNCTION_ID_Pos 27U
1361 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1363 #define DWT_FUNCTION_MATCHED_Pos 24U
1364 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1366 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1367 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1369 #define DWT_FUNCTION_ACTION_Pos 4U
1370 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1372 #define DWT_FUNCTION_MATCH_Pos 0U
1373 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1375  /* end of group CMSIS_DWT */
1376 
1377 
1388 typedef struct
1389 {
1390  __IM uint32_t SSPSR;
1391  __IOM uint32_t CSPSR;
1392  uint32_t RESERVED0[2U];
1393  __IOM uint32_t ACPR;
1394  uint32_t RESERVED1[55U];
1395  __IOM uint32_t SPPR;
1396  uint32_t RESERVED2[131U];
1397  __IM uint32_t FFSR;
1398  __IOM uint32_t FFCR;
1399  __IOM uint32_t PSCR;
1400  uint32_t RESERVED3[809U];
1401  __OM uint32_t LAR;
1402  __IM uint32_t LSR;
1403  uint32_t RESERVED4[4U];
1404  __IM uint32_t TYPE;
1405  __IM uint32_t DEVTYPE;
1406 } TPI_Type;
1407 
1408 /* TPI Asynchronous Clock Prescaler Register Definitions */
1409 #define TPI_ACPR_SWOSCALER_Pos 0U
1410 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
1412 /* TPI Selected Pin Protocol Register Definitions */
1413 #define TPI_SPPR_TXMODE_Pos 0U
1414 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1416 /* TPI Formatter and Flush Status Register Definitions */
1417 #define TPI_FFSR_FtNonStop_Pos 3U
1418 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1420 #define TPI_FFSR_TCPresent_Pos 2U
1421 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1423 #define TPI_FFSR_FtStopped_Pos 1U
1424 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1426 #define TPI_FFSR_FlInProg_Pos 0U
1427 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1429 /* TPI Formatter and Flush Control Register Definitions */
1430 #define TPI_FFCR_TrigIn_Pos 8U
1431 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1433 #define TPI_FFCR_FOnMan_Pos 6U
1434 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1436 #define TPI_FFCR_EnFmt_Pos 0U
1437 #define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
1439 /* TPI Periodic Synchronization Control Register Definitions */
1440 #define TPI_PSCR_PSCount_Pos 0U
1441 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
1443 /* TPI Software Lock Status Register Definitions */
1444 #define TPI_LSR_nTT_Pos 1U
1445 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
1447 #define TPI_LSR_SLK_Pos 1U
1448 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
1450 #define TPI_LSR_SLI_Pos 0U
1451 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/)
1453 /* TPI DEVID Register Definitions */
1454 #define TPI_DEVID_NRZVALID_Pos 11U
1455 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1457 #define TPI_DEVID_MANCVALID_Pos 10U
1458 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1460 #define TPI_DEVID_PTINVALID_Pos 9U
1461 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1463 #define TPI_DEVID_FIFOSZ_Pos 6U
1464 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1466 /* TPI DEVTYPE Register Definitions */
1467 #define TPI_DEVTYPE_SubType_Pos 4U
1468 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1470 #define TPI_DEVTYPE_MajorType_Pos 0U
1471 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1473  /* end of group CMSIS_TPI */
1474 
1475 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
1476 
1486 typedef struct
1487 {
1488  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];
1489 #if __PMU_NUM_EVENTCNT<31
1490  uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
1491 #endif
1492  __IOM uint32_t CCNTR;
1493  uint32_t RESERVED1[224];
1494  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];
1495 #if __PMU_NUM_EVENTCNT<31
1496  uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
1497 #endif
1498  __IOM uint32_t CCFILTR;
1499  uint32_t RESERVED3[480];
1500  __IOM uint32_t CNTENSET;
1501  uint32_t RESERVED4[7];
1502  __IOM uint32_t CNTENCLR;
1503  uint32_t RESERVED5[7];
1504  __IOM uint32_t INTENSET;
1505  uint32_t RESERVED6[7];
1506  __IOM uint32_t INTENCLR;
1507  uint32_t RESERVED7[7];
1508  __IOM uint32_t OVSCLR;
1509  uint32_t RESERVED8[7];
1510  __IOM uint32_t SWINC;
1511  uint32_t RESERVED9[7];
1512  __IOM uint32_t OVSSET;
1513  uint32_t RESERVED10[79];
1514  __IOM uint32_t TYPE;
1515  __IOM uint32_t CTRL;
1516  uint32_t RESERVED11[108];
1517  __IOM uint32_t AUTHSTATUS;
1518  __IOM uint32_t DEVARCH;
1519  uint32_t RESERVED12[3];
1520  __IOM uint32_t DEVTYPE;
1521  __IOM uint32_t PIDR4;
1522  uint32_t RESERVED13[3];
1523  __IOM uint32_t PIDR0;
1524  __IOM uint32_t PIDR1;
1525  __IOM uint32_t PIDR2;
1526  __IOM uint32_t PIDR3;
1527  __IOM uint32_t CIDR0;
1528  __IOM uint32_t CIDR1;
1529  __IOM uint32_t CIDR2;
1530  __IOM uint32_t CIDR3;
1531 } PMU_Type;
1532 
1535 #define PMU_EVCNTR_CNT_Pos 0U
1536 #define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/)
1540 #define PMU_EVTYPER_EVENTTOCNT_Pos 0U
1541 #define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/)
1545 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U
1546 #define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/)
1548 #define PMU_CNTENSET_CNT1_ENABLE_Pos 1U
1549 #define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos)
1551 #define PMU_CNTENSET_CNT2_ENABLE_Pos 2U
1552 #define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos)
1554 #define PMU_CNTENSET_CNT3_ENABLE_Pos 3U
1555 #define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos)
1557 #define PMU_CNTENSET_CNT4_ENABLE_Pos 4U
1558 #define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos)
1560 #define PMU_CNTENSET_CNT5_ENABLE_Pos 5U
1561 #define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos)
1563 #define PMU_CNTENSET_CNT6_ENABLE_Pos 6U
1564 #define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos)
1566 #define PMU_CNTENSET_CNT7_ENABLE_Pos 7U
1567 #define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos)
1569 #define PMU_CNTENSET_CNT8_ENABLE_Pos 8U
1570 #define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos)
1572 #define PMU_CNTENSET_CNT9_ENABLE_Pos 9U
1573 #define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos)
1575 #define PMU_CNTENSET_CNT10_ENABLE_Pos 10U
1576 #define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos)
1578 #define PMU_CNTENSET_CNT11_ENABLE_Pos 11U
1579 #define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos)
1581 #define PMU_CNTENSET_CNT12_ENABLE_Pos 12U
1582 #define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos)
1584 #define PMU_CNTENSET_CNT13_ENABLE_Pos 13U
1585 #define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos)
1587 #define PMU_CNTENSET_CNT14_ENABLE_Pos 14U
1588 #define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos)
1590 #define PMU_CNTENSET_CNT15_ENABLE_Pos 15U
1591 #define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos)
1593 #define PMU_CNTENSET_CNT16_ENABLE_Pos 16U
1594 #define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos)
1596 #define PMU_CNTENSET_CNT17_ENABLE_Pos 17U
1597 #define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos)
1599 #define PMU_CNTENSET_CNT18_ENABLE_Pos 18U
1600 #define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos)
1602 #define PMU_CNTENSET_CNT19_ENABLE_Pos 19U
1603 #define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos)
1605 #define PMU_CNTENSET_CNT20_ENABLE_Pos 20U
1606 #define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos)
1608 #define PMU_CNTENSET_CNT21_ENABLE_Pos 21U
1609 #define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos)
1611 #define PMU_CNTENSET_CNT22_ENABLE_Pos 22U
1612 #define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos)
1614 #define PMU_CNTENSET_CNT23_ENABLE_Pos 23U
1615 #define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos)
1617 #define PMU_CNTENSET_CNT24_ENABLE_Pos 24U
1618 #define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos)
1620 #define PMU_CNTENSET_CNT25_ENABLE_Pos 25U
1621 #define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos)
1623 #define PMU_CNTENSET_CNT26_ENABLE_Pos 26U
1624 #define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos)
1626 #define PMU_CNTENSET_CNT27_ENABLE_Pos 27U
1627 #define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos)
1629 #define PMU_CNTENSET_CNT28_ENABLE_Pos 28U
1630 #define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos)
1632 #define PMU_CNTENSET_CNT29_ENABLE_Pos 29U
1633 #define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos)
1635 #define PMU_CNTENSET_CNT30_ENABLE_Pos 30U
1636 #define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos)
1638 #define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U
1639 #define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos)
1643 #define PMU_CNTENSET_CNT0_ENABLE_Pos 0U
1644 #define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/)
1646 #define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U
1647 #define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos)
1649 #define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U
1650 #define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos)
1652 #define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U
1653 #define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos)
1655 #define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U
1656 #define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos)
1658 #define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U
1659 #define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos)
1661 #define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U
1662 #define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos)
1664 #define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U
1665 #define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos)
1667 #define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U
1668 #define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos)
1670 #define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U
1671 #define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos)
1673 #define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U
1674 #define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos)
1676 #define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U
1677 #define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos)
1679 #define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U
1680 #define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos)
1682 #define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U
1683 #define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos)
1685 #define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U
1686 #define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos)
1688 #define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U
1689 #define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos)
1691 #define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U
1692 #define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos)
1694 #define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U
1695 #define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos)
1697 #define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U
1698 #define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos)
1700 #define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U
1701 #define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos)
1703 #define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U
1704 #define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos)
1706 #define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U
1707 #define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos)
1709 #define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U
1710 #define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos)
1712 #define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U
1713 #define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos)
1715 #define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U
1716 #define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos)
1718 #define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U
1719 #define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos)
1721 #define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U
1722 #define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos)
1724 #define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U
1725 #define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos)
1727 #define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U
1728 #define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos)
1730 #define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U
1731 #define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos)
1733 #define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U
1734 #define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos)
1736 #define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U
1737 #define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos)
1741 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U
1742 #define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/)
1744 #define PMU_INTENSET_CNT1_ENABLE_Pos 1U
1745 #define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos)
1747 #define PMU_INTENSET_CNT2_ENABLE_Pos 2U
1748 #define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos)
1750 #define PMU_INTENSET_CNT3_ENABLE_Pos 3U
1751 #define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos)
1753 #define PMU_INTENSET_CNT4_ENABLE_Pos 4U
1754 #define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos)
1756 #define PMU_INTENSET_CNT5_ENABLE_Pos 5U
1757 #define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos)
1759 #define PMU_INTENSET_CNT6_ENABLE_Pos 6U
1760 #define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos)
1762 #define PMU_INTENSET_CNT7_ENABLE_Pos 7U
1763 #define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos)
1765 #define PMU_INTENSET_CNT8_ENABLE_Pos 8U
1766 #define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos)
1768 #define PMU_INTENSET_CNT9_ENABLE_Pos 9U
1769 #define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos)
1771 #define PMU_INTENSET_CNT10_ENABLE_Pos 10U
1772 #define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos)
1774 #define PMU_INTENSET_CNT11_ENABLE_Pos 11U
1775 #define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos)
1777 #define PMU_INTENSET_CNT12_ENABLE_Pos 12U
1778 #define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos)
1780 #define PMU_INTENSET_CNT13_ENABLE_Pos 13U
1781 #define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos)
1783 #define PMU_INTENSET_CNT14_ENABLE_Pos 14U
1784 #define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos)
1786 #define PMU_INTENSET_CNT15_ENABLE_Pos 15U
1787 #define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos)
1789 #define PMU_INTENSET_CNT16_ENABLE_Pos 16U
1790 #define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos)
1792 #define PMU_INTENSET_CNT17_ENABLE_Pos 17U
1793 #define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos)
1795 #define PMU_INTENSET_CNT18_ENABLE_Pos 18U
1796 #define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos)
1798 #define PMU_INTENSET_CNT19_ENABLE_Pos 19U
1799 #define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos)
1801 #define PMU_INTENSET_CNT20_ENABLE_Pos 20U
1802 #define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos)
1804 #define PMU_INTENSET_CNT21_ENABLE_Pos 21U
1805 #define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos)
1807 #define PMU_INTENSET_CNT22_ENABLE_Pos 22U
1808 #define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos)
1810 #define PMU_INTENSET_CNT23_ENABLE_Pos 23U
1811 #define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos)
1813 #define PMU_INTENSET_CNT24_ENABLE_Pos 24U
1814 #define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos)
1816 #define PMU_INTENSET_CNT25_ENABLE_Pos 25U
1817 #define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos)
1819 #define PMU_INTENSET_CNT26_ENABLE_Pos 26U
1820 #define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos)
1822 #define PMU_INTENSET_CNT27_ENABLE_Pos 27U
1823 #define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos)
1825 #define PMU_INTENSET_CNT28_ENABLE_Pos 28U
1826 #define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos)
1828 #define PMU_INTENSET_CNT29_ENABLE_Pos 29U
1829 #define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos)
1831 #define PMU_INTENSET_CNT30_ENABLE_Pos 30U
1832 #define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos)
1834 #define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U
1835 #define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos)
1839 #define PMU_INTENSET_CNT0_ENABLE_Pos 0U
1840 #define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/)
1842 #define PMU_INTENCLR_CNT1_ENABLE_Pos 1U
1843 #define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos)
1845 #define PMU_INTENCLR_CNT2_ENABLE_Pos 2U
1846 #define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos)
1848 #define PMU_INTENCLR_CNT3_ENABLE_Pos 3U
1849 #define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos)
1851 #define PMU_INTENCLR_CNT4_ENABLE_Pos 4U
1852 #define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos)
1854 #define PMU_INTENCLR_CNT5_ENABLE_Pos 5U
1855 #define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos)
1857 #define PMU_INTENCLR_CNT6_ENABLE_Pos 6U
1858 #define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos)
1860 #define PMU_INTENCLR_CNT7_ENABLE_Pos 7U
1861 #define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos)
1863 #define PMU_INTENCLR_CNT8_ENABLE_Pos 8U
1864 #define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos)
1866 #define PMU_INTENCLR_CNT9_ENABLE_Pos 9U
1867 #define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos)
1869 #define PMU_INTENCLR_CNT10_ENABLE_Pos 10U
1870 #define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos)
1872 #define PMU_INTENCLR_CNT11_ENABLE_Pos 11U
1873 #define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos)
1875 #define PMU_INTENCLR_CNT12_ENABLE_Pos 12U
1876 #define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos)
1878 #define PMU_INTENCLR_CNT13_ENABLE_Pos 13U
1879 #define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos)
1881 #define PMU_INTENCLR_CNT14_ENABLE_Pos 14U
1882 #define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos)
1884 #define PMU_INTENCLR_CNT15_ENABLE_Pos 15U
1885 #define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos)
1887 #define PMU_INTENCLR_CNT16_ENABLE_Pos 16U
1888 #define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos)
1890 #define PMU_INTENCLR_CNT17_ENABLE_Pos 17U
1891 #define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos)
1893 #define PMU_INTENCLR_CNT18_ENABLE_Pos 18U
1894 #define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos)
1896 #define PMU_INTENCLR_CNT19_ENABLE_Pos 19U
1897 #define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos)
1899 #define PMU_INTENCLR_CNT20_ENABLE_Pos 20U
1900 #define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos)
1902 #define PMU_INTENCLR_CNT21_ENABLE_Pos 21U
1903 #define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos)
1905 #define PMU_INTENCLR_CNT22_ENABLE_Pos 22U
1906 #define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos)
1908 #define PMU_INTENCLR_CNT23_ENABLE_Pos 23U
1909 #define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos)
1911 #define PMU_INTENCLR_CNT24_ENABLE_Pos 24U
1912 #define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos)
1914 #define PMU_INTENCLR_CNT25_ENABLE_Pos 25U
1915 #define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos)
1917 #define PMU_INTENCLR_CNT26_ENABLE_Pos 26U
1918 #define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos)
1920 #define PMU_INTENCLR_CNT27_ENABLE_Pos 27U
1921 #define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos)
1923 #define PMU_INTENCLR_CNT28_ENABLE_Pos 28U
1924 #define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos)
1926 #define PMU_INTENCLR_CNT29_ENABLE_Pos 29U
1927 #define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos)
1929 #define PMU_INTENCLR_CNT30_ENABLE_Pos 30U
1930 #define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos)
1932 #define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U
1933 #define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos)
1937 #define PMU_OVSSET_CNT0_STATUS_Pos 0U
1938 #define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/)
1940 #define PMU_OVSSET_CNT1_STATUS_Pos 1U
1941 #define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos)
1943 #define PMU_OVSSET_CNT2_STATUS_Pos 2U
1944 #define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos)
1946 #define PMU_OVSSET_CNT3_STATUS_Pos 3U
1947 #define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos)
1949 #define PMU_OVSSET_CNT4_STATUS_Pos 4U
1950 #define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos)
1952 #define PMU_OVSSET_CNT5_STATUS_Pos 5U
1953 #define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos)
1955 #define PMU_OVSSET_CNT6_STATUS_Pos 6U
1956 #define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos)
1958 #define PMU_OVSSET_CNT7_STATUS_Pos 7U
1959 #define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos)
1961 #define PMU_OVSSET_CNT8_STATUS_Pos 8U
1962 #define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos)
1964 #define PMU_OVSSET_CNT9_STATUS_Pos 9U
1965 #define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos)
1967 #define PMU_OVSSET_CNT10_STATUS_Pos 10U
1968 #define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos)
1970 #define PMU_OVSSET_CNT11_STATUS_Pos 11U
1971 #define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos)
1973 #define PMU_OVSSET_CNT12_STATUS_Pos 12U
1974 #define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos)
1976 #define PMU_OVSSET_CNT13_STATUS_Pos 13U
1977 #define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos)
1979 #define PMU_OVSSET_CNT14_STATUS_Pos 14U
1980 #define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos)
1982 #define PMU_OVSSET_CNT15_STATUS_Pos 15U
1983 #define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos)
1985 #define PMU_OVSSET_CNT16_STATUS_Pos 16U
1986 #define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos)
1988 #define PMU_OVSSET_CNT17_STATUS_Pos 17U
1989 #define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos)
1991 #define PMU_OVSSET_CNT18_STATUS_Pos 18U
1992 #define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos)
1994 #define PMU_OVSSET_CNT19_STATUS_Pos 19U
1995 #define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos)
1997 #define PMU_OVSSET_CNT20_STATUS_Pos 20U
1998 #define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos)
2000 #define PMU_OVSSET_CNT21_STATUS_Pos 21U
2001 #define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos)
2003 #define PMU_OVSSET_CNT22_STATUS_Pos 22U
2004 #define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos)
2006 #define PMU_OVSSET_CNT23_STATUS_Pos 23U
2007 #define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos)
2009 #define PMU_OVSSET_CNT24_STATUS_Pos 24U
2010 #define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos)
2012 #define PMU_OVSSET_CNT25_STATUS_Pos 25U
2013 #define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos)
2015 #define PMU_OVSSET_CNT26_STATUS_Pos 26U
2016 #define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos)
2018 #define PMU_OVSSET_CNT27_STATUS_Pos 27U
2019 #define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos)
2021 #define PMU_OVSSET_CNT28_STATUS_Pos 28U
2022 #define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos)
2024 #define PMU_OVSSET_CNT29_STATUS_Pos 29U
2025 #define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos)
2027 #define PMU_OVSSET_CNT30_STATUS_Pos 30U
2028 #define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos)
2030 #define PMU_OVSSET_CYCCNT_STATUS_Pos 31U
2031 #define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos)
2035 #define PMU_OVSCLR_CNT0_STATUS_Pos 0U
2036 #define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/)
2038 #define PMU_OVSCLR_CNT1_STATUS_Pos 1U
2039 #define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos)
2041 #define PMU_OVSCLR_CNT2_STATUS_Pos 2U
2042 #define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos)
2044 #define PMU_OVSCLR_CNT3_STATUS_Pos 3U
2045 #define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos)
2047 #define PMU_OVSCLR_CNT4_STATUS_Pos 4U
2048 #define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos)
2050 #define PMU_OVSCLR_CNT5_STATUS_Pos 5U
2051 #define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos)
2053 #define PMU_OVSCLR_CNT6_STATUS_Pos 6U
2054 #define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos)
2056 #define PMU_OVSCLR_CNT7_STATUS_Pos 7U
2057 #define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos)
2059 #define PMU_OVSCLR_CNT8_STATUS_Pos 8U
2060 #define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos)
2062 #define PMU_OVSCLR_CNT9_STATUS_Pos 9U
2063 #define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos)
2065 #define PMU_OVSCLR_CNT10_STATUS_Pos 10U
2066 #define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos)
2068 #define PMU_OVSCLR_CNT11_STATUS_Pos 11U
2069 #define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos)
2071 #define PMU_OVSCLR_CNT12_STATUS_Pos 12U
2072 #define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos)
2074 #define PMU_OVSCLR_CNT13_STATUS_Pos 13U
2075 #define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos)
2077 #define PMU_OVSCLR_CNT14_STATUS_Pos 14U
2078 #define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos)
2080 #define PMU_OVSCLR_CNT15_STATUS_Pos 15U
2081 #define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos)
2083 #define PMU_OVSCLR_CNT16_STATUS_Pos 16U
2084 #define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos)
2086 #define PMU_OVSCLR_CNT17_STATUS_Pos 17U
2087 #define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos)
2089 #define PMU_OVSCLR_CNT18_STATUS_Pos 18U
2090 #define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos)
2092 #define PMU_OVSCLR_CNT19_STATUS_Pos 19U
2093 #define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos)
2095 #define PMU_OVSCLR_CNT20_STATUS_Pos 20U
2096 #define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos)
2098 #define PMU_OVSCLR_CNT21_STATUS_Pos 21U
2099 #define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos)
2101 #define PMU_OVSCLR_CNT22_STATUS_Pos 22U
2102 #define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos)
2104 #define PMU_OVSCLR_CNT23_STATUS_Pos 23U
2105 #define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos)
2107 #define PMU_OVSCLR_CNT24_STATUS_Pos 24U
2108 #define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos)
2110 #define PMU_OVSCLR_CNT25_STATUS_Pos 25U
2111 #define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos)
2113 #define PMU_OVSCLR_CNT26_STATUS_Pos 26U
2114 #define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos)
2116 #define PMU_OVSCLR_CNT27_STATUS_Pos 27U
2117 #define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos)
2119 #define PMU_OVSCLR_CNT28_STATUS_Pos 28U
2120 #define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos)
2122 #define PMU_OVSCLR_CNT29_STATUS_Pos 29U
2123 #define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos)
2125 #define PMU_OVSCLR_CNT30_STATUS_Pos 30U
2126 #define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos)
2128 #define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U
2129 #define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos)
2133 #define PMU_SWINC_CNT0_Pos 0U
2134 #define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */)
2136 #define PMU_SWINC_CNT1_Pos 1U
2137 #define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos)
2139 #define PMU_SWINC_CNT2_Pos 2U
2140 #define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos)
2142 #define PMU_SWINC_CNT3_Pos 3U
2143 #define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos)
2145 #define PMU_SWINC_CNT4_Pos 4U
2146 #define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos)
2148 #define PMU_SWINC_CNT5_Pos 5U
2149 #define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos)
2151 #define PMU_SWINC_CNT6_Pos 6U
2152 #define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos)
2154 #define PMU_SWINC_CNT7_Pos 7U
2155 #define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos)
2157 #define PMU_SWINC_CNT8_Pos 8U
2158 #define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos)
2160 #define PMU_SWINC_CNT9_Pos 9U
2161 #define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos)
2163 #define PMU_SWINC_CNT10_Pos 10U
2164 #define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos)
2166 #define PMU_SWINC_CNT11_Pos 11U
2167 #define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos)
2169 #define PMU_SWINC_CNT12_Pos 12U
2170 #define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos)
2172 #define PMU_SWINC_CNT13_Pos 13U
2173 #define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos)
2175 #define PMU_SWINC_CNT14_Pos 14U
2176 #define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos)
2178 #define PMU_SWINC_CNT15_Pos 15U
2179 #define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos)
2181 #define PMU_SWINC_CNT16_Pos 16U
2182 #define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos)
2184 #define PMU_SWINC_CNT17_Pos 17U
2185 #define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos)
2187 #define PMU_SWINC_CNT18_Pos 18U
2188 #define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos)
2190 #define PMU_SWINC_CNT19_Pos 19U
2191 #define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos)
2193 #define PMU_SWINC_CNT20_Pos 20U
2194 #define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos)
2196 #define PMU_SWINC_CNT21_Pos 21U
2197 #define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos)
2199 #define PMU_SWINC_CNT22_Pos 22U
2200 #define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos)
2202 #define PMU_SWINC_CNT23_Pos 23U
2203 #define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos)
2205 #define PMU_SWINC_CNT24_Pos 24U
2206 #define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos)
2208 #define PMU_SWINC_CNT25_Pos 25U
2209 #define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos)
2211 #define PMU_SWINC_CNT26_Pos 26U
2212 #define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos)
2214 #define PMU_SWINC_CNT27_Pos 27U
2215 #define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos)
2217 #define PMU_SWINC_CNT28_Pos 28U
2218 #define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos)
2220 #define PMU_SWINC_CNT29_Pos 29U
2221 #define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos)
2223 #define PMU_SWINC_CNT30_Pos 30U
2224 #define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos)
2228 #define PMU_CTRL_ENABLE_Pos 0U
2229 #define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/)
2231 #define PMU_CTRL_EVENTCNT_RESET_Pos 1U
2232 #define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos)
2234 #define PMU_CTRL_CYCCNT_RESET_Pos 2U
2235 #define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos)
2237 #define PMU_CTRL_CYCCNT_DISABLE_Pos 5U
2238 #define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos)
2240 #define PMU_CTRL_FRZ_ON_OV_Pos 9U
2241 #define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos)
2243 #define PMU_CTRL_TRACE_ON_OV_Pos 11U
2244 #define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos)
2248 #define PMU_TYPE_NUM_CNTS_Pos 0U
2249 #define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/)
2251 #define PMU_TYPE_SIZE_CNTS_Pos 8U
2252 #define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos)
2254 #define PMU_TYPE_CYCCNT_PRESENT_Pos 14U
2255 #define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos)
2257 #define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U
2258 #define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)
2260 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U
2261 #define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)
2265 #define PMU_AUTHSTATUS_NSID_Pos 0U
2266 #define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/)
2268 #define PMU_AUTHSTATUS_NSNID_Pos 2U
2269 #define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos)
2271 #define PMU_AUTHSTATUS_SID_Pos 4U
2272 #define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos)
2274 #define PMU_AUTHSTATUS_SNID_Pos 6U
2275 #define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos)
2277 #define PMU_AUTHSTATUS_NSUID_Pos 16U
2278 #define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos)
2280 #define PMU_AUTHSTATUS_NSUNID_Pos 18U
2281 #define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos)
2283 #define PMU_AUTHSTATUS_SUID_Pos 20U
2284 #define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos)
2286 #define PMU_AUTHSTATUS_SUNID_Pos 22U
2287 #define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos)
2289 
2290 #endif
2291 
2292 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2293 
2303 typedef struct
2304 {
2305  __IM uint32_t TYPE;
2306  __IOM uint32_t CTRL;
2307  __IOM uint32_t RNR;
2308  __IOM uint32_t RBAR;
2309  __IOM uint32_t RLAR;
2310  __IOM uint32_t RBAR_A1;
2311  __IOM uint32_t RLAR_A1;
2312  __IOM uint32_t RBAR_A2;
2313  __IOM uint32_t RLAR_A2;
2314  __IOM uint32_t RBAR_A3;
2315  __IOM uint32_t RLAR_A3;
2316  uint32_t RESERVED0[1];
2317  union {
2318  __IOM uint32_t MAIR[2];
2319  struct {
2320  __IOM uint32_t MAIR0;
2321  __IOM uint32_t MAIR1;
2322  };
2323  };
2324 } MPU_Type;
2325 
2326 #define MPU_TYPE_RALIASES 4U
2327 
2328 /* MPU Type Register Definitions */
2329 #define MPU_TYPE_IREGION_Pos 16U
2330 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
2332 #define MPU_TYPE_DREGION_Pos 8U
2333 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
2335 #define MPU_TYPE_SEPARATE_Pos 0U
2336 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
2338 /* MPU Control Register Definitions */
2339 #define MPU_CTRL_PRIVDEFENA_Pos 2U
2340 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
2342 #define MPU_CTRL_HFNMIENA_Pos 1U
2343 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
2345 #define MPU_CTRL_ENABLE_Pos 0U
2346 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
2348 /* MPU Region Number Register Definitions */
2349 #define MPU_RNR_REGION_Pos 0U
2350 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
2352 /* MPU Region Base Address Register Definitions */
2353 #define MPU_RBAR_BASE_Pos 5U
2354 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
2356 #define MPU_RBAR_SH_Pos 3U
2357 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
2359 #define MPU_RBAR_AP_Pos 1U
2360 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
2362 #define MPU_RBAR_XN_Pos 0U
2363 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
2365 /* MPU Region Limit Address Register Definitions */
2366 #define MPU_RLAR_LIMIT_Pos 5U
2367 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
2369 #define MPU_RLAR_PXN_Pos 4U
2370 #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos)
2372 #define MPU_RLAR_AttrIndx_Pos 1U
2373 #define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos)
2375 #define MPU_RLAR_EN_Pos 0U
2376 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
2378 /* MPU Memory Attribute Indirection Register 0 Definitions */
2379 #define MPU_MAIR0_Attr3_Pos 24U
2380 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
2382 #define MPU_MAIR0_Attr2_Pos 16U
2383 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
2385 #define MPU_MAIR0_Attr1_Pos 8U
2386 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
2388 #define MPU_MAIR0_Attr0_Pos 0U
2389 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
2391 /* MPU Memory Attribute Indirection Register 1 Definitions */
2392 #define MPU_MAIR1_Attr7_Pos 24U
2393 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
2395 #define MPU_MAIR1_Attr6_Pos 16U
2396 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
2398 #define MPU_MAIR1_Attr5_Pos 8U
2399 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
2401 #define MPU_MAIR1_Attr4_Pos 0U
2402 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
2404 
2405 #endif
2406 
2407 
2408 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2409 
2419 typedef struct
2420 {
2421  __IOM uint32_t CTRL;
2422  __IM uint32_t TYPE;
2423 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
2424  __IOM uint32_t RNR;
2425  __IOM uint32_t RBAR;
2426  __IOM uint32_t RLAR;
2427 #else
2428  uint32_t RESERVED0[3];
2429 #endif
2430  __IOM uint32_t SFSR;
2431  __IOM uint32_t SFAR;
2432 } SAU_Type;
2433 
2434 /* SAU Control Register Definitions */
2435 #define SAU_CTRL_ALLNS_Pos 1U
2436 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
2438 #define SAU_CTRL_ENABLE_Pos 0U
2439 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
2441 /* SAU Type Register Definitions */
2442 #define SAU_TYPE_SREGION_Pos 0U
2443 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
2445 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
2446 /* SAU Region Number Register Definitions */
2447 #define SAU_RNR_REGION_Pos 0U
2448 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
2450 /* SAU Region Base Address Register Definitions */
2451 #define SAU_RBAR_BADDR_Pos 5U
2452 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
2454 /* SAU Region Limit Address Register Definitions */
2455 #define SAU_RLAR_LADDR_Pos 5U
2456 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
2458 #define SAU_RLAR_NSC_Pos 1U
2459 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
2461 #define SAU_RLAR_ENABLE_Pos 0U
2462 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
2464 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
2465 
2466 /* Secure Fault Status Register Definitions */
2467 #define SAU_SFSR_LSERR_Pos 7U
2468 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
2470 #define SAU_SFSR_SFARVALID_Pos 6U
2471 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
2473 #define SAU_SFSR_LSPERR_Pos 5U
2474 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
2476 #define SAU_SFSR_INVTRAN_Pos 4U
2477 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
2479 #define SAU_SFSR_AUVIOL_Pos 3U
2480 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
2482 #define SAU_SFSR_INVER_Pos 2U
2483 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
2485 #define SAU_SFSR_INVIS_Pos 1U
2486 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
2488 #define SAU_SFSR_INVEP_Pos 0U
2489 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
2491 
2492 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2493 
2494 
2505 typedef struct
2506 {
2507  uint32_t RESERVED0[1U];
2508  __IOM uint32_t FPCCR;
2509  __IOM uint32_t FPCAR;
2510  __IOM uint32_t FPDSCR;
2511  __IM uint32_t MVFR0;
2512  __IM uint32_t MVFR1;
2513  __IM uint32_t MVFR2;
2514 } FPU_Type;
2515 
2516 /* Floating-Point Context Control Register Definitions */
2517 #define FPU_FPCCR_ASPEN_Pos 31U
2518 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
2520 #define FPU_FPCCR_LSPEN_Pos 30U
2521 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
2523 #define FPU_FPCCR_LSPENS_Pos 29U
2524 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
2526 #define FPU_FPCCR_CLRONRET_Pos 28U
2527 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
2529 #define FPU_FPCCR_CLRONRETS_Pos 27U
2530 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
2532 #define FPU_FPCCR_TS_Pos 26U
2533 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
2535 #define FPU_FPCCR_UFRDY_Pos 10U
2536 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
2538 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
2539 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
2541 #define FPU_FPCCR_MONRDY_Pos 8U
2542 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
2544 #define FPU_FPCCR_SFRDY_Pos 7U
2545 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
2547 #define FPU_FPCCR_BFRDY_Pos 6U
2548 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
2550 #define FPU_FPCCR_MMRDY_Pos 5U
2551 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
2553 #define FPU_FPCCR_HFRDY_Pos 4U
2554 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
2556 #define FPU_FPCCR_THREAD_Pos 3U
2557 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
2559 #define FPU_FPCCR_S_Pos 2U
2560 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
2562 #define FPU_FPCCR_USER_Pos 1U
2563 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
2565 #define FPU_FPCCR_LSPACT_Pos 0U
2566 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
2568 /* Floating-Point Context Address Register Definitions */
2569 #define FPU_FPCAR_ADDRESS_Pos 3U
2570 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
2572 /* Floating-Point Default Status Control Register Definitions */
2573 #define FPU_FPDSCR_AHP_Pos 26U
2574 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
2576 #define FPU_FPDSCR_DN_Pos 25U
2577 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
2579 #define FPU_FPDSCR_FZ_Pos 24U
2580 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
2582 #define FPU_FPDSCR_RMode_Pos 22U
2583 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
2585 #define FPU_FPDSCR_FZ16_Pos 19U
2586 #define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos)
2588 #define FPU_FPDSCR_LTPSIZE_Pos 16U
2589 #define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos)
2591 /* Media and VFP Feature Register 0 Definitions */
2592 #define FPU_MVFR0_FPRound_Pos 28U
2593 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos)
2595 #define FPU_MVFR0_FPSqrt_Pos 20U
2596 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos)
2598 #define FPU_MVFR0_FPDivide_Pos 16U
2599 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos)
2601 #define FPU_MVFR0_FPDP_Pos 8U
2602 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos)
2604 #define FPU_MVFR0_FPSP_Pos 4U
2605 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos)
2607 #define FPU_MVFR0_SIMDReg_Pos 0U
2608 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
2610 /* Media and VFP Feature Register 1 Definitions */
2611 #define FPU_MVFR1_FMAC_Pos 28U
2612 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos)
2614 #define FPU_MVFR1_FPHP_Pos 24U
2615 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos)
2617 #define FPU_MVFR1_FP16_Pos 20U
2618 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos)
2620 #define FPU_MVFR1_MVE_Pos 8U
2621 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos)
2623 #define FPU_MVFR1_FPDNaN_Pos 4U
2624 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos)
2626 #define FPU_MVFR1_FPFtZ_Pos 0U
2627 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
2629 /* Media and VFP Feature Register 2 Definitions */
2630 #define FPU_MVFR2_FPMisc_Pos 4U
2631 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
2633 
2635 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
2636 
2646 typedef struct
2647 {
2648  __IOM uint32_t DHCSR;
2649  __OM uint32_t DCRSR;
2650  __IOM uint32_t DCRDR;
2651  __IOM uint32_t DEMCR;
2652  __OM uint32_t DSCEMCR;
2653  __IOM uint32_t DAUTHCTRL;
2654  __IOM uint32_t DSCSR;
2655 } CoreDebug_Type;
2656 
2657 /* Debug Halting Control and Status Register Definitions */
2658 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
2659 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
2661 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
2662 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
2664 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
2665 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
2667 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
2668 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
2670 #define CoreDebug_DHCSR_S_FPD_Pos 23U
2671 #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos)
2673 #define CoreDebug_DHCSR_S_SUIDE_Pos 22U
2674 #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
2676 #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U
2677 #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
2679 #define CoreDebug_DHCSR_S_SDE_Pos 20U
2680 #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos)
2682 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
2683 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
2685 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
2686 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
2688 #define CoreDebug_DHCSR_S_HALT_Pos 17U
2689 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
2691 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
2692 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
2694 #define CoreDebug_DHCSR_C_PMOV_Pos 6U
2695 #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
2697 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
2698 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
2700 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
2701 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
2703 #define CoreDebug_DHCSR_C_STEP_Pos 2U
2704 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
2706 #define CoreDebug_DHCSR_C_HALT_Pos 1U
2707 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
2709 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
2710 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
2712 /* Debug Core Register Selector Register Definitions */
2713 #define CoreDebug_DCRSR_REGWnR_Pos 16U
2714 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
2716 #define CoreDebug_DCRSR_REGSEL_Pos 0U
2717 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
2719 /* Debug Exception and Monitor Control Register Definitions */
2720 #define CoreDebug_DEMCR_TRCENA_Pos 24U
2721 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
2723 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
2724 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
2726 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
2727 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
2729 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
2730 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
2732 #define CoreDebug_DEMCR_MON_EN_Pos 16U
2733 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
2735 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
2736 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
2738 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
2739 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
2741 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
2742 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
2744 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
2745 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
2747 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
2748 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
2750 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
2751 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
2753 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
2754 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
2756 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
2757 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
2759 /* Debug Set Clear Exception and Monitor Control Register Definitions */
2760 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U
2761 #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
2763 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U
2764 #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
2766 #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U
2767 #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
2769 #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U
2770 #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
2772 /* Debug Authentication Control Register Definitions */
2773 #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U
2774 #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
2776 #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U
2777 #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
2779 #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U
2780 #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
2782 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
2783 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
2785 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
2786 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
2788 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
2789 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
2791 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
2792 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
2794 /* Debug Security Control and Status Register Definitions */
2795 #define CoreDebug_DSCSR_CDS_Pos 16U
2796 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
2798 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
2799 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
2801 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
2802 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
2804 
2817 typedef struct
2818 {
2819  __IOM uint32_t DHCSR;
2820  __OM uint32_t DCRSR;
2821  __IOM uint32_t DCRDR;
2822  __IOM uint32_t DEMCR;
2823  __OM uint32_t DSCEMCR;
2824  __IOM uint32_t DAUTHCTRL;
2825  __IOM uint32_t DSCSR;
2826 } DCB_Type;
2827 
2828 /* DHCSR, Debug Halting Control and Status Register Definitions */
2829 #define DCB_DHCSR_DBGKEY_Pos 16U
2830 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
2832 #define DCB_DHCSR_S_RESTART_ST_Pos 26U
2833 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
2835 #define DCB_DHCSR_S_RESET_ST_Pos 25U
2836 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
2838 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U
2839 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
2841 #define DCB_DHCSR_S_FPD_Pos 23U
2842 #define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)
2844 #define DCB_DHCSR_S_SUIDE_Pos 22U
2845 #define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
2847 #define DCB_DHCSR_S_NSUIDE_Pos 21U
2848 #define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
2850 #define DCB_DHCSR_S_SDE_Pos 20U
2851 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
2853 #define DCB_DHCSR_S_LOCKUP_Pos 19U
2854 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
2856 #define DCB_DHCSR_S_SLEEP_Pos 18U
2857 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
2859 #define DCB_DHCSR_S_HALT_Pos 17U
2860 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
2862 #define DCB_DHCSR_S_REGRDY_Pos 16U
2863 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
2865 #define DCB_DHCSR_C_PMOV_Pos 6U
2866 #define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)
2868 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U
2869 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
2871 #define DCB_DHCSR_C_MASKINTS_Pos 3U
2872 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
2874 #define DCB_DHCSR_C_STEP_Pos 2U
2875 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
2877 #define DCB_DHCSR_C_HALT_Pos 1U
2878 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
2880 #define DCB_DHCSR_C_DEBUGEN_Pos 0U
2881 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
2883 /* DCRSR, Debug Core Register Select Register Definitions */
2884 #define DCB_DCRSR_REGWnR_Pos 16U
2885 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
2887 #define DCB_DCRSR_REGSEL_Pos 0U
2888 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
2890 /* DCRDR, Debug Core Register Data Register Definitions */
2891 #define DCB_DCRDR_DBGTMP_Pos 0U
2892 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
2894 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
2895 #define DCB_DEMCR_TRCENA_Pos 24U
2896 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
2898 #define DCB_DEMCR_MONPRKEY_Pos 23U
2899 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
2901 #define DCB_DEMCR_UMON_EN_Pos 21U
2902 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
2904 #define DCB_DEMCR_SDME_Pos 20U
2905 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
2907 #define DCB_DEMCR_MON_REQ_Pos 19U
2908 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
2910 #define DCB_DEMCR_MON_STEP_Pos 18U
2911 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
2913 #define DCB_DEMCR_MON_PEND_Pos 17U
2914 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
2916 #define DCB_DEMCR_MON_EN_Pos 16U
2917 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
2919 #define DCB_DEMCR_VC_SFERR_Pos 11U
2920 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
2922 #define DCB_DEMCR_VC_HARDERR_Pos 10U
2923 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
2925 #define DCB_DEMCR_VC_INTERR_Pos 9U
2926 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
2928 #define DCB_DEMCR_VC_BUSERR_Pos 8U
2929 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
2931 #define DCB_DEMCR_VC_STATERR_Pos 7U
2932 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
2934 #define DCB_DEMCR_VC_CHKERR_Pos 6U
2935 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
2937 #define DCB_DEMCR_VC_NOCPERR_Pos 5U
2938 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
2940 #define DCB_DEMCR_VC_MMERR_Pos 4U
2941 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
2943 #define DCB_DEMCR_VC_CORERESET_Pos 0U
2944 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
2946 /* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
2947 #define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U
2948 #define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
2950 #define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U
2951 #define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
2953 #define DCB_DSCEMCR_SET_MON_REQ_Pos 3U
2954 #define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
2956 #define DCB_DSCEMCR_SET_MON_PEND_Pos 1U
2957 #define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
2959 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
2960 #define DCB_DAUTHCTRL_UIDEN_Pos 10U
2961 #define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
2963 #define DCB_DAUTHCTRL_UIDAPEN_Pos 9U
2964 #define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
2966 #define DCB_DAUTHCTRL_FSDMA_Pos 8U
2967 #define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
2969 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
2970 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
2972 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
2973 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
2975 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
2976 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
2978 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
2979 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
2981 /* DSCSR, Debug Security Control and Status Register Definitions */
2982 #define DCB_DSCSR_CDSKEY_Pos 17U
2983 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
2985 #define DCB_DSCSR_CDS_Pos 16U
2986 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
2988 #define DCB_DSCSR_SBRSEL_Pos 1U
2989 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
2991 #define DCB_DSCSR_SBRSELEN_Pos 0U
2992 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
2994 
3008 typedef struct
3009 {
3010  __OM uint32_t DLAR;
3011  __IM uint32_t DLSR;
3012  __IM uint32_t DAUTHSTATUS;
3013  __IM uint32_t DDEVARCH;
3014  __IM uint32_t DDEVTYPE;
3015 } DIB_Type;
3016 
3017 /* DLAR, SCS Software Lock Access Register Definitions */
3018 #define DIB_DLAR_KEY_Pos 0U
3019 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
3021 /* DLSR, SCS Software Lock Status Register Definitions */
3022 #define DIB_DLSR_nTT_Pos 2U
3023 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
3025 #define DIB_DLSR_SLK_Pos 1U
3026 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
3028 #define DIB_DLSR_SLI_Pos 0U
3029 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
3031 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
3032 #define DIB_DAUTHSTATUS_SUNID_Pos 22U
3033 #define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
3035 #define DIB_DAUTHSTATUS_SUID_Pos 20U
3036 #define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
3038 #define DIB_DAUTHSTATUS_NSUNID_Pos 18U
3039 #define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
3041 #define DIB_DAUTHSTATUS_NSUID_Pos 16U
3042 #define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
3044 #define DIB_DAUTHSTATUS_SNID_Pos 6U
3045 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
3047 #define DIB_DAUTHSTATUS_SID_Pos 4U
3048 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
3050 #define DIB_DAUTHSTATUS_NSNID_Pos 2U
3051 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
3053 #define DIB_DAUTHSTATUS_NSID_Pos 0U
3054 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
3056 /* DDEVARCH, SCS Device Architecture Register Definitions */
3057 #define DIB_DDEVARCH_ARCHITECT_Pos 21U
3058 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
3060 #define DIB_DDEVARCH_PRESENT_Pos 20U
3061 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
3063 #define DIB_DDEVARCH_REVISION_Pos 16U
3064 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
3066 #define DIB_DDEVARCH_ARCHVER_Pos 12U
3067 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
3069 #define DIB_DDEVARCH_ARCHPART_Pos 0U
3070 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
3072 /* DDEVTYPE, SCS Device Type Register Definitions */
3073 #define DIB_DDEVTYPE_SUB_Pos 4U
3074 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
3076 #define DIB_DDEVTYPE_MAJOR_Pos 0U
3077 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
3080 
3096 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
3097 
3104 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
3105 
3116 /* Memory mapping of Core Hardware */
3117  #define SCS_BASE (0xE000E000UL)
3118  #define ITM_BASE (0xE0000000UL)
3119  #define DWT_BASE (0xE0001000UL)
3120  #define TPI_BASE (0xE0040000UL)
3121  #define CoreDebug_BASE (0xE000EDF0UL)
3122  #define DCB_BASE (0xE000EDF0UL)
3123  #define DIB_BASE (0xE000EFB0UL)
3124  #define SysTick_BASE (SCS_BASE + 0x0010UL)
3125  #define NVIC_BASE (SCS_BASE + 0x0100UL)
3126  #define SCB_BASE (SCS_BASE + 0x0D00UL)
3128  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
3129  #define SCB ((SCB_Type *) SCB_BASE )
3130  #define SysTick ((SysTick_Type *) SysTick_BASE )
3131  #define NVIC ((NVIC_Type *) NVIC_BASE )
3132  #define ITM ((ITM_Type *) ITM_BASE )
3133  #define DWT ((DWT_Type *) DWT_BASE )
3134  #define TPI ((TPI_Type *) TPI_BASE )
3135  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
3136  #define DCB ((DCB_Type *) DCB_BASE )
3137  #define DIB ((DIB_Type *) DIB_BASE )
3139  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3140  #define MPU_BASE (SCS_BASE + 0x0D90UL)
3141  #define MPU ((MPU_Type *) MPU_BASE )
3142  #endif
3143 
3144  #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
3145  #define PMU_BASE (0xE0003000UL)
3146  #define PMU ((PMU_Type *) PMU_BASE )
3147  #endif
3148 
3149  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3150  #define SAU_BASE_CMSIS (SCS_BASE + 0x0DD0UL)
3151  #define SAU ((SAU_Type *) SAU_BASE_CMSIS )
3152  #endif
3153 
3154  #define FPU_BASE (SCS_BASE + 0x0F30UL)
3155  #define FPU ((FPU_Type *) FPU_BASE )
3157 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3158  #define SCS_BASE_NS (0xE002E000UL)
3159  #define CoreDebug_BASE_NS (0xE002EDF0UL)
3160  #define DCB_BASE_NS (0xE002EDF0UL)
3161  #define DIB_BASE_NS (0xE002EFB0UL)
3162  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
3163  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
3164  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
3166  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
3167  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
3168  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
3169  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
3170  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
3171  #define DCB_NS ((DCB_Type *) DCB_BASE_NS )
3172  #define DIB_NS ((DIB_Type *) DIB_BASE_NS )
3174  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3175  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
3176  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
3177  #endif
3178 
3179  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
3180  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
3182 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3183 
3192 #define ID_ADR (ID_AFR)
3193 
3196 /*******************************************************************************
3197  * Hardware Abstraction Layer
3198  Core Function Interface contains:
3199  - Core NVIC Functions
3200  - Core SysTick Functions
3201  - Core Debug Functions
3202  - Core Register Access Functions
3203  ******************************************************************************/
3204 
3210 /* ########################## NVIC functions #################################### */
3218 #ifdef CMSIS_NVIC_VIRTUAL
3219  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
3220  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
3221  #endif
3222  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
3223 #else
3224  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
3225  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
3226  #define NVIC_EnableIRQ __NVIC_EnableIRQ
3227  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
3228  #define NVIC_DisableIRQ __NVIC_DisableIRQ
3229  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
3230  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
3231  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
3232  #define NVIC_GetActive __NVIC_GetActive
3233  #define NVIC_SetPriority __NVIC_SetPriority
3234  #define NVIC_GetPriority __NVIC_GetPriority
3235  #define NVIC_SystemReset __NVIC_SystemReset
3236 #endif /* CMSIS_NVIC_VIRTUAL */
3237 
3238 #ifdef CMSIS_VECTAB_VIRTUAL
3239  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
3240  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
3241  #endif
3242  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
3243 #else
3244  #define NVIC_SetVector __NVIC_SetVector
3245  #define NVIC_GetVector __NVIC_GetVector
3246 #endif /* (CMSIS_VECTAB_VIRTUAL) */
3247 
3248 #define NVIC_USER_IRQ_OFFSET 16
3249 
3250 
3251 /* Special LR values for Secure/Non-Secure call handling and exception handling */
3252 
3253 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
3254 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
3255 
3256 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
3257 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
3258 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
3259 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
3260 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
3261 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
3262 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
3263 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
3264 
3265 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
3266 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
3267 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
3268 #else
3269 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
3270 #endif
3271 
3272 
3282 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
3283 {
3284  uint32_t reg_value;
3285  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3286 
3287  reg_value = SCB->AIRCR; /* read old register configuration */
3288  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
3289  reg_value = (reg_value |
3290  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3291  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
3292  SCB->AIRCR = reg_value;
3293 }
3294 
3295 
3301 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
3302 {
3303  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
3304 }
3305 
3306 
3313 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
3314 {
3315  if ((int32_t)(IRQn) >= 0)
3316  {
3317  __COMPILER_BARRIER();
3318  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3319  __COMPILER_BARRIER();
3320  }
3321 }
3322 
3323 
3332 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
3333 {
3334  if ((int32_t)(IRQn) >= 0)
3335  {
3336  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3337  }
3338  else
3339  {
3340  return(0U);
3341  }
3342 }
3343 
3344 
3351 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
3352 {
3353  if ((int32_t)(IRQn) >= 0)
3354  {
3355  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3356  __DSB();
3357  __ISB();
3358  }
3359 }
3360 
3361 
3370 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
3371 {
3372  if ((int32_t)(IRQn) >= 0)
3373  {
3374  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3375  }
3376  else
3377  {
3378  return(0U);
3379  }
3380 }
3381 
3382 
3389 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
3390 {
3391  if ((int32_t)(IRQn) >= 0)
3392  {
3393  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3394  }
3395 }
3396 
3397 
3404 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
3405 {
3406  if ((int32_t)(IRQn) >= 0)
3407  {
3408  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3409  }
3410 }
3411 
3412 
3421 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
3422 {
3423  if ((int32_t)(IRQn) >= 0)
3424  {
3425  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3426  }
3427  else
3428  {
3429  return(0U);
3430  }
3431 }
3432 
3433 
3434 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3435 
3443 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
3444 {
3445  if ((int32_t)(IRQn) >= 0)
3446  {
3447  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3448  }
3449  else
3450  {
3451  return(0U);
3452  }
3453 }
3454 
3455 
3464 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
3465 {
3466  if ((int32_t)(IRQn) >= 0)
3467  {
3468  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
3469  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3470  }
3471  else
3472  {
3473  return(0U);
3474  }
3475 }
3476 
3477 
3486 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
3487 {
3488  if ((int32_t)(IRQn) >= 0)
3489  {
3490  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
3491  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3492  }
3493  else
3494  {
3495  return(0U);
3496  }
3497 }
3498 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3499 
3500 
3510 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
3511 {
3512  if ((int32_t)(IRQn) >= 0)
3513  {
3514  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3515  }
3516  else
3517  {
3518  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3519  }
3520 }
3521 
3522 
3532 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
3533 {
3534 
3535  if ((int32_t)(IRQn) >= 0)
3536  {
3537  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
3538  }
3539  else
3540  {
3541  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
3542  }
3543 }
3544 
3545 
3557 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
3558 {
3559  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3560  uint32_t PreemptPriorityBits;
3561  uint32_t SubPriorityBits;
3562 
3563  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
3564  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
3565 
3566  return (
3567  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
3568  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
3569  );
3570 }
3571 
3572 
3584 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
3585 {
3586  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3587  uint32_t PreemptPriorityBits;
3588  uint32_t SubPriorityBits;
3589 
3590  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
3591  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
3592 
3593  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
3594  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
3595 }
3596 
3597 
3607 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
3608 {
3609  uint32_t *vectors = (uint32_t *)SCB->VTOR;
3610  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
3611  __DSB();
3612 }
3613 
3614 
3623 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
3624 {
3625  uint32_t *vectors = (uint32_t *)SCB->VTOR;
3626  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
3627 }
3628 
3629 
3634 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
3635 {
3636  __DSB(); /* Ensure all outstanding memory accesses included
3637  buffered write are completed before reset */
3638  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3639  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
3640  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
3641  __DSB(); /* Ensure completion of memory access */
3642 
3643  for(;;) /* wait until reset */
3644  {
3645  __NOP();
3646  }
3647 }
3648 
3649 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3650 
3659 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
3660 {
3661  uint32_t reg_value;
3662  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
3663 
3664  reg_value = SCB_NS->AIRCR; /* read old register configuration */
3665  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
3666  reg_value = (reg_value |
3667  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
3668  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
3669  SCB_NS->AIRCR = reg_value;
3670 }
3671 
3672 
3678 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
3679 {
3680  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
3681 }
3682 
3683 
3690 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
3691 {
3692  if ((int32_t)(IRQn) >= 0)
3693  {
3694  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3695  }
3696 }
3697 
3698 
3707 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
3708 {
3709  if ((int32_t)(IRQn) >= 0)
3710  {
3711  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3712  }
3713  else
3714  {
3715  return(0U);
3716  }
3717 }
3718 
3719 
3726 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
3727 {
3728  if ((int32_t)(IRQn) >= 0)
3729  {
3730  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3731  }
3732 }
3733 
3734 
3743 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
3744 {
3745  if ((int32_t)(IRQn) >= 0)
3746  {
3747  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3748  }
3749  else
3750  {
3751  return(0U);
3752  }
3753 }
3754 
3755 
3762 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
3763 {
3764  if ((int32_t)(IRQn) >= 0)
3765  {
3766  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3767  }
3768 }
3769 
3770 
3777 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
3778 {
3779  if ((int32_t)(IRQn) >= 0)
3780  {
3781  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
3782  }
3783 }
3784 
3785 
3794 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
3795 {
3796  if ((int32_t)(IRQn) >= 0)
3797  {
3798  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
3799  }
3800  else
3801  {
3802  return(0U);
3803  }
3804 }
3805 
3806 
3816 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
3817 {
3818  if ((int32_t)(IRQn) >= 0)
3819  {
3820  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3821  }
3822  else
3823  {
3824  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
3825  }
3826 }
3827 
3828 
3837 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
3838 {
3839 
3840  if ((int32_t)(IRQn) >= 0)
3841  {
3842  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
3843  }
3844  else
3845  {
3846  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
3847  }
3848 }
3849 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
3850 
3853 /* ########################## MPU functions #################################### */
3854 
3855 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
3856 
3857 #include "mpu_armv8.h"
3858 
3859 #endif
3860 
3861 /* ########################## PMU functions and events #################################### */
3862 
3863 #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
3864 
3865 #include "pmu_armv8.h"
3866 
3867 #endif
3868 
3869 /* ########################## FPU functions #################################### */
3885 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
3886 {
3887  uint32_t mvfr0;
3888 
3889  mvfr0 = FPU->MVFR0;
3890  if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
3891  {
3892  return 2U; /* Double + Single precision FPU */
3893  }
3894  else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
3895  {
3896  return 1U; /* Single precision FPU */
3897  }
3898  else
3899  {
3900  return 0U; /* No FPU */
3901  }
3902 }
3903 
3904 
3907 /* ########################## MVE functions #################################### */
3923 __STATIC_INLINE uint32_t SCB_GetMVEType(void)
3924 {
3925  const uint32_t mvfr1 = FPU->MVFR1;
3926  if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
3927  {
3928  return 2U;
3929  }
3930  else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
3931  {
3932  return 1U;
3933  }
3934  else
3935  {
3936  return 0U;
3937  }
3938 }
3939 
3940 
3944 /* ########################## Cache functions #################################### */
3945 
3946 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
3947  (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
3948 #include "cachel1_armv7.h"
3949 #endif
3950 
3951 
3952 /* ########################## SAU functions #################################### */
3960 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3961 
3966 __STATIC_INLINE void TZ_SAU_Enable(void)
3967 {
3968  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
3969 }
3970 
3971 
3972 
3977 __STATIC_INLINE void TZ_SAU_Disable(void)
3978 {
3979  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
3980 }
3981 
3982 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3983 
3989 /* ################################## Debug Control function ############################################ */
4003 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
4004 {
4005  __DSB();
4006  __ISB();
4007  DCB->DAUTHCTRL = value;
4008  __DSB();
4009  __ISB();
4010 }
4011 
4012 
4018 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
4019 {
4020  return (DCB->DAUTHCTRL);
4021 }
4022 
4023 
4024 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4025 
4030 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
4031 {
4032  __DSB();
4033  __ISB();
4034  DCB_NS->DAUTHCTRL = value;
4035  __DSB();
4036  __ISB();
4037 }
4038 
4039 
4045 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
4046 {
4047  return (DCB_NS->DAUTHCTRL);
4048 }
4049 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4050 
4056 /* ################################## Debug Identification function ############################################ */
4070 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
4071 {
4072  return (DIB->DAUTHSTATUS);
4073 }
4074 
4075 
4076 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4077 
4082 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
4083 {
4084  return (DIB_NS->DAUTHSTATUS);
4085 }
4086 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4087 
4093 /* ################################## SysTick function ############################################ */
4101 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
4102 
4114 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
4115 {
4116  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
4117  {
4118  return (1UL); /* Reload value impossible */
4119  }
4120 
4121  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
4122  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
4123  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
4124  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
4125  SysTick_CTRL_TICKINT_Msk |
4126  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
4127  return (0UL); /* Function successful */
4128 }
4129 
4130 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
4131 
4143 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
4144 {
4145  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
4146  {
4147  return (1UL); /* Reload value impossible */
4148  }
4149 
4150  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
4151  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
4152  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
4153  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
4154  SysTick_CTRL_TICKINT_Msk |
4155  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
4156  return (0UL); /* Function successful */
4157 }
4158 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
4159 
4160 #endif
4161 
4166 /* ##################################### Debug In/Output function ########################################### */
4174 extern volatile int32_t ITM_RxBuffer;
4175 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
4186 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
4187 {
4188  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
4189  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
4190  {
4191  while (ITM->PORT[0U].u32 == 0UL)
4192  {
4193  __NOP();
4194  }
4195  ITM->PORT[0U].u8 = (uint8_t)ch;
4196  }
4197  return (ch);
4198 }
4199 
4200 
4207 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
4208 {
4209  int32_t ch = -1; /* no character available */
4210 
4211  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
4212  {
4213  ch = ITM_RxBuffer;
4214  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
4215  }
4216 
4217  return (ch);
4218 }
4219 
4220 
4227 __STATIC_INLINE int32_t ITM_CheckChar (void)
4228 {
4229 
4230  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
4231  {
4232  return (0); /* no character available */
4233  }
4234  else
4235  {
4236  return (1); /* character available */
4237  }
4238 }
4239 
4245 #ifdef __cplusplus
4246 }
4247 #endif
4248 
4249 #endif /* __CORE_ARMV81MML_H_DEPENDANT */
4250 
4251 #endif /* __CMSIS_GENERIC */
__OM
#define __OM
Definition: core_armv81mml.h:317
DWT_Type::CPICNT
__IOM uint32_t CPICNT
Definition: core_armv81mml.h:1206
DWT_Type::COMP11
__IOM uint32_t COMP11
Definition: core_armv81mml.h:1256
ITM_Type::PID3
__IM uint32_t PID3
Definition: core_armv81mml.h:1130
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv81mml.h:2505
SCB_Type::DCCISW
__OM uint32_t DCCISW
Definition: core_armv81mml.h:581
ITM_Type::LSR
__IM uint32_t LSR
Definition: core_armv81mml.h:1118
ITM
#define ITM
Definition: core_armv81mml.h:3132
SCB_Type::SFAR
__IOM uint32_t SFAR
Definition: core_armv81mml.h:563
SCB_Type::DFSR
__IOM uint32_t DFSR
Definition: core_armv81mml.h:546
ITM_Type::u8
__OM uint8_t u8
Definition: core_armv81mml.h:1105
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv81mml.h:1202
DIB_Type
Structure type to access the Debug Identification Block Registers (DIB).
Definition: core_armv81mml.h:3008
DWT_Type::COMP6
__IOM uint32_t COMP6
Definition: core_armv81mml.h:1236
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_armv81mml.h:662
mpu_armv8.h
SCB_Type::AFSR
__IOM uint32_t AFSR
Definition: core_armv81mml.h:549
DWT_Type::FUNCTION7
__IOM uint32_t FUNCTION7
Definition: core_armv81mml.h:1242
ITM_Type::PID5
__IM uint32_t PID5
Definition: core_armv81mml.h:1124
DCB
#define DCB
Definition: core_armv81mml.h:3136
SCB_Type::DCCSW
__OM uint32_t DCCSW
Definition: core_armv81mml.h:579
SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Definition: core_armv81mml.h:580
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv81mml.h:3332
SysTick_Type::CTRL
__IOM uint32_t CTRL
Definition: core_armv81mml.h:1051
DCB_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_armv81mml.h:2819
DWT_Type::COMP2
__IOM uint32_t COMP2
Definition: core_armv81mml.h:1220
CoreDebug_Type::DHCSR
__IOM uint32_t DHCSR
Definition: core_armv81mml.h:2648
DWT_Type::COMP5
__IOM uint32_t COMP5
Definition: core_armv81mml.h:1232
SCB_Type::DCISW
__OM uint32_t DCISW
Definition: core_armv81mml.h:576
TPI_Type::FFSR
__IM uint32_t FFSR
Definition: core_armv81mml.h:1397
__NOP
#define __NOP()
No Operation.
Definition: cmsis_gcc.h:234
SCB_Type::RFSR
__IOM uint32_t RFSR
Definition: core_armv81mml.h:566
TPI_Type::LSR
__IM uint32_t LSR
Definition: core_armv81mml.h:1402
TPI_Type::SSPSR
__IM uint32_t SSPSR
Definition: core_armv81mml.h:1390
DCB_Type::DSCEMCR
__OM uint32_t DSCEMCR
Definition: core_armv81mml.h:2823
FPU
#define FPU
Definition: core_armv81mml.h:3155
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_armv81mml.h:647
DWT_Type::CYCCNT
__IOM uint32_t CYCCNT
Definition: core_armv81mml.h:1205
DWT_Type::FUNCTION8
__IOM uint32_t FUNCTION8
Definition: core_armv81mml.h:1246
SysTick_Type::CALIB
__IM uint32_t CALIB
Definition: core_armv81mml.h:1054
SysTick
#define SysTick
Definition: core_armv81mml.h:3130
SysTick_Type::VAL
__IOM uint32_t VAL
Definition: core_armv81mml.h:1053
DWT_Type::FUNCTION12
__IOM uint32_t FUNCTION12
Definition: core_armv81mml.h:1262
SCB_Type::CPUID
__IM uint32_t CPUID
Definition: core_armv81mml.h:536
SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Definition: core_armv81mml.h:572
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_armv81mml.h:4175
DWT_Type::FUNCTION4
__IOM uint32_t FUNCTION4
Definition: core_armv81mml.h:1230
DWT_Type::COMP3
__IOM uint32_t COMP3
Definition: core_armv81mml.h:1224
ITM_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: core_armv81mml.h:1122
FPU_MVFR1_MVE_Pos
#define FPU_MVFR1_MVE_Pos
Definition: core_armv81mml.h:2620
DIB_Type::DAUTHSTATUS
__IM uint32_t DAUTHSTATUS
Definition: core_armv81mml.h:3012
__IOM
#define __IOM
Definition: core_armv81mml.h:318
SCB_Type::CLIDR
__IM uint32_t CLIDR
Definition: core_armv81mml.h:555
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv81mml.h:3623
FPU_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_armv81mml.h:2513
TPI_Type::TYPE
__IM uint32_t TYPE
Definition: core_armv81mml.h:1404
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv81mml.h:3313
ITM_Type::CID0
__IM uint32_t CID0
Definition: core_armv81mml.h:1131
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv81mml.h:3370
IRQn_Type
enum IRQn IRQn_Type
SCB_Type::ID_DFR
__IM uint32_t ID_DFR
Definition: core_armv81mml.h:551
ITM_Type::PID0
__IM uint32_t PID0
Definition: core_armv81mml.h:1127
DWT_Type::FUNCTION1
__IOM uint32_t FUNCTION1
Definition: core_armv81mml.h:1218
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv81mml.h:4207
SCB_Type::ICSR
__IOM uint32_t ICSR
Definition: core_armv81mml.h:537
SCB_Type::CFSR
__IOM uint32_t CFSR
Definition: core_armv81mml.h:544
SysTick_Type::LOAD
__IOM uint32_t LOAD
Definition: core_armv81mml.h:1052
ITM_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: core_armv81mml.h:1120
FPU_MVFR0_FPDP_Msk
#define FPU_MVFR0_FPDP_Msk
Definition: core_armv81mml.h:2602
TPI_Type::CSPSR
__IOM uint32_t CSPSR
Definition: core_armv81mml.h:1391
DCB_SetAuthCtrl
__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
Set Debug Authentication Control Register.
Definition: core_armv81mml.h:4003
DIB_Type::DLSR
__IM uint32_t DLSR
Definition: core_armv81mml.h:3011
SCB_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_armv81mml.h:569
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv81mml.h:3389
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv81mml.h:390
CoreDebug_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_armv81mml.h:2651
CONTROL_Type::w
uint32_t w
Definition: core_armv81mml.h:469
ITM_Type::TPR
__IOM uint32_t TPR
Definition: core_armv81mml.h:1112
CoreDebug_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_armv81mml.h:2650
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv81mml.h:1388
SysTick_IRQn
Definition: cc27xx.h:24
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv81mml.h:4227
FPU_Type::FPCCR
__IOM uint32_t FPCCR
Definition: core_armv81mml.h:2508
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv81mml.h:3885
SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Definition: core_armv81mml.h:575
FPU_Type::FPCAR
__IOM uint32_t FPCAR
Definition: core_armv81mml.h:2509
DCB_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_armv81mml.h:2820
SCB_Type::SCR
__IOM uint32_t SCR
Definition: core_armv81mml.h:540
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv81mml.h:3584
SCB_GetMVEType
__STATIC_INLINE uint32_t SCB_GetMVEType(void)
get MVE type
Definition: core_armv81mml.h:3923
SCB_Type::BFAR
__IOM uint32_t BFAR
Definition: core_armv81mml.h:548
DWT_Type::COMP14
__IOM uint32_t COMP14
Definition: core_armv81mml.h:1268
NVIC
#define NVIC
Definition: core_armv81mml.h:3131
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:275
SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Definition: core_armv81mml.h:577
DWT_Type::PCSR
__IM uint32_t PCSR
Definition: core_armv81mml.h:1211
SCnSCB_Type::ICTR
__IM uint32_t ICTR
Definition: core_armv81mml.h:1027
CoreDebug_Type::DSCSR
__IOM uint32_t DSCSR
Definition: core_armv81mml.h:2654
DWT_Type::FUNCTION10
__IOM uint32_t FUNCTION10
Definition: core_armv81mml.h:1254
cmsis_version.h
CMSIS Core(M) Version definitions.
CoreDebug_Type::DCRSR
__OM uint32_t DCRSR
Definition: core_armv81mml.h:2649
xPSR_Type::w
uint32_t w
Definition: core_armv81mml.h:424
ITM_Type::CID2
__IM uint32_t CID2
Definition: core_armv81mml.h:1133
DCB_Type::DAUTHCTRL
__IOM uint32_t DAUTHCTRL
Definition: core_armv81mml.h:2824
TPI_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition: core_armv81mml.h:1405
FPU_MVFR0_FPSP_Msk
#define FPU_MVFR0_FPSP_Msk
Definition: core_armv81mml.h:2605
ITM_Type::u16
__OM uint16_t u16
Definition: core_armv81mml.h:1106
SCnSCB_Type::ACTLR
__IOM uint32_t ACTLR
Definition: core_armv81mml.h:1028
SCnSCB_Type::CPPWR
__IOM uint32_t CPPWR
Definition: core_armv81mml.h:1029
DWT_Type::FUNCTION3
__IOM uint32_t FUNCTION3
Definition: core_armv81mml.h:1226
CoreDebug_Type
Definition: core_armv81mml.h:2646
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv81mml.h:534
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_armv81mml.h:1177
DIB_Type::DLAR
__OM uint32_t DLAR
Definition: core_armv81mml.h:3010
ITM_Type::TCR
__IOM uint32_t TCR
Definition: core_armv81mml.h:1114
SCB
#define SCB
Definition: core_armv81mml.h:3129
DWT_Type::COMP7
__IOM uint32_t COMP7
Definition: core_armv81mml.h:1240
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv81mml.h:1101
ITM_Type::PID7
__IM uint32_t PID7
Definition: core_armv81mml.h:1126
IPSR_Type::w
uint32_t w
Definition: core_armv81mml.h:397
DWT_Type::COMP4
__IOM uint32_t COMP4
Definition: core_armv81mml.h:1228
DWT_Type::FUNCTION14
__IOM uint32_t FUNCTION14
Definition: core_armv81mml.h:1270
DWT_Type::COMP13
__IOM uint32_t COMP13
Definition: core_armv81mml.h:1264
CoreDebug_Type::DSCEMCR
__OM uint32_t DSCEMCR
Definition: core_armv81mml.h:2652
SCB_Type::CCR
__IOM uint32_t CCR
Definition: core_armv81mml.h:541
ITM_Type::PID4
__IM uint32_t PID4
Definition: core_armv81mml.h:1123
FPU_Type::FPDSCR
__IOM uint32_t FPDSCR
Definition: core_armv81mml.h:2510
ITM_Type::TER
__IOM uint32_t TER
Definition: core_armv81mml.h:1110
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv81mml.h:3607
SCB_Type::MVFR2
__IM uint32_t MVFR2
Definition: core_armv81mml.h:570
SCB_Type::MMFAR
__IOM uint32_t MMFAR
Definition: core_armv81mml.h:547
SCB_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_armv81mml.h:568
ITM_Type::LAR
__OM uint32_t LAR
Definition: core_armv81mml.h:1117
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv81mml.h:3301
APSR_Type::w
uint32_t w
Definition: core_armv81mml.h:364
DIB_Type::DDEVARCH
__IM uint32_t DDEVARCH
Definition: core_armv81mml.h:3013
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv81mml.h:3351
SCB_Type::CTR
__IM uint32_t CTR
Definition: core_armv81mml.h:556
TPI_Type::LAR
__OM uint32_t LAR
Definition: core_armv81mml.h:1401
SCB_Type::NSACR
__IOM uint32_t NSACR
Definition: core_armv81mml.h:560
DWT_Type::FUNCTION13
__IOM uint32_t FUNCTION13
Definition: core_armv81mml.h:1266
SCB_Type::SHCSR
__IOM uint32_t SHCSR
Definition: core_armv81mml.h:543
SCB_Type::HFSR
__IOM uint32_t HFSR
Definition: core_armv81mml.h:545
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_armv81mml.h:661
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv81mml.h:1024
DWT_Type::DEVARCH
__IM uint32_t DEVARCH
Definition: core_armv81mml.h:1278
SCB_Type::SFSR
__IOM uint32_t SFSR
Definition: core_armv81mml.h:562
SCB_Type::CPACR
__IOM uint32_t CPACR
Definition: core_armv81mml.h:559
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv81mml.h:498
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv81mml.h:1049
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_armv81mml.h:646
ITM_Type::PID1
__IM uint32_t PID1
Definition: core_armv81mml.h:1128
DWT_Type::COMP9
__IOM uint32_t COMP9
Definition: core_armv81mml.h:1248
ITM_Type::u32
__OM uint32_t u32
Definition: core_armv81mml.h:1107
DWT_Type::COMP8
__IOM uint32_t COMP8
Definition: core_armv81mml.h:1244
IRQn
IRQn
Definition: cc27xx.h:13
DWT_Type::FOLDCNT
__IOM uint32_t FOLDCNT
Definition: core_armv81mml.h:1210
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv81mml.h:3421
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition: cmsis_gcc.h:117
DWT_Type::FUNCTION11
__IOM uint32_t FUNCTION11
Definition: core_armv81mml.h:1258
SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Definition: core_armv81mml.h:557
DIB_GetAuthStatus
__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
Get Debug Authentication Status Register.
Definition: core_armv81mml.h:4070
ITM_Type::PID6
__IM uint32_t PID6
Definition: core_armv81mml.h:1125
FPU_MVFR1_MVE_Msk
#define FPU_MVFR1_MVE_Msk
Definition: core_armv81mml.h:2621
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_armv81mml.h:3233
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv81mml.h:3510
DIB
#define DIB
Definition: core_armv81mml.h:3137
SCB_Type::CSSELR
__IOM uint32_t CSSELR
Definition: core_armv81mml.h:558
TPI_Type::PSCR
__IOM uint32_t PSCR
Definition: core_armv81mml.h:1399
DCB_Type::DCRDR
__IOM uint32_t DCRDR
Definition: core_armv81mml.h:2821
DWT_Type::COMP0
__IOM uint32_t COMP0
Definition: core_armv81mml.h:1212
ITM_Type::PID2
__IM uint32_t PID2
Definition: core_armv81mml.h:1129
SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Definition: core_armv81mml.h:574
FPU_Type::MVFR1
__IM uint32_t MVFR1
Definition: core_armv81mml.h:2512
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_armv81mml.h:674
SCB_Type::BPIALL
__OM uint32_t BPIALL
Definition: core_armv81mml.h:582
cmsis_compiler.h
CMSIS compiler generic header file.
DWT_Type::FUNCTION5
__IOM uint32_t FUNCTION5
Definition: core_armv81mml.h:1234
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv81mml.h:351
NVIC_Type::STIR
__OM uint32_t STIR
Definition: core_armv81mml.h:514
CoreDebug_Type::DAUTHCTRL
__IOM uint32_t DAUTHCTRL
Definition: core_armv81mml.h:2653
DWT_Type::FUNCTION15
__IOM uint32_t FUNCTION15
Definition: core_armv81mml.h:1274
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_armv81mml.h:1072
DWT_Type::CTRL
__IOM uint32_t CTRL
Definition: core_armv81mml.h:1204
SCB_Type::STIR
__OM uint32_t STIR
Definition: core_armv81mml.h:565
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv81mml.h:3404
DCB_Type
Structure type to access the Debug Control Block Registers (DCB).
Definition: core_armv81mml.h:2817
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv81mml.h:459
DWT_Type::COMP12
__IOM uint32_t COMP12
Definition: core_armv81mml.h:1260
TPI_Type::SPPR
__IOM uint32_t SPPR
Definition: core_armv81mml.h:1395
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_armv81mml.h:1062
DIB_Type::DDEVTYPE
__IM uint32_t DDEVTYPE
Definition: core_armv81mml.h:3014
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_armv81mml.h:1068
DWT_Type::FUNCTION0
__IOM uint32_t FUNCTION0
Definition: core_armv81mml.h:1214
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_armv81mml.h:3248
FPU_Type::MVFR0
__IM uint32_t MVFR0
Definition: core_armv81mml.h:2511
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_gcc.h:47
pmu_armv8.h
DCB_Type::DEMCR
__IOM uint32_t DEMCR
Definition: core_armv81mml.h:2822
DWT_Type::LSR
__IM uint32_t LSR
Definition: core_armv81mml.h:1276
DWT_Type::SLEEPCNT
__IOM uint32_t SLEEPCNT
Definition: core_armv81mml.h:1208
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv81mml.h:3557
DWT_Type::COMP1
__IOM uint32_t COMP1
Definition: core_armv81mml.h:1216
DWT_Type::FUNCTION9
__IOM uint32_t FUNCTION9
Definition: core_armv81mml.h:1250
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv81mml.h:3634
DWT_Type::COMP10
__IOM uint32_t COMP10
Definition: core_armv81mml.h:1252
__IM
#define __IM
Definition: core_armv81mml.h:316
ITM_Type::CID3
__IM uint32_t CID3
Definition: core_armv81mml.h:1134
DWT_Type::LSUCNT
__IOM uint32_t LSUCNT
Definition: core_armv81mml.h:1209
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv81mml.h:408
DWT_Type::FUNCTION2
__IOM uint32_t FUNCTION2
Definition: core_armv81mml.h:1222
DCB_GetAuthCtrl
__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
Get Debug Authentication Control Register.
Definition: core_armv81mml.h:4018
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:264
DWT_Type::EXCCNT
__IOM uint32_t EXCCNT
Definition: core_armv81mml.h:1207
SCB_Type::ID_AFR
__IM uint32_t ID_AFR
Definition: core_armv81mml.h:552
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv81mml.h:3532
TPI_Type::FFCR
__IOM uint32_t FFCR
Definition: core_armv81mml.h:1398
SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Definition: core_armv81mml.h:578
TPI_Type::ACPR
__IOM uint32_t ACPR
Definition: core_armv81mml.h:1393
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_armv81mml.h:1065
DWT_Type::FUNCTION6
__IOM uint32_t FUNCTION6
Definition: core_armv81mml.h:1238
SCB_Type::VTOR
__IOM uint32_t VTOR
Definition: core_armv81mml.h:538
DWT_Type::COMP15
__IOM uint32_t COMP15
Definition: core_armv81mml.h:1272
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv81mml.h:3282
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_gcc.h:53
DCB_Type::DSCSR
__IOM uint32_t DSCSR
Definition: core_armv81mml.h:2825
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: cc27xx.h:106
ITM_Type::CID1
__IM uint32_t CID1
Definition: core_armv81mml.h:1132
SCB_Type::AIRCR
__IOM uint32_t AIRCR
Definition: core_armv81mml.h:539