Hardware Architecture
=====================

The |DEVICE| Family
-------------------

Arm Cortex-M0+ (Device Core)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^

The device core (CM0+) is designed to run the wireless
protocol stack from the radio layer up to the user
application. By only using one core for the solution, the
|DEVICE| family is optimized for both cost and power.


Flash, RAM, and Peripherals
^^^^^^^^^^^^^^^^^^^^^^^^^^^

Depending on the model, devices in the |DEVICE| family
contain between |FLASH_SIZE_LOW|-|FLASH_SIZE_LOW_PLUS| of
in-system programmable flash memory and
|CC23XX_MIN_RAM_SIZE|-|CC23XX_MAX_RAM_SIZE| of SRAM. See
the table below for a breakdown each device. The |DEVICE|
also hosts a full range of peripherals including UART, I2C,
AES, RNG, temperature and battery monitors, timers,
and 1 SSI.



.. table:: Flash and SRAM size for |DEVICE| devices

    +-------+--------------------+-------------------------+---------------------------+
    |       | |DEVICE_LOW|       | |DEVICE_LOW_PLUS|       | |DEVICE_LOW_PLUS_AUTO|    |
    +=======+====================+=========================+===========================+
    |       |                    |                         |                           |
    | Flash | |FLASH_SIZE_LOW|   |  |FLASH_SIZE_LOW_PLUS|  |  |FLASH_SIZE_LOW_PLUS|    |
    |       |                    |                         |                           |
    +-------+--------------------+-------------------------+---------------------------+
    |       |                    |                         |                           |
    | SRAM  |  |RAM_SIZE_LOW|    |  |RAM_SIZE_LOW_PLUS|    |  |RAM_SIZE_LOW_PLUS|      |
    |       |                    |                         |                           |
    +-------+--------------------+-------------------------+---------------------------+

.. _sec-programming-internal-flash-rom-bootloader:

Programming Internal Flash With the ROM Bootloader
--------------------------------------------------

The |DEVICE| internal flash memory can be programmed using
the bootloader located in device ROM. Both UART and SPI
protocols are supported. See the |TRM| for more details on
the programming protocol and requirements.

.. note:: Because the ROM bootloader uses predefined DIO
    pins for internal flash programming, allocate these
    pins in the board layout. The |TRM| has more details on
    the pins allocated to the bootloader based on the chip
    package type.

Startup Sequence
^^^^^^^^^^^^^^^^

For a complete description of the |DEVICE| reset sequence, see the |TRM|.

.. _sec-resets:

Resets
^^^^^^

Reset on the |DEVICE| may only be done by using hard resets.
From the software, this reset can be accomplished using:

:code:`Power_reset();`

In CCS, select Board Reset (automatic) from the reset menu:

.. figure:: resources/fig-board-reset.png

    Board Reset