.. _sec-debug-interface:

Debug Interfaces
================

The |DEVICEAND| platform supports serial wire debug (:term:`SWD`) debug
interface. SWD is an ARM bi-directional 2-wire protocol that communicates with the JTAG test access port controller, and allows for 
complete debug functionality. The SWD debug is inherently compatible with Texas Instruments' XDS family of debug probes.  

.. Other debug probes that only support JTAG,
  like the IAR I-Jet and Segger J-Link, need to inject a cJTAG sequence to enable
  JTAG functionality. 

The hardware resources included on the devices for
debugging are listed as follows. Not all debugging functionality is available
in all combinations of debug probe and IDE.

- Data Watchpoint and Trace Unit (DWT) - 2 watchpoints on memory access. 

- Breakpoint unit (BPU) -  4 breakpoint registers.


XDS110 Debug Probe
------------------
Some |DEVICEAND| platforms, like the LP-EM-CC2340R5 have a split-LaunchPad design, which is includes a detachable XDS110 debug board.
The |LP| supports a 20-pin LP-EM debug connector, and this is the assumed debug probe for most development.

The XDS110 is the latest entry level debug probe (emulators) for TI embedded
processors. Designed to be a complete solution that delivers JTAG and SWD
connectivity at a low cost, the XDS110 is the debug probe of choice for
entry-level debugging of TI microcontrollers, processors and SimpleLink
devices. Also, both Core Processor and System Trace are available for all Arm
and DSP devices that support Embedded Trace Buffer (ETB).

It is possible to buy the XDS110 as a standalone debugger.
For example: |LP_XDS110ET| 