UART2LPF3 Hardware attributes. More...

#include <UART2LPF3.h>

Data Fields
UART2_BASE_HWATTRS volatile uDMAControlTableEntry *	dmaTxTableEntryPri

volatile uDMAControlTableEntry *	dmaRxTableEntryPri

uint32_t	txChannelMask

uint32_t	rxChannelMask

int32_t	txPinMux

int32_t	rxPinMux

int32_t	ctsPinMux

int32_t	rtsPinMux

PowerLPF3_Resource	powerID

UART2LPF3_CodingScheme	codingScheme

uint8_t	irLPClkDivider

uint8_t	txChannelEvtMux

uint8_t	rxChannelEvtMux

bool	concatenateFIFO

uint32_t	txChannelSubscriberId

uint32_t	rxChannelSubscriberId

Detailed Description

UART2LPF3 Hardware attributes.

The fields, baseAddr and intNum are used by driverlib APIs and therefore must be populated by driverlib macro definitions. These definitions are found under the device family in:

inc/hw_memmap.h
inc/hw_ints.h
driverlib/uart.h

intPriority is the UART peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

The Low Power F3 devices use either three or two priority bits, depending on the device. That means ~0 has the same effect as (7 << 5) or (3 << 6), respectively.

Setting the priority to 0 is not supported by this driver. HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

A sample structure is shown below:

const UART2LPF3_HWAttrs UART2LPF3_hwAttrs[] = {
    {
         .baseAddr              = UART0_BASE,
         .intNum                = INT_UART0_COMB,
         .intPriority           = (~0),
         .rxPin                 = CONFIG_GPIO_UART2_0_RX,
         .txPin                 = CONFIG_GPIO_UART2_0_TX,
         .ctsPin                = GPIO_INVALID_INDEX,
         .rtsPin                = GPIO_INVALID_INDEX,
         .flowControl           = UART2_FLOWCTRL_NONE,
         .txPinMux              = GPIO_MUX_PORTCFG_PFUNC3,
         .rxPinMux              = GPIO_MUX_PORTCFG_PFUNC3,
         .ctsPinMux             = GPIO_MUX_GPIO_INTERNAL,
         .rtsPinMux             = GPIO_MUX_GPIO_INTERNAL,
         .rxChannelMask         = UDMA_CHANNEL_0_M,
         .txChannelMask         = UDMA_CHANNEL_1_M,
         .rxChannelEvtMux       = EVTSVT_DMACH0SEL_IPID_UART0RXTRG,
         .txChannelEvtMux       = EVTSVT_DMACH1SEL_IPID_UART0TXTRG,
         .rxChannelSubscriberId = EVTSVT_DMA_TRIG_UART0RXTRG,
         .txChannelSubscriberId = EVTSVT_DMA_TRIG_UART0TXTRG,
         .codingScheme          = UART2LPF3_CODING_UART,
         .concatenateFIFO       = false,
    },
};

To enable flow control, the .ctsPin and/or .rtsPin must be assigned. In addition, .flowControl must be set to UART2_FLOWCTRL_HARDWARE.

Field Documentation

§ dmaTxTableEntryPri

UART2_BASE_HWATTRS volatile uDMAControlTableEntry* UART2LPF3_HWAttrs::dmaTxTableEntryPri

uDMA controlTable primary TX entry

§ dmaRxTableEntryPri

volatile uDMAControlTableEntry* UART2LPF3_HWAttrs::dmaRxTableEntryPri

uDMA controlTable primary RX entry

§ txChannelMask

uint32_t UART2LPF3_HWAttrs::txChannelMask

Mask for uDMA TX channel number (1 << channel number)

§ rxChannelMask

uint32_t UART2LPF3_HWAttrs::rxChannelMask

Mask for uDMA RX channel number (1 << channel number)

§ txPinMux

int32_t UART2LPF3_HWAttrs::txPinMux

TX PIN mux value

§ rxPinMux

int32_t UART2LPF3_HWAttrs::rxPinMux

RX PIN mux value

§ ctsPinMux

int32_t UART2LPF3_HWAttrs::ctsPinMux

CTS PIN mux value for flow control

§ rtsPinMux

int32_t UART2LPF3_HWAttrs::rtsPinMux

RTS PIN mux value for flow control

§ powerID

PowerLPF3_Resource UART2LPF3_HWAttrs::powerID

Power driver ID for this UART instance

§ codingScheme

UART2LPF3_CodingScheme UART2LPF3_HWAttrs::codingScheme

UART TXD/RXD encoding/decoding scheme

§ irLPClkDivider

uint8_t UART2LPF3_HWAttrs::irLPClkDivider

Clock divider for IR Low-Power mode

§ txChannelEvtMux

uint8_t UART2LPF3_HWAttrs::txChannelEvtMux

DMA trigger ID for this UART TX channel, as defined in driverlib/evtsvt.h

§ rxChannelEvtMux

uint8_t UART2LPF3_HWAttrs::rxChannelEvtMux

DMA trigger ID for this UART RX channel, as defined in driverlib/evtsvt.h

§ concatenateFIFO

bool UART2LPF3_HWAttrs::concatenateFIFO

Concatenate RX and TX FIFO if write-only

§ txChannelSubscriberId

uint32_t UART2LPF3_HWAttrs::txChannelSubscriberId

DMA subscriber ID for this UART TX channel, as defined in driverlib/evtsvt.h

§ rxChannelSubscriberId

uint32_t UART2LPF3_HWAttrs::rxChannelSubscriberId

DMA subscriber ID for this UART RX channel, as defined in driverlib/evtsvt.h

The documentation for this struct was generated from the following file:

UART2LPF3.h

Data Fields